MC2674

MC2674 MOTOROLA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 33

Technical content

@ SEMICONDUCTOR SEE TECHNICAL DATA Mc2674 Advance Information Advanced Video Display Controller (AVDC) The MC2674 advanced video display controller (AVDC) is @ programmable device designed for use in CRT terminals and display systems that employ raster-scan techniques. The AVDC generates the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT monitor. It provides consecutive addressing to a user specified display buffer mem ory domain and controls the CPU-display buffer interface for various buffer configuration modes. A variety of operating modes, display formats, and timing profiles can be implemented by program: ming the control registers in the AVDC. A minimum CRT terminal system configuration consists of an AVDC, a keyboard controller, an asynchronous communications interface adapter, character ROM, and an attributes controller. Other necessary parts of the system are a single-chip microcomputer such as the MC6809, display buffer RAM, and a small amount of TTL for miscellaneous address decoding, interface, and control. Sys- tem complexity can be enhanced by upgrading the microprocessor and expanding via the system address and data buses. 3 © 4 MHz Character Rate © 1 to 256 Characters Per Row © 1 to 16 Raster Lines Per Character Row © Bit Mapped Graphics Mode @ Programmable Horizontal and Vertical Sync Generators © Interlaced or Non-Interlaced Operation @ Up to 64K RAM Address for Multiple-Page Operation @ Readable, Writeable, and Incrementable Cursor @ Programmable Cursor Size and Blink © AC Line Lock © Automatic Wraparound of RAM © Automatic Split Screen ®@ Automatic Bidirectional Soft Scrolling @ Programmable Scan Line Increment @ Row Table Addressing Mode ® Double Height Tops and Bottoms: © Double Width Control Output ® Selectable Buffer Interface Modes. @ Dynamic RAM Refresh © Completely TTL Compatible @ Single +5-Volt Power Supply @ Power-On Reset Circuit ® Applications Include: CRT Terminals, Word Processing Systems, Small Business Computers, and Home Computers ES MOTOROLA MICROPROCESSOR DATA 3-28

te Interface Contro! Lil Initialization, Osspiey CRY Vv inter "v w Read! Pointe Handshake era Control Display lode CTALS Decode Display Address Doubie Height | | oat

3 Logic

INTA [| if Multiplexors, 8 ° Cursor acy Logic Se Butter eee gic VSYNCICSWNIC MOTOROLA MICROPROCESSOR DATA 3-29

ABSOLUTE MAXIMUM RATINGS This device contains circuitry to pro: [Rating TT Symboi [Value [Unit] _ tect the inputs against damage due to high static voltages or electric fields; | Supply Voltage Veg [08 +70 Tv ee a ce —— ~ however, itis advised that normal pre. cautions be taken to avoid application of any voltage higher than maximum [Storage Temperature Range “tag [Set F160 TC] rated voltages to this high-impedance circuit. For proper operation it is rec ‘ommended that Vin and Vous be con: strained to the range GND={Viq or Vout!":Vce: Reliability of operation is THERMAL CHARACTERISTICS enhanced if unused inputs are tied to haractarieae Symbol! vate Rating) 2" @PPropriate logic voltage level e.g. Characteristic _—_[Svmbot] Value | Rating | Stet ee vay Thermal Resistance "ua cw Plastic Package 50 POWER CONSIDERATIONS The average chip-junction temperature, Ty, in °C can be obtained from: Ty=TaH(Pp* 8a) a where: Ta Ambient Temperature, °C “ja = Package Thermal Resistance, Junction-to-Ambient, “CW Po = Pint*Pport Pint = lec x Vcc. Watts — Chip Internal Power Pport = Port Power Dissipation, Watts — User Determined For most applications Pega T<Piny and can be neglected. PpORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and T, (if PpgRt is neglected) is: Pp=K+(Tj+273°C) (2) Solving equations (1) and (2) for K gives: K=Pp+ (Ta + 273°C) + 8yaPp? (3) where K is a constant pertaining to the particular part, K can be determined from equation (3) by measuring Pp (at equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (21 iteratively for any value of Ta DC ELECTRICAL CHARACTERISTICS (114~0°C to 70°C, Vec=5.0 V45%! [Toput Low Vettage ve 0 08 [ Output Low Vottoge Tou = 24 mAh vo a | [ Outout High Voltage (Excent INTA Output) ou=—200¢A) | Von | 2a fT — Tv | | input Leakage Current Win=0t0 Veg) in 0 | [Biz (Off Stotel Lookage Curent Wec=8.25ViVineO4wo2evi si | 10 [0 [A] LINTR Open-Droin Output Leakage Curent Vo=Oteveo | to | 1 nA _| [internal Fower Dissipation Measured atTa=oe) Tr | | 0 Tw MOTOROLA MICROPROCESSOR DATA 3-30

AC ELECTRICAL CHARACTERISTICS — BUS TIMING iT =0°C to 70°C, Vcc=5 Vt 5%! em a on | [nearest TT | [Rome Saop Trew toe rs Po ms RGAE Haid Tere ron A [ws fo | - | o | — | -s_ [Ce seup time oW Rue cs fo J fe | [CE ou Te hom We RMigh ef [Wor ruse wam tgs | [Deis vars ater Plow gg Pf 0 os] [Date Bus Foanng ater Rmgh oe | | 00 ff to fs [Dae Soup tmetoWrigh gg fe | [Daa ted Time fem Week os J 0 fs Ps | High Time from CE to CE tec Sonaocuve Commands ‘ce veer Omer Acces Ed Ea BUS TIMING DIAGRAM TAS TAH cE tRW- R o007 t : w I Os: 1OH voor CER. WI NCC: NOTES MOTOROLA MICROPROCESSOR DATA 3-31

AC ELECTRICAL CHARACTERISTICS — CHARACTER CLOCK (CCIK) TIMING (Ta ~0°C to 70°C. Voc =5 V4 8% 27Miz [40 Mz | Parameter [min [Max [Min [Max | Unie ToL Pa [tcce | ~am | ooo [20 0000 [rs] TELE High Time - scan | ie [Too ns | CCR Low Sime ice Ps os OvxDut Delay Time hom COUR Faye DADOO-13, MBC rceor | 0 | me | ao | 50 | ns BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREO recor} #@ | 2 | a ] 2m | ns BACK, BCE, WOH, ROB * BCE, WOE. and ADB delays track each other within 10 nanoseconds, Also, thoso output delays wil end to follow direction imanvmurn max imum) of DADDO-DADDI delays CLK TIMING DIAGRAM ‘cco con 3 oom cco tocpz Outputs ‘Note t) tecoz RDB, BCE Notes: = 1. DADDO-DADD13, BLANK, HSYNC, CSYNC VSYNC, CURSOR, BEXT, BRE, BCE, MBC, BACK 2. BCE changes state on both CCLK edges. 3. All voltage measurements are referenced to ground, All time measurements are at the 0.8 V to 20 V level for inputs and outputs. Input levels are 0.4 V to 24 V. AC ELECTRICAL CHARACTERISTICS - OTHER TIMING (T -0 C to 70, Voc=5V + 5%) 7 {- 27MHz | go Miz | | Parameter Symbol) Min | Max | Min | Max | Unit | READY RDFLG low trom W High* tro. | — _|tecp-30| — tccp-a0| ns | | BACK High trom FEREG vow teak [2s |7— | 20 [ons BEXT High from PBREO High text | 25 ns INTA Low from COUR Low ta | = 25 ns | INT High from W, A High Em | so | = | eo | ns AAGLL from HSYNG Lac [steer] = [Steep | = [ns “Timing is illustrated and specified referenced to W and A inputs. Device may also be operated withCE as the “strobing” input. In this case, al iming specifications apply reterenced to falling and rising edges of CE MOTOROLA MICROPROCESSOR DATA 3-32

interva ‘Address of ‘coor tcp of Row wm MOTOROLA MICROPROCESSOR DATA

OTHER TIMING DIAGRAMS (Sheet 2 of 2) SYNC J l | J BLANK J v Vep=n Sean Lines Normal VSYNC (ACL = 1) —| tac ACL Delayed VSYNC Yep +3 Scan res $a i 3 Wor a Delayed Command OL READY oF ROFLG Status Bi PSRED TBAK BNCK ‘ext aeEXT Wor Which Resets Interrup RH NTR NOTE: All voltage measurements are referenced to ground, All time measurements are at the 0.8 V to 2.0 V level for inputs and outputs. Input levels are 0.4 V to 24 V. MOTOROLA MICROPROCESSOR DATA 224

AC ELECTRICAL CHARACTERISTICS — ROW TABLE INPUT TIMING (Ta =0°C to 70°C, Voco=5 V45%) [ee ne fe | | Data Setup Time to CCLK Low toset | too [=f eo Pas] Dota Hold Time from ECLK Low [tonnr [eo [=P P= Ts] ROW TABLE FETCH 1/0 TIMING DIAGRAM Latch 00-07 Into Latch D0-D7 into SSRI Lower SSRI Upper BLANK tecor mac tccp2 >| cursor 3 tcco1 tosat tosat ‘OHAT OHRT- Pow Start Row Stan NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and outputs. Input levels are 0.4 V to 2.4 V. Even Field COMPOSITE SYNC TIMING DIAGRAM Last Displayed Scan of Fust Displayed Scan \\ 4 Horizontal csync SYNC Pulses BLANK l f v Odd Field iaptaye First Displayed Even Field | fen ore % Horieontal SYNC —> fe — fea Penon BLANK Notes: 1. In non-interlaced operation the even field is repeated continuously. Honzontal Blanking Interval 2. In interlaced operation the even field alternates with the odd fied MOTOROLA MICROPROCESSOR DATA aon

SIGNAL DESCRIPTION CURSOR GATE (CURSOR) This output becomes active for a specified number of scan The input and output signats for the AVDC are described lines when the address continued in the cursor register in the following paragraphs ‘matches the address output on DADDO through DADD13 for ‘displayable character addresses. The first and last lines of the . cursor and a blink option are programmable. When the row ADDRESS LINES (A0-A2) table addressing mode is enabled, this output is active for a These input lines are used to select AVDC internal register Portion of the blanking interval prior to the first scan line of a for read/watte operations end for commands, character row, while the AVOC is fetching the starting ad- dress for that row. DATA BUS (D0-071 ‘The &-bit bidirectional three-state data bus controls all INTERRUPT REQUEST (INTR) data, command, and status transfers between the CPU and This is an of is an open-drain output which supplies an active low the AVDC. Bit 0 is the least significant bit and bit 7 is the interupt request fam any ol five maskable sources, This pin most significant bit. The direction of the transfer is con: is inactive after a power-on reset ora master reset command ‘trolled by the read (Fi) and write (W) inputs when chip enable (CE! input is low. When the CE input is high, the data bus's, aC LINE LOCK (ACL) in the three-state condition if this input is (ow after the programmed vertical front fi porch interval, the vertical front porch will be lengthened by READ STROBE (R) increments of horizontal scan line times until this input goes This pin is an active iow input. A low on this pin while CE high is low causes the contents of the register selected by the ad dress ines to be placed on the data bus, The read cycle HANDSHAKE CONTROL 1 (CTRL1) butter (WDB) output which strobes deta from the interface WRITE STROBE (Wi) _ latch into the display memory. In transparent and shared ‘This is an active low input. A low on this pin while CE is modes, this is an active low processor bus request (PERE) also low causes the contents of the data bus to be transfer input which indicates that the CPU desires to access the red to the register selected by the address lines. The transfer display memory occurs on the trailing (rising) edge of W. ch HANDSHAKE CONTROL 2 (CTRL2) CHIP ENABLE (CE) fn independent mode, provides an active low read date This is an active low input. When low, data transfers bet butter (RDB) output which strobes data trom the display ween the CPU and the AVDC are enabled on the data bus as memory into the interface latch. In transparent and shared controlled by the write strobe, read strobe, and address modes, this is an active low bus external enable (BEXT! out lines. When CE is high, effectively, the AVDC is isolated put which indicates that the AVOC has relinquished control from the date bus and D0-D7 are placed in the three-state Of the display memory (DADDO-DADDI2 are in the thres- condition state condition) in response to a CPU bus request. BEXT also goes low in response to a ‘display off and float DADD™ CHARACTER CLOCK (CCK) command. In row buffer mode, it is an active iow bus re- This input is the timing signal derived from the video dot quest (BREQ) output which halts the CPU during a line clock which is used to synchronize the AVDC's timing func- DMA tions, HANDSHAKE CONTROL 3 (CTRL3) HORIZONTAL SYNC (HSYNC) In independent mode, provides the active low buffer chip This active high output provides video horizontal sync enable {BCE} signal to the display memory. In transparent pulses. The timing parameters are programmable. and shared modes, provides an active low bus acknowledge (BACK! output which serves as a ready signal to the CPU in VERTICAL SYNC/COMPOSITE SYNC (VSYNC/CSYNC) response to a processor bus request. In row buffer mode, A control bit selects either vertical or composite sync this ‘s an active high memory bus control (MBC) output pulses on this active high output. When CSYNC is selected, which configures the system for the DMA transfer of one equalization pulses are included. The timing parameters are row of character codes from system memory to the row programmable. display butter BLANK (BLANK) DISPLAY ADDRESS (DADDO-DADD13) This active high output defines the horizontal end vertical These outputs are used by the AVDC to address up to 16K borders of the display. Display control signals which are out of display memory directly, or to 64K of memory by demult put_on display addresses CADDO and DADD3 through Plexing DADD14 and DADDIS. These outputs are floated at DAOD13 are valid on the trailing edge of BLANK various times depending on the buffer made. Various control MOTOROLA MICROPROCESSOR DATA

signals are multiplexed on DADDO through DADD13 and are trol. The major blocks are described in the following valid at the trailing edge of BLANK. The following para- paragraphs. graphs describes the control signals. LINE GRAPHICS (DADDO/LG) — This is the output DATA BUS BUFFER which denotes bit: mapped graphics mode. The data bus buffer provides the interface between the ex DISPLAY ADDRESS 14 {DADD1/DADD14) — This is the ternal and internal data buses. It is controlled by the opera- multiplexed address bit used to extend addressing to 64K tion contro! block to allow read and write operations to take DISPLAY ADDRESS 15 (DADD2/DADD15) ~ This is the Place between the controlling CPU and the AVDC: multiplexed address bit used to extend addressing to 64K LAST ROW (DADD3/LR} — Thisis the output which indi- INTERFACE LOGIC cates the last active character row of each field, The interface logic contains address decoding and read outputs provide the number of the current scan ine count microprocessor vis the dota butter, The functions perlormes for vach ehorecter row y the and write operations are shown in Table of fST LINE (DADDE/EL! — Ths ouput i axared OPERATION CONTROL oe arate aayalorvat fast Prior fo the fist scan line of The operation control section decodes configuration and operation commands from the CPU and generates ap DOUBLE WIDTH (DADD3/OW)} ~ This output denotes @ propriate signals to other intemal sections to contro! the Souble width character row. overall device operation. It contains the timing and display UNDERLINE (DADD10/UL) — This output is asserted registers which configure the display format and operating during the blanking interval just prior to the scan fine which mode, the interrupt logic, and the status register which pro matches the programmed underline position (line 0 through vides operational feedback to the CPU 5) 3 BLINK FREQUENCY (DADDI1/BLINK) — Blink tre TIMING quency provides an output divided down from the vertical The timing section contains the counters and decoding sync rate logic necessary to generate the monitor timing outputs and 00D FIELD (DADD12/ODD) — This active high signal is to control the display format. These timing parameters ere asserted before each scan line of the odd field when interlace selected by programming of the initialization registers is specified. Replaces DADD4/LAQ as the least significant line address for interlaced sync and video applications, DISPLAY CONTROL LAST LINE (DADD13/LL) — This output is asserted dur The display control section generates linear addressing of ing the blanking interval just prior to the last scan line of each up to 16K bytes of display memory. Internal comparators character row imit the portion of the memory which is displayed to pro: grammed values. Additional functions performed in this sec Vee AND GND tion include cursor positioning and address comparisons re- Power is supplied to the AVDC using these two pins. Voc auired for generation of timing signals, double-height tons is the +5 volts +5% power input and GND is the ground and bottoms, smooth scroling, and the spit-soreen inter connection pts BUFFER CONTROL FUNCTIONAL DESCRIPTION The butfer control section generates three signals which control the transfer of data between the CPU and the display As shown in the block diagram, the AVDC contains the bulter memory. Four system configurations requiring four following major blocks: data bus butter, interface logic, different ‘handshaking’ schemes are supported. These are operation control, timing, display control, and buffer con described in SYSTEM CONFIGURATIONS. TABLE 1 — AVDC ADDRESSING [a2 Tar [ao | Read (R=0) 0 | @ | 0 |interunt Register initialization Registers 0 | 6 | 1 |status Regster [Command Register 0 | 1 | 0 |scteen start t Lower Register | Scroen Start 1 Lower Register 0 | 1 | 1 [Screen Start 1 Upper Register | Screen Start 1 Upper Register 1 | 0 | 6 |cursor Address Lower Register |Cursor Address Lower Register 1 | 0 | 1 |cursor Addcoss Upper Register [Cursor Address Upper Register i | 1 |G |screen Start 2 Lower Register |Screen Start 2 Lower Ragister 1 1 [Screen Start 2 Upper Register [Screen Start 2 Upper Regster “There aro 15 mitazation ragisters which are accessed sequentially via a single address The AVDC maintains an internal pointer to these registers which is ineremented alter each wie at this address untl the last register {IR4)s accessed, The pointer then con tinues to point to [R16 for addtional accesses. Upon a power-on ar a master reset com mand, the internal pointer is reset to point to the first register {IRO! of the initiakzation register group. The internal pointer can aiso be preset to any register of the group via the ‘ioad IR address pointer’ command MOTOROLA MICROPROCESSOR DATA 2.27

SYSTEM CONFIGURATIONS 6, AVDC sets RDFLG status to indicate that the write is completed Figure 1 illustrates the block diagram of a typical display Similarly, a read operation proceeds as follows: terminal that uses an MC2674, character ROM, a keyboard in- 1. Steps 1. and 3. as above terface, and an attribute controller. In this system, the CPU 2 cro. nop wath, “ examines inputs from the data communications line and the CPU issues “read at cursor with/without increment’ or keyboard and places the data to be displayed in the display ‘read at pointer” command. buffer memory. This butferis typically a RAM which holds the 3. AVDC generates control signals and outputs specified Gata for a single or multiple screenioad {page} or for a single address to perform requested operation. Data is copied character row. from memory to the interface latch and AVDC sets The AVDC supports four common system configurations RDFLG status to indicate that the read is completed. of display-buffer memory, designated the independent, 4. CPU checks RDFLG status to see if operation is com- transparent, shared, and row-butter modes. The first three pleted modes utilize a single or multiple page RAM and differ 5. CPU reads data from interface latch. primarily in the means used to transfer display data between the RAM and the CPU. The row-buffer mode makes use of a Loading the same data into a block of display memory is single row buffer (which can be a shift register or @ small accomplished via the “write ftom cursor to pointer” com. RAM) that is updated in real me to contain the appropriate mand: display data The user programs IRQ bits 0 and 1 select the mode best ‘ Fees ROFL status Dit to assure that any de- suited for the system environment. The CTRL1, CTRL2, and mean complet CTRL3 outputs perform different functions for each mode and 2. CPU loads data to be written to display memory into the are named accordingly in the description of each mode, interface latch 3. CPL writes beginning address of memory block into cursor address register and ending address of block into INDEPENDENT MODE pointer address register. The CPU-to-RAM intertace configuration for this mode is 4. CPU issues “write from cursor to pointer” command. illustrated in Figure 2. Transfer of data between the CPU and 5. AVDC generates contro! signals and outputs block ad- display memory is accomplished via a bidirectional latched dresses to copy data from the interface latch into the port and is controlled by read data butter (RDB), write data specified block of memory buffer (WDB), and butter chip enable (BCE. This mode pro- 6 AVDC sets RDFLG status to indicate that the block vides a non-contention type of operation that does not re: write is completed. quire address multiplexers. The CPU does not address the memory directly — the read or wnte operation is performed Similar sequences can be implemented on an interrupt at the address contained in the cursor address register or the driven basis using the READY interrupt output to advise the pointer address register as specified by the CPU. The AVDC CPU that a previously asserted delayed command has been enacts the data transfers during blanking intervals in order to completed Prevent visual disturbances of the displayed data. Two timing sequences are possible for the “read/write at Ksor/pointer"” commands. If the command is given during The CPU manages the data transfers by supplying com: Cursor mands to the AVOC. The commands used are the active display window (defined as first scan line of the

1 Rend a first character row to the last scan line of the last character

'ead/ write at pointer address, fowl, the operation takes place during the next horizontal 2, Read/write at cursor address (with optional increment blanking interval, as illustrated in Figure 3. If the command is of address), and given during the vertical blanking interval, or while the 3, Write from cursor address to pointer address. display has been commanded blanked, the operation takes The operational sequence for a write operation is: place immediately. in the latter case, the execution time for 1. CPU checks RDFLG status bit to assure that any de- the command is approximately five character clocks (see layed commands have been completed. Figure 4) . 2. CPU loads data to be written to display memory into the Timing for the “write from cursor to pointer operation is. ‘htertoce latch shown in Figure 5. The memory is filled at a rate of one loca- or vidtess int ter tion per two character times. The command will execute only 3. CPU wiites address into cursor or pointer registers. during blanking intervals and may require many horizontal or 4. CPU issues “write at cursor with/without increment’ vertical blanking intervals to complete. Additional delayed or “write at pointer” command ‘commands can be asserted immediately after this command 5. AVDC generates control signals and outputs specified has completed address to perform requested operation, Data is copied Immediately commands can be asserted at any time from the interface latch into the memory. regardless of the state of the ready state/interrupt MOTOROLA MICROPROCESSOR DATA

2eensel) 92 3 : 2 rs 2 = nl z i é |_| s g 8 : E = Z ‘ a= Bz Eg ge 5 “ KS £3 8 &2 es MOTOROLA MICROPROCESSOR DATA

B g Me 3 Fa 3 Sam ° 2 2 o) =] 2 3 z Be £ Sins 8 Ps ? a 2 5 < i} f 5 = 3

2 By = B q

5 4 a ES £ 3 ; aig & a 5 [=] EERQ 3 3 Be . Be < 1S 3] ge “i Ei 3 Be z Ee q 82 5 a og ba Se . 3 $8 ge Fa ° og §2 eq] 5 q | 22 B SB on s SmniGn: “ eo ep ey cig 3 a2 2 & 2 ¢ & 3 2 & gF reer MOTOROLA MICROPROCESSOR DATA aap

FOURE 6 ~ AVOC SHARED OR TRANSPARENT BUFFER MODES AVOC RAM Display Address ADR PRREG CTRL te cru cd BACK CTALS Ww on | | a conz +: i J} Ta Sons cpu { ° ASV 3 FAGURE? ~ TRANSPARENT BUFFER MODE THANG cox ares fa Denna aaa BACK (4h a set os zy ae @ ay NOTES: 1 PBRET must ne asetd prior to he king edge of BLANK in order for Sequence to begin ding that baning period 2. Hf PBREO is negated after the next to fast CCLK of the horizontal blanking interval, the next scan line will also be blanked. 3. Accesses during vertical blank or “display off” are granted only at the beginning of the horizontal front porch. te MOTOROLA MICROPROCESSOR DATA aan

[TS xt | atelatatetate Settee BLANK Ay ono XX} HEE GSS) NOTES: PREG BREG eo eee Ae BACK BACK = m= BLANK Sys ADO LAN System Processor Has Continuous Bus Control ‘Addeennes ‘bi Atter ‘crsplay off and 3 state’ command ‘the other modes, but circuitry must be added to route the OPERATION AVDC. Additionally, when not operating in row buffer After power is applied, the AVDC will be in an inactive mode, care must be taken to assure that the CPU does not slate. Two consecutive “master reset” commands are attempt to access the AVDC while it is reading the row table. necessary to release this circuitry and ready the AVOC for One way of preventing this is to latch prior to reading or operation. Two register groups exist within the ADC; the writing the AVDC. The AVOC should only be accessed if the initialization registers and the display control registers. The Figure 13 illustrates a typical hardware implementation for pointer address, scrolling region, double height and width MOTOROLA MICROPROCESSOR DATA 2.44

. = [., or ee ZS “nen i a See an 7 ii Ww cok BREO 2. Alt voltage measurements are referenced to ground. All time measurements are at the 08 V to 2.0 V level for inputs and MOTOROLA MICROPROCESSOR DATA 3-45

FIGURE 12 — ROW TABLE ADDRESS FORMAT Row Table in Memory } [>] Third Data Row | 3 | Fast

3 Data Row

FIGURE 13 — ROW TABLE MODE CONFIGURATION (NON-ROW BUFFER MODES) caK RAM paop jap Address avo AVDC [| Datei/0 CCR cK [BLN sian fe —a] 0 | » a W CURSOR ce 00-07 F ve g 8 : é K SN7ALS248 Display Data Bus Select = Decode = Tw] | suaaiszes si MOTOROLA MICROPROCESSOR DATA 3-46

me TOU Tm. BLANK Last Line of Row First Line of Row BREG | | Row Butter a 3 CURSOR ' Possible Cursors * 1 Possible Cursors I owe Th, Lee fol ws Butter Mode Bus Request Request wo a Bufter Mode woe ADB BCE MOTOROLA MICROPROCESSOR DATA 3-47

effects. The display control registers specify the mem- ditions generated by the AVDC supply the “handshaking” ory address of the base character (upper left corner of information necessary for the CPU to effect real time screen), the cursor position, and the split screen ad- display changes in the proper time frame if required. dresses associated with the scrolling area or an alter- nate memory. These may require modification during operation. INITIALIZATION REGISTERS Alter initial loading of the two register groups, the AVODC is ready to control the monitor screen. Prior to There are 15 initialization registers (IRO-IR14) which executing the AVDC commands which turn on the dis- are accessed sequentially via a single address. The AVOC play cursor, the user should load the display memory maintains an internal pointer to these registers which with the first data to be displayed. During operation, is incremented after each write at this address until the the AVDC will sequentially address the display memory last register (IR14) is accessed. The pointer then contin- within the Jimits programmed into its registers. The ues to point to IR14 for further accesses. Upon a power. memory outputs character codes to the system char- on or a master reset command, the internal pointer reset acter and graphics generation logic, where they are con- to point to the first register (IRO) of the initialization verted to the serial video stream necessary to display register group. The internal pointer can also be preset the data on the CRT. The user effects changes to the to any register of the group via the “load IR address CRT. The user effects changes to the display by modi- pointer" command. These registers are write only and fying the contents of the display memory, the AVDC are used to specify parameters such as the system con- display control and command registers, and the initial figuration, display format, cursor shape, and monitor 3 ization registers, if required. Interrupts and status con. timing. Register formats are shown in Figure 15. FIGURE 15 — ITALIZATION REGISTER FORMATS (Sheot 1 of 4 1 8 5 ‘ a 2 1 ° 90 ome Syne Baler Made Height interlaced Solect Select widtn ‘0000= 1 Line ‘WO0=2 Lines O=vs¥Nc | 00 Independent ont =2 Lines bo0i=4 tines | toeswnc | on Trancparen i0=3 tees po10=6 Lees 10. Shaves 1106 8 Unes 1110=30 Lnes 1 6 8 ‘ a 2 1 ° int Enable | oogoo00= 1 TCLK 9000001 = 2 TCIK Intertace : €C-08 act sep Hgync~Hap!~204gync!

1 Inter: 1111110 = 127 CCR

Jace TIN 1= 128 CCR , 5 5 a 3 2 1 ° = 08 ‘o000=2 GcuK ‘O00 = Not Allowed 1=0n 0001 =4 CCLK 01=3 CCK | 110-30 TOK 110= 23 TOR Wite 52 TOR 11527 TOK eee MOTOROLA MICROPROCESSOR DATA 3-48

FIGURE 15 — INITIALIZATION REGISTER FORMATS (Shoot2of 4) 1 ‘ 5 ‘ a 2 1 0 wa ootz8 scan tines Do00t = Sean Lins 1 8 5 ‘ 3 2 : 0 Sine fate Active Chavate Roms Pet Screen verne Coo000t = Rows vS¥Ne : , 6 A ‘ a 2 : 0 ins toot = on inet Qoot= Scan Le , A 5 4 3 2 1 A Wo = Sean Une 3 : MOTOROLA MICROPROCESSOR DATA 3-49

FIGURE 15 — INTIALIZATION REGISTER FORMATS Sheet 3 of 4) tae HFEF’ = 4.005, : seo a nazis , F 5 ‘ 2 2 0 ee Soon Rod MOTOROLA MICROPROCESSOR DATA 3-50

FIGURE 15 — INITIALIZATION REGISTER FORMATS (Sheet 4 of 4) 7 6 5 4 3 2 1 ° R13 {000000= Row 1 0000001 = Row 2 TT = Row 128 7 6 5 4 3 2 1 o ania Tines to Scroll = Normal ‘GO= Normal ‘Oa00= 1

01 Double With 01 = Double Wiath 0001 = 2

10= Double Width 10= Double Width . and Tops ‘and Tops .

11 Double With 11 Double Width 10=15

and Bottoms and Bottoms un=16 DOUBLE HEIGHT/WIDTH ENABLE (IROI71) ~ When this ODD, LO-L2 are used as the line address for the character 3 bits set, the value in IR14{7:6] is used to contro! the double generator. The resulting displays are shown in Figure 16 height and width conditions of each character row. Asser- For “interlaced sync” operation, the same information is tion of this bit also allows 1R1417:6} to be programmed in two displayed in both odd and even fields, resulting in enhanced ways: readability. The AVOC outputs successive line numbers in 1. By the CP writing to 1R14 directly ascending order on the LAQ-LA3 lines, one per scan line for each field » per ore chonged either by the CPU ting to thi The “interlaced syne and video" format doubles the char register or by the automatic loading of SSRI when acter density on the screen. The AVDC outputs successive operating in row table mode, the two most significant line numbers in ascending order on the odd and LAO-LA2 bits of SSRI upper are copied into IR14(7-6]. Thus, the lines, one per scan line for each field ‘most significant bits of each row table entry can be us- EQUALIZING CONSTANT (IR1I6:0}) — This field indiect- ed to control double height and double width attributes ly defines the horizontal front porch and is used internally to on a row-by-row basis. generate the equalizing pulses for the RS170 compatible 1R14(6:4] are not active when this bit is set. When this bit CSYNE. The value_for this field is the total number of is reset, the double height and width attributes operate as character clocks (CCLKs! during @ horizontal line period described in 1R14) divided by two, minus two times the number of character SCAN LINES PER CHARACTER ROW (IROI6:31) — Both locks in the horizontal sync pulse: interlaced and non- interlaced scanning are supported by the AVOC. For interlaced mode, two different formats can be ecu HACT*HEP+HSYNCTHSP 9 eves implemented, depending on the interconnection between 2 the AVDC and the character generator (see IR1[71). This field defines the number of scan lines used to compose a char- The definition of the individual parameters is illustrated in Fig- acter row for each technique. As scanning occurs, the scan ure 17. line count is output on the LA-LA3 and ODD pins. Note that when using the attributes controller it will delay VSYNC/CSYNC (1RO(2)) — This bit selects either vertical the blank pulse three CCLKs relative to the HSYNC pulse sync pulses or composite sync pulses on the VSYNC/ ROW TABLE MODE ENABLE (IR2[7]) — Assertion/ nega: CSYNC output (pin 18). The composite sync waveform con- tion of this bit causes the AVDC to begin/ terminate forms to EIA RS170 standards, with the vertical interval com- operating in row table mode starting at the next character posed of six equalizing pulses, six vertical sync pulses, and row. See ROW TABLE ADDRESS MODE. By using the split six more equalizing pulses interrupt capability of the AVDC, this mode can be enabled BUFFER MODE SELECT (1R0(1:0)) — Four buffer memory and disabled on a particular character row. This allows 2 modes may be selectively enabled to accommodate the ‘combination of row table and sequential addressing to be desired system configuration. See SYSTEM CONFIGURA- utilized to provide maximum flexibility in generating the TIONS. display. INTERLACE ENABLE (IR1I7]) ~ Specifies interlaced or HORIZONTAL SYNC PULSE WIDTH (IR2I6:31) — This non-interlaced timing operation. Two modes of interlaced field specifies the width of the HSYNC pulse in CCLK operation are available, depending on whether LO-L3 or periods. ne ET EST amma! MOTOROLA MICROPROCESSOR DATA 3-51

FIGURE 16 — INTERLACED DISPLAY MODES Odd > <—w— —_—v— <—b Line Address Line Address Line Adaress To Character Generator To Character Generator To Character Generator 8 . 7 Sg toe Lgrerere=e—— sg | 2 ag SPR z s2 |) os 324s 2 si},—. — $2 | 3 Ss 22 ff SS és Ce ees oe 5 | * Se-e-3 ee 7-0-0-0-0-0—— or _— 6 3 : 1=9-0-0-0-0—— _— 2-3 2 ec 3-9 48s. a 2 = — 7-0-0-0-0-0-— (eo a 4 S802 5-0 Non Interlacee Interiaced SYNC Interlaced SYNC and Video IRO= 1000; Total Lines! Row=9 1RO.= 1000; Total Lines/Row= 16 \\RO=0100; Total Lines/Row'= 10 HORIZONTAL BACK PORCH (1R2[2:0]) — This field CHARACTER ROWS PER SCREEN (IR4[6:0]) — This defines the number of CCLKs between the trailing edge field defines the number of character rows to be dis- of HSYNC and the trailing edge of BLANK played. The value multiplied by the scan lines per char- . acte row, plus the vertical front porch, the vertical back VERTICAL FRONT PORCH (IR3[7:3]) — This field spec- porch values, and the vertical sync pulse width is the ifies the number of scan line periods between the rising vertical scan period in scan lines ‘edges of BLANK and VSYNC during the vertical retrace interval. The vertical front porch is extended in incre- ments of scan lines if the ACLL input is low at the end ACTIVE CHARACTERS PER ROW (IRS(7:0]) — This of the programmed value field determines the number of characters to be dis- played on each row of the CRT screen. The sum of this VERTICAL BACK PORCH {1R3{4:0]) — This field de- value, the horizontal front porch, the horizontal sync termines the number of scan line periods between the width, and the horizont! back porch is the horizontal falling edges of the VSYNC and BLANK outputs. scan period in CCLKs, CHARACTER BLINK RATE (IR4{7]} — Specifies the fre FIRST AND LAST SCAN LINE OF CURSOR {IR6I7:4] ui a iming. 7 | quency for the character blink attribute timing, The blink IR6I3:01) — These two field specity the height and po: rate can be specified as 1:64 or 1/128 of the vertical field sition of the cursor on the character block. The “first’” rate. The timing signal has a duty cycle of 50% and is tine is the topmost line when scanning from the top to multiplexed onto the DADD1/BLINK output at the falling the button te sere edge of each BLANK MOTOROLA MICROPROCESSOR DATA 3-52

me 900469? 0743072 6cO

mm 900469? 0743073 7b?

DISPLAY CONTROL REGISTERS ing starts at the last address displayed on the screen and in- crements by one for each character clock during the retrace There are seven registers in this group, each with an in- interval. If the display butter last address is encountered, divduoladérecs Thor formate are australe in Figue 18 Tfresting continues om the Gapiy Water fet addrene The command register is used to invoke one of 19 possible The sequential operation described above will be modified AVDC commands as descnbed in COMMANDS. The re- upon the occurrence of any of three events. First, sf during maining registers in the group store address values which the incrementing of the memory address counter the specify the cursor location, the location of the first character “display buffer last address” (IR9{7:4]) is reached, the MAC to be be displayed on the screen, and any split screen ad- will be loaded from the “display butfer first address" register dress locations. The user initializes these registers after (JR9(3:0] and IRBI7:01) at the next character clock. Sequen: powering on the system and changes their values to control tial operation will then resume starting from this address. the data which is displayed. This wraparound operation allows portions of the display buffer to be used for purposes other than storage of display. able data and is completely automatic without any CPU SCREEN START REGISTERS 1 AND 2 intervention (see Figure 19a). The screen start 1 registers contain the address of the first The sequential row to row addressing can also be modified character of the first row (upper left corner of the active via split register 1 (IR12} and split register 2 (IR13), under display). At the beginning of the first scan line of the first CPU control, or by enabling the row table addressing mode. row, this address is transferred to the row start register If bit 6 of screen start register 2 upper ISPL1) is set, the (ASR) and into the memory address counter (MAC}. The ‘screen start register 2 contents will be loaded automatically. counter is then advanced sequentially at the character clock into the RSR at the beginning of the first scan line of the row rate for the number of times programmed into the active designated by split register 1 (IR12/6:0)). If bit 7 of screen characters per row register (IR5), thus reaching the address. start 2 upper (SPL2) is set, the screen start register 2 con- of the last character of the row pius one. At the beginning of tents is automatically loaded into the RSA at the end of the 3 each subsequent scan line of the first row, the MAC is. last scan line of the row designated by split register 2 reloaded from the RSR and the above sequence is repeated. (IR13(6:0]). SPL and SPL2 are write only bits and will read memory address for the secand character row. This process both) are changed during any character row (e.g , row ‘n’) is repeated for the programmed number af rows per screen the starting address of the next character row trow ‘n+ 1") Thus, the data in the display memory is displayed sequen- will be the new value of the screen start register and address: tially starting from the address contained in the screen start ing wil continue sequentially from there. This allows fea- register. After the ensuing vertical retrace interval, the entire tures such as split screen operation, partial scroll, or status: During vertical blanking, the address counter operation is ture of the AVDC is useful in controlling the CPU initiated modified by stopping the automatic load of the contents of ‘operations. Note that in order to obtain the correct screen the RSR into the counter, thereby allowing the address out- display, screen start register 1 must be reloaded with the puts to free-run. This allows dynamic memory refresh to oc- ‘original (origin of display! value prior to the end of the ver cur during the vertical retrace interval. The refresh address. tical retrace. See Figure 19b. PHGURE 18 = CISPLAY CONTROL REGIETER FORMATS Ieee 1 of 2) 1 6 5 ‘ 2 2 : ° a A a MOTOROLA MICROPROCESSOR DATA 3-55

FIGURE 18 — DISPLAY CONTROL REGISTER FORMATS (Shet 2 of 2) , ‘ 5 ‘ a 2 1 0 FOBT vate ioe2 ores 2 s Attribute 00 kee Seroon Sa 1 Regist (Rod and ite and Cursor Address Registers (Read and Write) 1 A 5 ‘ a 2 ! ° spf} crow | onon ’ ‘ 5 ‘ 3 2 \\ 0 tee a a2 (rer cess NOTE ‘Screen Start 2 Registers (Read and Write) When row table addressing mode is enabled, the first ac. range of the AVDC up to 64K. in that case, these two bits Gress of the row table is designated in SSR2. The AVDC act as 2 two-bit counter which is incremented each time that the blanking interval prior to the first scan line of each char- incremented at the falling edge of BLANK and that for pro- acter row and loads it into SSRI for use as the starting ad- er display operation the wraparound address should be pro- dress of the next row. Since the contents of SSR2 changes grammed to occur at the last character position of a row. a the table entries are fetched, it must be re-initialized to Also, the first address accessed in the new page will be the point to the first table entry during each vertical retrace inter address contained in the display buffer first address register val. (IR9[3:0] and IR8[7:0}). The vaiues of the two most significant bits of SSR1 upper are multiplexed onto the DADD1/DADD14 and DADD2/ CURSOR ADDRESS REGISTERS. DADDIS5 outputs during the falling edge of BLANK. If The contents of these registers define the buffer memory IROI7)=0, these two bits act as memory page select bits address of the cursor. The cursor output will be asserted which may be used to extend the display memory addressing when the memory address counter matches the value of the MOTOROLA MICROPROCESSOR DATA 3-56

FIGURE 19 — DISPLAY ADDRESSING OPERATION , | NS iad SY Re SSS Monto ri ‘Display Butter End Display 16k i Memory a) Display Memory Wraparound Td EE - ae Display Butter Start 3 PSS —sottom ot Scraen | | SSS Screen Start2— SS a) — Display Butler End Display 16k ory {(b) Display Memory Split Screen With Wraparound cursor address registers for the scen lines specified in IR6. (masked) from causing interrupts by certain AVDC com- The cursor address rogisters can be read orwritten by the mands. An interrupt condition which ls enabled (masked bit CPU or incremented via the “increment cursor address” ‘equat to one! will cause the INTA output to be asserted and command. In independent butfer mode, these registers will cause the corresponding bit in the interrupt register to be define a butter memory address for AVDC controlled access -—-set upon the occurrence of the interrupting condition. An in response to “read/write at cursor with/without incre- interrupt condition which is disabled (mask bit equal to zero) ment’ commands, or the first address to be used in has no effect on either the NTH output or the interrupt ‘The status register provides six bits of status information: INTERRUPT/STATUS REGISTERS the five possible interrupt conditions plus the RDFLG bit. For The interrupt and status registers provide information to _—this register, however, the contents are not affected by the the CPU to allow it to interact with the AVDC to effect state of the mask bits. desired changes that implement various display operations. Descriptions of each interrupt/status register bit follow. The interrupt register provides information on five display Unless otherwise indicated, a bit, once set, will remain set operations. The interupt register provides information on util reset by the CPU by issuing 2 "reset interrupt status five possible interrupt conditions, as shown in Figure 20. bits” command. The bits are also reset by a “master reset’ These conditions can be selectively enabled or disabled command and upon power-up. MOTOROLA MICROPROCESSOR DATA 3-57

FIGURE 20 — INTERRUPT AND STATUS REGISTER FORMAT D 6 5 4 3 2 1 ° Tine Not Used = Busy [O=No | O=No | O=No | O=Busy | 0=No Always Read as0_| 1=Ready | 1=Yes | 1=Yos | 1=Yes | t=Ready | 1= Yes RDFLG (I/SRI5)) — This bit is present in the status when execution of @ delayed command has been completed register only. A zero indicates that the AVDC is currently No other delayed command should be invoked until the prior executing the previously issued delayed command, A one delayed command is completed indicates that the AVDC is ready to accept a new delayed ‘SPLIT SCREEN 2 (1/SRI0]) — This bit is set when a match ‘command. Occurs between the current character row number and the VBLANK (1/SRI4}) — indicates the beginning of a vertical value contained in split register 2 (IR 1316:0)) blanking interval. Set to one at the beginning of the first scan line of the vertical front porch LINE ZERO (I/SRI3)) ~ Set to one at the beginning of the COMMANDS first scan line lline 0) of each active character row SPLIT SCREEN 1 (I/SRI2]} — This bit is set when a match The AVDC commands are divided into two classes: the in- occurs between the current character row number and the stantaneous commands which are executed immediately 3 value contained in split register 1, 1R12(6:01. The equality after they are invoked, and the delayed commands which condition is only checked at the beginning of line zero of ‘may need to wait for a blanking interval prior to their execu: each character row. tion. Command formats are shown in Table 3. The com- READY (I/SRI1]} ~ The delayed commands affect the mands are asserted by performing a write operation to the display and may require the AVOC to wait for a blanking command register with the appropriate bit pattern as the interval before enacting the command. This bit is set to one data byte TABLE 3 — AVDC COMMAND FORMATS [or [oe [os | oe [os [oe [or [oo [wm | mma Instantaneous Commands _ oo} o}ojoj}o foto | Master Reset ° 0 0 1 v v v vii | Load IR Pointer with Value V (V=0 to 14) o}ol]i}a}aial a) o Disable Graphics ee Enable Graphics o}ofr} ai rin ja fo | Display Off — Float DADD Bus if N~1 o}o;1iatlatnial + | Display On — Next Field (N= 1) or Scan Line (N-0} ofol]1]{r]fatala ilo Cursor Off ;ofo!}a) 1} a}lalayrw i Cursor On ofa fo}n{njuni nin | | Reset Interrupt/Status: bit Reset where N= 1 1 0 0 N N N N N | Disable Interrupt: Disable where N = 1 ofa} apn |u| nu} nin Enable Interrupt: Enables Interrupts where N=1 | | | vit}siris, Interrupt Bit 8B) z] plo. e | | Assignments tiyia \\ Delayed Commands 1 lofalofo]i]o | 0 | A@ [Road at Pointer Adcress 1 0 1 a) 1 | 0 | A2 | Write at Pointer Address rj) oe | 1 | o | 1 | 0 | 0 | 1 | Ag |inerement Cursor Address tT fo} a | o } a} 1 | o | oO | Ac |Read at Cursor Address 1} 0 | 4 | 0 J 7 | 0 | 4 | © | AA |Write at Cursor Address 1) o | t | o | 1 J 1 | 0 | 1 | AD jRead at Cursor Address and increment Address r | o | fo] 4 | 0 | 4 | a | AB [Wete at Cursor Address and increment Address 1 0 | 1 | 4 | 1 | 0 | 1 | 4 | BB [Write from Cursor Address to Pointer Address Pie Tt [aft ft | 0 | 1 | 80 [Read trom Cursor Address to Pointer Address. NOTES: “Any combination of these three commands is valid. d= Don't care MOTOROLA MICROPROCESSOR DATA 3-58

INSTANTANEOUS COMMANDS DISPLAY ON The instantaneous commands are executed immediately Restores normal blanking operation either at the beginning after the trailing edge of the write pulse during which the of the next field (bit 2= 1) or at the beginning of the next ‘command is issued. These commands do not affect the state scan line ibit 2=0). Also returns the DADDO-DADD13 of the ROFLG or READY interrupt/status bits and can be in- drivers to their active state. voked at any time. CURSOR OFF MASTER RESET Disables cursor operation. Cursor output is placed in the This command initializes the AVDC and can be invoked at low state any time to return the AVDC to its initial state. Upon power: up, tWo successive master reset commands must be applied CURSOR ON to release the AVDC’S intemal power-on circuits. In Enables normal cursor operation. transparent and shared buffer modes, the CTRL input must be! righ when the command is issued. The command causes RESET INTERRUPT/STATUS BITS 1. VSYNC and HSYNC are driven low for the duration of mans command resets the designated bits in the interrupt the command and BLANK goes high, After command and status registers. The bit positions correspond to the bit completion, HSYNC and VSYNC will begin operation pote oe ‘and BLANK will remain high until a ‘display on” com: ene ae mand is received Bit2 — Spin? 2. The interrupt and status bits and masks are set 10 zero, Bit3 — Line Zero except for the RDFLG flag which is set to a one. Bit4 — Vertical Blank 3. The row buffer mode, cursor-off, display-off, and line graphics disable states are set DISABLE INTERRUPTS 4. The initialization register pointer is set to address IRO. Sets the interrupt mask 10 zeros for the designated condi- 8. sR2{71 is rasa. tions, thus disabling these conditions trom being set in the - interrupt register and asserting the INTR output. Bit position LOAD IR ADDRESS correspondence is as above This command is used to preset the initialization register pointer with the value "V" defined by 03-00. Allowable ENABLE INTERRUPTS values are 0 10 14 This command writes the associated interrupt mask bit to one. This enables the corresponding conditions to be set in ENABLE GRAPHICS the interrupt register and asserts the INTR output. Bit post After invoking this command, the AVDC will increment tion correspondence is as above the MAC to the next consecutive memory address ‘or each ‘scan line even if more than one scan line per row is program- DELAYED COMMANDS med. This mode can be used for bit: mapped graphics where This group of commands is utilized for the independent each location in the display buffer within the defined area buffer move of operation. although the “increment cursor” contains the bit pattern to be displayed. This command is command can also be used in other modes. With the excep row buffered and should be asserted during the character tion of the “write from cursor to pointer” and “increment row prior to the row where this feature ws required. This cursor” commands, all the commands of this type wil be allows the user to enter and exit graphics mode on character executed immediately or will be delayed depending on when row boundaries the command is invoked. It invoked during the ective screen To perform split screen operations while in graphics mode time, the command is executed at the next horizontal blank use SSR2 only. ing interval. If invoked during @ vertical retrace interval or a DADDO/LG 1s asserted during the trailing edge of BLANK “display off” state, the command is executed immediately for each scan line while this mode 1s active The “increment cursor” command is executed immedi ately after it is issued and requires approximately three CCLK DISABLE GRAPHICS periods for completion The “write from cursor to pointer” Normal addressing resumes at the next row boundary command executes during blanking intervals. The AVOC will execute a many writes as possible during each blanking DISPLAY OFF interval. If the command is not completed during the current Asserts the BLANK output. The DADDO thraugh DADD13 blanking interval, the command will be held in suspension display address bus outputs can be optionally placed in the during the next active portion of the screen and continues three-state condition by setting bit 2 to @ one when invoking during the next blanking interval until the command. is the command. completed ORDERING INFORMATION !Vc¢=5 V+5%. Ta=0°C to 70°C) [_Packege Type | Frequency | Order Number | Plast 27 MAE ‘MIC2674B3P nee e MOTOROLA MICROPROCESSOR DATA 3459

3 p7 hs 26] oaoeseL MOTOROLA MICROPROCESSOR DATA 3-60