MC12XS6D2 NXP | Alldatasheet

Document overview

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Technical content

Features

  • Dual and triple high-side switches wit h high transient current capability
  • 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control including PWM duty-cycles, output ON and OFF openload detections, thermal shutdown and prewarning, and fault reporting
  • Output current monitoring with programmable synchronization signal and battery voltage feedback
  • Limp Home mode
  • External smart power switch control
  • Operating voltage is 7.0 V to 18 V with sleep current < 5.0 µA, extended mode from 6.0 V to 28 V
  • - 1 6 V reverse polarity and ground disconnect protections
  • Compatible PCB foot print and SPI software driver among the family

Figure 1. Triple 25 mΩ simplified application diagram

Applications

  • Low-voltage automotive lighting
  • Halogen lamps
  • Incandescent bulbs
  • Light-emitting diodes (LEDs)
  • HID Xenon ballasts EK SUFFIX (PB-FREE) 98ASA00368D 32-PIN SOICW-EP BEK SUFFIX (PB-FREE) 98ASA00894D 32-PIN SOICW-EP IN4 VCC SI CSB SO RSTB CLK CSNS LIMP IN1 IN2 IN3 VBAT CP OUT1 OUT2 OUT3 OUT6GND OUTVBAT GNDCSNS Smart Power 25XS6300 VCC SO CSB SCLK SI RSTB CLK A/D1 TRG1 A/D2 PORT PORT PORT PORT PORT GND SCLK SYNCB Main MCU VCCVBAT GND 5.0 V Regulator VBAT VBAT IN

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1 Orderable parts

Table 1. Orderable part variations

  1. To order parts in tape and reel, add the R2 suffix to the part number.

Table 2. Variation table (EK and BEK versions)

  • 10 mΩ power channel at TJ = -40 °C
  • 25 mΩ power channel at TJ = -40 °C 150 350 160 150 350 160 mA IOLOFF Openload current threshold in OFF state A RPULLUP Logic input pull-up resistor for CSB 20 – 100 20 – 130 k Ω ROUT6 DW OUT6 pull-down resistor 5 10 20 5 10 30 k Ω

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2 Internal block diagram

Figure 2. Simplified internal block diagram

3 Pin connections

3.1 Pinout diagram

Figure 3. 12XS6 pinout diagram

3.2 Pin definitions

Table 3. 12XS6 pin definitions supply Charge Pump This pin is the connection for an external capacitor for charge pump use only. place the device in a low-current sleep mode. This pin has a passive internal pull-down.

3 CSB SPI Chip Select

This input pin is connected to a chip select output of a master microcontroller (MCU). a high level. This pin has a passive internal pull-up to VCC through a diode. communication. This pin has a passive internal pull-down. sampled on the positive edge of the SCLK. This pin has a passive internal pull-down. Supply MCU Power Supply This pin is a power supply pin is for internal logic, the SPI I/Os, and the OUT6 driver.

7 SO SPI Serial Output

of SCLK. When CSB is high, this pin is high-impedance.

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OUT2 Output Channel #2 25XS6300: Protected high-side power output pins to the load. connect these pins to ground. OUT4 Output Channel #4 10XS6200 and 10XS6325: Protected high-side power output pins to the load. 15, 16, 17, 18 NC N/A Not Connected Pins are not connected. It is recommended to connect these pins to ground. 19, 20, 21 OUT3 Output Channel #3 Protected hi gh-side power output pins to the load. NC N/A Not Connected 10XS6200: Pins are not connected. It is recommended to connect these pins to ground.

25 CSNS Feedback Current Sense

externally to generate a ground referenced voltage for the microcontroller (MCU). Current recopy and analog voltage feedbacks are SPI programmable.

26 CSNS

inputs is SPI programmable.This pin has a passive internal pull-down. inputs is SPI programmable.This pin has a passive internal pull-down.

29 IN3 Input Direct Input #3

inputs is SPI programmable.This pin has a passive internal pull-down. inputs is SPI programmable.This pin has a passive internal pull-down.

32 CLK Input/Output

operating mode. This pin has a passive internal pull-down.

33 VBAT Power

operational power for the device. Table 3. 12XS6 pin definitions (continued)

4 General product characteristics

4.1 Relationship between ratings and operating requirements

case of a VCC disconnect, charge pump, gate drive,...) is derived from the VBAT pin.

  • the internal supply rail is protected (max. -16 V)
  • the output drivers are switched on, to reduce the power consumption in the drivers when using incandescent bulbs

Figure 4. Ratings vs. operating requirements (VBAT pin) externally in case of a reverse polarity, and in case of a high-voltage disturbance. Figure 5. Ratings vs. operating requirements (VCC pin)

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4.2 Maximum ratings

Table 4. Maximum ratings

  • IN1:IN4 and LIMP
  • CLK, SI, SCLK, CSB, and RSTB -0.3 -0.3 V (2) VOUT Digital output voltage
  • SO, CSNS, SYNC, OUT6, CLK -0.3 20 V (2) ICL Negative digital input clamp current – 5.0 mA (3) IOUT Power channel current
  • 1 0 mΩ channel
  • 2 5 mΩ channel 4.5 A (4) ECL Power channel clamp energy capability
  • 1 0 mΩ channel - Initial TJ = 25 °C
  • 1 0 mΩ channel - Initial TJ = 150 °C
  • 2 5 mΩ channel - Initial TJ = 25 °C
  • 2 5 mΩ channel - Initial TJ = 150 °C 120 mJ (5) VESD ESD voltage
  • Human Body Model (HBM) - VBAT, Power Channel, and GND pins
  • Human Body Model (HBM) - all other pins
  • Charge Device Model (CDM) - corner pins
  • Charge Device Model (CDM) - all other pins -8000 -2000 -750 -500 +8000 +2000 +750 +500 V (6) Notes 2. Exceeding voltage limits on those pins may ca use a malfunction or permanent damage to the device. 3. Maximum current in negative clamping for IN1:IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins. 4. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 5. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 Ω, VBAT = 14 V). See Output clamps. 6. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model.

4.3 Thermal characteristics

4.4 Operating conditions

This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted. Table 5. Thermal ratings

  • A m b i e n t
  • Junction -40 -40 +125 +150 TSTG Storage temperature -55 +150 °C TPPRT Peak Package Reflow Temperature During Reflow – 260 °C (7) (8) Thermal resistance and package dissipation ratings RΘJB Junction-to-Board – 8.0 °C/W (9) RΘJA Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) – 22 °C/W (10) (11) RΘJC Junction-to-Case (Case top surface) – 22 °C/W (12) Notes 7. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes), enter the core ID to view all orderable parts, and review parametrics. 9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 10. Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 11. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

Table 6. Operating conditions

  • Jump Start
  • Load dump V Reverse battery -16 – V VCC Functional operating supply voltage - Device is fully functional. All features are operating. 4.5 5.5 V

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4.5 Supply currents

This section describes the current consumption characteristics of the device. Table 7. Supply currents noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • T A = 25 °C
  • T A = 125 °C 1.2 5.0 µA (13) (14) IVBAT Operating mode measured at VPWR = 18 V – 7.0 8.0 mA (14) VCC current consumptions IQVCC Sleep mode measured at VCC = 5.5 V – 0.05 5.0 µA IVCC Operating mode measured at VPWR = 5.5 V (SPI frequency 5.0 MHz) – 2.8 4.0 mA Notes 13. With the Outputs power channels grounded. 14. With the Outputs power channels opened.

5 General IC functional description and application

5.1 Introduction

The 12XS6 is the latest SMARTMOS achievement in automotive drivers for all types of centralized automotive lighting applications. It is an evolution of the successful Gen3 by providing improved features of a complete family of devices using NXP's latest and unique technologies for the controller and the power stages. It consists of a scalable family of devices compatible in terms of software driver and package footprint. It allows diagnosing the light- emitting diodes (LEDs) with an enhanced current sense precision with synchronization pin. It combines flexibility through daisy chainable SPI 5.0 MHz, extended digital and analog feedbacks, safety, and robustness. It integrates an enhanced PWM module with 8-bit duty cycle capability and PWM frequency prescaler per power channel.

5.2 Features

The main attributes of 12XS6 are:

  • Dual, Triple, Quad or Penta high-side switches with overload, overtemperature, and undervoltage protection
  • Control output for one external smart power switch
  • 16-Bit SPI communication interface with daisy chain capability
  • Dedicated control inputs for use in Fail mode
  • Analog feedback pin with SPI programmable multiplexer and sync signal
  • Channel diagnosis by SPI communication
  • Advanced current sense mode for LED usage
  • Synchronous PWM module with external clo ck, prescaler, and multiphase feature
  • Excellent EMC behavior
  • Power net and reverse polarity protection
  • Ultra low-power mode
  • Scalable and flexible family concept
  • Board layout compatible SOIC54 and SOIC32 package with exposed pad

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5.3 Block diagram

Power control die lead to an optimized solution. Figure 6. Functional block diagram

5.3.1 Self-protected high-side switches

diagnostic functions are available.

5.3.2 Power supply

guarantees a low quiescent current in Sleep mode.

5.3.3 MCU interface and device control

overcurrent, overtemperature, clock-fail, and under and overvoltage. The device allows driving loads at different frequencies up to 400 Hz.

5.4 Functional description

  • In Normal mode by SPI interface. A second supply voltage (VCC) is required for bidirectional SPI communication
  • In Fail mode by the corresponding the direct inputs IN1:IN4. OUT6 is off in this mode Power Supply 12XS6 - Functional Block Diagram Parallel Control Inputs MCU Interface and Device Control SPI Interface Self-protected Supply MCU Interface and Output Cont rol Self-protected High-side Switches PWM Controller High-side Switches OUT[x] MCU Interface

5.5 Modes of operation

  • wake = (IN1_ON) OR (IN2_ON) OR (IN3_ON) OR (IN4_ON) OR (RSTB). More details in Logic I/O plausibility check section
  • fail = (SPI_fail) OR (LIMP). More details in Loss of communication interface section The following chapters provide information for OUT1:OUT4. Depending on the device part number, do not consider Non Connected outputs.

Figure 7. General IC operating modes

5.5.1 Power off mode

functionality is available but the device is protected by the clamping circuits. Refer to Supply voltages disconnection section.

5.5.2 Sleep mode

  • the component is inactive and all outputs are disabled
  • the outputs are protected by the clamping circuits
  • the pull-up/pull-down resistors are present The Sleep mode is the default mode of the device after applying the supply voltages (VBAT or VCC) prior to any wake-up condition (wake = [0]). The wake-up from Sleep mode is provided by the wake signal. wake = [0] wake = [0] wake = [1] fail = [1] fail = [0] and valid watchdog toggleFail Normal Sleep Power off (VBAT < VBATPOR) and (VCC < VCCPOR) (VBAT > VBATPOR) or (VCC > VCCPOR) (VBAT < VBATPOR) and (VCC < VCCPOR) (VBAT < VBATPOR) and (VCC < VCCPOR)

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5.5.3 Normal mode

The Normal mode is the regular operating mode of the device. The device is in Normal mode, when the device is in the wake state (wake = [1]) and no fail condition (fail = [0]) is detected. During Normal mode:

  • the power outputs are under control of the SPI
  • the power outputs are controlled by the programmable PWM module
  • the power outputs are protected by the overload protection circuit
  • the control of the power outputs by SPI programming
  • the digital diagnostic feature transfers status of the smart switch via the SPI
  • the analog feedback output (CSNS and CSNS SYNC) can be controlled by the SPI The channel control (CHx) can be summarized:
  • CH1:4 controlled by ONx or iINx (if it is programmed by the SPI)
  • CH6 controlled by ONx
  • Rising CHx by definition means starting overcurrent window for OUT1:4

5.5.4 Fail mode

The device enters the Fail mode, when:

  • the LIMP input pin is high (logic [1])
  • or the SPI failure is detected During Fail mode (wake = [1] and fail = [1]):
  • the OUT1:OUT4 outputs are directly controlled by the corresponding control inputs (IN1:IN4)
  • the OUT6 is turned off
  • the PWM module is not available
  • while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition):
  • the SO shall report the content of SO register defined by SOA0 to 3 bits
  • the outputs are fully protected in case of an overload, overtemperature, and undervoltage
  • no analog feedback is available
  • the max. output overcurrent profile is activated (OCLO and window times)
  • in case of an overload condition or undervoltage, the autorestart feature controls the OUT1:OUT4 outputs
  • in case of an overtemperature condition, OCHI1 detection, or severe short-circuit detection, the corresponding output is latched OFF until a new wake-up event. The channel control (CHx) can be summarized:
  • CH1: 4 controlled by iINx, while the over current windows are controlled by IN_ONx
  • CH6 is off

5.5.5 Mode transitions

After a wake-up:

  • a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])
  • the faults are blanked during t BLANKING The device enters in Normal mode after start-up if following sequence is provided:
  • V BAT and VCC power supplies must be above their undervoltage thresholds (Sleep mode)
  • generate wake-up event (wake =1) setting RSTB from 0 to 1 The device initialization is completed after 50 µsec (typ). During this time, the device is robust in case of VBAT interrupts higher than 150 nsec. The transition from “Normal mode” to “Fail mode” is executed immediately when a fail condition is detected. During the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared. When the Fail mode condition was a:
  • LIMP input, WD toggle timeout, WD toggle sequence, or the SPI modulo 16 error, the SPI diagnosis is available during Fail mode
  • SI/SO stuck to static level, the SPI di agnosis is not available during Fail mode

The transition from “Fail mode” to “Normal mode” is enabled, when:

  • the fail condition is removed and
  • two SPI commands are sent within a valid wa tchdog cycle (first WD=[0] and then WD=[1]) During this transition:
  • all SPI SI and SO registers are cleared (logic[0])
  • the DSF (device status flag) in the registers #1:#7 and the RCF (Register Clearer flag) in the device status register #1 are set (logic[1]) To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.

5.6 SPI interface and configurations

5.6.1 Introduction

The SPI is used to:

  • control the device in case of Normal mode
  • provide diagnostics in case of Normal and Fail mode The SPI is a 16 Bit full-duplex synchronous data transfer interface with daisy chain capability. The interface consists of four I/O lines with 5.0 V CMOS logic levels and termination resistors:
  • The SCLK pin clocks the internal shift registers of the device
  • The SI pin accepts data into the input shift register on the rising edge of the SCLK signal
  • The SO pin changes its state on the rising e dge of SCLK and reads out on the falling edge
  • The CSB enables the SPI interface
  • with the leading edge of CSB the registers are loaded
  • while CSB is logic [0] SI/SO data are shifted
  • with the trailing edge of the CSB signal, SPI data is latched into the internal registers
  • when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance When the RSTB input is:
  • low (logic [0]), the SPI and the fault registers are reset. The Wake state then depends on the status of the input pins (IN_ON1:IN_ON4)
  • high (logic[1]), the device is in Wake status and the SPI is enabled The functionality of the SPI is checked by a plausibility check. In case of the SPI failure the device enters the Fail mode.

5.6.2 SPI input register and bit descriptions

The first nibble of the 16-bit data word (D15:D12) serves as address bits. 11 bits (D10:D1) are used as data bits. The D11 bit is the WD toggle bit. This bit has to be toggled with each write command. When the toggling of the bit is not executed within the WD timeout, the SPI fail is detected. All register values are logic [0] after a reset. The predefined value is off/inactive unless otherwise noted. Register SI address SI data # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 name 8 4 Bit address WD 11 Bit address

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# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Initialization 1 0 0000 W D W D S E L SYNC EN1 SYNC EN0 MUX2 MUX1 MUX0 SOA MODE SOA3 SOA2 SOA1 SOA0 initialization 2 1 0001 W D OCHI THERM AL OCHI TRANSI ENT NO HID1 NO HID0 X OCHI OD4 OCHI OD3 OCHI OD2 OCHI OD1 PWM sync OTW SEL CH1 control 2 0 0 1 0 WD PH11 PH01 ON1 PWM71 PWM61 PWM51 PWM41 PWM31 PWM21 PWM11 PWM01 CH2 control 3 0 0 1 1 WD PH12 PH02 ON2 PWM72 PWM62 PWM52 PWM42 PWM32 PWM22 PWM12 PWM02 CH3 control 4 0 1 0 0 WD PH13 PH03 ON3 PWM73 PWM63 PWM53 PWM43 PWM33 PWM23 PWM13 PWM03 CH4 control 5 0 1 0 1 WD PH14 PH04 ON4 PWM74 PWM64 PWM54 PWM44 PWM34 PWM24 PWM14 PWM04 CH6 control 7 0 1 1 1 WD PH16 PH06 ON6 PWM76 PWM66 PWM56 PWM46 PWM36 PWM26 PWM16 PWM06 output control 8 1 0 0 0 WD X PSF4 PSF3 PSF2 PSF1 ON6 X ON4 ON3 ON2 ON1 Global PWM control 9-1 1001 W D 0XXXX GPWM EN6 X GPWM EN4 GPWM EN3 GPWM EN2 GPWM EN1 9-2 1 0 0 1 WD 1 X X GPWM7 GPWM6 GPWM5 GPWM4 GPWM3 GPWM2 GPWM1 GPWM0 overcurrent control 10-1 1 0 1 0 WD 0 X OCLO4 OCLO3 OCLO2 OCLO1 X ACM EN4 ACM EN3 ACM EN2 ACM EN1 10-2 1010 W D 1X NO OCHI4 NO OCHI3 NO OCHI2 NO OCHI1 X SHORT OCHI4 SHORT OCHI3 SHORT OCHI2 SHORT OCHI1 input enable 11 1 0 1 1 WD 0 X X INEN14 INEN04 INEN13 INEN03 INEN12 INEN02 INEN11 INEN01 prescaler settings 12-1 1 1 0 0 WD 0 X X PRS14 PRS04 PRS13 PRS03 PRS12 PRS02 PRS11 PRS01 12-2 1100 W D 1XXXXXXXX P R S 1 6 P R S 0 6 OL control 13-1 1101 W D 0X OLON DGL4 OLON DGL3 OLON DGL2 OLON DGL1 X OLOFF EN4 OLOFF EN3 OLOFF EN2 OLOFF EN1 OLLED control 13-2 1101 W D 1 r e s r e s r e s r e s OLLED TRIG X OLLED EN4 OLLED EN3 OLLED EN2 OLLED EN1 increment / decrement 14 1110 W D INCR SGN X X INCR14 INCR04 INCR13 INCR03 INCR12 INCR02 INCR11 INCR01 testmode 15 1111XXXXXXXXXXXX

WD #0~#14 = watchdog toggle bit #0 MUX2 MUX1 MUX0 CSNS SOA0 ~ SOA3 #0 = address of next SO data word 0 0 0 off SOA MODE #0 = single read address of next SO data word 0 0 1 OUT1 current MUX0 ~ MUX2 #0 = CSNS multiplexer setting 0 1 0 OUT2 current SYNC EN0~ SYNC EN1 #0 = SYNC delay setting 0 1 1 OUT3 current WD SEL #0 = watchdog timeout select 1 0 0 OUT4 current OTW SEL #1 = over temperature warning threshold selection 1 0 1 unused PWM SYNC #1 = reset clock module 1 1 0 VBAT monitor OCHI ODx #1 = OCHI window on load demand 1 1 1 control die temp.monitor NO HIDx #1 = HID outputs selection #0 SYNC SYNC Sync status OCHI THERMAL #1 = OCHI1 level depending on control die temperature EN1 EN0 OCHI TRANSIENT #1 = OCHIx levels adjusted during OFF-to-ON transition 0 0 sync off PWM0x ~ PWM7x #2~#7 = PWM value (8Bit) 0 1 valid PH0x ~ PH1x #2~#7 = phase control 10 t r i g 0 ONx #2~#8 = channel on/off incl. OCHI control 1 1 trig1/2 PSFx #8 = pulse skipping feature for power output channels GPWM ENx #9-1 = global PWM enable #2~#7 PH 1x PH 0x Phase GPWM1 ~ GPWM7 #9-2 = global PWM value (8Bit) 0 0 0° ACM ENx #10-1 = advanced current sense mode enable 0 1 90° OCLOx #10-1 = OCLO level control 1 0 180° SHORT OCHIx #10-2 = use short OCHI window time 1 1 270° NO OCHIx #10-2 = start with OCLO threshold #11 ONx INEN1x INEN0x GPWM INx=0 INx=1 INEN0x ~ INEN1x #11 = input enable control ENx OUTx PWMx OUTx PWMx PRS0x ~ PRS1x #12 = pre scaler setting 0 x x x OFF x OFF x OLOFF ENx #13-1 = OL load in off state enable 1 0 0 0 ON individual ON individual OLON DGLx #13-1 = OL ON deglitch time 1 ON global ON global OLLED ENx #13-2 = OL LED mode enable 0 1 0 OFF individual ON individual OLLED TRIG #13-2 = trigger for OLLED detection in 100% d.c. 1 OFF global ON global INCR SGN #14 = PWM increment / decrement sign 1 0 0 OFF individual ON individual INCR0x ~ INCR1x #14 = PWM increment / decrement setting 1 OFF global ON global 1 1 0 ON individual ON global

1 ON global ON individual

#12 PRS 1x PRS 0x PRS divider #1 NO HID1 NO HID0 HID Selection 0 0 /4 25Hz .... 100Hz 0 0 available for all channels 0 1 /2 50Hz .... 200Hz 0 1 available for channel 3 only 1 x /1 100Hz .... 400Hz 1 0 available for channels 3 and 4 only #14 INCR SGN increment/decrement 1 1 unavailable for all channels 0 decrement 1 increment #14 INCR 1x INCR 0x increment/decrement 0 0 no increment/decrement 01 4 L S B 10 8 L S B 11 1 6 L S B

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5.6.3 SPI output registe r and bit descriptions

The first nibble of the 16 Bit data word (D12:D15) serves as address bits. All register values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off/inactive unless otherwise noted. Register SO address SO data # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 not used 0 0 0 0 0 X X X X X X X X X X X X quick status 1 0 0 0 1 FM DSF OVLF OLF CPF RCF CLKF X QSF4 QSF3 QSF2 QSF1 CH1 status 2 0 0 1 0 FM DSF OVLF OLF res OTS1 OTW1 OC21 OC11 OC01 OLON1 OLOFF1 CH2 status 3 0 0 1 1 FM DSF OVLF OLF res OTS2 OTW2 OC22 OC12 OC02 OLON2 OLOFF2 CH3 status 4 0 1 0 0 FM DSF OVLF OLF res OTS3 OTW3 OC23 OC13 OC03 OLON3 OLOFF3 CH4 status 5 0 1 0 1 FM DSF OVLF OLF res OTS4 OTW4 OC24 OC14 OC04 OLON4 OLOFF4 device status 7 0 1 1 1 FM DSF OVLF OLF res res res TMF OVF UVF SPIF iLIMP I/O status 8 1 0 0 0 FM res TOGGL E iIN4 iIN3 iIN2 iIN1 X OUT4 OUT3 OUT2 OUT1 device ID 9 1 0 0 1 FM res res res DEVID DEVID DEVID DEVID DEVID DEVID DEVID DEVID not used 10-14 address from 1010 to 1110 X X X X X X X X X X X X testmode 15 1 1 1 1 X X X X X X X X X X X X QSFx #1 = quick status (OC or OTW or OTS or OLON or OLOFF) #2~#6 OC2x OC1x OC0x over current status CLKF #1 = PWM clock fail flag 0 0 0 no overcurrent RCF #1 = registers clear flag 0 0 1 OCHI1 CPF #1 = charge pump flag 0 1 0 OCHI2 OLF #1~#7 = open load flag (wired or of all OL signals) 0 1 1 OCHI3 OVLF #1~#7 = over load flag (wired or of all OC and OTS signals) 1 0 0 OCLO DSF #1~#7 = device status flag (RCF or UVF or OVF or CPF or CLKF or TMF) 1 0 1 OCHIOD FM #1~#8 = fail mode flag 110 S S C OLOFFx #2~#6 = open load in off state status bit 1 1 1 not used OLONx #2~#6 = open load in on state status bit #9 DEVID2 DEVID1 DEVID0 device type OTWx #2~#6 = over temperature warning bit 0 0 0 Penta3/2 OTSx #2~#6 = over temperature shutdown bit 0 0 1 Penta0/5 iLIMP #7 = limp input pin status 0 1 0 Quad2/2 SPIF #7 = SPI fail flag = under voltage flag 0 1 1 Quad0/4 UVF #7 100 T r i p l e 1 / 2 OVF #7 = over voltage flag 1 0 1 Triple0/3 TMF #7 = testmode activation flag 1 1 0 res OUTx #8 = status of VBAT/2 comparator (reported in real time) 1 1 1 res iINx #8 = status of iINx signal (reported in real time) TOGGLE #8 = status of INx_ON signals (IN1_ON or IN2_ON or IN3_ON or IN4_ON) DEVID0 ~ DEVID2 #9 = device type DEVID3 ~ DEVID4 #9 = device family DEVID5 ~ DEVID7 #9 = design status (incremented number)

5.6.4 Timing diagrams

Figure 8. Timing requirements during SPI communication Figure 9. Timing diagram for serial output (SO) data communication

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5.6.5 Electrical Characterization

Table 8. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  1. Parameter is derived from simulations.

6 Functional block requirements and behaviors

6.1 Self-protected high-side swit ches description and application

6.1.1 Features

Up to four power outputs are foreseen to drive automotive light applications. The outputs are optimized for driving automotive bulbs, but also HID ballasts, LEDs, and other primarily resistive loads. The smart switches are controlled by use of high sophisticated gate drivers. The gate drivers provide:

  • output pulse shaping
  • output protections
  • active clamps
  • output diagnostics

6.1.2 Output pulse shaping

The outputs are controlled with a closed loop active pulse shaping to provide the best compromise between:

  • low switching losses
  • low EMC emission performance
  • minimum propagation delay time Depending on the programming of the prescaler setting register #12-1, #12-2, the switching speeds of the outputs are adjusted to the output frequency range of each channel. The edge shaping shall be designed according the following table: The edge shaping provides full symmetry for rising and falling transition:
  • the slopes for the rising and falling edge are matched to provide the best EMC emission performance
  • the shaping of the upper edges and the lower edges are matched to provide the best EMC emission performance
  • the propagation delay time for the rising edge and the falling edge is matched to provide true duty cycle control of the output duty cycle error, < 1 LSB at max. frequency
  • a digital regulation loop is used to minimi ze the duty cycle error of the output signal Divider factor duty cycle 4 25 100 10 40 03 FB 4 252 156 2 50 200 5 20 07 F7 8 248 156 1 100 400 2.5 10 07 F7 8 248 78

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Figure 10. Typical power output switching (slow and fast slew rate)

6.1.2.1 SPI control and configuration

frequency), the output duty cycle is 100%.

  • PH0x:PH1x: phase assignment of the output channel x
  • ONx: on/off control including overcurrent window control of the output channel x
  • PWM0x:PWM7x: 8-bit PWM value individually for each output channel x The ONx bits are duplicated in the output control register #8 to control the outputs with either the CHx control register or the output control register. The PRS1x:PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2. The following changes of the duty cycle are performed asynchronous (with pos. edge of CSB signal):
  • turn on with 100% duty cycle (CHx = ON)
  • change of duty cycl e value to 100%
  • turn off (CHx = OFF)
  • phase setting (PH0x:PH1x)
  • prescaler setting (PRS1x:PRS0x) A change in phase setting or prescaler setting during CHx = ON may cause an unwanted long ON-time. Therefore it is recommended to turn off the output(s) before execution of this change. The following changes of the duty cycle are performed synchronous (with the next PWM cycle):
  • turn on with less than 100% duty cycle (OUTx = ONx)
  • change of duty cycle value to less than 100% A change of the duty cycle value can be achieved by a change of the:
  • PWM0x:PWM7x bits in individual channel control register #2:#7
  • GPWM EN1: GPWM EN6 bits (change between individual PWM and global PWM settings) in global PWM control register #9-1
  • incremental/decremental register #14 The synchronization of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2 register #1. Register SI address SI data # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CHx control 2-7 channel address WD PH1x PH0x Onx PWM7 x PWM6 x PWM5 x PWM4 x PWM3 x PWM2 x PWM1 x PWM0 x
  • initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module are reset with the positive edge of the CSB, i.e. the phase synchronization is performed immediately within one SPI frame. It could help to synchronize different 12XS6 devices in the board
  • when the bit D1 is logic[0], no action is executed The switching frequency can be adjusted for the corresponding channel as described in the following table: No PWM feature is provided in case of:
  • Fail mode
  • clock input signal failure

6.1.2.2 Global PWM control

In addition to the individual PWM register, each channel can be assigned independently to a global PWM register.

  • low (logic[0]), the output is assigned to individual PWM (default status)
  • high (logic[1]), the output is assigned to global PWM The PWM value of the global PWM channel is controlled by the global PWM control register #9-2. When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the corresponding output channel setting.

6.1.2.3 Incremental PWM control

To reduce the control overhead during soft start/stop of bulbs (e.g. theatre dimming), an incremental PWM control feature is implemented.

  • the global PWM channel
  • the external channel OUT6 The control is according the increment/decrement register #14:
  • INCR SGN: sign of incremental dimming (valid for all channels)
  • INCR 1x, INCR 0x increment/decrement CLK freq. (kHz) Prescaler setting Divider factor PWM freq. (Hz) Slew rate PWM resolution) min. max. PRS1x PRS0x min. max. (bit) (steps) 25.6 102.4 0 0 4 25 100 slow 8 2560 1 2 50 200 slow

1 X 1 100 400 fast

Table 9. Global PWM register

0 ON individual ON individual

1 ON global ON global

0 ON individual ON global

24 NXP Semiconductors

This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.

6.1.2.4 Pulse skipping

Due to the output pulse shaping feature and the resulting switching delay time of the smart switches, duty cycles close to 0% resp. 100% can not be generated by the device. Therefore the pulse skipping feature (PSF) is integrated to interpolate this output duty cycle range in Normal mode. The pulse skipping provides a fixed duty cycle pattern with eight states to interpolate the duty cycle values between F7 (Hex) and FF (Hex). The range between 00 (Hex) and 07 (Hex) is not considered to be provided. The pulse skipping feature:

  • is available individually for the power output channels (OUT1:OUT4)
  • is not available for the external channel (OUT6) The feature is enabled with the PSF bits in the output control register #8. When the corresponding PSF bit is:
  • low (logic[0]), the pulse skipping feature is disabled on this channel (default status)
  • high (logic[1]), the pulse skipping feature is enabled on this channel INCR SGN increment/decrement 0d e c r e m e n t 1 increment INCR 1x INCR 0x inc rement/decrement 0 0 no in crement/ decr em ent 014 0 8 1 1 16 hex dec [%] S0 S1 S2 S3 S4 S5 S6 S7 FF 256 100,00% FF FF FF FF FF FF FF FF FE 255 99,61% F7 FF FF FF FF FF FF FF FD 254 99,22% F7 FF FF FF F7 FF FF FF FC 253 98,83% F7 FF F7 FF F7 FF FF FF FB 252 98,44% F7 FF F7 FF F7 FF F7 FF FA 251 98,05% F7 F7 F7 FF F7 FF F7 FF F9 250 97,66% F7 F7 F7 FF F7 F7 F7 FF F8 249 97,27% F7 F7 F7 F7 F7 F7 F7 FF F7 248 96,88% F6 247 96,48% F5 246 96,09% .. . .. . 03 4 1,56% 02 3 1,17% 01 2 0,78% 00 1 0,39% PWM duty cycle pulse skipping frame

6.1.2.5 Input control

  • wake-up the device
  • fully control the corresponding output in case of Fail mode
  • control the corresponding output in case of Normal mode The control during Normal mode is according the INEN0x and INEN1x bits in the input enable register #11. See Table 9. An input deglitcher is provided at each control input to avoid high frequency control of the outputs. The internal signal is called iINx. The channel control (CHx) can be summarized:
  • Normal mode:
  • CH1: 4 controlled by ONx or INx (if it is programmed by the SPI)
  • CH6 controlled by ONx
  • Rising CHx by definition means starting overcurrent window for OUT1:4
  • Fail mode:
  • CH1: 4 controlled by iINx, while the over current windows are controlled by IN_ONx
  • CH6 are off The input thresholds are logic level compatible, so the input structure of the pins are able to withstand battery voltage level (max.40 V) The inputs have an integrated pull-down resistor.

6.1.2.6 Electrical characterization

Table 10. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • T J = 25 °CV
  • T J = 150 °C
  • T J = 25 °C, VBAT = -12 V
  • T J = 150 °C, VBAT = -12 V 9.0 17.5 m Ω RDS(on) ON-Resistance, Drain-to-Source for 25 mΩ power channel
  • T J = 25 °C
  • T J = 150 °C
  • T J = 25 °C, VBAT = -12 V
  • T J = 150 °C, VBAT = -12 V m Ω ILEAK SLEEP Sleep mode output leakage current (output shorted to GND) per channel
  • T J = 25 °C, VBAT = 12 V
  • T J = 125 °C, VBAT = 12 V
  • T J = 25 °C, VBAT = 35 V
  • T J = 125 °C, VBAT = 35 V 0.5 5.0 5.0 µA IOUT OFF Operational output leakage current in OFF-State per channel
  • T J = 25 °C, VBAT = 18 V
  • T J = 125 °C, VBAT = 18 V µA δPWM Output PWM duty cycle range (measured at VOUT = VBAT/2)
  • Low frequency range (25 to 100 Hz)
  • Medium frequency range (50 to 200 Hz)
  • High frequency range (100 to 400 Hz) 4.0 8.0 8.0 252 248 248 LSB

26 NXP Semiconductors

6.1.3 Output protections

  • overload conditions
  • harness short-circuit
  • overcurrent protection against ultra-low resistive short-circuit conditions thanks to smart overcurrent profile and severe short- circuit protection
  • overtemperature protection including overtemperature warning
  • under and overvoltage protections
  • charge pump monitoring
  • reverse battery protection In case a fault condition is detected, the corresponding output is commanded off immediately after the deglitch time tFAULT SD. The turn off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature (fast turn off). The FTO:
  • does not use edge shaping
  • is provided with high slew rate to minimize the output turn-off time tOUTPUT SD, in regards to the detected fault
  • uses a latch which keeps the FTO active during an undervoltage condition (0 < VBAT < VBAT UVF) SR Rising and falling edges slew-rate at VBAT = 14 V (measured from VOUT = 2.5 V to VBAT - 2.5 V)
  • Low frequency range
  • Medium frequency range
  • High frequency range 0.3 0.3 0.65 0.55 0.55 1.15 0.8 0.8 1.65 V/µs (16) ΔSR Rising and falling edges slew rate matching at V BAT = 14 V (SRr/SRf) 0.8 1.0 1.1 (16) tDLY Turn-on and Turn-off delay times at VBAT = 14 V
  • Low frequency range
  • Medium frequency range
  • High frequency range 100 100 µs (16) ΔtDLY Turn-on and Turn-off delay times matching at VBAT = 14 V
  • Low frequency range
  • Medium frequency range
  • High frequency range -20 -20 -10 0.0 0.0 0.0 µs (16) tOUTPUT SD Shutdown delay time in case of fault 0.5 2.5 4.5 µs Reference PWM clock fCLK Clock input frequency range 25.6 – 102.4 kHz Notes 16. With nominal resistive load: 2.5 Ω and 5.0 Ω respectively for 10 mΩ and 25 mΩ channel.

Table 10. Electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Figure 11. Power output switching in nominal operation and in case of fault

  • the status is reported in the qui ck status register #1 and the corresponding channel status register #2:#5. To restart the output:
  • the channel must be restarted by writing the corresponding ON bit in the channel control register #2:#5 or output control register #8

28 NXP Semiconductors

Figure 12. Output control diagram in normal mode

30 NXP Semiconductors

6.1.3.1 Overcurrent protections

Each output channel is protected against overload conditions by use of a multilevel overcurrent shutdown. Figure 15. Transient overcurrent profile The current thresholds and the threshold window times are fixed for each type of power channel.

  • the clock for the t OCHI counter is activated when the output = [1] respectively CHx = 1
  • the clock for the t OCHI counter is stopped when the output = [0] respectively CHx = 0

Figure 16. Transient overcurrent profile in PWM mode

This strategy counts the OCHI time only when the bulb is actually heated up. The window counting is stopped in case of UV, CPF and OTS. of the over current window depends on the ON bits inside channel control registers #2:#7 or the output control register #8.

  • toggled (turn OFF and then ON), t he OCHI window counter is reset and the full OCHI windows are applied

Figure 17. Resetable overcurrent profile

  • rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI counter

Figure 18. Overcurrent level fixed to OCLO

6.1.3.1.1 Overcurrent control programming

A smart overcurrent window control strategy is implemented to turn on an HID ballast, even in the case of a long power on reset time. time counter is divided by eight, when no load current is demanded from the output driver.

32 NXP Semiconductors

  • the clock for the tOCHI2 counter is divided by eight when the open load signal is high (logic[1]), to accommodate the HID ballast while in power on reset mode
  • the clock for the tOCHI2 counter is connected directly to the window time counter when the open load signal is low (logic[0]), to accommodate the HID demanding load current from the output

Figure 19. HID ballast overcurrent profile of HID ballast. Nominal tOCHI2 duration is up to 64 ms (instead of 8.0 ms). following. The functionality is controlled by the NO_HID1 and NO_HID0 bits inside the initialization #2 register.

  • [0 0]: smart HID feature is available for a ll channels (default status and during Fail mode)
  • [0 1]: smart HID feature is available for channel 3 only
  • [1 0]: smart HID feature is available for channels 3 and 4 only
  • [1 1]: smart HID feature is not available for any channel OCHI on demand (OCHI OD) In some instances, a lamp might be de-powered when its supply is interrupted by the opening of a switch (as in a door), or by disconnecting the load (as in a trailer harness). In these cases, the driver should be tolerant of the inrush current occurring when the load is reconnected. The OCHI On Demand feature allows such control individually for each channel through the OCHI ODx bits inside the Initialization #2 register. When the OCHI ODx bit is:
  • low (logic[0]), the channel operates in its Normal, Default mode. After end of OCHI window timeout the output is protected with an OCLO threshold
  • high (logic[1], the channel operates in the OCHI On Demand mode and uses the OCHI2 and OCHI3 windows and times after an OCLO event To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register and then turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output. The fault detection status is reported in the quick status register #1 and the corresponding channel status registers #2:#6, as presented in Figure 20. time IOCHI1 IOCHI2 IOCHI3 IOCLO current tOCHI38 x tOCHI2 tOCHI1 Over Current Threshold Profile Channel Current

Figure 20. OCHI on demand profile variety of loads. Electrical values of this threshold are slightly different when the load is driven in PWM compared to static fully On mode.

  • low (logic[0]), the output is protecte d with the higher OCLO threshold (default status and during Fail mode)
  • high (logic[1]), the lower OCLO threshold is applied Short OCHI The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis and to reduce the potential stress inside the switch during an overload condition. The setting is controlled individually for each output by the SHORT OCHIx bits inside the overload control register #10-2. When the SHORT OCHIx bit is:
  • low (logic[0]), the default OCHI window times are applied (default status and during Fail mode)
  • high (logic[1]), the short OCHI window times are applied (50% of the regular OCHI window time) No OCHI The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis. The setting is controlled individually for each channel by the NO OCHIx bits inside the overcurrent control register #10-2. When the NO OCHIx bit is:
  • low (logic[0]), the regular OCHI window is applied (default status and during Fail mode)
  • high (logic[1]), the turn on of the ou tput is provided without OCHI windows The NO OCHI bit is applied in real time. The OCHI window is left immediately when the NO OCHI is high (logic[1]). The overcurrent threshold is set to OCLO when:
  • the NO OCHIx bit is set to logic [1] while CHx is ON or
  • CHx turns ON if NO OCHIx is already set Thermal OCHI To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHI1 level can be automatically adjusted in regards to the control die temperature. The functionality is controlled for all channels by the OCHI THERMAL bit inside the initialization 2. When the OCHI THERMAL bit is:
  • low (logic[0]), the output is protected with default OCHI1 level
  • high (logic[1]), the outp ut is protected with the OCHI1 level reduced by RTHERMAL OCHI = 15% (typ) when the control die temperature is above TTHERMAL OCHI = 63 °C (typ) timetOCHI3 current tOCHI2 IOCHI2 IOCHI3 IOCLO OCHI2 fault reported OCHI3 fault reported OCLO fault reported OCHI OD fault reported solid line: nominal operation dotted lines: fault conditions

34 NXP Semiconductors

  • low (logic[0]), the output is pr otected with default OCHIx levels
  • high (logic[1]), the output is protected with an OCHIx levels depending on the output voltage (VOUT):
  • OCHIx level reduced by RTRANSIENT OCHI = 50% typ for 0 < VOUT < VOUT DETECT (VBAT/2 typ),
  • Default OCHIx level for VOUT DETECT < VOUT If the resistive load is less than VBAT/IOCHI1, the overcurrent threshold is exceeded before output reaches VBAT/2, and the output current reaches IOCHI1. The output is then switched off at much lower and safer currents. When the load has significant series inductance, the output current transition falls behind voltage with LLOAD/RLOAD constant time. The intermediate overcurrent threshold could not reach and the output current continues to rise up to OCHIx levels.

6.1.3.1.2 Electrica l characterization

Table 11. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • High level
  • Low level 14.5 7.7 9.0 10.2 A IOCLO PWM Low overcurrent for 10 mΩ power channel in PWM mode
  • High level
  • Low level 10.9 3.5 9.0 10.2 A IOCLO ACM Low overcurrent for 10 mΩ power channel in ACM mode
  • High level
  • Low level 7.7 3.8 9.0 4.5 10.2 5.2 A IOCHI1 High overcurrent Level 1 for 25 mΩ power channel 31 38.5 46 A IOCHI2 High overcurrent Level 2 for 25 mΩ power channel 21 24.5 28 A IOCHI3 High overcurrent Level 3 for 25 mΩ power channel 13.2 15 17.5 A IOCLO Low overcurrent for 25 mΩ power Channel
  • High level
  • Low level 8.3 4.0 9.6 4.9 5.5 A IOCLO PWM Low overcurrent for 25 mΩ power channel in PWM mode
  • High level
  • Low level 8.3 3.0 9.6 4.9 5.5 A IOCLO ACM Low overcurrent for 25 mΩ power channel in ACM mode
  • High level
  • Low level 4.0 2.0 4.9 2.4 5.5 2.75 A RTRANSIENT OCHI High overcurrent ratio 1 0.45 0.5 0.55 RTHERMAL OCHI High overcurrent ratio 2 0.835 0.85 0.865 TTHERMAL OCHI Temperature threshold for IOCHI1 level adjustment 50 63 70 °C

6.1.3.2 Overtemperature protection

  • selectable overtemperature warning threshold (T OTW1, TOTW2), the output stays on and the event is reported in the SPI
  • overtemperature threshold (T OTS), the output is switched off immediately after the deglitch time tFAULT SD and the event is reported in the SPI after the deglitch time tFAULT SD

6.1.3.2.1 Overtemperature warning (OTW)

  • the output remains in current state
  • the status is reported in the qui ck status register #1 and the corresponding channel status register #2:#5 The OTW threshold can be selected by the OTW SEL bit inside the initialization 2 register #1. When the bit is:
  • low (logic[0]), the high overtemperatur e threshold is enabled (default status)
  • high (logic[1]), the low overtemperature threshold is enabled To delatch the OTW bit (OTWx):
  • the temperature has to drop below the corre sponding overtemperature warning threshold
  • a read command of the corresponding channel status register #2:#5 must be performed

6.1.3.2.2 Overtemperature shutdown (OTS)

  • the corresponding output is disabled immediately after the deglitch time t FAULT SD
  • the status is reported after t FAULT SD in the quick status register #1 and the corresponding channel status register #2:#5. To restart the output after an overtemperature shutdown event in Normal mode:
  • the overtemperature condition must be remo ved, and the channel must be restarted by a write command of the ON bit in the corresponding channel control register #2:#5, or in the output control register #8 tOCHI1 High overcurrent Time 1
  • Default value
  • SHORT OCHI option 1.5 0.75 2.0 1.0 2.5 1.25 ms tOCHI2 High overcurrent Time 2
  • Default value
  • SHORT OCHI option 6.0 3.0 8.0 4.0 5.0 ms Power outputs OUT1:OUT4 (continued) tOCHI3 High overcurrent Time 3
  • Default Value
  • SHORT OCHI option ms RSC MIN Minimum severe short-circuit detection
  • 1 0 mΩ power channel
  • 2 5 mΩ power channel 5.0 mΩ tFAULT SD Fault deglitch time
  • OCLO and OCHI OD
  • OCHI1:3 and SSC 1.0 1.0 2.0 2.0 3.0 3.0 µs (17) tAUTORESTART Fault autorestart time in Fail mode 48 64 80 ms tBLANKING Fault blanking time after wake-up – 50 100 µs Notes 17. Guaranteed by testmode.

Table 11. Electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

36 NXP Semiconductors

  • the overtemperature condition must be removed:
  • a read command of the corresponding channel status register #2:#5 must be performed To restart the output after an overtemperature shutdown event in Fail mode:
  • a mode transition is needed. See Mode transitions.

6.1.3.2.3 Electrica l characterization

6.1.3.3 Undervoltage and overvoltage protections

6.1.3.3.1 Undervoltage

  • in the device status flag (DSF) in the registers #1:#7
  • in the undervoltage flag (UVF) insi de the device status register #7 Normal mode The reactivation of the outputs is controlled by the microcontroller. To restart, the output the undervoltage condition must be removed and:
  • a write command of the ON Bit must be performed in the corresponding channel control register #2:#5 or in the output control register #8 To delatch the diagnosis:
  • the undervoltage condition must be removed
  • a read command of the device st atus register #7 must be performed Fail mode When the device is in Fail mode, the restart of the outputs is controlled by the autorestart feature.

6.1.3.3.2 Overvoltage

The device is protected against overvoltage on VBAT.

  • jump start condition, the device may be o perated, but with respect to the device limits
  • load dump condition (V BAT LD MAX = 40 V) the device does not conduct energy to the loads The overvoltage condition (VBAT > VBAT OVF) is reported in the:
  • device status flag (DSF) in the registers #1:#7
  • overvoltage flag (OVF) inside th e device status register #7 To delatch the diagnosis:
  • the overvoltage condition must be removed
  • a read command of the device st atus register #7 must be performed

Table 12. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • T OW1 level
  • T OW2 level 100 120 115 135 130 150 (18) TOTS Overtemperature shutdown 155 170 185 °C (18) tFAULT SD Fault deglitch time
  • O T S 2.0 5.0 10 µs Notes 18. Guaranteed by testmode.

In case of an overvoltage (VBAT > VBAT HIGH), the device is not "short-circuit" proof.

6.1.3.3.3 Electrical characterization

6.1.3.4 Charge pump protection

  • power up
  • failure of external capacitor
  • failure of charge pump circuitry During power up, when the charge pump voltage has not yet settled to its nominal output voltage range, the outputs can not be turned on. Any turn on command during this phase is executed immediately after settling of the charge pump. When the charge pump voltage is not within its nominal output voltage range:
  • the power outputs are disabled immediately after the deglitch time t FAULT SD
  • the failure status is reported after tFAULT SD in the device status flag DSF in the registers #1:#7 and the CPF in the quick status register #1
  • Any turn on command during this phase is executed includ ing the OCHI windows immediately after the charge pump output voltage has reached its valid range To delatch the diagnosis:
  • the charge pump failure condition must be removed
  • a read command of the quick st atus register #1 is necessary

6.1.3.4.1 Electrical characterization

Table 13. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • UV and OV 2.0 3.5 5.5 µs

Table 14. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • C P F –4 . 0 6 . 0 µs

38 NXP Semiconductors

6.1.3.5 Reverse battery protection

The device is protected against reverse polarity of the VBAT line.

  • the output transistors OUT1:4 are turned ON in or der to prevent the device from thermal overload
  • the OUT6 pin is pulled down to GND. An external current limit resistor shall be added in series with OUT6 pin
  • no output protection is available in this condition

6.1.4 Output clamps

6.1.4.1 Negative output clamp

In case of an inductive load (L), the energy is dissipated after the turn-off inside the N-channel MOSFET. When tCL (= Io x L/VCL) > 1.0 ms, the turn-off waveform can be simplified with a rectangle as shown in Figure 21. Figure 21. Simplified negative output clamp waveform The energy dissipated in the N-Channel MOSFET is: ECL = 1/2 x L x Io² x (1+ VBAT/|VCL|). In the case tCL < 1.0 ms, please contact the factory for guidance.

6.1.4.2 Battery clamp

load, or drained by an external clamping circuit, during a high ohmic load.

6.1.4.3 Electrical characterization

6.1.5 Digital diagnostics

The device offers several modes for load status detection in ON state and OFF state through the SPI.

6.1.5.1 Openload detections

6.1.5.1.1 Openload in ON state

Open load detection during ON state is provided for each power output (OUT1:OUT4), based on the current monitoring circuit. The detection is activated automatically when the output is in ON state.

  • the OLLED EN bits inside the OLLED control register #13-2 The detection result is reported in:
  • the corresponding QSFx bit in the quick status register #1
  • the global open load flag OLF (registers #1:#7)
  • the OLON bit of the corresponding channel status registers #2:#5 To delatch the diagnosis:
  • the open load condition must be removed
  • a read command of the corresponding channel status register #2:#5 must be performed When an open load has been detected, the output remains in on state. The deglitch time of the open load in on state can be controlled individually for each output in order to be compliant with different load types. The setting is dependent on the OLON DGL bits inside the open load control register #13-1:
  • low (logic[0]) the deglitch time is t OLON DGL = 64 µs typ (bulb mode)
  • high (logic[1]) the deglitch time is t OLON DGL = 2.0 ms typ (converter mode) The deglitching filter is reset whenever output falls low and is only active when the output is high.

6.1.5.1.2 Openload in ON state for LED

on and the falling edge of the output voltage is evaluated by a comparator at VBAT - 0.75 V (typ). Table 15. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • 1 0 mΩ
  • 2 5 mΩ -20.5 -21 -17.5 -18 V

40 NXP Semiconductors

Figure 22. Openload in ON state diagram for LED

  • low (logic[0]), the standard open lo ad in ON state (OLON) is enabled
  • high (logic[1]), the OLLED detection is enabled The detection result is reported in:
  • the corresponding QSFx bit in the quick status register #1
  • the global open load flag OLF (register #1:#7)
  • the OLON bit of the correspondi ng channel status register #2:#5 When an open load has been detected, the output remains in ON state. When output is in PWM operation:
  • the detection is performed at the end of the on time of each PWM cycle
  • the detection is active during the off time of the PWM signal, up to 2.0 ms max. The current source (IOLLED) is disabled after “no OLLED” detection or after 2.0 ms.

Figure 23. Openload in ON state for LED in PWM operation (off time > 2.0 ms)

42 NXP Semiconductors

6.1.5.1.3 Open load in off state

An Open Load in off state detection is provided individually for each power output (OUT1:OUT4). The detection is enabled individually for each channel by the OLOFF EN bits inside the open load control register #13-1.

  • low (logic[0]), the diagnosis mo de is disabled (default status)
  • high (logic[1]), the diagnosis mode is started for tOLOFF. It is not possible to restart any OLOFF or disable the diagnosis mode during active OLOFF state This detection can be activated independently for each power output (OUT1:OUT4). When it is activated, it is always activated synchronously for all selected outputs (with positive edge of CSB). When the detection is started, the corresponding output channel is turned on with a fixed overcurrent threshold of IOLOFF threshold. When this overcurrent threshold is:
  • reached within the detection timeout tOLOFF, the output is turned off and the OLOFF EN bit is reset. No OCLOx and no OLOFFx is reported
  • not reached within t he detection timeout tOLOFF, the output is turned off after tOLOFF and the OLOFF EN bit is reset. The OLOFFx is reported The overcurrent behavior as commanded by the overcurrent control settings (NO OCHIx, OCHI ODx, SHORTOCHIx, OCLOx, and ACM ENx) is not be affected by applying the OLOFF ENx bit. The same is true for the output current feedback and the current sense synchronization. The detection result is reported in:
  • the corresponding QSFx bit in the quick status register #1
  • the global open load flag OLF (register #1:#7)
  • the OLOFF bit of the corresponding channel status register #2:#5 To delatch the diagnosis, a read command of the corresponding channel status register #2:#5 must be performed. During any fault during tOLOFF (OTS, UV, CPF,), the open load in off state detection is disabled and the output(s) is (are) turned off after the deglitch time tFAULT SD. The corresponding fault is reported in the SPI SO registers.

6.1.5.1.4 Electrica l characterization

Table 16. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • 1 0 mΩ power channel at TJ = -40 °C
  • 1 0 mΩ power channel at TJ = 25 °C and 125 °C
  • 2 5 mΩ power channel at TJ = -40 °C
  • 2 5 mΩ power channel at TJ = 25 °C and 125 °C 150 150 350 300 160 150 mA δPWM OLON Output PWM duty cycle range for open load detection in ON state
  • Low frequency range (25 Hz to 100 Hz)
  • Medium frequency range (100 Hz to 200 Hz)
  • High frequency range (200 Hz to 400 Hz) LSB IOLLED Open load current threshold in ON state/OLLED mode 2.0 4.0 5.0 mA tOLLED100 Maximum open load detection time/OLLED mode with 100% duty cycle 1.5 2.0 2.6 ms tOLOFF Open load detection time in OFF state 0.9 1.2 1.5 ms

6.1.5.2 Output shorted to VBAT in off state

comparator referenced to VBAT/2 (VOUT DETECT) and an external pull-down circuitry. The detection result is reported in the OUTx bits of the I/O status register #8 in real time. In case of UVF, the OUTx bits are undefined.

6.1.5.2.1 Electrical characterization

6.1.5.3 SPI fault reporting

depending on the SOA MODE bit.

  • low (logic[0]), the programmed SO address is used for a singl e read command. After the reading the SO address returns to quick status register #1 (default state)
  • high (logic[1]), the programm ed SO address is used for the next and all further read commands until a new programming The “quick status register” #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no control action by the microcontroller is necessary.
  • FM: Fail mode indication. This bit is also present in all ot her SO data words, and indicates the fail mode by a logic[1]. When the device is in Normal mode, the bit is logic[0]
  • global device status flags (D10:D8): These flags are also pres ent in the channel status registers #2:#5, the device status register #7, and are cleared when all fault bits are cleared by reading the registers #2:#7
  • DSF = device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the device status register #7
  • OVLF = over load flag (wired OR of all OC and OTS signals) Power outputs OUT1:OUT4 (continued) tFAULT SD Fault deglitch time
  • O L O F F
  • OLON with OLON DGL = 0
  • OLON with OLON DGL = 1 2.0 1.5 3.3 2.0 5.0 2.5 µs ms ms I OLOFF Open load current threshold in OFF state
  • 1 0 mΩ power channel
  • 2 5 mΩ power channel 0.7 0.385 0.875 0.55 1.1 0.715 A

Table 17. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Table 16. Electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

44 NXP Semiconductors

  • OLF = open load flag
  • CPF: charge pump flag
  • RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset
  • CLKF: clock fail flag. Refer to Logic I/O plausibility check section
  • QSF1:QSF5: channel quick status flags (QSFx = OC0x, or OC 1x, or OC2x, or OTWx, or OTSx, or OLONx, or OLOFFx) The SOA address #0 is also mapped to register #1 (D15:D12 bits report logic [0001]). When a fault condition is indicated by one of the quick status bits (QSF1:QSF5, OVLF, OLF), the detailed status can be evaluated by reading of the corresponding channel status registers #2:#6.
  • OTSx: overtemperature shutdown flag
  • OTWx: overtemperature warning flag
  • OC0x: OC2x: overcurrent status flags
  • OLONx: Openload in ON state flag
  • OLOFFx: Openload in OFF state flag The most recent OC fault is reported by the OC0x:OC2x bits, if a new OC occurs before an old OC on the same output that was read: When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of the device status registers #7:
  • TMF: test mode activation flag. Test mode is used for manufacturing testing only. If this bit is set to logic [1], the MCU shall reset the device
  • OVF: overvoltage flag
  • UVF: undervoltage flag
  • SPIF: SPI fail flag
  • iLIMP (real time reporting after the t IN_DGL, not latched) The I/O status register #8 can be used for system test, fail mode test and the power down procedure: Register SO address SO data # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C H 1 s t a t u s 20010 F M D S F O V L F O L F r e s O T S 1 O T W 1 O C 2 1 O C 1 1 O C 0 1 OLON

1 OLOFF1

C H 2 s t a t u s 30011 F M D S F O V L F O L F r e s O T S 2 O T W 2 O C 2 2 O C 1 2 O C 0 2 OLON

2 OLOFF2

C H 3 s t a t u s 40100 F M D S F O V L F O L F r e s O T S 3 O T W 3 O C 2 3 O C 1 3 O C 0 3 OLON

3 OLOFF3

C H 4 s t a t u s 50101 F M D S F O V L F O L F r e s O T S 4 O T W 4 O C 2 4 O C 1 4 O C 0 4 OLON

4 OLOFF4

# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 device status 7 0 1 1 1 FM DSF OVLF OLF res res res TMF OVF UVF SPIF iLMP #2 ~# 6 OC 2x OC1x OC 0x over current st atus 0 0 0 no ov erc urrent

001 O C H I 1

010 O C H I 2

011 O C H I 3

100 O C L O

101 O C H I O D

110 S S C

The register provides the status of the control inputs, the toggle signal, and the power outputs state in real time (not latched).

  • TOGGLE = status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or IN4_ON), reported in real time
  • iINx = status of iINx signal (real time reporting after the t IN_DGL, not latched)
  • OUTx = status of output pins OUTx (the detection threshold is V BAT/2) when undervoltage condition does not occur The device can be clearly identified by the device ID register #9 when the battery voltage is within its nominal range: The register delivers DEVIDx bits = 42hex for the 08XS6421. During an undervoltage condition (UVF = 1), DEVIDx bits report 00hex.

6.1.6 Analog diagnostics

initialization 1 register #0.

6.1.6.1 Output current monitoring

1.0 mA full scale range current source reporting channel 1:4 current feedback (IFSR). Figure 26. Output current sensing frequency (see Electrical characterization). accuracy for low current loads. In the ACM mode, the offset sign of current sense amplifier is toggled on every CSNS SYNCB rising edge.

46 NXP Semiconductors

sequential current sense measurements. The ACM mode is enabled with the ACM ENx bits inside the ACM control register #10-1.

  • low (logic[0]), ACM disabled (default status and during Fail mode)
  • high (logic[1]), ACM enabled In ACM mode:
  • the precision of the current rec opy feature (CSNS) is improved especially at low output current by averaging CSNS reporting on sequential PWM periods
  • the current sense full scale range (FSR ) is reduced by a factor of two
  • the overcurrent protection threshold OC LO is reduced by a factor of two Figure 27 describes the timings between the selected channel current and the analog feedback current. Current sense validation time pertains to stabilization time needed after turn on. Current sense settling time pertains to the stabilization time needed after the load current changes while the output is continuously on or when another output signal is selected.

Figure 27. Current sensing response time

6.1.6.2 Battery voltage monitoring

Figure 28. Battery voltage reporting

6.1.6.3 Temperature monitoring

min/max range of 5.0 kΩ to 50 kΩ. Temperature feedback range, TFB, -40 °C to 150 °C. Figure 29. Temperature reporting

48 NXP Semiconductors

6.1.6.4 Analog diagnostic synchronization

A current sense synchronization pin is provided to simplify the synchronous sampling of the CSNS signal. The CSNS SYNCB pin is an open drain requiring an external 5.0 kΩ (min) pull-up resistor to VCC.

  • available during Normal mode only
  • behavior depends on the type of signal selected by the MUX2:MUX0 bits in the initialization 1 register #0. This signal is either a current proportional to an output current or a voltage proportional to temperature or the battery voltage Current sense signal When a current sense signal is selected:
  • the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0, SYNC EN1 bits inside the initialization 1 register #0

Figure 30. CSNS SYNCB valid setting

50 NXP Semiconductors

Figure 33. CSNS SYNCB when the output is programmed with 100%

  • During an output fault, the CSNS SYNCB signal for current sensing does not deliver a trigger signal until the output is enabled again Temperature signal or VBAT monitor signal When a voltage signal (average control die temperature or battery voltage) is selected:
  • the CSNS SYNCB delivers a signal with 50% duty cycle and the period of the lowest prescaler setting (fCLK/1024)
  • and a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50% duty cycle at a fixed period of 6.5 ms (tSYNC DEFAULT)

6.1.6.5 Electrical characterization

Table 18. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • High OCLO and ACM = 0
  • Low OCLO and ACM = 0
  • High OCLO and ACM = 1
  • Low OCLO and ACM = 1 4.5 A ACC I CSNS Current sense accuracy for 9.0 V < VBAT < 18 V for 10 mΩ power channel
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -11 -14 -20 -29 +11 +14 +20 +29 (19) OUT1 time OUT2 time OUT1 for CSNS selected OUT2 for CSNS selected timechange of CSNS MUX from OUT1 to OUT2 CSNS SYNC\\ tDLY(ON)+tCSNS(SET)
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -7.0 -7.0 -20 -29 +7.0 +7.0 +20 +29 (23) (21) ACC ICSNS 2 CAL Current sense accuracy for 9.0 V < VBAT < 18 V with two calibration points at 25 °C for 2.0% and 50% FSR and VBAT = 14 V for 10 mΩ power channel
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -6.0 -6.0 -9.0 -16 +6.0 +6.0 +9.0 +16 (23) (21) ICSNSMIN Minimum current sense reporting for 10 mΩ
  • 9 . 0 V < VBAT < 18 V –– 1 . 0 % F S R (19)(22) IFSR Current sense full scale range for 25 mΩ power channel
  • High OCLO and ACM = 0
  • Low OCLO and ACM = 0
  • High OCLO and ACM = 1
  • Low OCLO and ACM = 1 9.6 4.8 4.8 2.4 A ACC I CSNS Current sense accuracy for 9.0 V < VBAT < 18 V for 25 mΩ power channel
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -11 -14 -20 -29 +11 +14 +20 +29 (19) ACC ICSNS 1 CAL Current sense accuracy for 9.0 V < VBAT < 18 V with one calibration point at 25 °C for 50% FSR and VBAT = 14 V for 25 mΩ power channel
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -7.0 -7.0 -20 -29 +7.0 +7.0 +20 +29 (19) (21) ACC ICSNS 2 CAL Current sense accuracy for 9.0 V < VBAT < 18 V with two calibration points at 25 °C for 2.0% and 50% FSR and VBAT = 14 V for 25 mΩ power channel
  • I OUT = 80% FSR
  • I OUT = 25% FSR
  • I OUT = 10% FSR
  • I OUT = 5.0% FSR -6.0 -6.0 -8.0 -11 +6.0 +6.0 +8.0 +11 (19) (21) ICSNSMIN Minimum current sense reporting for 25 mΩ
  • for 9.0 V < VBAT < 18 V –– 1 . 0 % F S R (19) (22) VBAT Battery voltage feedback range V BATMAX –2 0V ACC VBAT Battery feedback precision
  • D e f a u l t
  • 1 calibration point at 25 °C and VBAT = 12 V, for 7.0 V < VBAT < 20 V
  • 1 calibration point at 25 °C and VBAT = 12 V, for 6.0 V < VBAT < 7.0 V -6.0 -1.0 -2.2 +6.0 +1.0 +2.2 (21) TFB Temperature feedback range -40 – 150 °C (20)

Table 18. Electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

52 NXP Semiconductors

  • Default
  • 1 calibration point at 25 °C and VBAT = 7.0 V -15 -5.0 +15 +5.0 °C (21) tCSNS(SET) Current sense settling time
  • Current sensing feedback for IOUT from 75% FSR to 50% FSR
  • Current sensing feedback for IOUT from 10% FSR to 1.0% FSR Temperature and battery voltage feedbacks 260 µs (20) tCSNS(VAL) Current sense valid time Current sensing feedback
  • Low/medium frequency ranges for IOUT > 20% FSR
  • Low/medium frequency ranges for IOUT < 20% FSR
  • High frequency range for IOUT > 20% FSR
  • High frequency range for IOUT < 20% FSR Temperature voltage feedback Battery voltage feedback 5.0 150 300 300 µs (23) tSYNC DEFAULT Current sense Synchronization Period for PWM Clock Failure 4.8 6.5 8.2 ms Current sense synchronization CSNS SYNCB RCSNS SYNC Pull-up current sense synchronization resistor range 5.0 – – k Ω VOL Current sense synchronization logic output low state level at 1.0 mA – – 0.4 V IOUT max Current sense synchronization leakage current in Tri-state (CSNS SYNC from 0 to 5.5 V) -1.0 – +1.0 µA Notes 19. Precision either OCLO and ACM setting. 20. Parameter is derived mainly from simulations. 21. Parameter is guaranteed by design characteri zation. Measurements are taken from a statistically relevant sample size across process variations. 22. Error of ±100% without calibration and ±50% with 1 calibration point done at 25 °C.

noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.2 Power supply functional blo ck description and application

6.2.1 Introduction

presence of VCC. The employed IC architecture guarantees a low quiescent current in Sleep mode (wake= [0]).

6.2.2 Wake state reporting

The CLK input/output pin is also used to report the wake state of the device to the microcontroller as long as RSTB is logic [0].

  • “wake state” and RSTB is inactive, the CLK pin reports a high signal (logic[1])
  • “sleep mode” or the device is wake by the RSTB pin, the CLK is an input pin

6.2.2.1 Electrical characterization

6.2.3 Supply voltages disconnection

6.2.3.1 Loss of V BAT

  • V CC < VCC POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
  • V CC > VCC POR: all registers and faults are maintained. OUT1:4 are shut off immediately. The ON/OFF state of OUT6 depends on the current SPI configuration. SPI reporting is available when VCC remains within its operating voltage range (4.5 to 5.5 V) The wake-up event is not reported to the CLK pin. The clamping structures (battery clamp, negative output clamp) are available to protect the device. No current is conducted from VCC to VBAT. An external current path shall be available to drain the energy from an inductive load, in case a battery disconnection occurs when an output is ON.

6.2.3.2 Loss of V CC

  • V BAT < VBAT POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
  • V BAT > VBAT POR: the SPI is not available. Therefore, the device enters WD timeout The clamping structures (battery clamp, negative output clamp) are available to protect the device. No current is conducted from VBAT to VCC.

6.2.3.3 Loss of device GND

be provided externally in order to limit the current to ICL. Table 19. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

54 NXP Semiconductors

6.2.3.4 Electrical characterization

6.3 Communication interface and d evice control functional block

6.3.1 Introduction

not required and this mode can be forced by the LIMP input pin.

6.3.2 Fail mode input (LIMP)

The Fail mode of the component can be activated by LIMP direct input. The Fail mode is activated when the input is logic [1].

6.3.2.1 Electrical characterization

Table 20. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Table 21. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.3.3 MCU communication interface protections

6.3.3.1 Loss of communication interface

If the SPI communication error occurs, the device is switched into Fail mode.

  • the WD bit is not toggled with each SPI message or
  • WD timeout is reached or
  • protocol length error (modulo 16 check) The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by a WD toggle error. The SPI communication error is reported in:
  • SPI failure flag (SPIF) inside the device stat us register #7 in the next SPI communication As long as the device is in Fail mode, the SPIF bit retains its state. The SPIF bit is delatched during the transition from fail-to-normal modes.

6.3.3.2 Logic I/O plausibility check

The LIMP and IN1:IN4 have an input symmetrically deglitch time tIN_DGL = 200 µs (typ). If the LIMP input is set to logic [1] for a delay longer than 200 µs typ, the device is switched into Fail mode (internal signal called iLIMP).

  1. Parameter is derived mainly from simulations.

Table 21. Electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

56 NXP Semiconductors

Figure 34. LIMP and iLIMP signal Figure 35. IN, iIN and IN_ON signal cycle depends on the corresponding SPI configuration.

  • the clock failure condition must be removed
  • a read command of the quick stat us register #1 must be performed LIMP time iLIMP time tIN_DGL 200µs typ. tIN_DGL 200µs typ. INx time iINx time INx_ON time ttoggle tIN_DGL ttoggle 1024ms typ. tIN_DGL 200µs typ. tIN_DGL tIN_DGL tIN_DGL tIN_DGL

6.3.3.3 Electrical characterization

6.3.4 External smart power control (OUT6)

6 settings in the SPI input data register.

  • The protection and current feedback of the external SMARTMOS device are under the responsibility of the microcontroller
  • The output delivers a 5.0 V CMOS logic signal from VCC The output is protected against overvoltage. An external current limit resistor (i.e. 1.0 kΩ:10 kΩ) is used to handle negative output voltage conditions. The output has an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and Fail mode. In case of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of external smart power device and to limit possible reverse OUT6 current (i.e. resistor in series).

6.3.4.1 Electrical characterization

Table 22. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

  • WD SEL = 0
  • WD SEL = 1 128 160 ms tTOGGLE Input toggle time for IN1:IN4 768 1024 1280 ms tDGL Input deglitching time
  • LIMP and IN1:IN4
  • C L K
  • R S T B 150 1.5 7.5 200 2.0 250 2.5 12.5 µs fCLOCK LOW Clock low frequency detection 50 100 200 Hz

Table 23. Electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

58 NXP Semiconductors

7 Typical applications

7.1 Introduction

The 12XS6 family is the latest achievement in automotive drivers for all types of centralized automotive lighting applications.

7.1.1 Application diagram

Figure 36. Typical automotive front lighting (penta version)

7.1.2 Application instructions

7.1.3 Bill of material

7.2 EMC and EMI considerations

7.2.1 EMC/EMI tests

This paragraph gives EMC/EMI performances. Further generic design recommendations can be found on the NXP website www.nxp.com. Table 24. 12XS6 Bill of material (25)

  1. NXP does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables.

While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. Table 25. 12XS6 EMC/EMI performances

60 NXP Semiconductors

7.2.2 Fast transient pulse tests

This paragraph gives the device performances.against fast transient disturbances.

7.3 Robustness considerations

affect the device’s reliability. Moreover, the availability of the lighting is guaranteed in fail mode by the unlimited autorestart feature. For either condition, see the application note AN5066 or contact NXP’s local Field Application Engineer (email: support@nxp.com). Table 26. 12XS6 fast transient capability on VBAT

7.4 PCB layout recommendations

each device variant. The PCB Copper layer is similar for all devices in the 12XS6 family, only the solder Stencil opening is different. footprint, pin 1 of the SOIC32 package must be located at pin 3 of the SOIC54 package. Figure 37. PCB copper layer and solder stencil opening recommendations

62 NXP Semiconductors

7.5 Thermal information

This section is to provide thermal information.

7.5.1 Thermal transient

Figure 38. Transient thermal response curve

7.5.2 R/C thermal model

Contact our local Field Application Engineer (email: support@nxp.com).

8 Packaging

8.1 Marking information

and the last two digits indicate the week. For instance, the date code “1229” indicates the 29th week of the year 2012.

8.2 Package mechanical dimensions

perform a keyword search for the drawing’s document number. Table 27. Package Outline

64 NXP Semiconductors

66 NXP Semiconductors

68 NXP Semiconductors

70 NXP Semiconductors

9 Revision history

Revision Date Description of changes 1.0 5/2015 • Initial release 8/2016 • Updated to NXP document form and style 2.0 4/2018

  • Added Table 2
  • Added MC10XS6200BEK, MC10XS6225BEK, MC10XS6325BEK, and MC25XS6300BEK parts to Table 1 and associated 98ASA00894D package information
  • Updated the ON-Resistance, Drain-to-Source max. value for 10 mΩ power channel, TJ = 150 °C (replaced 16 by 17.5) in Table 10
  • Updated the ON-Resistance, Drain-to-Source max. value for 25 mΩ power channel, TJ = 150 °C (replaced 39 by 41) in Table 10
  • Updated Figure 16 (added IOCLO_PWM item)
  • Updated OCLO threshold setting description in Overcurrent control programming
  • Corrected typo in Table 11 for IOCHI1 (replaced 5.0 mΩ by 10 mΩ)
  • Updated the min. value for I OCLO (replaced 16 by 14.5) in Table 11
  • Updated the max. value for I OCLO ACM (replaced 5.1 by 5.2) in Table 11
  • Added values for I OCLO PWM (10 mΩ power channel) and IOCLO PWM (25 mΩ power channel) to Table 11
  • Updated the min. value for I OL 10 mΩ power channel at TJ = -40 °C (replaced 30 by 20) in Table 16
  • Updated the min. value for I OL 25 mΩ power channel at TJ = -40 °C (replaced 30 by 20) in Table 16
  • Updated the max. value for I OLOFF (replaced 1.05 by 1.1) in Table 16 3.0 11/2018
  • Updated as per CIN 201811005I
  • Updated Table 2
  • Added note 15 to Table 8, Electrical characteristics and note 26 to Table 23, Electrical characteristics 4.0 9/2020
  • Changed document status from Advance Information to Technical Data
  • Added values for R PULL-CSB to Table 8, Electrical characteristics
  • Updated the max value for R OUT6 DWN in Table 23, Electrical characteristics (replaced 20 by 30)

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo, and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2020 NXP B.V. Document Number: MC12XS6D2 Rev. 4.0