MC1505

MC1405 MOTOROLA | Alldatasheet

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DUAL RAMP A/D CONVERTER SUBSYSTEM ‘The MC1605/MC1408 is intended to perform the dual ramp function for TO-1 either » 3-1/2 or 4-1/2 digit DVM or use as a general-purpose analog-to-digital ANALOG-TO-DIGITAL (A/D) converter. It can be combined with the CMOS MC14435 logic system CONVERTER SUBSYSTEM to produce the complete 3-1/2 digit DVM function. ‘The MC1505 uses the proven dual ramp A/D conversion technique. The SILICON MONOLITHIC subsystem consists of an on-chip voltage reference, a pair of voltage/current INTEGRATED CIRCUIT converters, an integrator, a comparator, @ current switch and associated con- trol and calibration circuitry. Only one capacitor and two calibration potentiometers are required for normal operation. © Accuracies to 13 Bits © Low Power Consumption: 42 mW @ +5.0 Vv ‘© Single Power Supply Operation ~ +5.0V to +18 V ‘© Low Power Supply and Temperature Sensitivity 16 © Digital Inputs and Outputs Compatible with Both MTTL and ‘CMOS a © Accepts Either Positive or Negative Input Voltages . (top view) ‘@ Combines with MC14436 to Produce 3-1/2 Digit A/D Converter ao FIGURE 1 ~ COMPLETE A/D CONVERTER SYSTEM Se YY) + a): { 4 -_ © 1700" CASE 620 CERAMIC PACKAGE Taune PW CONNECTIONS AND FUNCTIONAL DIAGRAM torumdin Feu 1) | 8 | cane x ee fab on ge - sa 2 | men ee TCL, “TH rH faye cre, Ce eG _ aa TYPICAL APPLICATIONS BCD A/D Converter: 2-1/2 t0 41/2 Digits (LS! or MSI Logic) Other Uses: Panel Maters Date Acquistion Systems with Remote MC1505 Digital Vottmeters Voltage to Frequeney Conversion Portable Instruments Delta Modulation and Signel Generation Industriel Measurement and Control Binary A/D Converter: 6-t0-13 Bits (LSI or MSI Logic) Industrial Measurement and Control High Nol Environments (Integrating Converter with MTTL, MHTL, and CMOS Compatibility) 8-3

MC1405, MC1505 MAXIMUM RATINGS Chai a Foe Sply Voge [ec [68 vee [ita put Vote ng 8 oe [_ Referee input Voge 80 ore J i ee ower Dipeion (Package ito) Garam Dal Le PoC 7000 a erate above Ta = +25°C 60 mic Operating Ambient Temperature Range ° moras “a5 10 425 pany Seo [ Bev rnin Ree ELECTRICAL CHARACTERISTICS (Vcc = +15 Vde, VR = 1.000 Vdc, V1 = 2.000 Vde, V2 = 0.000 Vdc, V10 >2.0 Vdc, Ta = 26°C unless otherwise noted.) | mcrs05 TT craos Charette sim | pene [mT te [ae | wee me] ae CoNVERSGN oreTEM TT Tinea: Bevatlan vs Som mar as we Tha Sone Pon Sony Serato a aaa] aaa a Topo Garon oa Baa eal aneae aor canoe | aaare| Rim [Fa see Temperate Brfeia) ROR |= oe [oe re [ze cnitraton Tempore ona [ ree 8 = [oon [==] “0001 |= far) VOLTAGE REFERENCE [[peterence votupe.pnt1 +d Vage [3 Due] me pas Dv] ae] a] ve] [ Reternce Voroae Powe Sul Sensivin [ P5SVner [3 | — | ooos| coor, | woos | 02] x] [Creterence votogn Tergerairs Ont | WeVaerI] 3 | = | oo | - | -] cow] — | wre] [PReteenes Curent ww 0 oe] RT [jiouiAongeotve —] ve fa foe | - [vz ost [a] ve] [nowt ort Varage views. Want | 3 | = | 0 [ep - [20] ss] mv [nknown Current 8 TO To a [rout Resse a go a [rout Diterentr Range vy | ano | 20 J =f 2 [20 f — ] vor | [input Common Mode Range | CMR | 1012] 15 | - | ts | a5] — [| 18] vow] FA FE [input ortier vor iviaevay T vxxt | 3 [= | vo [2s [ = [20] ssf mv] aie OFFSET SOURCE (1) System paramters meanred ung exteral olgeaarence, independent of VIN = VA ge Chock Freeney = 204 weenie (2) Bows ot include auntiingaor. Sa igre 10 focabvaton 8-4

MC1405, MC1505 GENERAL INFORMATION Dual Ramp Analog to-Digital Conversion AID Subsystem Circuit Description ‘The dual ramp method of A/D conversion is a proven The MC1505 incorporates special circuit features which system which is capable of very high accuracy. The con- allow all the analog functions of the dual ramp system to version is an integrating process which offers high noise be performed on a single monolithic chip using standard rejection and immunity to changes in the clock rate and bipolar processing. integrator capacitor value. The particular method used in ‘Voltage-to-current conversion for both the input and the MC1505 is a noniterating dual slope technique which reference voltages allows the use of a high-speed current produces an accurate result after one conversion period. ‘switch and single supply operation, The unbuffered dif- Dual ramp conversion is accomplished with the system ferential inputs have sufficiently high input impedance for of Figure 2. The conversion begins at time t1, when current power supply monitoring applications, and provide flexi- 1x causes the integrator output, or ramp, to cross the bility for other input formats since they will accept either ‘comparator threshold, as shown in Figure 6. The clock is positive or negative voltages. activated and the counters begin counting from zero. The The voltage reference, shown in Figure 7, is one of the system counts for a fixed period T, with a ramp slope six basic circuits in the subsystem. It provides tow im- which depends on the input voltage, i.e., a steep slope is pedance output which has excellent temperature stability, ‘caused by a high input voltage. When the counters have ‘and high power supply rejection. Biasing for the other reached full scale, the overflow count triggers a + 2 flip- circuits in the MC1505 is derived from the voltage flop which changes the ramp control polarity current. IR reference circuitry. FIGURE 6 - DUAL RAMP A/D CONVERSION WAVEFORMS "Xtmex) In ‘AV on capacitor is equal in T1 and 72 x > & (Constant Slope) if? i7® af, xa bf Inet at 2 Integrator Where Ix is opposite 1 polarity. a Ig T= I T2 " 2 13 Vx T1= VR T2 fe T24man? Vx PLE Tate Comparator ‘72 corresponds to the number of counts in the rs ‘output digital word. Ramp ee ee ee Tt and T2 are derived from the lock. 20 their Contra ratio is independent of clock frequency. now controls the integrator and the down ramp begins at The same basic amplifier circuit is used in both the 12, This ramp continues at a fixed slope for a time period reference and input voltage-to-current convertors, It is an Which depends on the amplitude achieved by the up ramp. extremely well balanced amplifier with low input offset Thus T2 is determined by the input voltage. When the voltage temperature drift. The reference converter uses a ramp crosses the comparator threshold at t3, the clock pair of PNP transistors to derive current Ip, in conjunction stops and the counter holds a digital value which is pro- with a reference resistor which has the same temperature portional to the unknown input voltage. coefficient as those used in the input converter. The value ‘After the down ramp crosses the comperator threshold, of the reference current is VR/RS. The collectors of 2 timing sequence in the digital section strobes the latches transistors Q1, Q2 and Q3 in Figure 7 all track with a two to store the data, resets the counters, and reverses the diode temperature coefficient, which assures constant ramp at t4 to begin a new conversion. current ratios. ‘Since the voltage change across the capacitor is equal The reference resistor value can vary by 30% of 4.0 ‘on the up and down ramps, an equal amount of charge is ka due to process variations. Moreover, these variations exchanged. The equations of Figure 6 show that the will also affect the input bridge resistors. Thus, the ratio system output is the ratio of the unknown and reference of reference to unknown current has a close tolerance for currents, and long term changes in the clock rate and ‘a wide range of resistor values. integrator capacitor do not effect the reading. 8-6

MC1405, MC1505 ‘The input voltage-to-current converter is a bridge or of the diode in the current switch at low levels, re- bilateral current source whose output current is Vx/R 1. If stricting the voltage change at the output of the resistor the bridge is perfectly balanced, its output impedance and bridge. Still another feature is that it provides @ con- common mode rejection are infinite. However, the design venient temperature compensated zero adjust which can has the ability to tolerate bridge mismatches of approxi- correct errors in the resistor bridge and input buffer mately 0.5%. In order to tolerate this mismatch, the amplifiers when they are used. The ramp offset current is ‘output of the bridge current source is connected to the compensated by 100 extra counts in the digital logic current switch which is a low temperature coefficient, low during ramp down, so it does not appear in the digital impedance source of 1.25 volts. This technique effectively output (see Figure 8). eliminates output current changes due to finite output ‘The current switch uses current steering for very high impedance which is caused by resistor mismatch. This speed operation. A smooth transition occurs as one current input current converter makes possible the use of a single is turned on while the other is turned off. This minimizes supply voltage and differential inputs which can be used at error during the ramp reversal at its peak, especially since or below ground potential. ‘the reference current source has a very high output im- An important feature of the MC1505 is the ramp offset pedance and does not change value when switched. The ‘current source which is added to the unknown current and settling time of the input current converter is not a factor does not allow the ramp to reach zero slope when the in system accuracy. At the ramp peak, |x is turned off, so input voltage is zero. The ramp range is shown in Figure 8. the amplifier settles after the unknown current is de- The ramp offset current has a value of 1R/10, so that the coupled from the integrator. When the ramp is below the minimum ramp slope is 5% of the full scale slope. This comparator threshold, the unknown current is switched on allows reliable conversion at low input voltages by assuring and thus the current can settle before the ramp enters the a nearly constant comparator propagation delay and a active conversion range. The switch operates into a voltage good ramp signal-to-noise ratio. It also prevents turn-off of 1.95 volts and is translated by a follower so its input FIGURE 7 ~ A/D CONVERTER ANALOG SUBSYSTEM Vee

16 VW Vaer = 128 V

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MC1405, MC1505 FIGURE 8 ~ C1505 SYSTEM TIMING DIAGRAM (2.0 Volt Full Scale input) x(maxd * 10. in NX (Content Slope) = Xmen, ixtlo ‘0 20 1g corressonds to remo sfope wan Ix = 0 Integ ator " 1 —-

7000 Counts ——— T2imex) —

convo! | ! a “ factor nicimcaee threshold is 1.25 volts. ations in the value of the comparator threshold are not an The integrator is a single stage, wide bandwidth ampli: error factor, since the only requirement is that the fier, Its low propagation delay and low output impedance threshold remain constant during a given conversion cycle. minimize ramp spikes due to output current reversal during Voltage gain of the comparator is 2,000,000 when driving ramp turn-around. The input bias current is typically one CMOS, and 40,000 with one TTL load. The comparator part in 50,000 of the full scale current, so that its temper: ‘output is slew rate controlled to provide output rise and ature change contributes negligible error. Gain and input fall times of approximately 80 ns, This minimizes noise offset voltage are not critical since the integrator is driven generation which could affect system stability. from current sources. The system is zeroed and full scale calibrated by The comparator is designed for low hysteresis by potentiometers which provide temperature compensation. maintaining a constant power dissipation regardless of All the other resistors are diffused in close proximity, ‘output state. This hysteresis is typically 0.1 mV and yielding reference and unknown currents which have a remains constant with temperature variations, so that no closely tracking resistive temperature coefficient. measurable system error is contributed. Temperature vari- 8-8

MC1405, MC1505 APPLICATIONS INFORMATION The input configurations for the MC1505 are shown for error in the input resistor bridge. This error, known as in Figure 11, Note that the differential input voltage must 1X0, is current which flows to or from the input con- ‘always remain the same polarity with Pin 1 positive with verter with zero volts applied to the input. It is typically respect to Pin 2. Figures 11 and 13 will aid in the under- between +5.0 WA, which is 1% of full scale in a 2 volt standing of the input circuitry. system. A 10 count delay would need a 0.5% ramp offset The input common mode rejection of the MC1505 is current, which would not always be able to cancel this high enough to maintain rated accuracy with small changes error, Also, a 10 count delay does not provide enough in common mode voltage, such as would be seen with signal-to-noise margin for consistently accurate low-level ground errors and noise. The system must be recalibrate, conversion, however, for larger changes in common mode input ‘The integrating capacitor is chosen with the equations voltage. shown in Figure 9. The maximum ramp voltage should The MC1505 is arranged so that Ix = IR when be used for best signal-to-noise ratio, but temperature Vx = VR, oF so that the ramp slopes are equal for input changes in Ix, IR and the capacitor should be anticipated and reference voltages of 1 volt. As shown in Figure 8, a to prevent integrator saturation. Veriations in clock fre- system with a 2 volt full-scale input requires twice as quency should also be considered. A polar capacitor with many digital counts during T2 as for T1. A system with a Pin 7 at the + terminal may be used. However, settling 1 volt full scale would require an equal number of counts ‘time will be increased when electrolytics are used, Tantalum in T1 and T2. Figure 9 illustrates a 3-1/2 digit system, electrolytics are preferred, but typical accuracies of the MC1506 allow its use in 4 ‘The lower half of the diode current switch is split with digit applications. 1t can also be used in systems which separate diodes for |x and IQ. In most applications Pins require 4-1/2 digit resolution. 12 and 13 will be connected so that the two device ‘The ramp offset current and 100 count delay are shown, emitters are effectively one, since the main purpose of jin Figure 8. In certain applications, a different number of these pins is for testing, Connecting these pins allows counts may be used. The system will not always operate proper system zero adjustment and prevents turn-off of properly, however, with a 10 count delay since the ramp the switch diode with low unknown current levels. This offset current is used to zero the system and compensate yields better conversion accuracy. FIGURE 9¢— ACCURACY TEST 3.1/2 Digit Panel Meter oF —_ ‘ya. » | fa _ common cathode corse v Voo : Teo Oselane rae . ; - ie at s fee). ti ronson subvstem FO gg, | Submvstem TSS | Bevery He | Caleraton ere mersass [gatas pecmvenrtrtsnety sano? merses [Ramo Conver eae were Cote THI eo! ope ae (Boreyy, Poe DO | Ororay Bok TOO rs <EMAMEIIIONED OF court 2 7 te oe it ° ¥ pean eres erie ? tht]: iL 4 4 4 tdi tHe Integrator Gopacitor Zero Canbravion | “SS” | ~ * He es, | overs | to ye Viimany (Up Ramp Count) if clock Bai _Lso __ UBS MSO See Electrical Cheracirisics Table fay be nanaed for recovery om VT na typenliy 100 8-9

MC1405, MC1505 A o83 R ow g ooo eo 20 L\\ (.) gs 82 « « 3 |e i g 2 2 o Fu }e] oo 22 o> LO - r ; v0] lca“ €0| 2° sot ——18 = a son § Q a | ° o oF g ——}. ovaos PE | 2 3 an a2 Es Hi i ovoos $3 = 2 yA o1ose 3 z 0 9 e < 5 e8 , in > 8 FA “3 25 rorre—es cots in Eo ort —tis fertt4 Deeks 53 2 10 00, 00| Pools 3 | i 3 tI ears is b: vo} 4— ca“ co} + ae | 33 rp—te fet R ge] $3 oe _ tof e400 i A, s 38 : 3 3 r | ie Fr is 1 Ba HS] 56 siy ay’ as a | a oRD ste tT] 2 385s | 8 g3hbae > feet: 53528: * Bee3ck ea TBi ese an ° pil ie 3 2b S30 383 ze Ee eRe e338 38 in ooiszhe 2 83 220 8 8 g 8-10

MC1405, MC1505 FIGURE b: ~ FUNCTIONAL DIAGRAM OF IMC14436 CMOS DIGITAL SUBSYSTEM ey 8 SSo—o 552 ER é Cc], oe. Oo Cpaate © TT “cers TI ‘Be st comparator § es ba] HY = aco Latches, ae 12, I ne es a fot) oye cs [ey I}, ays [vay] eco ZT) dhes bel rans, a ete yore CJ p . —- ~ a | 2 | | 10

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FIGURE 10 — CALIBRATION SET-UP Bec itnanr at 0.0005 . ert sewers for panel mater dpi wansition a.com Aaiet are Brsge ana O08 Now: an enaog input ot [| accurate ory ides reoding of 0.098 re both onan oft ele, oT mcssos bet MNajtt andard for the desired panel mater transition and 8-11

MC1405, MC1505 FIGURE 11 - ANALOG INPUT RANGE ‘The input circult for the MC1505 has # unipolar differential Input range of #2 volte and a bipolar commen mode input renee oF t.s vor, Ponitive Input: Ve V1 V2 Vx Range 010 42.0 Vom= v2 Ven Range 21.5 V ov s20V0 uy 104 osv Vx 2 xezov io) 2 AsV Vom= ov Vom = #15 Negative input Vx 2 VI=¥2_ Vix Range 0 10 +2.0V Vom = Vt Vom Range #1.6.V 1 wy t ra

2 Vx #20 2

+ 05 010-20 av Vem=0v Vom =£18V Allowable Pin Voltages: Pint -15V t043.5V Pin 2: -3.5V tO+15V FIGURE 12 ~ CIRCUIT TO PREVENT POSSIBLE LATCHUP WITH APPLICATION OF NEGATIVE INPUT VOLTAGES The MC1405/1505 A/D analog subsystem is intended c ane 4 ‘ +Vee for positive input voltages only (i.e., pin 1 positive with re- + spect to pin 2). However, should pin 2 become more than gf % 100 mv positive with respect to pin 1, the internal input fet Ye, ‘amplifier may go into a latchup mode which will require +e-04 Comet OY -onnections that the system power be turned off and then reapplied to Yin 0 reset the system. To prevent this problem a PNP transistor - 02 rc [2o J Mcraaas ‘can be used as shown in the accompanying figure, The Lt base-emitter junction of the transistor clamps pin 13 at o!2 eros bit, fone diode drop above the reference voltage (pin 11) to prevent the latchup, The gain of the transistor insures that ae Full Seale the reference need not sink more than 500 #A of current. ° ° The 47 k{& resistor is required only if the A/D system is to continue to convert under reverse polarity conditions [eras . = such as for autopolarity schemes. % x; ° Zero as aa A. Asiuat +47 &®1 resistor required if conversions are to continue during Input polarity reversal, otherwise tie pins 12 and 13 together. 8-12

MC1405, MC1505 TYPICAL PERFORMANCE CURVES OU A AN eenaTne, INPUT FIGURE 14 — INPUT CURRENT versus INPUT VOLTAGE Pes ae a a a "5 gu |] | a i}yug ou on RaSSeaas=aan tl: === = on 2 Bt 3 oes ee ey -e ee pS CS BES fn ai w= 2.2 a ae === ae op ae ee 5 ‘Note: V1 limits the common made 2 2 aa8l Lot At ptt ori ont core 105 ee oe a Sa a a) ae ea T.TewPenaTune 9) Ver ANALOG NPT VOLTAGE VOLTS FIGURE 16 — UNKNOWN CURRENT venus ANALOG FIGURE 16— REFERENCE CURRENT worn REFERENCE INPUT VOLTAGE INPUT VOLTAGE a o ost —j—+ — = in LI Ng oie nt WE | zt |_| WA : i Wer +— bot 4 EZ Ea | GZ) al eZ Fi _ LG pref |

5 WZ 3 oy] >“P- -+

Bo eZ, r | vow err ma nion a e | 4 Soe ae ery o Tr eS er OS ‘ 02 0¢ O08 08 10 12 14 16 18 20 ve mNALOG INPUT VOLTAGE VOLT) REFERENCE NPUT VOLTAGE PN 4 FIGURE 17 — TYPICAL POWER SUPPLY CURRENT FIGURE 18 — TVPICAL POWER SUPPLY CURRENT ran POWER SUPPLY VOLTAGE nus TEMPERATURE Ss — ‘ , pa Et rrr WSs eeREEEEERES z T2250 t A — 5 a, tt fa é z ; | | | § jo tft é Ed 3 ee S, 2} —|-— Ean WERE ES ESE NeeeReREr Er % 50 10 8 Ey ° 58 0 98 +15 ESrry +175 ve: POWER SUPLY (ve 1. TEMPERATURE) 8-13

MC1405, MC1505 on et oer scoop) CTT EE i a a a see Pe ee - = Fe {. 8 [yo BE" TTT vec IT] aL ~ zs (SEE | 5 |= es ee a Oa OO OO pe LETT | wef ty | o 10, 20 30 40 50 ° 5 0 +5 475 125 75 seomcanaTon ri 22 ae cum «a a To Si6 2 a2 Ep a OO i HH woo oe — ea oo x” eT 7 ry O +250 75 #128 oir s cry 10 1 20 ie oo Si oe ‘ a Full Seale Current Readings ork gee me L Full Seale Voltage Range + 419998 2. 19.99 If ® voltage crop: ot 20 V full scale can be tolerated the & 199.9 8-14

MC1405, MC1505 ot g carton Loe Re I ae 3, PR 8.1L iil 3 Ey aay fC y gigi pier] A te aia il g 3hi 3h, bbe 2 _ od S288 358 - a a 3 oz Zeb agie 2h} oR See eee 8 8 858 = r— | TJ 3 eae of § z fle $s) Ss ox 5 =: 8 39 8&8) 2 6 i eeu = ae3 au ee 283 8 58 B59 Hi aes eee ° ge H RR . ga x fo aa

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2 8 | a A \\e 18 # 83 8-15

MC1405, MC1505 FlOURE 26 — 12417 BINARY A/D LOGIC SUBSYSTEM sna owos name Sco so > 2 Clock Capacitor I>] comowater | > ob hse wert D> RA pa LP Oo

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