MC14001B_14 ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
Features
- Supply V oltage Range = 3.0 Vdc to 18 Vdc
- All Outputs Buffered
- Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range.
- Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B
- Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices
- NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
- These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range −0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) −0.5 to V DD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C VESD ESD Withstand Voltage Human Body Model Machine Model Charged Device Model > 3000 > 300 N/A V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW//C0095C From 65/C0095C To 125/C0095C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V in and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Device Description DEVICE INFORMATION MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14023B Triple 3−Input NAND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MARKING DIAGRAMS SOIC−14 D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G 140xxBG AWLYWW 0xxB ALYW/C0071 /C0071 xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or /C0071= Pb−Free Package MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com (Note: Microdot may be in either location) SOIC−14 TSSOP−14
http://onsemi.com LOGIC DIAGRAMS
2 INPUT
3 INPUT
NC = 6, 8 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES NOR MC14001B Quad 2−Input NOR Gate MC14025B Triple 3−Input NOR Gate MC14023B Triple 3−Input NAND Gate NAND MC14011B Quad 2−Input NAND Gate OR MC14071B Quad 2−Input OR Gate AND MC14081B Quad 2−Input AND Gate MC14073B Triple 3−Input AND Gate MC14082B Dual 4−Input AND Gate PIN ASSIGNMENTS 105 OUT C OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUT C OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUT C IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUT C IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUT C OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUT C IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUT C OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 IN 2 B IN 3B IN 4B OUTB VDD NC IN 1B IN 3A IN 2A IN 1A OUTA VSS NC IN 4A NC = NO CONNECTION MC14023B Triple 3−Input NAND Gate MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14082B Dual 4−Input AND Gate MC14081B Quad 2−Input AND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate
http://onsemi.com ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VDD Vdc − 55/C0095C 25/C0095C 125/C0095C UnitMin Max Min Typ (Note 2) Max Min Max Output Voltage “0” Level Vin = VDD or 0 VOL 5.0 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 Vdc “1” Level Vin = 0 or VDD VOH 5.0 4.95 9.95 14.95 4.95 9.95 14.95 5.0 4.95 9.95 14.95 Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH 5.0 3.5 7.0 3.5 7.0 2.75 5.50 8.25 3.5 7.0 Vdc Output Drive Current (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) IOH 5.0 5.0 –3.0 –0.64 –1.6 –4.2 –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 –1.7 –0.36 –0.9 –2.4 mAdc (VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOL 5.0 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 /C0109Adc Input Capacitance (Vin = 0) Quiescent Current (Per Package) IDD 5.0 0.25 0.5 1.0 0.0005 0.0010 0.0015 0.25 0.5 1.0 7.5 /C0109Adc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) IT 5.0 IT = (0.3 /C0109A/kHz) f + IDD/N IT = (0.6 /C0109A/kHz) f + IDD/N IT = (0.9 /C0109A/kHz) f + IDD/N /C0109Adc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25 /C0095C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in /C0109A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
- The formulas given are for the typical characteristics only at 25 /C0095C.
- Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
*All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. Figure 1. Switching Time Test Circuit and Waveforms
http://onsemi.com CIRCUIT SCHEMATIC NOR, OR GATES VSS 3, 4, 10, 11 VDD VSS VDD *Inverter omitted in MC14001B 1, 6, 8, 13 2, 5, 9, 12 9, 6, 10 VSS VDD 1, 3, 11 2, 4, 12 VSS VDD VSS VDD 8, 5, 13 MC14001B, MC14071B One of Four Gates Shown MC14025B One of Three Gates Shown *Inverter omitted in MC14025B CIRCUIT SCHEMATIC NAND, AND GATES 3, 4, 10, 11 VSS VDD *Inverter omitted in MC14011B 9, 6, 10 VSS VDD *Inverter omitted in MC14023B 2, 5, 9, 12 1, 6, 8, 13 2, 4, 12 1, 3, 11 VDD VDD VSS VSS 8, 5, 13 MC14011B, MC14081B One of Four Gates Shown MC14023B, MC14073B One of Three Gates Shown
http://onsemi.com Device Package Shipping† MC14001BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14001BDG* MC14001BDR2G SOIC−14 (Pb−Free)
2500 Units / Tape & Reel
NLV14001BDR2G* MC14001BDTR2G TSSOP−14 (Pb−Free)NLV14001BDTR2G* MC14001BFELG SOEIAJ−14 (Pb−Free) 2000 Units / Tape & Reel MC14011BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14011BDG* MC14011BDR2G SOIC−14 (Pb−Free) NLV14011BDR2G* MC14011BDTR2G TSSOP−14 (Pb−Free)NLV14011BDTR2G* MC14011BFG SOEIAJ−14 (Pb−Free)
50 Units / Rail
MC14011BFELG 2000 Units / Tape & Reel MC14023BDG SOIC−14 (Pb−Free) 55 Units / Rail MC14023BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel NLV14023BDR2G* MC14023BFELG SOEIAJ−14 (Pb−Free) 2000 Units / Tape & Reel MC14025BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14025BDG* MC14025BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel NLV14025BDR2G* MC14071BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14071BDG* MC14071BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel NLV14071BDR2G* MC14071BDTG TSSOP−14 (Pb−Free)
96 Units per Rail
NLV14071BDTR2G* MC14073BDG SOIC−14 (Pb−Free) 55 Units / Rail MC14073BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel
http://onsemi.com ORDERING INFORMATION (continued) Device Shipping†Package MC14081BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14081BDG* MC14081BDR2G SOIC−14 (Pb−Free) NLV14081BDR2G* MC14081BDTR2G TSSOP−14 (Pb−Free)NLV14081BDTR2G* MC14082BDG SOIC−14 (Pb−Free)
55 Units / Rail
NLV14082BDG* MC14082BDR2G 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
http://onsemi.com PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SU0.15 (0.006) T 2X L/2 SUM0.10 (0.004) V ST L −U− SEATING PLANE 0.10 (0.004) −T− ÇÇÇ ÇÇÇ SECTION N−N DETAIL E J J1 K ÉÉÉ ÉÉÉ DETAIL E F M −W− 0.25 (0.010) 814 PIN 1 IDENT. HG A D C B SU0.15 (0.006) T −V− 14X REFK N N 7.06 14X 0.36 14X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. H 14 8 M0.25 B M C h X 45 SEATING PLANE A M /C0095 SAM0.25 B SC b13X B A E D e DETAIL A L DETAIL A DIM MIN MAX MIN MAX INCHESMILLIMETERS D 8.55 8.75 0.337 0.344 E 3.80 4.00 0.150 0.157 A 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 L 0.40 1.25 0.016 0.049 e 1.27 BSC 0.050 BSC A3 0.19 0.25 0.008 0.010 A1 0.10 0.25 0.004 0.010 M 0 7 0 7 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 6.50 14X 0.58 14X 1.18 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidia ries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 MC14001B/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative