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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
- Supply V oltage Range = 3.0 Vdc to 18 Vdc
- All Outputs Buffered
- Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range.
- Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B
- Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices
- Pb−Free Packages are Available MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range −0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) −0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW//C0095C From 65/C0095C To 125/C0095C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V in and Vout should be constrained to the range VSS /C0118 (Vin or Vout) /C0118 VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Device Description DEVICE INFORMATION MC14001B Quad 2 −Input NOR Gate MC14011B Quad 2 −Input NAND Gate MC14023B Triple 3 −Input NAND Gate MC14025B Triple 3 −Input NOR Gate MC14071B Quad 2 −Input OR Gate MARKING DIAGRAMS PDIP−14 P SUFFIX CASE 646 MC140xxBCP AWLYYWWG SOIC−14 D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G 140xxBG AWLYWW 0xxB ALYW/C0071 /C0071 xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY , Y = Year WW, W = Work Week G or /C0071= Pb−Free Package SOEIAJ−14 F SUFFIX CASE 965 MC140xxB ALYWG MC14073B Triple 3 −Input AND Gate MC14081B Quad 2 −Input AND Gate MC14082B Dual 4 −Input AND Gate See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com (Note: Microdot may be in either location)
http://onsemi.com LOGIC DIAGRAMS
2 INPUT
3 INPUT
NC = 6, 8 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES NOR MC14001B Quad 2−Input NOR Gate MC14025B Triple 3−Input NOR Gate MC14023B Triple 3−Input NAND Gate NAND MC14011B Quad 2−Input NAND Gate OR MC14071B Quad 2−Input OR Gate AND MC14081B Quad 2−Input AND Gate MC14073B Triple 3−Input AND Gate MC14082B Dual 4−Input AND Gate PIN ASSIGNMENTS 105 OUTC OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUTC OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUTC IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUTC IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUT C OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 OUT C IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 105 OUTC OUTD IN 1D IN 2D VDD IN 1C IN 2C OUTB OUTA IN 2A IN 1A VSS IN 2B IN 1B 105 IN 2 B IN 3B IN 4B OUTB VDD NC IN 1B IN 3A IN 2A IN 1A OUTA VSS NC IN 4A NC = NO CONNECTION MC14023B Triple 3−Input NAND Gate MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14082B Dual 4−Input AND Gate MC14081B Quad 2−Input AND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate
http://onsemi.com ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Characteristic ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎ ÎÎÎ ÎÎÎ VDD Vdc ÎÎÎÎÎ ÎÎÎÎÎ − 55/C0095C ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 25/C0095C ÎÎÎÎÎ ÎÎÎÎÎ 125/C0095C ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ Max ÎÎÎÎ ÎÎÎÎ Min ÎÎÎ ÎÎÎ Typ (2) ÎÎÎÎ ÎÎÎÎ Max ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ Max ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Output Voltage “0” Level Vin = VDD or 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOL ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.05 0.05 0.05 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.05 0.05 0.05 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.05 0.05 0.05 ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ “1” Level Vin = 0 or VDD ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOH ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ 4.95 9.95 14.95 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4.95 9.95 14.95 ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 4.95 9.95 14.95 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.5 3.0 4.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.25 4.50 6.75 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 3.0 4.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.5 3.0 4.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3.5 7.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3.5 7.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.75 5.50 8.25 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3.5 7.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Output Drive Current (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5.0 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 3.0 – 0.64 – 1.6 – 4.2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ – 2.4 – 0.51 – 1.3 – 3.4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 4.2 – 0.88 – 2.25 – 8.8 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 1.7 – 0.36 – 0.9 – 2.4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ (VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ 0.64 1.6 4.2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.51 1.3 3.4 ÎÎÎ ÎÎÎ ÎÎÎ 0.88 2.25 8.8 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.36 0.9 2.4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Input Current ÎÎÎÎ ÎÎÎÎ Iin ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ± 0.1 ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ±0.00001 ÎÎÎÎ ÎÎÎÎ ± 0.1 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ± 1.0 ÎÎÎ ÎÎÎ /C0109Adc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Input Capacitance (Vin = 0) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Cin ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 7.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ pF ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Quiescent Current (Per Package) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IDD ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.25 0.5 1.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.0005 0.0010 0.0015 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.25 0.5 1.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 7.5 ÎÎÎ ÎÎÎ ÎÎÎ /C0109Adc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Total Supply Current (3) (4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IT ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ IT = (0.3 /C0109A/kHz) f + IDD/N IT = (0.6 /C0109A/kHz) f + IDD/N IT = (0.9 /C0109A/kHz) f + IDD/N ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0109Adc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25 /C0095C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in /C0109A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
- The formulas given are for the typical characteristics only at 25 /C0095C.
- Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
*All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. Figure 1. Switching Time Test Circuit and Waveforms
http://onsemi.com CIRCUIT SCHEMATIC NOR, OR GATES VSS 3, 4, 10, 11 VDD VSS VDD *Inverter omitted in MC14001B 1, 6, 8, 13 2, 5, 9, 12 9, 6, 10 VSS VDD 1, 3, 11 2, 4, 12 VSS VDD VSS VDD 8, 5, 13 MC14001B, MC14071B One of Four Gates Shown MC14025B One of Three Gates Shown *Inverter omitted in MC14025B CIRCUIT SCHEMATIC NAND, AND GATES 3, 4, 10, 11 VSS VDD *Inverter omitted in MC14011B 9, 6, 10 VSS VDD *Inverter omitted in MC14023B 2, 5, 9, 12 1, 6, 8, 13 2, 4, 12 1, 3, 11 VDD VDD VSS VSS 8, 5, 13 MC14011B, MC14081B One of Four Gates Shown MC14023B, MC14073B One of Three Gates Shown
http://onsemi.com Device Package Shipping† MC14001BCP PDIP−14
25 Units / RailMC14001BCPG PDIP−14
(Pb−Free) MC14001BD SOIC−14
55 Units / RailMC14001BDG SOIC−14
(Pb−Free) MC14001BDR2 SOIC−14
2500 Units / Tape & Reel
MC14001BDR2G SOIC−14 (Pb−Free) MC14001BDTR2 TSSOP−14* MC14001BDTR2G TSSOP−14* (Pb−Free) MC14001BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14001BFELG SOEIAJ−14
(Pb−Free) MC14011BCP PDIP−14
25 Units / RailMC14011BCPG PDIP−14
(Pb−Free) MC14011BD SOIC−14
55 Units / RailMC14011BDG SOIC−14
(Pb−Free) MC14011BDR2 SOIC−14 MC14011BDR2G SOIC−14 (Pb−Free) MC14011BDTR2 TSSOP−14* MC14011BDTR2G TSSOP−14* (Pb−Free) MC14011BF SOEIAJ−14
50 Units / RailMC14011BFG SOEIAJ−14
(Pb−Free) MC14011BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14011BFELG SOEIAJ−14
(Pb−Free) MC14023BCP PDIP−14
25 Units / RailMC14023BCPG PDIP−14
(Pb−Free) MC14023BD SOIC−14
55 Units / RailMC14023BDG SOIC−14
(Pb−Free) MC14023BDR2 SOIC−14
2500 Units / Tape & ReelMC14023BDR2G SOIC−14
(Pb−Free) MC14023BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14023BFELG SOEIAJ−14
(Pb−Free)
http://onsemi.com Device Shipping†Package MC14025BCP PDIP−14
25 Units / RailMC14025BCPG PDIP−14
(Pb−Free) MC14025BD SOIC−14
55 Units / RailMC14025BDG SOIC−14
(Pb−Free) MC14025BDR2 SOIC−14
2500 Units / Tape & ReelMC14025BDR2G SOIC−14
(Pb−Free) MC14025BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14025BFELG SOEIAJ−14
(Pb−Free) MC14071BCP PDIP−14
25 Units / RailMC14071BCPG PDIP−14
(Pb−Free) MC14071BD SOIC−14
55 Units / RailMC14071BDG SOIC−14
(Pb−Free) MC14071BDR2 SOIC−14
2500 Units / Tape & ReelMC14071BDR2G SOIC−14
(Pb−Free) MC14071BDT TSSOP−14*
96 Units per RailMC14071BDTG TSSOP−14*
(Pb−Free) MC14071BDTR2 TSSOP−14*
2500 Units / Tape & ReelMC14071BDTR2G TSSOP−14*
(Pb−Free) MC14071BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14071BFELG SOEIAJ−14
(Pb−Free) MC14073BCP PDIP−14
25 Units / RailMC14073BCPG PDIP−14
(Pb−Free) MC14073BD SOIC−14
55 Units / RailMC14073BDG SOIC−14
(Pb−Free) MC14073BDR2 SOIC−14
2500 Units / Tape & ReelMC14073BDR2G SOIC−14
(Pb−Free) MC14073BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14073BFELG SOEIAJ−14
(Pb−Free)
http://onsemi.com Device Shipping†Package MC14081BCP PDIP−14
25 Units / RailMC14081BCPG PDIP−14
(Pb−Free) MC14081BD SOIC−14
55 Units / RailMC14081BDG SOIC−14
(Pb−Free) MC14081BDR2 SOIC−14 MC14081BDR2G SOIC−14 (Pb−Free) MC14081BDTR2 TSSOP−14* MC14081BDTR2G TSSOP−14* (Pb−Free) MC14081BFEL SOEIAJ−14
2000 Units / Tape & ReelMC14081BFELG SOEIAJ−14
(Pb−Free) MC14082BCP PDIP−14
2000 Units / BoxMC14082BCPG PDIP−14
(Pb−Free) MC14082BD SOIC−14
55 Units / RailMC14082BDG SOIC−14
(Pb−Free) MC14082BDR2 SOIC−14
2500 Units / Tape & ReelMC14082BDR2G SOIC−14
(Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free.
http://onsemi.com PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 B A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L N 0.015 0.039 0.38 1.01 /C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F HG D K C SEATING PLANE N −T− 14 PL M0.13 (0.005) L M J 0.290 0.310 7.37 7.87
http://onsemi.com PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− −B− G P 7 PL 14 8 M0.25 (0.010) B M SBM0.25 (0.010) A ST −T− FR X 45 SEATING PLANE D 14 PL K C JM /C0095 DIM MIN MAX MIN MAX INCHESMILLIMETERS A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 7.04 14X 0.58 14X 1.52 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SU0.15 (0.006) T 2X L/2 SUM0.10 (0.004) V ST L −U− SEATING PLANE 0.10 (0.004) −T− ÇÇÇ ÇÇÇ SECTION N−N DETAIL E J J1 K ÉÉÉ ÉÉÉ DETAIL E F M −W− 0.25 (0.010) 814 PIN 1 IDENT. HG A D C B SU0.15 (0.006) T −V− 14X REFK N N 7.06 14X 0.36 14X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com PACKAGE DIMENSIONS SOEIAJ−14 CASE 965−01 ISSUE A HE DIM MIN MAX MIN MAX INCHES --- 2.05 --- 0.081 MILLIMETERS 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 BSC 0.050 BSC 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 A HE LE /C009510 /C00950 /C009510 /C0095 LE /C0095 NOTES: /C8195/C81991. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /C8195/C81992. CONTROLLING DIMENSION: MILLIMETER. /C8195/C81993. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. /C8195/C81994. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. /C8195/C81995. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). D Z E 14 8 e A b VIEW P c L DETAIL P M A b c D E e 0.50 M Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MC14001B/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca l Sales Representative