MC13224V FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved. Freescale Semiconductor Product Preview This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Document Number: MC1322x Rev. 1.7 06/2008 MC13224V
Package Information
99-Pin [9.5X9.5X1.2mm]
Ordering Information
Device Device Marking Package MC13224V1 1 See Table 1 for more details. 13224V LGA MC13224VR21 13224V LGA
1 Introduction
The MC13224V is Freescale’s third-generation ZigBee platform which incorporate a complete, low power, 2.4 GHz radio frequency transceiver, 32-bit ARM7 core based MCU, hardware acceleration for both the IEEE
802.15.4 MAC and AES security, and a full set of MCU
peripherals into a 99-pin LGA Platform-in-Package (PiP). The MC13224V solution can be used for wireless applications ranging from simple proprietary point-to-point connectivity to complete ZigBee mesh networking. The MC13224V is designed to provide a highly integrated, total solution, with premier processing capabilities and very low power consumption. The MC13224V MCU resources offer superior processing power for ZigBee applications. A full 32-bit ARM7TDMI-S core operates up to 26 MHz. A 128 Kbyte FLASH memory is mirrored into a 96 Kbyte RAM for upper stack and applications software. In addition, an 80 Kbyte ROM is available for boot software, standardized IEEE 802.15.4 MAC and MC13224V Advanced ZigBee™ - Compliant Platform-in-Package (PiP) for the 2.4 GHz IEEE® 802.15.4 Standard
Contents
8 Preliminary Mech anical Diagrams
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transceiver packet data complement the processor core. package except the crystal and antenna. Figure 1. MC13224V RF Radio Interface including sleep or restricted performance operation.
- Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HV AC) — Automated meter reading (AMR)
- Industrial Control ANALOG TRANSMITTER ANALOG RECEIVER RF TX/RX SWITCH BALUN LNA PA
- Health Care — Patient monitoring — Fitness monitoring
- Consumer — Remote control — Entertainment systems — Cellular phone attach
1.1 Ordering Information
Table 1. Orderable Parts Details
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This section provides a simplified block diagram and highlights MC13224V features.
2.1 Block Diagram
Figure 2 shows a simplified block diagram of the MC13224V . Figure 2. MC13224V Simplified Block Diagram
2.2 Features Summary
- IEEE 802.15.4 standard complian t on-chip transceiver/modem — 2.4 GHz ISM Band operation — 16 selectable channels — Programmable transmitter output pow er (-30 dBm to +4 dBm typical) — World-class receiver sensitivity – < -96 dBm typical receiver sensitivity using DCD mode (<1% PER, 20-byte packets) – < -100 dBm typical receiver sensitivity us ing NCD mode (<1% PER, 20-byte packets)
- Hardware acceleration fo r IEEE 802.15.4 applications — MAC accelerator (seque ncer and DMA interface) TIMER MODULE (TMR) (4 Tmr Blocks) UART MODULE (UART0) UART MODULE (UART1) SYNC SERIAL INTERFACE (SSI/i2S) KEYBOARD INTERFACE (KBI) INTER-IC BUS MODULE (I2C) SERIAL PERIPHERAL INTERFACE (SPI) DUAL 12-BIT ADC MODULE GPIO and IO CONTROL UP TO 64 IO PINS ARM7 TDMI-S 32-BIT CPU BUS INTERFACE & MEMORY ARBITRATOR ARM INTERRUPT CONTROLLER (AITC) JTAG/ Nexus DEBUG ADVANCED SECURITY MODULE (ASM) CLOCK & RESET MODULE (CRM) RADIO INTERFACE MODULE (RIF) 96KBYTE SRAM (24K WORDS x
32 BITS)
MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 5 — Advanced encryption/decryption hardware engine (AES 128-bit)
- Supports standard IEEE 802.15.4 si gnaling with 250 kbps data rate
- 32-bit ARM7TDMI-S CPU core with programmable performance up to 26 MHz (24 MHz typical)
- Extensive on-board memory resources — 128 Kbyte serial FLASH memory (will be mirrored into RAM) — 96 Kbyte SRAM — 80 Kbyte ROM
- Best-in-class power dissipation — 21mA typical RX current draw (DCD mode) with radio and MCU active — 28 mA typical TX current draw with radio and MCU active (coin cell capable) — 5mA maximum current draw with MCU active (radio off) — 0.9mA maximum current with MCU idle (radio off) — 1.1 μA maximum Hibernate current (retain 8 Kbyte SRAM contents) — 0.3 μA maximum Off current (device in reset)
- Extensive sleep mode control and variation — Hibernate and Doze low power modes — Programmable degree of power down — Clock management — Onboard 2kHz oscillator for wake-up timer. — Optional 32.768 kHz crystal oscill ator for accurate real-time sleep mode timing and wake-up with a possible sleep period greater than 36.4 hours — Wake-up through programmable timer, extern al real-time interrupts, or ADC timer
- Extensive MCU peripherals set — Dedicated 802.15.4 modem/radio interface module (RIF) — Dedicated NVM SPI interface for managing FLASH memory — Two dedicated UART modules capable of 2Mbps with CTS/RTS support — SPI port with programmable master and slave operation — 8-pin keyboard interface (KBI) supports up to a 4x4 matrix. Also, provides up to 4 asynchronous interrupt inputs for wake-up — Two 12-bit analog-to-digital convert ers (ADCs) share 8 input channels — Four independent 16-bit timers with PWM capa bility. These can cascade in combinations up to 64-bit operation — Inter-integrated circuit (I 2C) interface — Synchronous Serial Interface (SSI) with I 2S and SPI capability and FIFO data buffering — Up to 64 programmable I/O sh ared by peripherals and GPIO
- Powerful In-circuit debug and FLASH pr ogramming available via on-chip debug ports — JTAG debug port — Nexus extended feature debug port
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- System protection features — Low battery detect — Watchdog timer (COP) — Sleep mode timer
- Low external component count — Only antenna needed for single-ended 50- Ω RF interface (balun in package) — Only a single crystal is required for the main os cillator; programmable crystal load capacitors are on-chip — All bypass capacitors in package
- Supports single crystal reference clock source (typical 24 MHz crystal with 13 - 26 MHz usable) with on-chip programmable crystal load capacitance or external frequency source. Also provides onboard 2kHz oscillator for wake-up timing or an optional 32.768 kHz crystal for accurate low power timing.
- 2.0V to 3.6V operating voltage w ith on-chip voltage regulators; down to 1.8V with off-chip regulation
- Optional buck converter fo r better battery life.
- -40°C to +105°C temperature range
- RoHS-compliant 9.5mm x 9.5mm x 1.2mm 99-pin LGA package 2.3 High Density, Low Component Count, Integrated IEEE 802.15.4 Solution The MC13224V is more than a high performance, low power platform-in-a-package IEEE 802.15.4 solution. Not only are the transceiver (radio) and MCU on an SoC, the packaged solution contains a 128 Kbyte serial FLASH memory, onboard bypass capacitors for critical nodes, and RF components that present a single-ended 50-Ω interface for an external antenna. The radio is a full differential design with an on-chip transmit/receive (TX/RX) switch, and the PiP also has an onboard balun for differential to singled-ended conversion. On-chip RF matching is also provided to present the proper impedance to the antenna. To further simplify the application, single crystal operation (optimized for 24 MHz) is supported for full radio and MCU operation. If the default 24 MHz crystal is not used, the device supports 13-26 MHz crystals also. The load capacitance to the crystal oscillator is supplied on-chip to eliminate the need for the otherwise required external capacitors. 2.4 Integrated IEEE 802.15.4 Transceiver (Radio and Modem) The MC13224V IEEE 802.15.4 fully-compliant transceiver provides a complete 2.4 GHz radio with 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 5.0 MHz channels and full spread-spectrum encode and decode. The modem supports transmit, receive, clear channel assessment (CCA), Energy Detect (ED), and Link Quality Indication (LQI) as required by the 802.15.4 Standard.
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2.4.1 RF Interface and Usage
The MC13224V RF interface provides for a single-ended, 50-Ω port that connects directly to an antenna. There is an onboard balun that converts the single-ended interface to a full differential, bi-directional, on-chip interface with transmit/receive switch, LNA, and complementary PA outputs. The required port impedance matching is also onboard. This combination allows for a very small footprint and a very low cost RF solution. The receiver demodulator includes a module called the Differential Chip Detector which has two modes of operation:
- Non-coherent Detection (NCD) with automatic frequency control (AFC)
- Non-coherent Differential Chip Detection (DCD) without AFC IEEE 802.15.4 standard allows a maximum clock drift of ±40 ppm (which equals ±80 ppm station-to-station). The MC13224V 802.15.4 demodulator includes two different methods of operating in the presence of such large frequency errors, i.e., NCD and DCD. With DCD mode, RX performance loses ~3.5 dB of sensitivity. Alternately, NCD mode provides an increased ~3.5 dB of sensitivity, however, the addition of the AFC increases the demodulator current drain about 3-4 mA. For longer range applications where external amplification may be desired (LNA and/or PA), additional ports are provided for secondary complementary PA outputs. These can be used as a separate PA interface while the single-ended port through the balun is used as an input only. Also, 4 control pins and a regulated 20 mA voltage source are provided to control external components and supply power to the PA outputs. The RF Interface functionality can be summarized as follows:
- Programmable output power — 0 dBm nominal output power, programmable from -30 to +4 dBm
- Receive sensitivity (at 1% PER, 20-byte packet) - — < -96 dBm (typical) DCD re ceive (well above IEEE 802.15.4 specification of -85 dBm) — < -100 dBm (typical) NCD receive (higher current)
- Single-ended 50- Ω antenna port — Uses integrated tran smit/receive (T/R) switch, LNA, and onboard balun. Impedance matching onboard.
- Maximum flexibility — Optionally, single-ended por t becomes RF input only and a separate set of full differential PA outputs are provided. Separate input and outputs allow for a variety of RF configurations including external LNA and PA for increased range
- Four control signals for external RF components such as a LNA or PA
- Regulated voltage source for PA bias ing and powering external components
2.4.2 Modem
The modem supports the full requirement of the IEEE 802.15.4 Standard to transmit and receive data packets. In additional, the mechanism is present to measure received signal level to provide CCA, ED, and LQI as required by the 802.15.4 Standard.
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2.5 High Performance, Low Power 32-Bit ARM7 Processor
- The ARM7TDMI-S processor is a member of the 32-bit ARM family of general-purpose 32-bit microprocessors that offers high performance with very low-power consumption
- A three stage instruction pipeline (fetch, decode , execute) increases the speed of the flow of instructions to the processor
- Data access can be 8-bit bytes, 16-bit half words, or 32-bit words. Words must be aligned to 4-byte boundaries. Half words must be aligned to 2-byte boundaries
- The ARM7TDMI-S processor supports two instruct ion sets, i.e., the 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb mode incorporates 16-bit instructions for higher code density while retaining all the benefits of a 32-bit architecture, i.e., full 32-bit registers, 32-bit operations, and 32-bit memory transfer. The use of the instruction sets can be intermixed for maximizing performance while retaining higher code density
Figure 3. ARM7TDMI-S 32-Bit CPU Core
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2.6 Low Power Operation and Power Management
The MC13224V is inherently a very low power device, but it also has extensive power management and an onboard buck regulator option to maximize battery life.
2.6.1 Operating Current
The MC13224V operating currents are a function of operating mode. There are two basic low power modes of Hibernate and Doze, and both have options of how much RAM contents are retained. The difference between Hibernate and Doze is that Doze mode keeps the primary reference oscillator running. Highest operating current is when the radio is active for transmit or receive. Refer to Section 6.4, “Supply Current Characteristics” for more details and specifications.
2.6.2 Power Management
The MC13224V power management is controlled through the Clock and Reset Module (CRM). The CRM is a dedicated module to handle MCU clock, reset, and power management functions which includes control of the power regulators. All these functions have impact on attaining lowest power.
2.6.2.1 CRM Features
The CRM features include:
- Control of system reset
- Control clock gating for power savings
- Sleep mode (Hibernate and Doze) management — Degree of chip power down — Retention of programmed parameters — Programmable retention of RAM contents — Clock management
- Wake-up management — Graceful power-up — Clock management — Wake-up via programmable tim er or external interrupts.
- Wake-up timer — For Hibernate mode, based on onboard 2 kH z oscillator or optional 32.768 kHz crystal oscillator — For Doze mode, based on main refe rence oscillator, typically 24 MHz
- Controls reference clocks based on default 24 MHz crystal oscillator or optional 13-26 MHz oscillator with PLL (external filter) for 24 MHz frequency synthesis.
- MCU watchdog timer (COP)
- Software initiated reset
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- Management control of onboard linear regulators and optional buck regulator
2.6.2.2 CRM Operation
The CRM has primary control of the entire system:
- Reset and power up — After release of the hard ware RESETB signal, the CRM will perform a power up sequence of the MCU. The linear regulators and clock sources are managed for a graceful start-up of the MCU and its resources. The radio is not powered until needed
- Normal operation of MCU — The cl ock management of the MCU and its resources are controlled by the CRM. The processor clock is programmable from low frequencies up to the maximum reference frequency (13-26 MHz optional w/24 MHz standard) to allow the application to trade-off processing speed versus power savings
- Sleep modes and recovery — There are two sl eep modes of Hibernate and Doze. The primary difference is that Doze mode keeps the reference oscillator running. Both modes can retain critical programmed parameters and have selectable sizes of RAM retention. Hibernate has lowest power, but Doze allows high accuracy sleep timing. The CRM manages the recovery from low power, similar to power-up from reset, providing regulator and clock management. — Wake-up can be based on external interrupts through 4 KBI inputs — Wake-up can be from internal interrupts — Wake-up can be based on an RTI (wake-up) timer.
- The RTI timer with 2 possible frequency sources provides a very low power wake-up option from sleep — One option is an onboard, lo w accuracy 2 kHz oscillator — A second option is to add an external 32.768 kHz crystal for the RTI clock source — A 32-bit timer allows greater than a 36.4 hour wake-up delay with the 32.768 crystal oscillator
- Other features of the CRM: — An optional COP watchdog timer to monitor CPU program activity — A programmable software reset
2.6.3 Optional Buck Regulator
For battery based applications, an optional buck regulator is provided to maximize battery life. Figure 4 shows the configuration of the buck regulator versus the normal connection. An onboard MOSFET is used as a switch with an external 100μH inductor and 10μF capacitor when the buck regulator is enabled. The buck regulator drops the higher battery voltage to 1.8 - 2.0 Vdc that is applied to the onboard linear regulators. This allows lower net current from the battery to maximize the life of the battery.
Figure 4. Optional Buck Regulator
2.6.4 Battery Detect
to end-of-life for the battery, monitoring charging, and controlling buck regulator operation. includes 802.15.4 MAC acceleration and AES encryption/decryption. control registers. Figure 5 shows a MACA simplified block diagram. MACA facilitates these activities via control of the transceiver and off loads the functions from the CPU. does not require intervention from the CPU. packets. The MACA will also handle ACKs and TxPoll sequences independent of the ARM processor.
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receiving the packet with the first bit of frame length, and finally, will check the FCS. Figure 5. MAC Accelerator Simplified Block Diagram
2.7.1.1 MACA Features
- Sequence Manager sequences / auto sequences — RX only — TX only — Automatic acknowledgment frame r eception on transmitted packets — Automatic acknowledgment frame transmission on received packets — Auto-RX for continuous re ception as coordinator — Auto sequence for transmitted MAC data.request — Assist for efficient res ponse to MAC data.request — Embedded channel assessment in sequence — Support for sequences with slotted mode access — Timer triggered and imme diately executed actions — Support for extended RX for reception in ra ndom backoff and battery life extension — Support for promiscuous mode
- Programmable auto sequence timing - Each CCA, RX, or TX event is an independent operation. The radio gets through a power-up or “warm-up” sequence for each operation (including VCO), TX Packet Buffer RX Packet Buffer Sequencer Timers FCS Generator/ Checker DMA Control Registers MACA To Transceiver Modem To MCU Bus
MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 13 and there is also a power-down or “warm-down” time. Sequences are combinations of radio operations and are highly configurable. — RX warm-up is 72 µs — TX warm-up is 92 µs — Turnaround times – The IEEE 802.15.4 Standard requires a TX-to-RX or a RX-to-TX turnaround time to be less than or equal to 12 symbols times (192 µs). – Best practice for maximum station-to-stati on performance is to minimize TX-to-RX turnaround time and to maximize (within spec) RX-to-TX turnaround time. – Auto sequences should use r ecommended turnaround times of: a) 11 symbols times (176 µs) RX-to-TX b) 96 µs TX-to-RX.
- Dedicated DMA for transfer of TX/RX data from/to RAM (minimum bus clock of 2 MHz for 802.15.4 modem operation)
- Maskable, event-driven interrupt generation
- Address header filtering for rece ived packets. A promiscuous mode allows bypass of the filtering for monitoring network traffic
- Packet manager — Handles preamble data — Handles frame check sequence (FCS) a.k.a CRC — Embedded header filter for received packets
- Beacon Support Mode
- Control/status registers mapped into CPU memory map
- 32-Bit random number generator — Runs at the bus clock rate, a 32-bit Linear Feedback Shift Register (LFSR) can be set with a seed value and uses a 32-bit primitive polynomial. A 32-bit random number is fetched with every read of the proper control register
2.7.2 Advanced Security Module (ASM)
The IEEE 802.15.4 Standard and the ZigBee Standard both provide for optional use of data encryption.The ASM engine is a hardware block that accelerates encryption/decryption using the Advanced Encryption Standard (AES). The engine can perform “Counter” (CTR) and Cipher Block Chaining (CBC) encryption. The combination of these two modes of encryption are known as CCM mode encryption. CCM is short for Counter with CBC-MAC. CCM is a generic authenticate and encrypt block cipher mode. CCM is only defined for use with 128 bit block ciphers, such as AES. The definition of CCM mode encryption is documented in the NIST publication SP800-38C. The ASM has the following features:
- 32-Bit wide bus interface
- CTR encryption in 13 clock cycles
- CBC encryption in 13 clock cycles
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- Encrypts 128 bits as a unit
- The 128-bit registers are ali gned on quad word boundaries (16 byte)
- Self-test mode
- Maskable “action complete” interrupt 3M e m o r y The MC13224V memory resources consist of RAM, ROM, and serial FLASH.
3.1 RAM and ROM
The RAM and ROM features include:
- 96 Kbytes RAM. — RAM0: 8 Kbytes, 2 Kwords (2048 x 32 bits) — RAM1: 24 Kbytes, 6 Kwords (6144 x 32 bits) — RAM2: 32 Kbytes, 8 Kwords (8192 x 32 bits) — RAM3: 32 Kbytes, 8 Kwords (8192 x 32 bits)
- All read or write accesses require a minimum of two system clock cycles
- Stall signal generated for read after write cycles
- Clock is enabled only on the accessed memory device for low power consumption
- RAMs have been divided to allow for power sa vings. While sleeping, the above RAM blocks can be turned off (combinations include 8, 32, 64, and 96 Kbytes active) and the RAM remainder can be placed in a low voltage mode for data retention. If more RAMs are turned on, then less battery life will be achieved. Depending on the amount of RAM powered during sleep, the boot time may be longer with less RAM as the non-powered RAM must be reloaded from FLASH.
- 80 Kbytes ROM — 20 Kwords (20480 x 32 bits) — Initially contains bootstrap code, 802.15.4 MAC ( no security), UART driver, and SPI driver. The MAC software builds on the lower level hardware capability of the transceiver and MACA. All code except the bootstrap is “patchable”. — Can be extended later to communications st ack software and NVM services (erase, program, and read routines)
3.2 Serial FLASH (NVM)
The MC13224V also contains a 128 Kbyte serial FLASH memory that can be mirrored into the 96 Kbyte RAM. The serial FLASH is accessed via an internal dedicated SPI module (SPIF). The FLASH erase, program, and read capability are programmed through the SPIF port. The FLASH is accessed at boot time to load/initialize RAM. All actual CPU program and data access is from RAM or ROM.
4 MCU Peripherals
The MC13224V has a rich set of MCU peripherals. Figure 6 shows the peripheral modules. Figure 6. MCU Peripherals
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4.1 Parallel IO (GPIO)
The parallel I/O features include:
- A total of 64 general-purpose I/O pins
- Individual control (direction and output st ate) for each pin when in GPIO mode
- Pad hysteresis enables
- Software-controlled pull-ups/ pull-downs on each input pin
- When not used as GPIO, the IO provide alternative functions — Debug ports for JTAG (four signals) and Nexus (fourteen signals) modules — Four control signals for external RF componen ts such as an LNA, PA, and antenna switch — Eight analog inputs for ADC input channels — Four signals for ADC reference voltages — Eight signals for UART1 and UART2 —T w o I 2C signals — Four timer block signals — Four SPI block signals — Four SSI block signals — Eight KBI signals
- Eight KBI pins are kept alive during Hibernate or Doze. Four KBI are output and four are inputs. The input can be used as wake-up interrupts
4.2 Keyboard Interface (KBI)
The MC13224V designates 8 pins (KBI_0 to KBI_7) as a keyboard interface, where four of these signals typically are outputs and four are inputs (KBI_4 to KBI_7) that support interrupts. These 8 pins could typically be used as a matrix interface to support up to 16 switches or buttons, such as a keypad. These signals can also be used as general purpose IO if a keyboard is not present. During Hibernate or Doze, the KBI are unique in that they are kept alive. Four KBI are outputs and four KBI are inputs. The inputs can be enabled as asynchronous interrupts to wake-up the MC13224V from the sleep mode.
4.3 Timer (TMR) Module
range of operational modes is useful for many control and sensor applications. Figure 7 shows a block diagram of an individual timer group. Figure 7. Timer Group Block Diagram register, two compare registers, and status and control registers.
- Load Register — Provides the ini tialization value to the counter when the counter’s terminal value has been reached
- Hold Register — Captures the counter’s value wh en other counters are being read. This feature supports the reading of cascaded counters
- Capture Register — Enables an external signal to take a snap shot of the counter’s current value
- COMP1 and COMP2 Registers — Provides the values to which the counter is compared. If a match occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated (if enabled), and the new compare value is loaded into the COMP1 or COMP2 registers from CMPLD1 and CMPLD2 if enabled CMPLD1 COMP1 LOAD HOLD STATUS AND CONTROL CMPLD2 COMP2 COUNTER Comparator Comparator CAPTURE M U X Prescaler M U X Peripheral Reference Clock Other Counter Reference OFLAG Output External MCU DATA BUS
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- The Prescaler provides different time ba ses useful for clocking the counter/timer
- The Counter provides the ability to count internal or external events
- Control and Status Registers — Provides operationa l mode control of the counter, status, clock source control, interrupt control, and external interface control Four GPIO pins (TMR0 -TMR3) are programmable and can be used with any counter/timer group. The TMR module feature include:
- Four 16-bit counters/timers groups
- Up/down count
- Counters are cascadable for up to 64 bit delay counter
- Programmable count modulo.
- Peripheral reference clock equates to reference oscillator frequency
- External clock max count rate equa ls peripheral clock divided by 2
- Internal clock max count ra te equals peripheral clock.
- Count once or repeatedly
- Counters are preloadable
- Compare registers are preloadable
- Counters share available 4 GPIO pins (programmable as inputs or outputs and programmable for falling or rising edge)
- Separate prescaler for each counter
- Each counter has capture and compare capability
- Optional input glitch filter
- Functional modes include stop, count, edge-count, gated-count, quadrature-count, signed-count, triggered-count, one-shot, cascade-count, pulse-output, fixed frequency PWM, and variable-frequency PWM
4.4 UART Modules
The MC13224V has two universal asynchronous receiver/transmitter (UART) modules. Each UART has an independent fractional divider, baud rate generator that is clocked by the peripheral bus clock (typically 24 MHz) which enables a broad range of baud rates up to 1,843.2 kbaud. Transmit and receive use a common baud rate for each module. Each UART provides the following features:
- 8-bit only data
- One or two stop bits
- Programmable parity (even, odd, and none)
- Four-wire serial interface (RXD, TXD, RTS, and CTS)
- Hardware flow control support for RTS and CTS signals
- 32-byte receive FIFO a nd 32-byte transmit FIFO
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- Programmable sense for RTS/CT S pins (high true/low true)
- Status flags for various fl ow control and FIFO states
- Receiver detects framing errors, st art bit error, break characters, parity errors, and overrun errors.
- V oting logic for improved noise immunity (16X/8X oversampling)
- Maskable interrupt request
- Time-out counter, which times out after eight non-present characters
- Receiver and transmitter enable/disable
- Low-power modes
- Baud rate generator to provide any multipl e-of-2 baud rate between 1.2 kbaud and 1,843.2 kbaud
4.5 Inter-Integrated Circuit (I 2C) Module
The MC13224V provides an Inter-Integrated Circuit (I2C) module for the I2C which is a two-wire, serial data (SDA) and serial clock (SCL), bidirectional serial bus. The I2C allows for data exchange between the MC13224V and other devices such as MCUs, serial EEPROM, serial ADC and DAC devices, and LCDs. The I2C minimizes interconnections between devices and is a synchronous, multi-master bus that allows additional devices to be connected and still handle system expansion and development. The bus includes collision detection and arbitration to prevent data corruption if two or more masters attempt to simultaneously control the I2C. The I2C module is driven by the peripheral bus clock (typically 24 MHz) and the SCL bit clock is generated from a prescaler. The prescaler divide ratio can be programmed from 61,440 to 160 (decimal) which gives a maximum bit clock of 150 kbps. The I2C module supports the following features:
- Two-wire (SDA and SCL) interface
- Multi-master operation
- Master or slave mode
- Arbitration lost interrupt with automati c mode switching from master to slave
- Calling address iden tification interrupt
- START and STOP signal generation/detection
- Acknowledge bit generation/detection
- Bus busy detection
- Software-programmable bit clock frequency up to 150 kbps
- Software-selectable acknowledge bit
- On-chip filtering for spikes on the bus
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4.6 Serial Peripheral Interface (SPI) Modules
The MC13224V has two SPI modules that use a common architecture
4.6.1 External SPI Module
The MC13224V offers a dedicated Serial Peripheral Interface (SPI) module for external use. The SPI is a high-speed synchronous serial data input/output port used for interfacing with serial memories, peripheral devices, or other processors. The SPI allows a serial bit stream of a programmed length (1 to 32 bits) to be shifted simultaneously into and out of the device at a programmed bit-transfer rate (called 4-wire mode). There are four pins associated with the SPI port (SPI_SCK, SPI_MOSI, SPI_MISO, and SPI_SS). The SPI module can be programmed for master or slave operation. It also supports a 3-wire mode where for master mode the MOSI becomes MOMI, a bidirectional data pin, and for slave mode the MISO becomes SISO, a bidirectional data pin. In 3-wire mode, data is only transferred in one direction at a time. The SPI bit clock is derived from the peripheral reference clock (typically 24 MHz with a maximum of 26 MHz). A prescaler divides the peripheral reference clock with a programmed divide ratio from 2 to 256. Typical bit clock range will be from 12 MHz to 93.75 kHz. The SPI has the following features:
- Master or slave mode operation
- Data buffer is 4 bytes (32 bits) in length
- SPI transfer length program mable from 1 to 32 bits
- MSB-first shifting
- Programmable transmit bit rate (typically 12 MHz max)
- Serial clock phase and polarity options
- Full-duplex (4-wire) or bidire ctional data (3-wire) operation
- SPI transaction can be polled or interrupt driven
- Slave select signal
- Low Power (SPI Master uses ga ted clocks. SPI Slave clock derived completely from SPI_SCK.)
4.6.2 SPI FLASH Module (SPIF)
The SPIF is an internal SPI block dedicated to control, reading, and writing of the serial FLASH memory (NVM). It uses the same architecture as the general SPI block, but will be limited by the characteristics of the FLASH SPI interface.
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4.7 Synchronous Serial Interface (SSI) Module
The MC13224V provides a versatile Synchronous Serial Interface (SSI) which is a full-duplex, serial port that allows communication with a variety of serial devices. These serial devices can be digital signal processors (DSPs), MCUs, peripherals, popular industry audio CODECs, and devices that implement the Inter-Integrated Circuit sound bus standard (I2S). The SSI typically transfers samples in a periodic manner and it consists of independent transmitter and receiver sections with common clock generation and frame synchronization. The external signals include the bit clock (SSI_BITCK), frame sync (SSI_FSYN), RX data (SSI_RX), and TX data (SSI_TX). The SSI has the following basic operating modes all with synchronous protocol:
- Normal mode — The simplest SSI mode transfers data in one time slot per frame
- Network mode — Creates a Time Division Mult iplexed (TDM) network, such as a TDM CODEC network or a network of DSPs
- Gated Clock mode — Connects to SPI-type inte rfaces on MCUs or external peripheral chips With its multi-modes, the SSI can be programmed for two very useful functions:
- A second SPI port augmen ting the MC13224V SPI module
- I 2S interface - the SSI is capable of generating the required clock frequencies and data format to drive a serial stereo audio DAC The SSI includes the following features:
- Synchronous transmit and receive s ections with shared internal/external clocks and frame syncs operating in Master or Slave mode
- Normal mode operation using frame sync
- Network mode operation allowing mu ltiple devices to share the port with as many as thirty-two time slots
- Gated Clock mode opera tion requiring no frame sync
- Transmit and Receive FIFOs. Each of the FIFOs is 8x24 bits. The TX/RX FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception
- Programmable data interface modes such as I 2S, LSB, MSB aligned
- Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
- Program options for frame sync and clock generation
- Programmable I 2S modes (Master, Slave or Normal). Oversampling clock available as output in I2S Master mode
- External SSI_BITCLK input for use in I 2S Master mode. Programmable oversampling clock of the sampling frequency available as output in master mode, when operated in sync mode
- Programmable internal clock divider
- Time Slot Mask Registers for reduced CPU overhead (for both TX and RX)
- SSI power-down feature
MC13224V Product Preview, Rev. 1.7
22 Freescale Semiconductor
4.8 Analog-to-Digital Converter (ADC) Module
The MC13224V ADC module provides two 12-bit analog-to-digital converters (ADC1 and ADC2) with 8 external channels (ADC7 - ADC0) that can be multiplexed to either ADC. ADC1 can also sample the battery voltage for monitoring purposes. External pins (ADC2_VREFH, ADC2_VREFL, ADC1_VREFH, and ADC1_VREFL) are provided for independent ADC reference voltages. The minimum sample time is 20 us. Figure 8 shows a block diagram of the ADC module. Each ADC can be programmed to scan multiple selected channels on a timed basis. The primary clock to the ADC module is the peripheral reference clock (typically 24 MHz). For the time period between scan sequences, the primary clock is first divided by an 8-bit prescale (1-255), and the derived clock drives both the 32-bit delay timer and the ADC sequencer. Each ADC has its own delay timer and sequencer. Once a scan sequence has been initiated, all selected channels can be sampled. Registers are provided to define thresholds that can be enabled for the sampled channels. A threshold can be assigned to a specific channel and can be programmed to be a less-than or greater-than threshold. Multiple thresholds can be assigned to a single channel. Warm-up of the analog portion of the ADC circuitry is provided for power management, and a separate 300 kHz ADC clock must be programmed via its own divider. The battery monitor has two (2) dedicated threshold registers to set the high and low limits of the battery sample channel. Sample values are stored in a 8x16-bit FIFO. The FIFO accumulates samples from both ADCs, and the 12-bit sample value and a 4-bit channel tag are saved for each sample. The FIFO is read by the CPU from a register address. The module can be programmed to interrupt the processor based on the timed sample activity. Sample activity, sequencer activity, or FIFO “fullness” can all be enabled to generate an interrupt. The ADCs can also be overridden to sample on command as opposed to sequencer, time-based activity.
Figure 8. ADC Module Block Diagram
- 12 bit resolution
- Separate input voltage ranges: VREFH to VREFL. Max input of 3.6 Vdc. Min input of 0.0 Vdc
- Typical resolution of 10.5 bits
- Conversion rate has a minimum sample time of 20us. Effective number of bits varies with sample rate.
- 8-bit prescaler to provide the time base for the 32-bit timers
- Two independent channels, each with a 32-bit timer
- Simultaneous channel sampling or seque ntial channel sampling with dual ADCs
- On-board battery detect sample channel
- Primary ADC has 9 channels. 8 exte rnal channels plus battery detect
- Secondary ADC has 8 external channels
- Active channels for each ADC are programmable
- A maximum of 8 active monitors can generate a interrupt request
- A 8-deep FIFO for recording data ( 12-bit sample plus 4-bit channel tag)
- Interrupt requests can be generated by the channel compare values, end-of-scan sequence, out-of-range, FIFO status, and 32-bit timers
- Independent soft reset M U X M U X Analog Channels ADC0 - ADC7 Battery ADC1 ADC2 FIFO (8 x 16-Bit, 12-bit value + 4- bit channel Tag) Control Registers Divider M U X Control Override Mode Sequencer M U X Control Override Mode Sequencer Compare MCU DATA BUS Prescaler Analog ADC2 Mux Sel ADC1 Mux Sel ADC1 Enable ADC2 Enable ADC Clock ADC Clock 32-Bit Timer 32-Bit Timer Peripheral Reference Clock 300 kHz
24 Freescale Semiconductor
5 Pin Assignments and Connections
Figure 9. MC13224V Pinout (Top View; active bottom pads shown)
- Only active substrate bottom pads are shown.
- Additional substrate pads (see mechanical drawings)
no connect and are for mechanical attach only.
5.1 Pin Definitions
Table 2 details the MC13224V pinout and functionality. Table 2. Pin Function Description
1 ADC0 Analog Input
2 ADC1 Analog Input
3 ADC2 Analog Input
4 ADC3 Analog Input
5 ADC4 Analog Input
6 ADC5 Analog Input
7 ADC6 Analog Input
8 ADC7_RTCK Analog Input
TCK for JTAG to support adaptive clocking.
9 TDO Digital
JTAG debug port serial data output.
10 TDI Digital
JTAG Test Data Input / GPIO48 JTAG debug port serial data input.
11 TCK Digital
JTAG Test Clock Input / GPIO47 JTAG debug port clock input.
12 TMS Digital
JTAG debug port test mode select input.
13 UART2_RTS Digital
14 UART2_CTS Digital
15 UART2_RX Digital
UART2 RX data input / GPIO19 UART2 receive data input.
16 UART2_TX Digital
26 Freescale Semiconductor
17 UART1_RTS Digital
18 UART1_CTS Digital
19 UART1_RX Digital
UART1 RX data input / GPIO15 UART1 receive data input.
20 UART1_TX Digital
21 I2C_SDA Digital
22 I2C_SCL Digital
23 TMR3 Digital
24 TMR2 Digital
25 TMR1 Digital
26 TMR0 Digital
27 SPI_SCK Digital
SPI Port clock / GPIO7 SPI port clock.
28 SPI_MOSI Digital
29 SPI_MISO Digital
30 SPI_SS Digital
SPI Port SS / GPIO4 SPI Port Slave Select (SS) signal.
31 SSI_BITCK Digital
SSI Bit Clock / GPIO3 SSI serial TX/RX clock and is bi-directional.
32 SSI_FSYN Digital
33 SSI_RX Digital
SSI RX data input / GPIO1 SSI serial RX data input.
34 SSI_TX Digital
SSI TX data output / GPIO0 SSI serial TX data output.
35 KBI_7 Digital
Asynchronous interrupt input.
36 KBI_6 Digital
Asynchronous interrupt input. Table 2. Pin Function Description (continued)
37 KBI_5 Digital
Asynchronous interrupt input.
38 KBI_4 Digital
Asynchronous interrupt input.
39 KBI_3 Digital
Used as output for keyboard interface.
40 KBI_2 Digital
Used as output for keyboard interface.
41 KBI_1 Digital
Used as output for keyboard interface.
42 KBI_0_HST
(based on a timer) to external device.
43 COIL_BK Power Switch
external coil, driven by onboard MOSFET.
44 LREG_BK_FB Power Input Voltage input to onboard
- When using onboard buck converter, connect to load side of coil.
- When not using buck converter, connect to VBATT.
45 VBATT Power Input High side supply voltage to buck
46 RF_PLL_FLT Analog
frequency other than 24 MHz (13-26 MHz).
- No Connect for 24 MHz crystal. 47 XTAL_32_IN Analog Input Optional 32.768 kHz crystal oscillator input Connect to 32.768 kHz crystal 48 XTAL_32_OUT Analog Output Optional 32.768 kHz crystal oscillator output Connect to 32.768 kHz crystal
49 XTAL_24_OUT Analog Output Primary 24 MHz crystal
- Connect to 13-26 MHz crystal (24 MHz default).
- No load capacitor required
- Do not load with any capacitance.
50 XTAL_24_IN Analog Input Primary 24 MHz crystal
- Connect to 13-26 MHz crystal (24 MHz default).
- No load capacitor required
- Do not load with any capacitance.
51 RESETB Digital Input System reset input Active low, asynchronous reset
52 TX_ON Digital
28 Freescale Semiconductor
53 PA_NEG RF Output RF power amplifier (PA) ouput
- Open drain. Must be connected to RF_BIAS through a bias network.
- Only used for external dual port operation.
- Do not use for single port operation. No Connect.
54 PA_POS RF Output RF power amplifier (PA) ouput
- Open drain. Must be connected to RF_BIAS through a bias network.
- Only used for external dual port operation.
- Do not use for single port operation. No Connect.
55 RF_BIAS Analog Power
PA_POS and PA_NEG through bias networks.
56 ANT_1 Digital input /
57 ANT_2 Digital input /
58 RF_GND Power Input RF ground. Connect to ground VSS.
59 RX_ON Digital input /
60 RF_RX_TX RF
- Interfaces to onboard balun. 50 Ω impedance
- Full bidirectional port with onboard T/R switch.
- Used as single-ended RF input port for dual port operation with PA_NEG and PA_POS PA outputs.
61 ADC2_VREFL Analog Input
62 ADC1_VREFL Analog Input
63 ADC1_VREFH Analog Input
64 ADC2_VREFH Analog Input
75-79 VSS Power input External package GND pads. 84-88 VSS Power input External package GND pads. 93-97 VSS Power input External package GND pads.
102 MDO01 Digital
Nexus debug port message data output Bit 1.
103 MDO00 Digital
Nexus debug port message data output Bit 0. VSS Power input External package GND pads.
111 MDO03 Digital
Nexus debug port message data output Bit 3.
112 MDO02 Digital
Nexus debug port message data output Bit 2.
113 MSEO1_B Digital
Bit 1. Signal is active low.
114 MSEO0_B Digital
Bit 0. Signal is active low. 115 VSS Power input External package GND pads.
120 MDO05 Digital
Nexus debug port message data output Bit 5.
121 MDO04 Digital
Nexus debug port message data output Bit 4.
122 RDY_B Digital
123 EVTO_B Digital
124 DIG_REG Digital Power
digital logic core. No Connect,.
129 MDO07 Digital
Nexus debug port message data output Bit 7.
130 MDO06 Digital
Nexus debug port message data output Bit 6.
131 MCKO Digital
Nexus debug port message clock output.
132 EVTI_B Digital
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5.2 Hardware Development Interface Interconnects
The MC13224V supports two development hardware interfaces.
5.2.1 ARM JTAG Interface Connector
133 NVM_REG NVM Power
FLASH (NVM) VDD supply. VDD supply to FLASH. Typically No Connect. 1 Pins described as GPIO have an alternative general purpose I/O function. Table 3. ARM JTAG 20-Pin Connector Assignments 2 MC13224V does not support separate JTAG reset TRST.
34 G N D
3 VBATT through a 100k-Ω pullup.
5.2.2 Nexus Mictor Interface Connector
associated Mictor pin outs if the Mictor connector is used. Table 4. Nexus 38-Pin Mictor Connector Assignments 2 VBATT through a 100k-Ω pullup. 3 VBATT isolated by a 1k-Ω resistor. 4 VBATT through a 100k-Ω pullup.
32 Freescale Semiconductor
6 System Electrical Specification
conditions, DC characteristics, and AC characteristics.
6.1 LGA Package Maximum Ratings
damage to the device. For functional operating conditions, refer to the remaining tables in this section. programmable pull-up resistor associated with the pin is enabled. Table 5 shows the maximum ratings for the 99-Pin LGA package. Table 5. LGA Package Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection.
6.2 Recommended Oper ating Conditions
6.3 DC Electrical Characteristics
Table 6. Recommended Operating Conditions Table 7. DC Electrical Characteristics
34 Freescale Semiconductor
6.4 Supply Current Characteristics
configuration used in an application. See Table 6, “Power Supply Voltage”. 2 Measurement condition for pull resistors: VIN = VSS for pullup and VIN = VDD for pulldown. Table 8. Supply Current Characteristics
8 Kbyte RAM retention
32 Kbyte RAM retention
64 Kbyte RAM retention
96 Kbyte RAM retention
Table 7. DC Electrical Characteristics (continued)
Table 8. Supply Current Characteristics (continued)
36 Freescale Semiconductor
6.5 RF AC Electrical Characteristics
Table 9. Receiver AC Electrical Characteristics for 802.15.4 Modulation Mode Detection (NCD) mode which has 3-4dBm greater sensitivity but requires 3-4mA greater receiver current. Table 10. Transmitter AC Electrical Characteristics for 802.15.4 Modulation Mode 1 Register sets output power to nominal (0 dBm typical). 2 Register sets output power to maximum. 3 Measurements taken at output of evaluation circuit set for maximum power out and averaged over 100ms.
6.6 Crystal Reference Clock Oscillator Characteristics
Figure 10. Reference Oscillator Model Table 11. Reference Oscillator Specifications Oscillator frequency tolerance over temperature range. 1 This is part of device wake-up time.
1 MEG (nom)
38 Freescale Semiconductor
Figure 11. 32.768 KHz Oscillator Model Table 12. 32.768 Oscillator Specifications
32.768 KHz
6.8 Internal Low Speed Reference Oscillator Specifications
6.9 Control Timing and CPU Bus Specifications
6.9.1 Timer Module Input Characteristics
from the peripheral clock rate. Table 15 shows timer input timing values. Table 13. Internal 2 KHz Oscillator Specifications Table 14. MCU Control Timing 1 Normal operation uses a 24 MHz reference. The MC13224V allows up to a 26 MHz max reference oscillator. operating oscillator; this can vary from the low power oscillators to the reference oscillator. Table 15. Timer Input Timing
40 Freescale Semiconductor
6.10 SPI Timing
Figure 12. SPI Timing Diagram Table 16 describes the timing requirements for the SPI system. Table 16. SPI Timing
6.11 SSI Timing
6.12 I 2C Specifications
Table 17 describes the timing requirements for the I2C system. which gives a maximum bit clock of 150 kbps. Figure 13. I2C Timing Diagram Table 17. I2C Signal DC Specifications (I2C_SDA and I2C_SCL)
1 SDA and SCL are open drain outputs
42 Freescale Semiconductor
Table 18. I2C Signal AC Specifications1
1 All values referred to VIHmin and VILmax levels
Hold time (repeated) START condition. signal) to bridge the undefined region of the falling edge of SCL. 3 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. 5 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, the faster fall-times are allowed.
6.13 FLASH Specifications
6.14 ADC Characteristics
Table 19. FLASH Characteristics Table 20. ADC Electrical Characteristics (Operating) 1 Maximum electrical operating range, not valid conversion range. Table 21. ADC Timing/Performance Characteristics
44 Freescale Semiconductor
7 Developer Environment
The MC1322x family is supported by a full set of hardware/software evaluation and development tools.
7.1 Hardware Development Interfaces
7.1.1 JTAG Hardware Debug Port
of FLASH memory, and software debug can be accomplished.
7.1.2 A7S Nexus3 (NEX) ARM7 Core Development Interface
(compliant with a Class 3 device of the IEEE-ISTO 5001 standard for real-time embedded system design).
- Program Trace via Branch Trace Messaging (BTM ). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus static code may be traced.
- Data Trace via Data Write Me ssaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to (selected) internal memory resources.
- Ownership Trace via Ownership Trace Messagi ng (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace Number of input channels 8 ADC conversion clock frequency f ADCCLK --5 0 K H z Conversion cycles (continuous convert) CCP 6 ADCCLK cycles Conversion time T conv —2 0 μs Input Leakage Current — — - nA Analog Input Voltage
1 VAIN VDD V REFL VREFH V
1 Analog input must be between VREFL + 0.2 and VREFH - 0.2 for valid conversion. Table 21. ADC Timing/Performance Characteristics (continued)
MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 45 Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow.
- Run-time access to the memory map via the JTAG port. This allows for enhanced download/upload capabilities
- Watchpoint Messaging (WPM) via the auxiliary pins
- Watchpoint Trigger enable of Pr ogram and/or Data Trace Messaging
- Auxiliary interface for higher data input/output
- Registers for Program Trace, Ownership Trace , Watchpoint Trigger, and Read/Write Access
- Programmable processor st all function to mitigate message queue overrun risk
- All features controllable and configurable via the JTAG port
7.2 Software Development Tools
An Integrated Development Environment (IDE) is available to facilitate the development of embedded applications targeting the MC13224V platform. Features of the IDE include:
- Project management tools and code editor
- Highly optimizing ARM compiler supporting C and C++
- Extensive JTAG and RDI debugger support
- Run-time libraries including source code
- Relocating ARM assembler
- Linker and librarian tools
- Debugger with ARM simulator, JTAG suppor t and support for RTOS-aware debugging on hardware
- RTOS plug-ins available
- Code templates for commonly used code constructs
- Sample projects for evaluation boards
- User and reference guides, bot h printed and in PDF format
- Context-sensitive online help The IDE is complemented by the BeeKit ™ Wireless Connectivity Toolkit. BeeKit is a stand alone software application targeting Windows® operating systems. BeeKit provides a graphical user interface (GUI) in which users can create, modify, save, and update wireless networking solutions. With the solution explorer property list windows, users can set configuration parameters to control the setup and execution behavior of the wireless link within their application. The configuration parameters can be validated inside BeeKit to ensure all values provided are within acceptable ranges prior to generation of a workspace. All this functionality provides a mechanism for developers to configure and validate their network parameters without having to navigate through multiple source files to configure the same parameters. BeeKit supports Freescale’s Simple MAC (SMAC), IEEE 802.15.4-compliant MAC, and the Freescale BeeStack™ .
46 Freescale Semiconductor
7.3 Development Hardware
8 Preliminary Mechanical Diagrams
Figure 14. Mechanical Diagram (1 of 2)
Figure 15. Mechanical Diagram Bottom View (2 of 2)
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