MC1321X_09 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008, 2009. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC1321x Rev. 1.8 08/2009 MC1321x
Package Information
71-pin LGA [9x9 mm]
Ordering Information
Device Device Marking Package MC132111 1 See Table 1 for more details.
13211 LGA
1 Introduction
The MC1321x family is Freescale’s second-generation ZigBee platform which incorporates a low power 2.4 GHz radio frequency transceiver and an 8-bit microcontroller into a single 9x9x1 mm 71-pin LGA package. The MC1321x solution can be used for wireless applications from simple proprietary point-to-point connectivity to a complete ZigBee mesh network. The combination of the radio and a microcontroller in a small footprint package allows for a cost-effective solution. The MC1321x contains an RF transceiver which is an
802.15.4 Standard compliant radio that operates in the
2.4 GHz ISM frequency band. The transceiver includes a low noise amplifier, 1mW nominal output power, PA with internal voltage controlled oscillator (VCO), integrated transmit/receive switch, on-board power supply regulation, and full spread-spectrum encoding and decoding. The MC1321x also contains a microcontroller based on the HCS08 Family of Microcontroller Units (MCU), specifically the HCS08 Version A, and can provide up to 60KB of flash memory and 4KB of RAM. The onboard MC13211/212/213 ZigBee™ - Compliant Platform -
2.4 GHz Low Power Transceiver
for the IEEE® 802.15.4 Standard plus Microcontroller
Contents
2 MC1321x Pin Assignment and Connections 8
3 MC1321x Serial Peripheral Interface (SPI) . 14
MC13211/212/213 Technical Data, Rev. 1.8
2 Freescale Semiconductor
MCU allows the communications stack and also the application to reside on the same system-in-package (SIP). The MC1321x family is organized as follows:
- The MC13211 has 16KB of flash and 1KB of RA M and is an ideal solution for low cost, proprietary applications that require wireless point-to-point or star network connectivity. The MC13211 combined with the Freescale Simple MAC (SMAC) provides the foundation for proprietary applications by supplying the necessary source code and application examples to get users started on implementing wireless connectivity.
- The MC13212 contains 32K of flas h and 2KB of RAM and is intended for use with the Freescale implemented to fit user needs. The 802.15.4 Standard supports star, mesh and cluster tree topologies as well as beaconed networks.
- The MC13213 contains 60K of flash and 4KB of RAM and is also intended for use with the Freescale fully compliant 802.15.4 MAC and the fully ZigBee compliant Freescale BeeStack. WARNING
- The MC1321x now uses an update d version of the 689S08A 8-bit microprocessor to correct errata associated with the onboard FLL and reset pin. Refer to the associated errata for this new device, Document Number MSE9S08GB60A_4L11Y, on the Freescale web site.
- The MC1321x also now uses an u pdated version of the transceiver device that is functionally fully compliant with earlier versions of the transceiver. However, for proper performance of the radio the following modem registers must be over-programmed: Register 0x31 to 0xA0C0 Register 0x34 to 0xFEC6 These registers must be over-programmed for MC1321x devices in which the modem Chip_ID Register 0x2C reads 0x6800. Applications include, but are not limited to, the following:
- Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HV AC) — Automated meter reading (AMR)
- Industrial Control — Asset tracking and monitoring — Homeland security — Process management — Environmental mon itoring and control
- Health Care — Patient monitoring — Fitness monitoring
- Consumer — Human interface devices (keyboard, mice, etc.) — Remote control — Wireless toys
1.1 Ordering Information
Table 1 provides additional details about the MC1321x family. Considerations Reference Manual (ZHDCRM). Table 1. Orderable Parts Details
MC13211/212/213 Technical Data, Rev. 1.8
4 Freescale Semiconductor
1.2 General Platform Features
- 802.15.4 Standard compliant on-chip transceiver/modem — 2.4GHz — 16 selectable channels — Programmable output power
- Multiple power saving modes
- 2V to 3.4V operating voltage wi th on-chip voltage regulators
- -40°C to +85°C temperature range
- Low external component count
- Supports single 16 MHz crystal clock sour ce operation or dual crystal operation
- Support for SMAC, IEEE 802.15.4 Standard-Compliant MAC, SynkroRF, BeeStack, BeeStack Consumer (ZigBee RF4CE) software solutions
- 9mm x 9mm x 1mm 71-pin LGA
1.3 Microcontroller Features
- Low voltage MCU with 40 MHz low power HCS08 CPU core
- Up to 60K flash memory with block protection and security and 4K RAM — MC13211: 16KB Flash, 1KB RAM — MC13212: 32KB Flash, 2KB RAM — MC13213: 60KB Flash, 4KB RAM
- Low power modes (Wait plus Stop2 and Stop3 modes)
- Dedicated serial peripheral interface (S PI) connected internally to 802.15.4 modem
- One external 4-channel (5-channel internal) 16- bit timer/pulse width modulator (TPM) module and one external 1-channel (3-channel internal) 16-bit timer/pulse width modulator module, each with selectable input capture, output capture, and PWM capability.
- 8-bit port keyboard interrupt (KBI)
- 8-channel 8-10-bit ADC
- Two independent serial communication interfaces (SCI)
- Multiple clock source options — Internal clock generator (ICG) with 243 kHz os cillator that has +/-0.2% trimming resolution and +/-0.5% deviation across voltage. — Startup oscillator of approximately 8 MHz — External crystal or resonator — External source from modem clock for very hi gh accuracy source or system low-cost option
- Inter-integrated ci rcuit (IIC) interface.
- In-circuit debug and flash programming availa ble via on-chip background debug module (BDM) — Two comparator and 9 trigger modes — Eight deep FIFO for storing change -of-flow addresses and event-only data
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 5 — Tag and force breakpoints — In-circuit debugging wi th single breakpoint
- System protection features — Programmable low voltage interrupt (LVI) — Optional watchdog timer (COP) — Illegal opcode detection
- Up to 32 MCU GPIO with programmable pullups
1.4 RF Modem Features
- Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode
- Operates on one of 16 selectable channels in the 2.4 GHz ISM band
- -1 dBm to 0 dBm nominal ou tput power, programmable from -27 dBm to +3 dBm typical
- Receive sensitivity of <-92 dBm (typical) at 1% PER, 20-byte packet, much better than the
802.15.4 Standard of -85 dBm
- Integrated transm it/receive switch
- Dual PA ouput pairs which can be programmed for full differential single-port or dual-port operation that supports an external LNA and/or PA.
- Three low power modes fo r increased battery life
- Programmable frequency clock output for use by MCU
- Onboard trim capability for 16 MHz crystal refere nce oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration
- Four internal timer comparators availa ble to supplement MCU timer resources
- Supports both packet data mode and streaming data mode
- Seven GPIO to supplement MCU GPIO
1.5 Software Features
Freescale provides a wide range of software functionality to complement the MC1321x hardware. There are three levels of application solutions:
- S M A C
- IEEE 802.15.4 Standard-Compliant MAC
- SynkroRF
- BeeStack
- BeeStack Consumer (ZigBee RF4CE)
MC13211/212/213 Technical Data, Rev. 1.8
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1.5.1 Simple Media Access Controller (SMAC)
- Small memory footprint (about 3 Kbytes typical)
- Supports point-to-point and st ar network configurations
- Proprietary networks
- Source code and applicat ion examples provided 1.5.2 802.15.4 Standard-Compliant MAC
- Supports star, mesh and cluster tree topologies
- Supports beaconed networks
- Supports GTS for low latency
- Multiple power saving mode s (idle doze, hibernate)
1.5.3 SynkroRF
- Based on the IEEE 802.15.4 Standard
- Bi-directional Communication
- Interference Avoidance
- Channel Agility
- Low Latency Transmission fo r high duty cycle interferers
- Easy Device Pairing
- Fragmentation Support
- Standardized Command Set
1.5.4 BeeStack
- Based on the IEEE 802.15.4 Standard
- Supports ZigBee 2006 Specification
- Supports star, mesh and tree networks
- Advanced Encryption Standa rd (AES) 128-bit security
- Supports the ZigBee Home Automation Profile
- Supports the ZigBee Smart Energy Profile
1.5.5 BeeStack Consumer (ZigBee RF4CE)
- Based on the IEEE 802.15.4 Standard
- Supports application profiles that define standardized command sets for multi-vendor interoperability
- Supports vendor specific extensions to standa rd application profiles for vendor specific customizing
- Supports AES-128 bit encryption
- Provides a mechanism for secured key generation
- Specifies various power saving modes
- Provides a simple mechanism to pair devices (such as a remote to a TV)
- Ensures only authorized devices are able to comm unicate (a user’s remote will not turn their neighbor's TV on or off)
1.6 System Block Diagram
Figure 1 shows a simplified block diagram of the MC1321x solution. Figure 1. MC1321x System Level Block Diagram
1.7 System Clock Configuration
- Pins are provided for a se parate external clock source for the CPU. The external clock source can by derived from a crystal oscillator or from an external clock source
- Pins are provided for a 16 MHz crystal for the modem clock source (required)
- The modem crystal oscillator frequency can be trimmed through programming to maintain the tight tolerances required by the 802.15.4 Standard
- The modem provides a CLKO pr ogrammable frequency clock output that can be used as an external source to the CPU. As a result, a single crystal system clock solution is possible
- Out of reset, the MCU uses an internally generated clock (approximately 8-MHz) for start-up. This allows recovery from stop or reset without a long crystal start-up delay
- The MCU contains an internal cl ock generator (which can be trimmed) that can be used to run the MCU for low power operation. This internal reference is approximately 243 kHz Digital Transceiver Transmit/Receiv e Sw itch Analog Receiv er Analog Transmitter Frequency Generator Buffer RAM IRQ Arbiter RAM Arbiter Pow er Management Voltage Regulators HCS08 CPU 16-60 KB Flash Memory 1-4 KB RAM Low Voltage Detect Key board Interrupt Internal Clock Generator Up to 32 GPIO COP
1 Channel & 4
8 Channel
10 Bit ADC
802.15.4 Modem HCS08 MCU
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Figure 2. MC1321x Single Crystal System Clock Structure
2 MC1321x Pin Assignment and Connections
Figure 3 shows the MC1321x pinout. Figure 3. MC1321x Pinout (Top View)
2.1 Pin Definitions
Table 2 details the MC1321x pinout and functionality. Table 2. Pin Function Description
1 PTA3/KBI1P3 Digital
2 PTA4/KBI1P4 Digital
3 PTA5/KBI1P5 Digital
4 PTA6/KBI1P6 Digital
5 PTA7/KBI1P7 Digital
6 VDDAD Power Input MCU power supply to ATD Decouple to ground.
7 PTG0/BKGND/MS Digital
Pin is I/O when used as BDM function.
8 PTG1/XTAL Digital
Full I/O when not used as clock source.
9 PTG2/EXTAL Digital
Full I/O when not used as clock source.
10 CLKO Digital Output Modem Clock Output Programmable frequencies of:
11 RESET Digital
12 PTC0/TXD2 Digital
13 PTC1/RXD2 Digital
14 PTC2/SDA1 Digital
15 PTC3/SCL1 Digital
16 PTC4 Digital
17 PTC5 Digital
18 PTC6 Digital
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19 PTC7 Digital
20 PTE0/TXD1 Digital
21 PTE1/RXD1 Digital
22 VDDD Power Output Modem regulated output
23 VDDINT Power Input Modem digital interface
24 GPIO51 Digital
25 GPIO61 Digital
26 GPIO71 Digital
27 XTAL1 Input Modem crystal reference
Connect to 16 MHz crystal and load capacitor.
28 XTAL2 Input/Output Modem crystal reference
not load this pin by using it as a 16 MHz source. 29 VDDLO2 Power Input Modem LO2 VDD supply Connect to VDDA externally. 30 VDDLO1 Power Input Modem LO1 VDD supply Connect to VDDA externally.
31 VDDVCO Power Output Modem VCO regulated
32 VBATT Power Input Modem voltage regulators’
Decouple to ground. Connect to Battery.
33 VDDA Power Output Modem analog regulated
34 CT_Bias RF Control
35 RFIN_M RF Input
36 RFIN_P RF Input
37 NC Not used May be grounded or left open
Table 2. Pin Function Description (continued)
38 PAO_P RF Output Modem power amplifier RF
when internal T/R switch is used.
39 PAO_M RF Output Modem power amplifier RF
when internal T/R switch is used.
40 SM Input Test Mode pin Must be grounded for normal operation
41 GPIO41 Digital Input/
42 GPIO31 Digital
43 GPIO2 Test Point MCU Port E Bit 6 / Modem
44 GPIO1 Test Point MCU Port E Bit 7 / Modem
45 VDD Power Input MCU main power supply Decouple to ground. 46 ATTN2 Digital Input Active Low Attention.
47 PTD2/TPM1CH2 Digital
48 PTD4/TPM2CH1 Digital
49 PTD5/TPM2CH2 Digital
50 PTD6/TPM2CH3 Digital
51 PTD7/TPM2CH4 Digital
52 PTB0/AD1P0 Input/Output MCU Port B Bit 0 / ATD
53 PTB1/AD1P1 Input/Output MCU Port B Bit 1 / ATD
54 PTB2/AD1P2 Input/Output MCU Port B Bit 2 / ATD
55 PTB3/AD1P3 Input/Output MCU Port B Bit 3 / ATD
56 PTB4/AD1P4 Input/Output MCU Port B Bit 4 / ATD
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57 PTB5/AD1P5 Input/Output MCU Port B Bit 5 / ATD
58 PTB6/AD1P6 Input/Output MCU Port B Bit 6 / ATD
59 PTB7/AD1P7 Input/Output MCU Port B Bit 7 / ATD
60 VREFH Input MCU high reference
61 VREFL Input MCU low reference voltage
62 PTA0/KBI1P0 Digital
63 PTA1/KBI1P1 Digital
64 PTA2/KBI1P2 Digital
65 PTE5/SPSCK1 SPICLK MCU SPI master SPI clock
66 PTE4/MOSI1 MOSI MCU SPI master MOSI
67 PTE3/MISO1 MISO Modem SPI slave MISO
68 PTE2/SS1 CE MCU SPI master SS
69 IRQ M_IRQ Modem interrupt request
70 PTD1 RXTXEN MCU Port D Bit 1 drives
71 PTD3 M_RST MCU Port D Bit 3 drives
FLAG VSS Power input External package flag. should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU.
2.2 Internal Functional Interconnects
points. These signals can be useful when writing and debugging software. to be programmed appropriately for the stated function. Table 3. Internal Functional Interconnects
43 PTE6 GPIO2 Modem GPIO2 output acts as “CRC Valid” status indicator for Stream Data
44 PTE7 GPIO1 Modem GPIO1 output acts as “Out of Idle” status indicator for Stream Data
46 PTD0 ATTN MCU Port D Bit 0 drives the attention (ATTN) input of the modem to wake
modem from Hibernate or Doze Mode. 1 During low power modes, input must remain driven by MCU. MCU SPI master SPI clock output drives modem SPICLK slave clock input. to zero so that MISO is driven low when CE is negated. PTD3 M_RST MCU Port D Bit 3 drives the reset M_RST input to the modem.
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3 MC1321x Serial Peripheral Interface (SPI)
The MC1321x modem and CPU communicate primarily through the onboard SPI command channel.
3.1 SiP Level SPI Pin Connections
with the SPI bus highlighted. Figure 4. MC1321x Internal Interconnects Highlighting SPI Bus Table 4. MC1321x Internal SPI Connections PTE5/SPSCK1 SPICLK MCU SPI master SPI clock out put drives modem SPICLK slave clock input.
3.2 SPI Features
- MCU bus master
- Modem bus slave
- Programmable SPI clock rate ; maximum rate is 8 MHz
- Double-buffered transmit and receive at MCU
- Serial clock phase and polarity must meet modem requirements (MCU control bits
- Slave select programmed to meet modem protocol
3.3 SPI System Block Diagram
Figure 5 shows the SPI system level diagram. Figure 5. SPI System Block Diagram the slave. The slave device must be selected by a low level on the slave select input (SS1 pin).
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4.1 Block Diagram
Figure 6. 802.15.4 Standard Modem Block Diagram
256 MHz
2.45 GHz
24 Bit Ev ent Timer
16 MHz
4 Programmable
4.2 Data Transfer Modes
- Packet Mode — Data is buffered in on-chip RAM
- Streaming Mode — Data is processed word-by-word
applications, packet mode can be used to conserve MCU resources.
4.3 Packet Structure
Figure 7 shows the packet structure of the 802.15.4 modem. Payloads of up to 125 bytes are supported. appended to the end of the data. Figure 7. 802.15.4 modem Packet Structure
4.4 Receive Path Description
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. µs period after the packet preamble and stored in an SPI register. If the 802.15.4 modem is in Packet Mode, the data is stored in RAM and processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. about -57 dBm input power which is well above 802.15.4 Standard requirements.
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level to center the level over temperature in the graphs. Figure 8. Reported Power Level versus Input Power in Clear Channel Assessment Mode Figure 9 shows energy detection/LQI reported level versus input power. Figure 9. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
802.15.4 Accuracy
4.5 Transmit Path Description
spread, and then up-converted to the transmit frequency. interrupt when the whole packet has successfully been transmitted. In both modes, a two-byte FCS is calculated in hardware from the payload data and appended to the packet. This done without intervention from the user.
4.6 Functional Description
operating modes and the Serial Peripheral Interface (SPI). Table 8, DC Electrical Characteristics. Table 5. 802.15.4 Modem Mode Definitions and Transition Times can be programmed to enter Idle Mode through an internal timer comparator. Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
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4.6.2 Serial Peripheral Interface (SPI)
- Chip Enable (CE ) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
- SPI Clock (SPICLK) - The host drives the SPICLK input to the 802.15.4 modem. Data is clocked
changes state on the trailing (falling) edge of SPICLK. and the clock polarity control bit CPOL = 0.
- Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
- Master In/Slave Out (MISO) - The 802.15.4 modem presents data to the master on the MISO
4.6.2.1 SPI Burst Operation
because the modem is limited by this number. Figure 10. SPI Single Burst Timing Diagram
4.6.2.2 SPI Transaction Operation
(MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). to signal the end of the transaction. An example SPI read transaction with a 2-byte payload is shown in Figure 11. Figure 11. SPI Read Transaction Diagram
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4.7 Modem Crystal Oscillator
The modem crystal oscillator uses the following external pins as shown in Figure 12.
- XTAL1 - reference oscillator input.
- XTAL2 - reference oscillator output . Note that this pin should not be loaded as a reference source
or to measure frequency; instead use CLKO to measure or supply 16 MHz. Figure 12. Modem Crystal Oscillator
- The initial (or make) tolerance of the crystal resonant frequency itself.
- The variation of the crystal res onant frequency with temperature.
- The variation of the crystal resonant frequency with time, also commonly known as aging.
- The variation of the crystal re sonant frequency with load capacitance, also commonly known as
such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading.
802.15.4 MODEM
by programming CLKO_Ctl Register 0A, Bits 2-0, to value 000. Figure 13 shows typical oscillator frequency decrease versus the value programmed in xtal_trim[7:0]. Figure 13. Crystal Frequency Variation vs. xtal_trim[7:0]
4.8 Radio Usage
PAO outputs can be utilized for separate RX and TX antennae or external LNA and PA designs. Figure 14 shows three possible configurations for the transceiver radio RF usage.
- Figure 14A shows a single antenna configuration in which the MC1321x internal T/R switch is
- Figure 14B shows a single antenna configuration with an external low noise amplifier (LNA) for
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external switch control is selectable.
- Figure 14C shows a dual antenna configuration where there is a RX antenna and a TX antenna. For
outputs, and inductors L4 and L5 provide dc-biasing to VDDA but are ac isolated. Figure 14. Using the MC1321x with External RF Components
5.1 MCU Block Diagram
Figure 15. MCU Block Diagram (HCS08, Version A)
- All Port F and Port G signals are present on the MCU,
but only the signals used by the MC1321x are designated. as outputs during initialization.
MC13211/212/213 Technical Data, Rev. 1.8
26 Freescale Semiconductor
5.2 MCU Modes of Operation
The MCU has multiple operational modes to facilitate maximum system performance while also providing low-power modes. In the MC1321x, the MCU can use the following modes:
- R u n
- W a i t
- Stop2
- Stop3 NOTE
- The MCU can also be programmed for Stop1 mode, but this mode IS NOT USABLE. The reset to the modem function is controlled by an MCU GPIO and the GPIO state must be maintained during the MCU “stop” condition. Stop1 mode does not control I/O states as required during modem power down condition.
- To attain specified Stop2 and Stop3 currents, all unused port signals must be programmed to a known state (recommended as outputs in the low state)
5.2.1 Run Mode
This is the normal operating mode for the HCS08. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at $FFFE:$FFFF after reset.
5.2.2 Wait Mode
Wait Mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in Wait Mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from Wait Mode and enter active background mode.
5.2.3 Stop 2
The Stop2 Mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in Stop Modes (either LVDE or LVDSE not set).
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 27 Before entering Stop2 Mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers they want to restore after exit of Stop2, to locations in RAM. Upon exit of Stop2, these values can be restored by user software before pin latches are opened. When the MCU is in Stop2 Mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry into Stop2, the states of the I/O pins are latched. The states are held while in Stop2 Mode and after exiting Stop2 Mode until a 1 is written to PPDACK in SPMSC2. Exit from Stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in Stop2, regardless of how it was configured before entering Stop2. Upon wake-up from Stop2 Mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After waking up from Stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a Stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. A separate self-clocked source (approximately 1 kHz) for the real-time interrupt allows a walk-up from Stop2 or Stop3 Modes with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop.
5.2.4 Stop3
Upon entering the Stop3 Mode, all of the clocks in the MCU, including the oscillator itself, are halted. The ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in Stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from Stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
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the MCU taking the appropriate interrupt vector. is disabled, but in that case the real-time interrupt cannot wake the MCU from stop.
5.3 MCU Memory
- Direct-page registers ($0000 through $007F)
- High-page registers ($1800 through $182B)
- Nonvolatile registers ($FFB0 through $FFBF)
Figure 16. MC1321X Memory Maps
4096 BYTES
1920 BYTES
59348 BYTES
32768 BYTES
2048 BYTES
26580 BYTES
3968 BYTES
16384 BYTES
42964 BYTES
4992 BYTES
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 29
5.4 MCU Internal Clock Generator (ICG)
The ICG provides multiple options for MCU clock sources. This block along with the ability to provide the MCU clock form the modem offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 17, the ICG consists of four functional blocks.
- Oscillator Block — The Oscillator Block provides means for connecting an external crystal or resonator. Two frequency ranges are software selectable to allow optimal start-up and stability. Alternatively, the oscillator block can be used to route an external square wave to the MCU system clock. External sources such as the modem CLKO output can provide a low cost source or a very precise clock source. The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO.
- Internal Reference Generator — The Internal Reference Genera tor consists of two controlled clock sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source.
- Frequency-Locked Loop — A Frequency-Locked Loop (FLL) st age takes either the internal or external clock source and multiplies it to a higher frequency. Status bits provide information when the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the external reference clock and signals whether the clock is valid or not.
- Clock Select Block — The Clock Select Block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC). The module is intended to be very user friendly with many of the features occurring automatically without user intervention.
5.4.1 Features
Features of the ICG and clock distribution system:
- Several options for the MCU primary clock source allow a wide range of cost, frequency, and precision choices: — 32 kHz–100 kHz crystal or resonator — 1 MHz–16 MHz crystal or resonator — External clock supplied by modem CLKO or other source — Internal reference generator
- Defaults to self-clocked mode to minimize startup delays
- Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz). When using modem CLKO as external source, maximum FLL frequency is 32 MHz (16 MHz bus rate) with CLKO = 16 MHz or maximum FLL frequency is 40 MHz (20 MHz bus rate) with CLKO = 4 MHz.
MC13211/212/213 Technical Data, Rev. 1.8
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— Uses external or internal clock as reference frequency
- Automatic lockout of non-running clock sources
- Reset or interrupt on loss of clock or loss of FLL lock
- Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode
- DCO will maintain operating fre quency during a loss or removal of reference clock. When FLL is engaged (FEE or FEI) loss of lock or loss of clock adds a divide-by-2 to ICG to prevent over-clocking of the system.
- Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
- Separate self-clocked s ource for real-time interrupt
- Trimmable internal clock so urce supports SCI communications without additional external components
- Automatic FLL engagement after lock is acquired
- Selectable low-power/high- gain oscillator modes
5.4.2 Modes of Operation
This section provides a high-level description only.
- Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is executed.
- Mode 2 — Self-clocked (SCM) Default mode of operation that is entered out of reset. The ICG’s FLL is open loop and the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits.
- Mode 3 — FLL engaged internal (FEI) In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the internal reference clock. — FLL engaged internal unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged internal locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference.
- Mode 4 — FLL bypassed external (FBE) In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
- Mode 5 — FLL engaged external (FEE) The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLL engaged external unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency.
locked to a multiple of the internal reference. Figure 17. ICG Block Diagram
5.5 Central Processing Unit (CPU)
5.5.1 CPU Features
- Object code fully upward-compatible with M68HC05 and M68HC08 Families
- All registers and memory are mappe d to a single 64-Kbyte address space
- 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
- 16-bit index register (H:X) with powerful indexed addressing modes
- 8-bit accumulator (A)
- Many instructions treat X as a second general-purpose 8-bit register
- Seven addressing modes: OSCILLATOR (OSC) FREQUENCY INTERNAL PTG2/EXTAL PTG1/XTAL REFERENCE GENERATORS CLOCK SELECT
8 MHz
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- Memory-to-memory data move instructions with four address mode combinations
- Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations
- Efficient bit manipulation instructions
- Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
- STOP and WAIT instructions to invoke low-power operating modes
5.5.2 Programmer’s Mo del and CPU Registers
Figure 18 shows the five CPU registers. CPU registers are not part of the memory map. Figure 18. CPU Registers
5.6 Parallel Input/Output
Figure 15. Port F and part of port G are not utilized. The MC1321x family makes use of the remaining I/O as pinned-out I/O or as internally dedicated signal for communication with the 802.15.4 modem. with on-chip peripherals such as timer systems, various communication ports, or keyboard interrupts.
- A total of 32 general-purpose I/O pins in seven ports (PTG0 is output only)
- High-current drivers on port C
- Hysteresis input buffers
- Software-controlled pu llups on each input pin
- Software-controlled sl ew rate output buffers
- Eight port A pins shared with KBI1
- Eight port B pins shared with ATD1
- Eight high-current port C pins shared with SCI2 and IIC1
- Eight port D pins shared with TPM1 and TPM2
- Eight port E pins shared with SCI1 and SPI1
- Eight port G pins shared wi th EXTAL, XTAL, and BKGD/MS NOTE Not all port G signals and no port F signals are bonded out, but are present in the MCU hardware (see Figure 15). These port I/O signals should be programmed as outputs set to the low state.
5.7 MCU Peripherals
5.7.1 Modem Dedicated Serial Pe ripheral Interface (SPI) Module
the SPI is enabled, the direction of pins is controlled by module configuration. the proper use to support the modem transaction protocol for the modem CE signal.
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5.7.1.1 SPI Features
- Used in master mode only
- Programmable transmit bit rate (maxim um usable rate is 8 MHz with modem)
- Double-buffered transmit and receive
- Serial clock phase and polarity option must be programmed to CPHA = 0 and CPOL = 0
- Programmable slave select output to support modem SPI protocol
- MSB-first data transfer
5.7.1.2 SPI Module Block Diagram
Figure 19 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. connections between MCU pins and the SPI module. routed to MOSI, and the shifter input is routed from the MISO pin. Figure 19. Modem Dedicated SPI Block Diagram
5.7.2 Keyboard Interrupt (KBI) Module
The HCS08 has one KBI module with eight keyboard interrupt inputs that share port A pins. from stop or wait low-power modes.
5.7.3 KBI Features
- Keyboard interrupts selectable on eight port pins: — Four falling-edge/low-level sensitive — Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode
5.7.3.1 KBI Block Diagram
Figure 20 shows the block diagram for the KBI module. Figure 20. KBI Block Diagram
MC13211/212/213 Technical Data, Rev. 1.8
36 Freescale Semiconductor
5.7.4 Timer/PWM (TPM) Module Introduction
The HCS08 includes two independent Timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions. In each of these two TPMs, timing functions are based on a separate 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference. This timing system is ideally suited for a wide range of control applications, and the center-aligned PWM capability on the 3-channel TPM extends the field of applications to motor control in small appliances. The use of the fixed system clock, XCLK, as the clock source for either of the TPM modules allows the TPM prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This clock source must be selected only if the ICG is configured in either FBE or FEE mode. In FBE mode, this selection is redundant because the BUSCLK frequency is the same as XCLK. In FEE mode, the proper conditions must be met for XCLK to equal ICGERCLK/2. Selecting XCLK as the clock source with the ICG in either FEI or SCM mode will result in the TPM being non-functional.
5.7.4.1 TPM Features
The timer system in the MC1321x family MCU includes a one external 4-channel (5-channel internal) TPM1 and one external 1-channel (3-channel internal) TPM2. Timer system features include
- A total of 5 external channels: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs
- Each TPM may be configured fo r buffered, center-aligned pulse-width modulation (CPWM) on all channels
- Clock source to prescaler for each TPM is inde pendently selectable as bus clock, fixed system clock, or an external pin
- Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
- 16-bit free-running or up/ down (CPWM) count operation
- 16-bit modulus register to control counter range
- Timer system enable
- One interrupt per channel pl us terminal count interrupt
5.7.4.2 TPM Block Diagram
The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 1–4). The TPM shares its I/O pins with general-purpose I/O port pins. Figure 21 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels.
Figure 21. TPM Block Diagram
5.7.5 Serial Communications Interface (SCI) Module
communicate with other embedded controllers. has a separate baud rate generator. buffering on transmit and receive are also included.
5.7.5.1 SCI Features
- Full-duplex, standard non-re turn-to-zero (NRZ) format
- Double-buffered transmitter and re ceiver with separate enables
- Programmable baud rates (13-bit modulo divider)
- Interrupt-driven or polled operation: — Transmit data register em pty and transmission complete PRESCALE AND SELECT 16-BIT COMPARATOR MAIN 16-BIT COUNTER 16-BIT COMPARATOR 16-BIT LATCH PORTCHANNEL 1 LOGIC INTERRUPT COUNTER RESET DIVIDE BY CLOCK SOURCE OFF, BUS, XCLK, EXT BUSCLK XCLK SELECT SYNC INTERRUPT 1, 2, 4, 8, 16, 32, 64, or 128 LOGIC LOGIC CLKSACLKSB PS2 PS1 PS0 CPWMS TFIE TOF ELS1A CH1F ELS1B CH1IEMS1B MS1A TPM1MODH:TPM1MODL TPM1) EXT CLK TPM1C1VH:TPM1C1VL TPM1CH1
MC13211/212/213 Technical Data, Rev. 1.8
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— Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect
- Hardware parity generation and checking
- Programmable 8-bit or 9-bit character length
- Receiver walk-up by idle-line or address-mark
5.7.5.2 SCI Block Diagrams
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Figure 22 and Figure 23 show the SCI transmitter and receiver block diagrams.
Figure 22. SCI Transmitter
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Figure 23. SCI Receiver
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 41
5.7.6 Inter-Integrated Circuit (IIC) Module
The HCS08 microcontroller provides one inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SDA and SCL share port C pins 2 and 3, respectively. All functionality as described in this section is available on HCS08. When the IIC is enabled, the direction of pins is controlled by module configuration. If the IIC is disabled, both pins can be used as general-purpose I/O. The inter-integrated circuit (IIC) provides a method of communication between a number of devices{statement}. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
5.7.6.1 IIC Features
The IIC includes these features:
- IP bus V2.0 compliant Compa tible with IIC bus standard
- Multi-master opera tion {statement}
- Software programmable for one of 64 different serial clock frequencies {iic_prescale.asm}
- Software selectable acknow ledge bit {iic_ack.asm}
- Interrupt driven byte-by-byte data transfer {iic_int.asm}
- Arbitration lost interrupt with automatic mode switching from master to slave {iic_int.asm}
- Calling address identificati on interrupt {iic_int.asm}
- START and STOP signal generation/detection {iic_transmit.asm}{iic_receive.asm}{iic_receive_addon.asm}
- Repeated START signal generation {iic_transmit.asm}
- Acknowledge bit generation/ detection {iic_ack.asm}
- Bus busy detection {iic_bus_busy.asm}
5.7.6.2 IIC Modes of Operation
The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various MCU modes is given here. Run mode This is the basic mode of operation. To conserve power in this mode, disable the module. Wait mode The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. Stop mode The IIC is inactive in Stop3 Mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop1 and Stop2 will reset the register contents.
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5.7.6.3 IIC Block Diagram
Figure 24 shows a block diagram of the IIC module. Figure 24. IIC Functional Block Diagram
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 43
5.7.7 Analog-to-Digital (ATD) Module
The HCS08 provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share Port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality.
5.7.7.1 ATD Features
- 8-/10-bit resolution
- 14.0 μsec, 10-bit single conversion time at a conversion frequency of 2 MHz
- Left-/right-justified result data
- Left-justified signed data mode
- Conversion complete flag or convers ion complete interrupt generation
- Analog input multiplexer for up to eight analog input channels
- Single or continuous conversion mode
5.7.7.2 ATD Modes of Operation
The ATD has two modes for low power 1. Stop mode 2. Power-down mode
5.7.7.2.1 ATD Stop Mode
When the MCU goes into Stop Mode, the MCU stops the clocks and the ATD analog circuitry is turned off, placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have their previous values. As long as the ATDPU bit is set prior to entering stop mode, the module is reactivated coming out of stop.
5.7.7.2.2 ATD Power Down Mode
Clearing the ATDPU bit in register ATD1C also places the ATD module in a low-power state. The ATD conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD module aborts any conversion in progress. Upon setting the ATDPU bit, the module is reactivated. During power-down mode, the ATD registers are still accessible. NOTE The reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state.
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5.7.7.3 ATD Block Diagram
Figure 25 shows the functional structure of the ATD module. Figure 25. ATD Block Diagram
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 45
5.7.8 Development Support
Development support systems in the include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other non-volatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. Address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. The alternate BDC clock source for HCS08 is the ICGLCLK.
5.7.8.1 Development Support Features
Features of the background debug controller (BDC) include:
- Single pin for mode selecti on and background communications
- BDC registers are not located in the memory map
- SYNC command to determine target communications rate
- Non-intrusive commands for memory access
- Active background mode comma nds for CPU register access
- GO and TRACE1 commands
- BACKGROUND command can wake CPU from stop or wait modes
- One hardware address br eakpoint built into BDC
- Oscillator runs in stop mode, if BDC enabled
- COP watchdog disabled while in active background mode Features of the debug module (DBG) include:
- Two trigger comparators: — Two address + read/write (R/W) or — One full address + data + R/W
- Flexible 8-word by 16-bit FI FO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data
- Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access
- Nine trigger modes:
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6 System Electrical Specification
DC characteristics, and AC characteristics for the modem, and the MCU.
6.1 SiP LGA Package Maximum Ratings
damage to the device. For functional operating conditions, refer to the remaining tables in this section. pull-up resistor associated with the pin is enabled. Table 6 shows the maximum ratings for the 71 Pin LGA package. Table 6. LGA Package Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection.
6.2.1 Modem Recommended Operating Conditions
resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. present, or if the clock rate is very low which would reduce overall power consumption. Table 7. Recommended Operating Conditions 1 If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak.
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6.2.2 Modem DC Electr ical Characteristics
6.2.3 Modem AC Electr ical Characteristics
Table 8. DC Electrical Characteristics 2 CLKO frequency at default value of 32.786 kHz. Table 9. Receiver AC Electrical Characteristics
Figure 26. RF Parametric Evaluation Circuit Table 10. Transmitter AC Electrical Characteristics 1 SPI Register 12 is default value of 0x00BC which sets output power to nominal (-1 dBm typical). 2 SPI Register 12 programmed to 0xFF which sets output power to maximum.
3 Measured with output power set to nominal (0 dBm) and temperature @ 25 °C
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6.3 MCU Electrical Characteristics
6.3.1 MCU DC Characteristics
Table 11. RF Port Impedance
2.405 GHz
2.442 GHz
2.480 GHz
Table 12. MCU DC Characteristics
1 Typicals are measured at 25°C. 2 This parameter is characterized and not tested on each device. 3 Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. clock rate is very low which would reduce overall power consumption. 5 All functional non-supply pins are internally clamped to VSS and VDD. resistance values for positive and negative clamp voltages, then use the larger of the two values. Table 12. MCU DC Characteristics (continued)
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6.3.2 MCU Supply Cu rrent Characteristics
known condition; recommended as outputs in the low state. 7 This parameter is characterized and not tested on each device. 8 IRQ does not have a clamp diode to VDD. Do not drive IRQ above VDD. Table 13. MCU Supply Current Characteristics
1 Typicals are measured at 25°C. 2 Values given here are preliminary estimates prior to completing characterization.
3 All modules except ATD active, ICG configured for FBE, and does not include any dc loads on port pins
4 Values are characterized but not tested on every part. 5 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. mode. Wait mode typical is 560 μA at 3 V and 422 μA at 2V with fBus = 1 MHz. Table 13. MCU Supply Current Characteristics (continued)
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6.3.3 MCU ATD Characteristics
Table 14. MCU ATD Electrical Characteristics (Operating)
1 ATD supply 1
1 VDDAD must be at same potential as VDD.
3 Differential supply voltage V DD–VDDAD |VDDLT| — — 100 mV
4 Differential ground voltage V SS–VSSAD |VSDLT — — 100 mV
5 Reference potential, low |V REFL|— — V SSAD V
6 Reference supply current
7 Analog input voltage 2
2 Maximum electrical operating range, not valid conversion range.
Table 15. ATD Timing/Performance Characteristics1 will vary based on board layout and the type and magnitude of the activity.
1 ATD conversion clock
2 Conversion cycles
4 Source impedance at
fully charge the input circuitry of the ATD resulting in accuracy error.
5 Analog Input Voltage 4
6 Ideal resolution (1 LSB) 5
5 The resolution is the ideal step size or 1LSB = (VREFH–VREFL)/1024
7 Differential non-linearity 6
width is the difference in the transition voltages to and from the current code.
8 Integral non-linearity 7
voltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((VREFH+EFS)–(VREFL+EZS))).
9 Zero-scale error 8
transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).
10 Full-scale error 9
transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).
11 Input leakage error 10
10 Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. Reducing the impedance of the network reduces this error.
12 Total unadjusted
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6.3.4 MCU Internal Clock Gene ration Module Characteristics
Figure 27. ICG Clock Basic Schematic and full-scale) error. The specified value of ET assumes zero EIL (no leakage or zero real source impedance). Table 16. MCU ICG DC Electrical Specifications 2 See crystal or resonator manufacturer’s recommendation. Use fundamental mode crystal or ceramic resonator only.
6.3.5 MCU ICG Frequency Specifications
Table 17. MCU ICG Frequency Specifications
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6.4 MCU AC Peripheral Characteristics
This section describes ac timing characteristics for each peripheral system.
6.4.1 MCU Control Timing
1 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. it is not in the desired range. (if an external reference exists) if it is not in the desired range. 4 This parameter is characterized before qualification rather than 100% tested. 5 Proper PC board layout procedures must be followed to achieve specifications. modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT. Table 18. MCU Control Timing Table 17. MCU ICG Frequency Specifications (continued)
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6.4.2 MCU Timer/PWM (TPM) Module Timing
Figure 31. Timer External Clock Figure 32. Timer Input Capture Pulse Table 19. TPM Input Timing
6.4.3 System SPI Timing
Table 20 describes the timing requirements for the SPI system. Figure 33. SPI Master Timing (CPHA = 0) Table 20. SPI Timing
1 SCK period
2 Enable lead time
3 Enable lag time
4 Clock (SCK) high or low time
5 Data setup time (inputs)
6 Data hold time (inputs)
7 Data valid (after SCK edge)
8 Data hold time (outputs)
10 Fall time
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6.4.4 FLASH Specifications
Table 21. FLASH Characteristics 1 The frequency of this clock is controlled by a software setting. for calculating approximate time to program and erase. retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Non-volatile Memory.
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 63
7 Application Considerations
The following sections describe crystal requirements and RF port options for end user applications.
7.1 Crystal Oscillator Reference Frequency
The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC1321x transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting the 802.15.4 Standard, is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal res onant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal re sonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - init ial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - incl uding stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim st ep will be performed in production
7.1.1 Crystal Oscillator Design Considerations
Freescale requires that a 16 MHz crystal with a <9 pF load capacitance is used. The MC1321x does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC1321x requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the Figure 34 crystal reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately ±15%.
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using/specifying a crystal with a tighter stability tolerance, but the crystal will be slightly higher in cost. the needed specifications for the crystal and external load capacitors to meet the 802.15.4 Standard. Figure 34. MC1321x Modem Crystal Circuit
7.1.2 Crystal Requirements
Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x. Table 22. MC1321x Crystal Specifications1
7.2 Low Power Considerations
- Program and use the modem IO pi ns properly for low power operation — All unused modem GPIOx signals must be used one of 2 ways: – If the Off mode is to be us ed as a long term low power mode, unused GPIO should be tied to ground. The default GPIO mode is an input and there will be no conflict. – If only Hibernate and/ or Doze modes are used as long term low power modes, the GPIO should programmed as outputs in the low state. — When modem GPIO are used as outputs: – Pullup resistors should be provi ded (can be provided by the MCU IO pin if tied to the MCU) if the modem Off condition is to be used as a long term low power mode. – During Hibernate and/or Doze modes, the GP IO will retain its programmed output state. — If the modem GPIO is used as an input, the GPIO should be driven by its source during all low power modes or a pullup resistor should be provided. — Digital outputs IRQ , MISO, and CLKO: – MISO - is always an output. During Hibern ate, Doze, and active modes, the default condition is for the MISO output to go to tristate when CE is de-asserted, and this can cause a problem with the MCU because one of its inputs can float. Program Control_B Register 07, Bit 11, miso_hiz_en = 0 so that MISO is driven low when CE is de-asserted. As a result, MISO will not float when Doze or Hibernate Mode is enabled. –I R Q - is an open drain output (OD) and should always have a pullup resistor (typically provided by the MCU IO). IRQ acts as the interrupt request output. NOTE It is good practice to have the IRQ interrupt input to the MCU disabled during the hardware reset to the modem. After releasing the modem hardware reset, the interrupt request input to the MCU can then be enabled to await the IRQ that signifies the modem is ready and in Idle mode; this can prevent a possible extraneous false interrupt request. – CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used. Shunt capacitance <2 pF max Mode of oscillation fundamental 1 User must be sure manufacturer specifications apply to the desired package. 2 A wider frequency tolerance may acceptable if application uses trimming at production final test. 3 A wider frequency stability may be acceptable if application uses trimming at production final test. 4 A wider aging tolerance may be acceptable if application uses trimming at production final test. 5 Higher ESR may be acceptable with lower load capacitance. 6 Lower load capacitance can allow higher ESR and is better for low temperature operation in Doze mode.
Table 22. MC1321x Crystal Specifications1 (continued)
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- When the MCU is used in low po wer modes, be sure that all unused IO are programmed properly for low power operation (typically best case is as outputs in the low state). The MC1321x is commonly used with the Freescale MC9S08GT/GB 8-bit devices. For these MCUs: — Use only STOP2 and STOP3 modes (not STOP1) wi th these devices where the GPIO states are retained. The MCU must retain control of the MC1321x IO during low power operation. — As stated above all unused GP IO should be programmed as outputs low for lowest power and no floating inputs. — The MCU has IO signals that are not pinned-ou t on the package. These signals must also be initialized (even though they cannot be used) to prevent floating inputs.
7.3 RF Single Port Appli cation with an F Antenna
single-ended to interface with the F antenna. provides a simple bandpass filter to limit out-of-band harmonics from the transmitter. required to obtain best matching and RF performance. Figure 35. RF Single Port Application with an F-Antenna
7.4 RF Dual Port Appli cation with an F-Antenna
provided to the PAO and RFIN ports. required to obtain best matching and RF performance. switch is powered. In this manner, the antenna switch only consumes current when it needs to be active. The GPIO1 can only be used as a VDD source for a very low current load. Figure 36. RF Dual Port Application with an F-Antenna
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8 Mechanical Diagrams
Figure 37 and Figure 38 show the MC1321x mechanical information. Figure 37. MC1321x Mechanical (1 of 2)
Figure 38. MC1321x Mechanical (2 of 2)
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