MC13201

MC13201 FREESCALE | Alldatasheet

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© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC13201 Rev. 1.0, 10/2006 MC13201

Package Information

Ordering Information

Device Device Marking Package MC13201 13201 QFN-32

1 Introduction

The MC13201 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13201 contains a complete packet data modem which is compliant with the IEEE® 802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 Standard compliance, the MC13202/203 and Freescale's 802.15.4 MAC software are required. When combined with an appropriate microcontroller (MCU), the MC13201 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems to star networks. MC13201

2.4 GHz Low Power Transceiver

for the IEEE® 802.15.4 Standard

Contents

8 Crystal Oscillator Reference Frequency . . 17

MC13201 Technical Data, Rev. 1.0,

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For more detailed information about MC13201 operation, refer to the MC13201 Reference Manual, (MC13201RM). Applications include, but are not limited to, the following:

• Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HVAC) — Automated meter reading (AMR)
• Industrial Control — Asset tracking and monitoring — Homeland security — Process management — Environmental mon itoring and control — HVAC — Automated meter reading
• Health Care — Patient monitoring — Fitness monitoring
• Consumer — Human interface devices (keyboard, mice, etc.) — Remote control — Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2F e a t u r e s
• Recommended power supply range: 2.0 to 3.4 V
• Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode
• Operates on one of 16 selectable channels in the 2.4 GHz band
• -1 to 0 dBm nominal output power, program mable from -27 dBm to +3 dBm typical
• Receive sensitivity of <-91 dBm (typical) at 1% PER, 20-byte packet, much better than the

802.15.4 Standard of -85 dBm

MC13201 Technical Data, Rev. 1.0, Freescale Semiconductor 3

• Integrated transm it/receive switch
• Dual PA output pairs which can be programmed for full differential single port or dual port operation that supports an external LNA and/or PA
• Three power down modes for increased battery life — < 1 µA Off current — 1.0 µA Typical Hibernate current — 35 µA Typical Doze current (no CLKO)
• Programmable frequency clock output (CLKO) for use by MCU
• Onboard trim capability for 16 MHz crystal refere nce oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration
• Four internal timer comparators availa ble to supplement MCU timer resources
• Buffered transmit and receive data packet s for simplified use with low cost MCUs
• Seven GPIO to supplement MCU GPIO
• Operating temperature range: -40 °C to 85 °C
• Small form factor QFN-32 Package — Meets moisture sensitivity level (MSL) 3 — 260 °C peak reflow temperature — Meets lead-free requirements

2.1 Software Support

Freescale provides a software suite to complement the MC13201 hardware which is called the Freescale Simple MAC (SMAC):

• Simple proprietary wireless connectivity.
• Small memory footprint (about 3 Kbytes typical)
• Supports point-to-point and st ar network configurations
• Proprietary networks
• Source code and applicat ion examples provided

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3 Block Diagrams

transceiver that provides the functions required in the physical layer (PHY) specification. Figure 1. 802.15.4 modem Simplified Block Diagram Figure 2. System Level Block Diagram

256 MHz

2.45 GHz

24 Bit Ev ent Timer

16 MHz

4 Programmable

4 Data Transfer Mode

4.1 Packet Structure

Figure 3 shows the packet structure of the MC13201 which is consistent with the 802.15.4 Standard. Sequence (FCS) is calculated and appended to the end of the data. Figure 3. MC13201 Packet Structure

4.2 Receive Path Description

QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. over a 64 µs period after the packet preamble and stored in RAM. RAM. The MCU is notified that an entire packet has been received via an interrupt. detection/LQI reported level versus input power. level to center the level over temperature in the graphs.

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Figure 4. Reported Power Level versus Input Power in CCA Mode Figure 5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator

4.3 Transmit Path Description

packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. an interrupt when the whole packet has successfully been transmitted.

802.15.4 Accuracy

5 Electrical Characteristics

5.1 Maximum Ratings

5.2 Recommended Oper ating Conditions

Table 1. Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection. Table 2. Recommended Operating Conditions 1 If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak.

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5.3 DC Electrical Characteristics

5.4 AC Electrical Characteristics

Table 3. DC Electrical Characteristics 1 CLKO frequency at default value of 32.786 kHz. Table 4. Receiver AC Electrical Characteristics

Figure 6 shows a typical AC parameter evaluation circuit. Table 5. Transmitter AC Electrical Characteristics

1 Pout -5 -1 - dBm

1 SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical). 2 SPI Register 12 programmed to 0x00FC which sets output power to maximum. Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted. SPI timing parameters are referenced to Figure 8.

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Figure 6. RF Parametric Evaluation Circuit

6 Functional Description

modes, and the Serial Peripheral Interface (SPI).

6.1 MC13201 Operational Modes

Table 7. MC13201 Mode Definitions and Transition Times be programmed to enter Idle Mode through an internal timer comparator. Idle Crystal Reference Oscillator On with CLKO output available. SPI active.

6.2 Serial Peripheral Interface (SPI)

1. Chip Enable (CE ) - A transaction on the SPI port is framed by the active low CE input signal. A

transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.

1. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13201. Data is clocked into the

state on the trailing (falling) edge of SPICLK. control bit CPHA = 0 and the clock polarity control bit CPOL = 0.

1. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
2. Master In/Slave Out (MISO) - The MC13201 pres ents data to the master on the MISO output.

A typical interconnection to a microcontroller is shown in Figure 7. Figure 7. SPI Interface

6.2.1 SPI Burst Operation

of a single SPI burst is shown in Figure 8.

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Figure 8. SPI Single Burst Timing Diagram SPI digital timing specifications are shown in Table 6.

6.2.2 SPI Transaction Operation

data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). MC13201 Reference Manual, (MC13201RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9. Figure 9. SPI Read Transaction Diagram

7 Pin Connections

Table 8. Pin Function Description

3 CT_Bias Control voltage Bias voltage/control signal for external

for external LNA, PA, or T/R switch. 7 SM Input Test mode pin. Must be grounded for normal operation. 8 GPIO4 Digital Input/ Output General Purpose Input/Output 4. 9 GPIO3 Digital Input/ Output General Purpose Input/Output 3. 10 GPIO2 Digital Input/ Output General Purpose Input/Output 2. 11 GPIO1 Digital Input/ Output General Purpose Input/Output 1. Mode, with SPI in default state.

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be held high through the sequence. 15 CLKO Digital Output Clock output to host MCU.

16 MHz, 8 MHz, 4 MHz, 2 MHz, 1

16 SPICLK Digital Clock Input External clock input for the SPI

20 IRQ Digital Output Active Low Interrupt Request. Open drain device. 21 VDDD Power Output Digital regulated supply bypass. Decouple to ground.

22 VDDINT Power Input Digital interface supply & digital

regulator input. Connect to Battery. 2.0 to 3.4 V. Decouple to ground. 23 GPIO5 Digital Input/Output General Purpose Input/Output 5. 24 GPIO6 Digital Input/Output General Purpose Input/Output 6. 25 GPIO7 Digital Input/Output General Purpose Input/Output 7. Table 8. Pin Function Description (continued)

27 XTAL2 Input/Output Crystal Reference oscillator output

16 MHz output at Pin 15,

Reference Manual for details. 30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 31 VBATT Power Input Analog voltage regulators Input. 32 VDDA Power Output Analog regulated supply Output. circuitry external to the chip. EP Ground External paddle / flag ground. Connect to ground.

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Figure 10. Pin Connections (Top View)

MC13201 Technical Data, Rev. 1.0, Freescale Semiconductor 17

8 Crystal Oscillator Reference Frequency

This section provides application specific information regarding crystal oscillator reference design and recommended crystal usage.

8.1 Crystal Oscillator Design Considerations

The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13201 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal res onant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal re sonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - init ial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - incl uding stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim st ep will be performed in production Freescale requires the use of a 16 MHz crystal with a <9 pF load capacitance. The MC13201 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13201 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the Figure 11 crystal reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately ±15%.

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using/specifying a crystal with a tighter stability tolerance, but the crystal will be slightly higher in cost. the needed specifications for the crystal and external load capacitors to meet the 802.15.4 Standard. Figure 11. MC13201 Modem Crystal Circuit

8.2 Crystal Requirements

Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x. Table 9. MC13201 Crystal Specifications1 1 User must be sure manufacturer specifications apply to the desired package. 2 A wider frequency tolerance may acceptable if application uses trimming at production final test.

8.3 Transceiver RF Configurati ons and External Connections

• Programmable output power — 0 dBm nominal output power, programmable from -27 dBm to +4 dBm typical
• <-91 dBm (typical) receive se nsitivity — At 1% PER, 20- byte packet (well above 802.15.4 Standard of -85 dBm)
• Optional integrated transmit/recei ve (T/R) switch for low cost operation — With internal PAs and LNA, the internal T/R switch allows a minimal part count radio interface using only a single balun to interface to a single-ended antenna
• Maximum flexibility — There are fu ll differential RF I/O pins for use with the internal T/R switch. Optionally, these pins become the RF_IN signals and a separate set of full differential PA outputs are also provided. Separate inputs and outputs allow for a variety of RF configurations including external LNA and PA for increased range
• CT_Bias Output — The CT_Bias sign al provides a switched bias reference for use with the internal T/R switch, and alternatively can be programmed as an antenna switch signal for use with an external antenna switch
• Onboard trim capability for 16 MHz crystal refe rence oscillator — The 802.15.4 Standard puts a +/- 40 ppm requirement on the carrier frequency. The onboard trim capability of the modem crystal oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration. Also tighter tolerance can produce greater receive sensitivity

8.4 RF Interface Pins

operation and dual port differential operation. Figure 12. RF Interface Pins 3 A wider frequency stability may be acceptable if application uses trimming at production final test. 4 A wider aging tolerance may be acceptable if application uses trimming at production final test. 5 Higher ESR may be acceptable with lower load capacitance. 6 Lower load capacitance can allow higher ESR and is better for low temperature operation in Doze mode.

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8.4.1 Single Port Operation

that converts a single-ended antenna to the differential interface required by the transceiver. Figure 13. Single Port RF Operation with a Balun providing the proper DC bias voltage to the balun depending on RX or TX.

8.4.2 Dual Port Operation

amplifier, or antenna switch. differential output pins and the associated TX PA is enabled for transmit. between receive and transmit. An LNA is in the receive path to add gain for greater receive sensitivity. switch control is selectable.

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8.5 Controlling RF Modes of Operation

Figure 15. Control_B Register 07 Model

• RF_switch_mode (Bit 12) - This bit selects Dual Port Mode versus Single Port Mode: — The default condition (Bit 12 = 0) is Dual Po rt Mode where the RF inputs are RFIN_M and RFIN_P and the RF outputs are PAO_M and PAO_P, and operation is as described in Section 8.4.2, “Dual Port Operation. The use of CT_Bias pin in Dual Port Mode is controlled by Bit 13 and Bit 12. — When Bit = 1, the Single Port Mode is se lected where RFIN_M (PAO_M) and RFIN_P (PAO_P) become bidirectional pins and operation is as described in Section 8.4.1, “Single Port Operation. The use of CT_Bias pin in Dual Port Mode in controlled by Bit 13 and Bit 12.
• Ct_bias_en (Bit 14) - This bit is the enable for the CT_Bias output. When Bit 14 = 0 (default), the CT_Bias is disabled and stays in a Hi-Z or tri-stated condition. When Bit 14 = 1, the CT_Bias output is active and its state is controlled by the selected mode (Bit 12), ct_bias_inv, and operation of the radio.
• Ct_bias_inv (Bit 13) - This bit onl y affects the state of CT_Bias when Dual Port Mode is selected and CT_bias is active. The CT_Bias changes state in Dual Port Mode based on the TX or RX state of the radio. The ct_bias_inv bit causes the sense of the active state to change or invert based on Bit 13’s setting. In this manner, the user can select the CT_Bias as a control signal for external components and make the control signal active high or active low. Register 07 0x07 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr_load ct_bias_en ct_bias_inv RF_switch_mode miso_hiz_en clko_doze_en tx_done_mask rx_done_mask use_strm_mode hib_en doze_en TYPE r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w RESET 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0x0C00

Table 10 summarizes the operation of the RF interface control bits.

8.6 RF Control Output CT_Bias

• Single Port Operation - In this mode, the CT_Bia s can be used to establish the proper DC bias voltage to a balun depending on the RX state versus TX state as described in Section 8.4.1, “Single Port Operation. Note that in single port operation, the ct_bias_inv has no effect and CT_Bias is at VDDA for TX and is at ground for RX.
• Dual Port Operation - In this m ode, the CT_Bias can be used as a control signal to enable a LNA or PA or to determine the direction of an antenna switch as described in Section 8.4.2, “Dual Port Operation. In dual port operation, ct-bias_inv is used to control the sense of the output control, i.e., CT_Bias can be active high or active low for TX and vice-versa for RX. Table 11 defines the CT_Bias output state depending on control bits and operation mode of the modem. Note that the output state is also defined in Idle, Hibernate, and Doze state as well as RX and TX operation.

Table 10. RF Interface Control Bits 14 ct_bias_en 0 1 = CT_Bias enabled. Output state is defined by Table 11. 0 = CT_Bias disabled. Output state is tri-stated. has effect for dual port operation.

12 RF_switch_mode 0 1= Single Port Mode selected where RF switch is active and RFIN_M and RFIN_P and

and PAO_N are separate outputs. (This is default operation). Table 11. CT_Bias Output vs. Register Settings

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8.7 RF Single Port Appli cation with an F Antenna

provides a simple bandpass filter to limit out-of-band harmonics from the transmitter. Figure 16. RF Single Port Application with an F-Antenna Table 11. CT_Bias Output vs. Register Settings (continued)

9 Packaging Information

Figure 17. Outline Dimensions for QFN-32, 5x5 mm

1.5 BACKSIDE

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
4. CORNER CHAMFER MAY NOT BE PRESENT.
5. COPLANARITY APPLIES TO LEADS, CORNER
6. FOR ANVIL SINGULATED QFN PACKAGES,

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