MC13191

MC13191_07 FREESCALE | Alldatasheet

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© Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC13191 Rev. 1.5, 03/2007 MC13191

Package Information

(QFN-32) Scale 1:1

Ordering Information

Device Device Marking Package MC13191 13191 QFN-32

1 Introduction

The MC13191 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceiver. The MC13191 contains a complete packet data modem which is compliant with the IEEE 802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 Standard compliance, the MC13192 and Freescale's 802.15.4 MAC software are required. When combined with an appropriate microcontroller (MCU), the MC13191 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point to star networks. MC13191

2.4 GHz ISM Band Low Power

Contents

MC13191 Technical Data, Rev. 1.5

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For more detailed information about MC13191 operation, refer to the MC13191 Reference Manual, (MC13191RM). Applications include, but are not limited to, the following:

• Remote control and wire repla cement in industrial systems such as wireless sensor networks
• Factory automation and motor control
• Energy Management (l ighting, HVAC, etc.)
• Asset tracking and monitoring Potential consumer applications include:
• Home automation and control (l ighting, thermostats, etc.)
• Human interface devices (keyboard, mice, etc.)
• Remote control
• Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2F e a t u r e s
• 802.15.4 Standard compliant tran sceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode/decode
• Operates on one of 16 selectable channels in the 2.4 GHz band
• Receive sensitivity of <-91 dBm (t ypical) at 1.0% packet error rate
• Recommended power supply range: 2.0 to 3.4 V
• 0 dBm nominal output pow er, programmable from -27 dBm to 4 dBm typical
• Buffered transmit and receive data packet s for simplified use with low cost MCUs
• Three power down modes for increased battery life: — < 1.0 µA Off current — 2.3 µA Typical Hibernate current — 35 µA Typical Doze current (no CLKO)
• Two internal timer comparators av ailable to supplement MCU resources
• Programmable frequency clock output (CLKO) for use by MCU
• Onboard trim capability for 16 MHz crystal referen ce oscillator eliminates the need for external variable capacitors and allows for automated production frequency calibration.
• Seven general purpose input/output (GPIO) signals
• Operating temperature range: -40 °C to +85 °C
• Small form factor QFN-32 Package

2.1 Software Support

• Simple proprietary wireless connectivity
• Small memory footprint (about 3 Kbytes typical)
• Supports point-to-point and st ar network configurations
• Proprietary networks
• Source code and applicat ion examples provided

3 Block Diagrams

Figure 1. MC13191 Simplified Block Diagram

256 MHz

2.45 GHz

24 Bit Ev ent Timer

16 MHz

2 Programmable

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Figure 2. System Level Block Diagram

4 Data Transfer Mode

4.1 Packet Structure

Figure 3 shows the packet structure of the MC13191 which is consistent with the 802.15.4 Standard. Check Sequence (FCS) is calculated and appended to the end of the data. Figure 3. MC13191 Packet Structure

4.2 Receive Path Description

(O-QPSK) signal, determines the symbols and packets, and detects the data. over a 64 µs period after the packet preamble and stored in RAM. RAM. The MCU is notified that an entire packet has been received via an interrupt. Figure 4 shows energy detection reported power versus input power. The 802.15.4 Standard accuracy and range limits are shown for reference. Figure 4. Reported Power Level Versus Input Power for ED or LQI

4.3 Transmit Path Description

packets, spread, and then up-converted to the transmit frequency. an interrupt when the whole packet has successfully been transmitted.

802.15.4 Accuracy

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5 Electrical Characteristics

5.1 Maximum Ratings

5.2 Recommended Oper ating Conditions

Table 1. Absolute Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. Note: ESD protection meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection. Table 2. Recommended Operating Conditions 1 If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak.

5.3 DC Electrical Characteristics

Table 3. DC Electrical Characteristics 2 CLKO frequency at default value of 32.786 kHz.

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5.4 AC Electrical Characteristics

Table 4. Receiver AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. 1 SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). 2 SPI Register 12 programmed to 0x00FF which sets output power to maximum.

Figure 5 shows a typical AC parameter evaluation circuit. Figure 5. AC Parameter Evaluation Circuit Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted.

16 MHz CLK

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6 Functional Description

6.1 MC13191 Operational Modes

along with the transition times while Table 3 lists current drain in the various modes.

6.2 Serial Peripheral Interface (SPI)

1. Chip Enable (CE ) - A transaction on the SPI port is framed by the active low CE input signal. A

transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.

1. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13191. Data is clocked into the

state on the trailing (falling) edge of SPICLK. control bit CPHA = 0 and the clock polarity control bit CPOL = 0.

1. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
2. Master In/Slave Out (MISO) - The MC13191 pres ents data to the master on the MISO output.

A typical interconnection to a microcontroller is shown in Figure 6. Table 7. MC13191 Mode Definitions and Transition Times programmed to enter Idle Mode through an internal timer comparator. Idle Crystal Reference Oscillator On with CLKO output available. SPI active.

Figure 6. SPI Interface

6.2.1 SPI Burst Operation

of a single SPI burst is shown in Figure 6. Figure 7. SPI Single Burst Timing Diagram. SPI digital timing specifications are shown in Table 6.

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6.2.2 SPI Transaction Operation

the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 8. Figure 8. SPI Read Transaction Diagram

7 Pin Connections

Table 8. Pin Function Description 1 RFIN- RF Input LNA negative differential input. 2 RFIN+ RF Input LNA positive differential input.

5 PAO+ RF Output /DC

9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” indicator. 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” indicator. high, IC goes to IDLE Mode, with SPI in default state. return RXTXEN to low. When held low, forces Idle Mode. 20 IRQ Digital Output Active Low Interrupt Request. Open drain device. 21 VDDD Power Output Digital regulated supply bypass. Decouple to ground. Table 8. Pin Function Description (continued)

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27 XTAL2 Input/Output Crystal Reference oscillator output

Note: Do not load this pin by using it as a 16 MHz source. 28 VDDLO2 Power Input LO2 VDD supply. Connect to VDDA externally. 29 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally. 30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 31 VBATT Power Input Analog voltage regulators Input. Connect to Battery. Decouple to ground. EP Ground External paddle / flag ground. Connect to ground. should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. zero so that MISO is driven low when CE is negated.

Figure 9. Pin Connections (Top View)

MC13191 Technical Data, Rev. 1.5

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8 Applications Information

This section provides application specific information regarding crystal oscillator reference frequency, a basic design example for interfacing the MC13191 to an MCU and recommended crystal usage.

8.1 Crystal Oscillator Reference Frequency

For low long term drift, users may require that several frequency tolerances be kept as low as ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13191 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors exist that contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal res onant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal re sonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - init ial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - incl uding stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. Freescale requires the use of a 16 MHz crystal with a <9 pF load capacitance. The MC13191 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13191 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF for a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately ±15%.

MC13191 Technical Data, Rev. 1.5 Freescale Semiconductor 17 Because the MC13191 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis. A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the desired specification.

8.2 Design Example

Figure 10 shows a basic application schematic for interfacing the MC13191 with an MCU. Table 9 lists the Bill of Materials (BOM). The MC13191 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design. The 16 MHz crystal should be mounted close to the MC13191 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table 10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. Other crystals are listed in Section 8.3, “Crystal Requirements”. VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13191. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. In this case, RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO.

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Figure 10. MC13191 Configured With a MCU

8.3 Crystal Requirements

Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x. Table 9. MC13191 to MCU Bill of Materials (BOM)

21 C 1 1 µF

81 I C 2 µPG2012TK-E2 NEC

Table 10. MC13191 Crystal Specifications1

MC13191 Technical Data, Rev. 1.5

20 Freescale Semiconductor

8.4 Low Power Considerations

• Program and use the modem IO pi ns properly for low power operation — All unused modem GPIOx signals must be used one of 2 ways: – If the Off mode is to be us ed as a long term low power mode, unused GPIO should be tied to ground. The default GPIO mode is an input and there will be no conflict. – If only Hibernate and/ or Doze modes are used as long term low power modes, the GPIO should programmed as outputs in the low state. — When modem GPIO are used as outputs: – Pullup resistors should be provi ded (can be provided by the MCU IO pin if tied to the MCU) if the modem Off condition is to be used as a long term low power mode. – During Hibernate and/or Doze modes, the GP IO will retain its programmed output state. — If the modem GPIO is used as an input, the GPIO should be driven by its source during all low power modes or a pullup resistor should be provided. — Digital outputs IRQ , MISO, and CLKO: – MISO - is always an output. During Hibern ate, Doze, and active modes, the default condition is for the MISO output to go to tristate when CE is de-asserted, and this can cause a problem with the MCU because one of its inputs can float. Program Control_B Register 07, Bit 11, miso_hiz_en = 0 so that MISO is driven low when CE is de-asserted. As a result, MISO will not float when Doze or Hibernate Mode is enabled. –I R Q - is an open drain output (OD) and should always have a pullup resistor (typically provided by the MCU IO). IRQ acts as the interrupt request output. NOTE It is good practice to have the IRQ interrupt input to the MCU disabled during the hardware reset to the modem. After releasing the modem hardware reset, the interrupt request input to the MCU can then be enabled to await the IRQ that signifies the modem is ready and in Idle mode; this can prevent a possible extraneous false interrupt request. – CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used.
• If the MCU is also going to be used in low power modes, be sure that all unused IO are programmed properly for low power operation (typically best case is as outputs in the low state). The MC13191 is commonly used with the Freescale MC9S08GT/GB 8-bit devices. For these MCUs: — Use only STOP2 and STOP3 modes (not STOP1) wi th these devices where the GPIO states are retained. The MCU must retain control of the MC13191 IO during low power operation. 1 User must be sure manufacturer specifications apply to the desired package. 2 A wider frequency tolerance may acceptable if application uses trimming at production final test. 3 A wider frequency stability may be acceptable if application uses trimming at production final test. 4 A wider aging tolerance may be acceptable if application uses trimming at production final test. 5 Higher ESR may be acceptable with lower load capacitance. 6 Lower load capacitance can allow higher ESR and is better for low temperature operation in Doze mode.

MC13191 Technical Data, Rev. 1.5 Freescale Semiconductor 21 — As stated above all unused GP IO should be programmed as outputs low for lowest power and no floating inputs. — MC9S08GT devices have IO signals that are not pinned-out on the package. These signals must also be initialized (even though they cannot be used) to prevent floating inputs.

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9 Packaging Information

Figure 11. Outline Dimensions for QFN-32, 5x5 mm

1.5 BACKSIDE

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
4. CORNER CHAMFER MAY NOT BE PRESENT.
5. COPLANARITY APPLIES TO LEADS, CORNER
6. FOR ANVIL SINGULATED QFN PACKAGES,

MC13191 Technical Data, Rev. 1.5 Freescale Semiconductor 23

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