MC13191 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC13191 Rev. 1.3, 08/2005 MC13191
Package Information
(QFN-32) (Scale 1:1)
Ordering Information
Device Device Marking Package MC13191 13191 QFN-32
1 Introduction
The MC13191 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13191 contains a complete packet data modem which is compliant with the IEEE® 802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 compliance, the MC13192 and Freescale's 802.15.4 MAC software are required. When combined with an appropriate microcontroller (MCU), the MC13191 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point to star networks. MC13191
2.4 GHz ISM Band Low Power
Contents
MC13191 Technical Data, Rev. 1.3
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Features
For more detailed information about MC13191 operation, refer to the MC13191 Reference Manual, part number MC13191RM. Applications include, but are not limited to, the following:
- Remote control and wire repla cement in industrial systems such as wireless sensor networks
- Factory automation and motor control
- Energy Management (lighting, HV AC, etc.)
- Asset tracking and monitoring Potential consumer applications include:
- Home automation and control (l ighting, thermostats, etc.)
- Human interface devices (keyboard, mice, etc.)
- Remote entertainment control
- Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.
2 Features
- IEEE 802.15.4 PHY Compliant — 16 Channels — Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode/decode — RX sensitivity of -91 dBm (typi cal) at 1.0% packet error rate
- Recommended power supply range: 2.0 to 3.4 V
- 0 dBm nominal, programmable from -27 dB m to 4 dBm typical maximum output power
- Buffered transmit and receiv e data packets for simplified use with low cost MCUs
- Three power down modes for power conservation: — < 1.0 µA Off current — 2.3 µA Typical Hibernate current — 35 µA Typical Doze current (no CLKO)
- Two internal timer comparators availa ble to reduce MCU resource requirements
- Programmable frequency clock output for use by MCU
- Onboard trim capability for 16 MHz crystal referen ce oscillator eliminates the need for external variable capacitors and allows for automated production frequency calibration.
- Seven general purpose in put/output (GPIO) signals
- Operating temperature range: -40 °C to 85 °C
- Small form factor QFN-32 Package
MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 3 — RoHS compliant — Meets moisture sensitivity level (MSL) 3 — 260 °C peak reflow temperature — Meets lead-free requirements
3 Block Diagrams
Figure 2 shows a simplified block diagram of the MC13191 transceiver that meets the requirements of the IEEE 802.15.4 PHY . Figure 3 shows the basic system block diagram for the MC13191 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.
4 Data Transfer Mode
The MC13191 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits wide.
4.1 Packet Structure
Figure 4 shows the packet structure of the MC13191 which is consistent with the IEEE 802.15.4 Standard. Payloads of up to 125 bytes are supported. The MC13191 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data.
4.2 Receive Pa th Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. An Energy Detect can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM. The MC13191 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet RAM. The MCU is notified that an entire packet has been received via an interrupt.
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accuracy and range limits are shown for reference. Figure 1. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
802.15.4 Accuracy
4.3 Transmit Path Description
packets, spread, and then up-converted to the transmit frequency. an interrupt when the whole packet has successfully been transmitted. Figure 2. MC13191 Simplified Block Diagram
256 M Hz
2.45 GHz
24 Bit Ev ent Timer
16 M Hz
2 Programmable
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Figure 3. System Level Block Diagram Figure 4. MC13191 Packet Structure
Electrical Characteristics
MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 7
5 Electrical Characteristics
5.1 Maximum Ratings
5.2 Recommended Operating Conditions
Table 1. Absolute Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. PAO± = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection. Table 2. Recommended Operating Conditions
MC13191 Technical Data, Rev. 1.3
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5.3 DC Electrical Characteristics
Table 3. DC Electrical Characteristics
MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 9
5.4 AC Electrical Characteristics
All AC parameters measured with SPI Registers at default settings except where noted and the following registers over-programmed: Register 08 = 0xFFF7 and Register 11 = 0x20FF Table 4. Receiver AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. 1 SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). 2 SPI Register 12 programmed to 0x00FC which sets output power to maximum.
MC13191 Technical Data, Rev. 1.3
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Figure 5. Parameter Evaluation Circuit
16 MHz CLK
6 Functional Description
6.1 MC13191 Operational Modes
Table 6. MC13191 Mode Definitions and Transition Times Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
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6.2 Serial Periphe ral Interface (SPI)
- Chip Enable (CE ) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
- SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13191. Data is clocked into
changes state on the trailing (falling) edge of SPICLK. control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
- Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
- Master In/Slave Out (MISO) - The MC13191 pres ents data to the master on the MISO output.
A typical interconnection to a microcontroller is shown in Figure 6. Figure 6. SPI Interface
6.2.1 SPI Burst Operation
of a single SPI burst is shown in Figure 6. Figure 7. SPI Single Burst Timing Diagram. Table 7. SPI Timing Specifications
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6.2.2 SPI Transaction Operation
the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 8. Figure 8. SPI Read Transaction Diagram
7 Pin Connections
Table 8. Pin Function Description 1 RFIN- RF Input LNA negative differential input. 2 RFIN+ RF Input LNA positive differential input. functions as a “CRC Valid” indicator. functions as an “Out of Idle” indicator. is lost from RAM and SPI registers. either Hibernate or Doze Modes to Idle. 15 CLKO Digital Output Clock output to host MCU.
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz,
16 SPICLK Digital Clock Input External clock input for the SPI interface.
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20 IRQ Digital Output Active Low Interrupt Request. Open drain device. 21 VDDD Power Output Digital regulated supply bypass. Decouple to ground.
22 VDDINT Power Input Digital interface supply & digital regulator
27 XTAL2 Input/Output Crystal Reference oscillator output
30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 32 VDDA Power Output Analog regulated supply Output. circuitry external to the chip. EP Ground External paddle / flag ground. Connect to ground. should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. Table 8. Pin Function Description (continued)
Figure 9. Pin Connections (Top View)
MC13191 Technical Data, Rev. 1.3
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8 Applications Information
8.1 Crystal Oscillat or Reference Frequency
For low long term drift, users may require that several frequency tolerances be kept as low as ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13191 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors exist that contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal res onant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal re sonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - init ial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - incl uding stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. The MC13191 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13191 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF for a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately ±15%. Because the MC13191 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis.
MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 19 A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the desired specification.
8.2 Design Example
Figure 10 shows a basic application schematic for interfacing the MC13191 with an MCU. Table 9 lists the Bill of Materials (BOM). The MC13191 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design. The 16 MHz crystal should be mounted close to the MC13191 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table 10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. A second crystal that has been evaluated and also gives acceptable performance is the Toyocom TSX-10A 16 MHZ TN4-26139 (see Table 11). VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13191. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. In this case, RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO.
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Figure 10. MC13191 Configured With a MCU
Table 9. MC13191 to MCU Bill of Materials (BOM)
21 C 1 1 µF
81 I C 2 µPG2012TK-E2 NEC
Table 10. Daishinku, KDS - DSX321G, ZD00882 Crystal Specifications
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Table 11. Toyocom TSX-10A 16 MHZ TN4-26139 Crystal Specifications
9 Packaging Information
Figure 11. Outline Dimensions for QFN-32, 5x5 mm
1.5 BACKSIDE
- ALL DIMENSIONS ARE IN MILLIMETERS.
- DIMENSIONING AND TOLERANCING PER ASME
- THE COMPLETE JEDEC DESIGNATOR FOR THIS
- CORNER CHAMFER MAY NOT BE PRESENT.
- COPLANARITY APPLIES TO LEADS, CORNER
- FOR ANVIL SINGULATED QFN PACKAGES,
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