MC13145FTA

ML13145 LANSDALE | Alldatasheet

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www.lansdale.comPage 1 of 17 Issue 0 ML13145 UHF Wideband Receiver Subsystem (LNA, Mixer, VCO, Prescaler, IF Subsystem, Coiless Detector) Legacy Device: Motorola MC13145 The ML13145 is a dual conversion integrated RF receiver intended for ISM band applications. It features a Low Noise Amplifier (LNA), two 50 Ω linear Mixers with linearity control, V oltage Controlled Oscillator (VCO), second LO amplifier, divide by 64/65 dual modulus Prescalar, split IF Amplifier and Limiter, RSSI output, Coilless FM/FSK Demodulator and power down con- trol. Together with the transmit chip (ML13146) and the baseband chip (MC33410 or MC33411A/B), a complete 900 MHz cordless phone system can be implemented. This device may be used in applications up to 1.8 GHz, and operating temperature TA = –20° to +70°C.

• Low (<1.8 dB @ 900 MHz) Noise Figure LNA with 14 dB Gain
• Externally Programmable Mixer linearity: IIP3 = 10(nom.) to 17 dBm (Mixer1); IIP3 = 10 (nom.) to 17 dBm (Mixer2)
• 50 Ω Mixer Input Impedance and Open Collector Output (Mixer 1 and Mixer 2); 50 Ω Second LO (LO2) Input Impedance
• Low Power 64/65 Dual Modulus Prescalar (ML12054A type)
• Split IF for Improved Filtering and Extended RSSI Range
• Internal 330 Ω Terminations for 10.7 MHz Filters
• Linear Coilless FM/FSK Demodulator with Externally Programmable Bandwidth, Center Frequency and Audio level
• 2.7 to 6.5 V Operation, Low Current Drain (<27 mA, T yp @ 3.6 V) with Power Down Mode (<10 µA, T yp)
• 2.4 GHz RF , 1.0 GHz IF1 and 50 MHz IF2 Bandwidth LQFP 48 = -9P PLASTIC PACKAGE CASE 932 48 1 CROSS REFERENCE/ORDERING INFORMATION MOTOROLA LQFP 48 MC13145FTA ML1 3145-9P LANSDALEPACKAGE Note: Lansdale lead free ( Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.PIN CONNECTIONS AND FUNCTIONAL BLOCK DIAGRAM VEE BWadj Lim Dec2 Lim Dec1 Lim In VCC VCC IF Out VEE LNA In VEE VEE LNA Out VEE Mxr1In Lin Adj1 V CC +1FI 25 26 29 30 31 3227 28 12 11 8 7 6 510 9 Enable oscC oscE oscB 4321 33 34 35 36 IF Dec2 IF Dec1 IF In VEE V EE –1FI 2jdAniL nI rxM V CC V EE 2OL V EE +2FI –2FI V CC V CC CM tuO CSRP V EE ISSR tuO teD niaG teD nI TFA tuO TFA V EE F jda Lim Demod LNA lortnoC /64, 65 IF LO RF IF2 IF1 ESD Sensitive — Handle with Care This device contains 626 active transistors. LOW POWER INTEGRATED RECEIVER FOR ISM BAND APPLICATIONS SEMICONDUCTOR TECHNICAL DATA

www.lansdale.comPage 2 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage VCC(max) 7.0 Vdc Junction Temperature TJ(max) 150 Storage Temperature Range Tstg –65 to 150 Maximum Input Signal P in 5.0 dBm NOTES: 1. Meets Human Body Model (HBM) ≤250 V and Machine Model (MM) ≤25 V. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Power Supply Voltage (TA = 25°C) VCC 2.7 6.5 Vdc VEE Input Frequency (LNA In, Mxr1 In) fin 100 1800 MHz Ambient Temperature Range TA –20 Input Signal Level (with minor performance degradation) Pin –10 dBm RECEIVER DC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; No Input Signal, unless otherwise noted) Characteristics Symbol Min Typ Max Unit Total Supply Current (Enable = VCC) Itotal mA Power Down Current (Enable = VEE) Itotal A RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = ±40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit) Characteristics Input Pin Measure Pin Symbol MIn Typ Max Unit SINAD @ –110 dBm LNA Input LNA In Det Out SINAD dB 12 dB SINAD Sensitivity (Apps Circuit with C–message filter at DetOut) LNA In Det Out SINAD12dB –115 dBm 30 dB SINAD Sensitivity (No IF filter distortion within ±40 kHz) LNA In Det Out SINAD30dB –100 dBm SINAD Variation with IF Offset of ±40 kHz (No IF filter distortion within ±40 kHz) LNA In Det Out 5.0 dB Noise Figure: LNA, 1st Mixer & 2nd Mixer LNA In IF Out NF – 3.5 5.0 dB Power Gain: LNA, 1st Mixer & 2nd Mixer LNA In IF Out G 15 19 25 dB RSSI Dynamic Range IF In RSSI dB RSSI Current IF In RSSI – µA –10 dBm @ IF Input 35 40 55 –20 dBm @ IF Input –3 5– –30 dBm @ IF Input –3 0– –40 dBm @ IF Input –2 5– –50 dBm @ IF Input 15 20 37 –60 dBm @ IF Input –1 5– –70 dBm @ IF Input –1 0– –80 dBm @ IF Input – 5.0 – –90 dBm @ IF Input – 1.0 7.0 Input 1.0 dB Compression Point(Measured at IF output) Pin1dB –18 dBm Input 3rd Order Intercept Point (Measured at IF output) IIP3 –8.0 dBm Demodulator Output Swing (50 k || 56 pF Load) IF In Det Out Vout 0.8 1.0 1.2 Vpp

www.lansdale.comPage 3 of 17 Issue 0 RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = ±40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit) Characteristics UnitMaxTypMInSymbol Measure Pin Input Pin Demodulator Bandwidth (±1.0 dB bandwidth) Det Out BW 100 kHz Prescalar Output Level (10 k //8.0 pF load) PRSCout Vout Vpp Prescaler 64 Frequency = 16.72968 MHz 0.4 0.51 0.6 Prescaler 65 Frequency = 16.4723 MHz 0.4 0.51 0.6 MC Current Input (High) MC I ih 70 100 130 µA MC Current Input (Low) MC I il –130 –100 –70 µA Input high voltage Enable V ih VCC – 0.4 –V CC V Input low voltage Enable V il 0 – 0.4 V Input Current Enable I in –50 – 50 µA PLL Setup Time [Note 1] MC PRSC out TPLL –1 0–n S SNR @ –30 dBm Signal Input (<40 kHz deviation;with C–Message Filter) dB Total Harmonic Distortion (<40 kHz deviation;with C–Message Filter) 1.0 Spurious Response SINAD (RF In: –50 dBm) dB LANSDALE Semiconductor, Inc. ML13145

Figure 1. Test Circuit

900 Mhz ISM Band Cordless phones and wideband data links

detector, and a device enable function. applications. Supply current is typically 27 mA at 3.6 Vdc. up and ”low” powers down the entire circuit. transistor under all power levels. under PLL synthesizer control. rent proportional to the log of the received signal amplitude. ly 80 dB of dynamic range with temperature compensation. 330 Ω source and load impedance. of the IF amplifier block is approximately 40 dB up to 40MHz. nally drives the coilless quadrature detector section. conventional tunable quadrature coil in FM receiver systems. put) and the other to filter and tune the detector (AFT). Figure 2. 2nd Mixer NF & Gain

www.lansdale.comPage 6 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 PIN FUNCTION DESCRIPTION Pin Symbol/Type

Description

47 BWadj See Figure 3. COILLESS DETECTOR Bandwidth Adjust The deviation bandwidth of the detector response is determined by the combination of an on–chip capacitor and an external resistor to ground. Fadj Frequency Adjust The free running frequency of the detector oscillator is defined by the combination of an on–chip capacitor and an external resistor, Radj from frequency adjust pin to ground. 1, 48 V EE VEE, Negative Supply These pins are VEE supply for the coilless detector circuit.

3 AFT Out AFT Out

The AFT is low pass filtered with a corner frequency below the audio bandwidth allowing the error to be added to the center frequency adjust signal at Fadj, Pin 2. The low frequency high pass corner is set by the external capacitor, Ct from AFT out (Pin 3) to AFT in (Pin 4) and external resistor, Rt from AFT out to Fadj (Pin 2). AFT In AFT In The AFT in is used to set the buffer transfer function. Det Gain Detector Gain The AFT buffer is used to set the buffer transfer function. Det Out Detector Output Set gain and output level of detector with resistor to Det Out Pin. Figure 3. Coilless Detector Internal Circuit

www.lansdale.comPage 7 of 17 Issue 0 LANSDALE Semiconductor, Inc. ML13145 Pin Symbol/Type VEE, Negative Supply Voltage PRSCout PRSC Out VEE

8 VCC

1.0 mA Prescaler Output The prescaler output provides typically 500 mVpp drive to the fin pin of a PLL synthesizer. Conjugately matching the interface will increase the drive delivered to the PLL input. 10 MC VEE MC Dual Modulus Control Current Input This requires a current input of typically 200 µApp. 11, 12 VCC VCC, Positive Supply VCC pin is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It decoupled to VEE ground at the pin of the IC. LNA In LNAout VEE 15, 16 LNA In The input is the base of the common emitter transistor. Minimum external matching is required to optimize the input return loss and gain. 13, 15, & 16 VEE 2.0 mA Vref2 Vref1 VEE LNAin VCC 11,12 VEE, Negative Supply VEE pin is taken to an ample dc ground plane through a low impedance path. The path should be kept as short as possible. A minimum two sided PCB is recommended so that ground returns can be easily made through via holes. LNAout CC LNA Out The output is from the collector of the cascode transistor amplifier. The output may be conjugately matched with a shunt L (needed to dc bias the open collector), and series L and C network. Mxr1In LinAdj1 VCC 1st Mixer Input The mixer input impedance is broadband 50 Ω for applications up to 2.4 GHz. It easily interfaces with a RF ceramic filter. Lin Adj1 Mxr1 In 450 µA 1st Mixer Linearity Control The mixer linearity control circuit accepts approximately 0 to 300 µA control current to set the dynamic range of the mixer. An Input Third Order Intercept Point, IIP3 of 17 dBm may be achieved at 300 µA of control current.

www.lansdale.comPage 8 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 Enable the receiver by pulling the pin up to VCC. VEE VEE, Negative Supply VEE supply for the mixer IF output. IF1+ IF1+ VEE 1st Mixer Outputs The Mixer is a differential open collector output configuration which is designed to use over a wide frequency range. The differential output of the mixer has back to back diodes across them to limit the out ut voltage swing and to revent ulling of the IF1– IF1– out ut voltage swing and to revent ulling of the VCO. Differential to single–ended circuit configuration and matching options are shown in the Test Circuit. Additional mixer gain can be achieved by matching the outputs for the desired passband Q. Collector On–board VCO Transistor The transistor has the emitter, base, collector, VCC, and VEE pins available. Internal biasing which is Emitter VCC compensated for stability over temperature is provided. It is recommended that the base pin is pulled up to VCC through an RFC chosen for the particular oscillator center frequency Base Base 18, 26 particular oscillator center frequency . VCC VEE Emitter 500 µA2.0 mA VCC, Positive Supply Voltage A VCC pin is provided for the VCO. The operating supply voltage range is from 2.7 Vdc to 6.5 Vdc. 18, 26 VEE Collector VEE, Negative Supply Voltage Lin Adj2 Lin Adj2 31, VCC 2nd Mixer Linearity Control The mixer linearity control circuit accepts approximately 0 to 400 µA control current to set the dynamic range of the mixer. An Input Third Order Intercept Point, IIP3 of 17 dBm may be achieved at 400 µA of control current. IIP3 default with no external bias is 10 dBm. Mxr2 In Mxr2 In 450 µ 2nd Mixer Input The mixer input impedance is broadband 50 Ω. VCC 450 µA VCC, Positive Supply pp p

www.lansdale.comPage 9 of 17 Issue 0 LANSDALE Semiconductor, Inc. ML13145 32, 34 VEE VCC LO Out+ LO Out– (to Mxr2) VEE, Negative Supply Voltage LO2 LO2 VEE 390 µA 2nd Local Oscillator The 2nd LO input impedance is broadband 50 Ω; it is driven from an external 50 Ω source. Typical level is –15 to –10 dBm. IF2+ IF2+ VEE 2nd Mixer Outputs The Mixer is a differential open collector configuration. IF2– IF2– VEE See Figure 4. VEE, Negative Supply Voltage IF In IF Amplifier Input IF amplifier input source impedance is 330 Ω.. The three stage amplifier has 40 dB of gain with 3.0 dB bandwidth of 40 MHz. 39, 40 IF Dec1, IF Dec2 IF Decoupling These pins are decoupled to VCC to provide stable operation of the limiting IF amplifier. IF Out IF Amplifier Output IF amplifier output load impedance is 330 Ω. VCC VCC, Positive Supply Voltage RSSI RSSI The RSSI circuitry in the 2nd & 3rd amplifier stages outputs a current when the output of the previous stage enters limiting. The net result is a RSSI current which represents the logarithm of the IF input voltage. An external resistor to ground is used to provide a voltage output.

Table 1. LNA S–Parameters: 3.6 Vdc

www.lansdale.comPage 14 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 tuO teD1 ISSR NE xR DP xR CM XR xRF 184/0841FC nI ANL rxM 1 nI Bcso 2OL 1PJ 2X5H p 001 1C p 001 3C p 001 15C k 33 3R 41C p 0.4 – 0.2 nI ANL Ccso Ecso Bcso 2OL 1jdA niL 2jdA niL jdaWB jdaF tuO TFA nI TFA elbanE CM NE xR CM xR DP xR 10.0 51C V CC 10.0 61C D/U 7R n 0.1 33C n 0.1 43C D/U 8R k 86 9R k 7.2 01R k 86 11R 10.0 53C k 15 6R D/U 21R rxM 2 nI V CC dnG 2PT 1PT 01 04C22 94C 0.1 05C n 0.1 63C n 0.1 73C n 0.1 83C n 0.1 93C p 001 44C p 001 34C p 001 24C p 001 14C V CC CFR 6L n 6.5 D/U p 001 5C n 0.1 6C V CC 54C p 3.3 D/U D/U tuO ANL tuO 1FI V CC tuO 1FID/U 25C p 61 9C 10.0 8C p 001 7C 01 2R V CC p 01 01C p 21 11C 10.0 35C 7.2 4L 7.2 5L p 03 02C O/I 2FI 3PT nI FI repmuJ 2PJ p 001 71C 10.0 81C n 7.2 7L 31R p 0.2 64C p 0.2 74C p 001 84C 908VBMM 1D n 0.1 21C p 001 31C p 5.1 2C V CC p 63 91C n 0.1 62C n 0.1 72C 1.0 52C n 0.1 82C n 0.1 92C 1.0 03C k 72 5R p 001 13C k 15 41R n 0.1 45C 10.0 23C V CC CF2 CF3 tuO teD ISSR n 0.1 12C 1.0 22C n 0.1 32C 1.0 42C 4PT tuO FI 01 FI 01 FI tuO ANL +1FI –1FI +2FI –2FI 1ceD FI 2ceD FI nI FI tuO FI 1ceD miL 2ceD miL nI miL niaG teD tuO teD ISSR tuO CSRP xRF 5PT rxM 2 nI rxM 1 nI Figure 15. citamehcS BCP noitaulavE 54131LM .51 erugiF n 8.6 1L ML13145

Figure 16. Evaluation PCB Component Side Figure 17. Evaluation PCB Solder Side

www.lansdale.comPage 16 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 Legacy Applications Information

www.lansdale.comPage 17 of 17 Issue 0 LANSDALE Semiconductor, Inc.ML13145 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.