MC10E016 ONSEMI | Alldatasheet

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/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA 2–1 REV 2 Motorola, Inc. 1996 /C0056/C0262/C0066/C0105/C0116 /C0083/C0121/C0110/C0099/C0104/C0114/C0111/C0110/C0111/C0117/C0115 /C0066/C0105/C0110/C0097/C0114/C0121 /C0085/C0112 /C0067/C0111/C0117/C0110/C0116/C0101/C0114 The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to a utomatically reload u pon T C = L OW , thus functioning a s a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.

  • 700MHz Min. Count Frequency
  • 1000ps CLK to Q, TC
  • Internal TC Feedback (Gated)
  • 8-Bit
  • Fully Synchronous Counting and TC Generation
  • Asynchronous Master Reset
  • Extended 100E VEE Range of – 4.2V to – 5.46V
  • 75kΩ Input Pulldown Resistors FUNCTION TABLE CE PE TCLD MR CLK Function X L X L Z Load Parallel (Pn to Qn) L H L L Z Continuous Count L H H L Z Count; Load Parallel on TC = LOW H H X L Z Hold X X X L ZZ Masters Respond, Slaves Hold X X X H X Reset (Qn : = LOW, TC : = HIGH) Z = clock pulse (low to high); ZZ = clock pulse (high to low) PIN NAMES Pin Function P0 – P7 Parallel Data (Preset) Inputs Q 0 – Q7 Data Outputs CE Count Enable Control Input PE Parallel Load Enable Control Input MR Master Reset CLK Clock TC Terminal Count Output TCLD TC-Load Control Input /C0077/C0067/C0049/C0048/C0069/C0048/C0049/C0054 /C0077/C0067/C0049/C0048/C0048/C0069/C0048/C0049/C0054 8-BIT SYNCHRONOUS BINARY UP COUNTER FN SUFFIX PLASTIC PACKAGE CASE 776-02 Pinout: 28-Lead PLCC (Top View) MR CLK TCLD VEE NC 25 24 23 22 21 20 19 115 6 7 8 9 10 PE CE P7 P6 P5 VCCO TC Q 7 Q 6 VCC Q 5 Q 4 Q 3 P2 P3 P4 VCCO Q 0 Q 1 Q 2 VCCO * All VCC and VCCO pins are tied together on the die.

MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 4 2–2 8-BIT BINARY COUNTER LOGIC DIAGRAM Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. SLAVEMASTER TC Q 1Q 0 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 CE Q 0 BIT 1CE Q 0Q0M Q0M BIT 0 PE TCLD CE PO MR CLK BIT 7 BITS 2–6 Q 7

2–3 MOTOROLAECLinPS and ECLinPS Lite DL140 — Rev 4 DC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) 0°C 25°C 85°C Symbol Characteristic min typ max min typ max min typ max Unit Condition IIH Input HIGH Current 150 150 150 µA IEE Power Supply Current mA 10E 151 181 151 181 151 181 100E 151 181 151 181 174 208 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) 0°C 25°C 85°C Symbol Characteristic min typ max min typ max min typ max Unit Condition fCOUNT Max. Count Frequency 700 900 700 900 700 900 MHz tPLH Propagation Delay to Output ps tPHL CLK to Q 600 725 1000 600 725 1000 600 725 1000 MR to Q 600 775 1000 600 775 1000 600 775 1000 CLK to TC 550 775 900 550 775 900 550 775 1050 MR to TC 625 775 1000 625 775 1000 625 775 1000 ts Setup Time ps Pn 150 – 30 150 – 30 150 – 30 CE 600 400 600 400 600 400 PE 600 400 600 400 600 400 TCLD 500 300 500 300 500 300 th Hold Time Pn 350 100 350 100 350 100 CE 0 – 400 0 – 400 0 – 400 PE 0 – 400 0 – 400 0 – 400 TCLD 100 – 300 100 – 300 100 – 300 tRR Reset Recovery Time 900 700 900 700 900 700 ps tPW Minimum Pulse Width ps CLK, MR 400 400 400 tr Rise/Fall Times ps tf 20 - 80% 300 510 800 300 510 800 300 510

E016 as a programmable divider set up to divide by 113. Figure 2. Mod 2 to 256 Programmable Divider Table 1. Preset Values for Various Divide Ratios

2 H H H H H H H L

3 H H H H H H L H

4 H H H H H H L L

5 H H H H H L H H

112 H L L H L L L L

113 H L L L H H H H

114 H L L L H H H L

254 L L L L L L H L

255 L L L L L L L H

256 L L L L L L L L

divided as desired with a 50% duty cycle. used for multiple E016 divider chains.

  • •• PE
  • ••
  • •• Clock TC Load DIVIDE BY 113 Load1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111

Figure 3. Divide by 113 E016 Programmable Divider Waveforms

2–7 MOTOROLAECLinPS and ECLinPS Lite DL140 — Rev 4 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) T L –M S N SM 0.007 (0.180) T L –M S N SM 0.007 (0.180) T L –M S N SM 0.010 (0.250) T L –M S N SS 0.007 (0.180) T L –M S N SM 0.010 (0.250) T L –M S N SS 0.007 (0.180) T L –M S N SM 0.007 (0.180) T L –M S N SM 0.004 (0.100) SEATING PLANE -T- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10° 10.92

1.27 BSC

A B C E F G H J K R U V W X Y Z MIN MIN MAX MAX INCHES MILLIMETERS DIM NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). VIEW S B U Z G1X VIEW D-D H K F VIEW S G C Z A R E J 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10° 0.430

0.050 BSC

-N- Y BRK D DW -M--L- 28 1 V

MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 4 2–8 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; T atsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P .O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 T atsumi Koto–Ku, T okyo 135, Japan. 03–81–3521–8315 INTERNET : http://Design–NET .com 51 Ting Kok Road, T ai Po, N.T ., Hong Kong. 852–26629298 MC10E016/D /C0042/C0077/C0067/C0049/C0048/C0069/C0048/C0049/C0054/C0047/C0068/C0042