MC07XSG517DEK

NXP Semiconductors

Multi-purpose high-side switches Rev. 5-21 July 2021

Manufacturer: NXP Semiconductors

Document: 66 Pages / 3Mb

Request Quote Download Datasheet Read online HTML view

More from NXP Semiconductors Browse M parts

Online Datasheet

Read MC07XSG517DEK online.

MC32XSG NXP | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 66

Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Simplified application diagram
4 Applications
5 Ordering information
6 Internal block diagram
7 Pinning information
7.1 Pinning
7.2 Pin description
8 General product characteristics
8.1 Relationship between ratings and operating
8.2 Maximum ratings
8.3 Thermal characteristics
8.4 Operating conditions
8.5 Supply currents
9 General IC functional description and
9.1 Introduction
9.2 Features
9.3 Block diagram
9.3.1 Self-protected high-side switches
9.3.2 Power supply
9.3.3 MCU interface and device control
9.4 Functional description
9.5 Modes of operation
9.5.1 Power Off mode
9.5.2 Sleep mode
9.5.3 Normal mode
9.5.4 Fail mode
9.5.5 Mode transitions
9.6 SPI interface and configurations
9.6.1 Introduction
9.6.2 SPI input register and bit descriptions
9.6.3 SPI output register and bit descriptions
9.6.4 Timing diagrams
9.6.5 Electrical characterization
10 Functional block requirements and
10.1 Self-protected high-side switches
10.1.1 Features
10.1.2 Output pulse shaping
10.1.2.1 SPI control and configuration
10.1.2.2 Global PWM control
10.1.2.3 Incremental PWM control
10.1.2.4 Input control
10.1.2.5 Electrical characterization
10.1.3 Output protections
10.1.3.1 Overcurrent protections
10.1.3.2 Overcurrent control programming
10.1.3.3 Electrical characterization
10.1.3.4 Overtemperature protection
10.1.3.5 Undervoltage and overvoltage protections
10.1.3.6 Charge pump protection
10.1.4 Digital diagnostics
10.1.4.1 Openload detections
10.1.4.2 Output shorted to VPWR in OFF state
10.1.4.3 SPI fault reporting
10.1.5 Analog diagnostics
10.1.5.1 Output current monitoring
10.1.5.2 Supply voltage monitoring
10.1.5.3 Temperature monitoring
10.1.5.4 Analog diagnostic synchronization
10.1.5.5 Electrical characterization
10.2 Power supply functional block description
10.2.1 Introduction
10.2.2 Wake state reporting
10.2.2.1 Electrical characterization
10.2.3 Supply voltage disconnection
10.2.3.1 Loss of VPWR
10.2.3.2 Loss of VCC
10.2.3.3 Loss of device GND
10.2.3.4 Electrical characterization
10.3 Communication interface and device
10.3.1 Introduction
10.3.2 Fail mode input (LIMP)
10.3.2.1 Electrical characterization
10.3.3 MCU communication interface protections
10.3.3.1 Loss of communication interface
10.3.3.2 Logic I/O plausibility check
10.3.3.3 Electrical characterization
10.3.4 External smart power control (OUT6)
10.3.4.1 Electrical characterization
11 Typical applications
11.1 Introduction
11.1.1 Application diagram
11.1.2 Bill of materials
12 Packaging
12.1 Package mechanical dimensions
13 Revision history
14 Legal information

Multi-purpose high-side switches Rev. 5 — 21 July 2021 Product data sheet

1 General description

The 32XSG family is designed to control, protect and diagnose various type of low- voltage loads with enhanced precision. It combines flexibility, extended digital and analog feedbacks, safety, and robustness. This family offers the possibility to configure outputs to improve EMC, manage frequency and duty cycle, adapt the dynamic overcurrent profiles to the load, program the current sense ratio of each output, and many more. Devices can be driven either by the embedded SPI module or by direct inputs in Fail-safe operation mode and remains operational, controllable and protected in this case. This product is driven by SMARTMOS technology.

2 Features and benefits

Penta high-side switches with high transient capability
16-bit 5.0 MHz SPI control of overcurrent profiles, channel control including PWM duty cycles, output On and Off openload detections, thermal shutdown and prewarning, and fault reporting
Output current monitoring with programmable synchronization signal and supply voltage feedback
Fail-safe mode
External smart power switch control
Operating voltage is 7.0 V to 30 V with sleep current < 5.0 μA, extended mode from

6.0 V to 32 V

-16 V reverse polarity and ground disconnect protections
Compatible PCB foot print and SPI software driver among the family

3 Simplified application diagram

Figure 1. Simplified application diagram

4 Applications

Low-voltage exterior lighting
Low-voltage industrial lighting
Low-voltage automation systems
Halogen lamps
Incandescent bulbs
Light-emitting diodes (LEDs)
HID Xenon ballasts
DC Motors Product data sheet Rev. 5 — 21 July 2021

5 Ordering information

Table 1. Orderable parts [1] To order parts in tape and reel, add the R2 suffix to the part number. numbers for this device, go to nxp.com and perform a part number search.

6 Internal block diagram

Figure 2. 32XSG simplified internal block diagram

7 Pinning information

7.1 Pinning

Figure 3. Pin configuration for 32-pin SOIC-EP package

Figure 4. Pin configuration for 54-pin SOIC-EP package

7.2 Pin description

32 SOIC-EP

54 SOIC-EP [1]

has a passive internal pull-down. has a passive internal pull-down. Table 2. Pin description

Smart Power Switch by logic level. Table 2. Pin description...continued

external pull-up resistor to VCC. corresponding channel in Fail mode. corresponding channel in Fail mode. corresponding channel in Fail mode. corresponding channel in Fail mode. pin has a passive internal pull-down. [1] Pins 17 and 38 are omitted.

8 General product characteristics

8.1 Relationship between ratings and operating requirements

pump, gate drive,…) is derived from the VPWR pin.

The internal supply rail is protected (max. –16 V)
The output drivers (OUT1… OUT5) are switched on, to reduce the power consumption in the drivers when using incandescent bulbs.

Figure 5. Ratings vs. operating requirements (VPWR pin) disconnected, the logic part is supplied by the VPWR pin. in case of a high-voltage disturbance.

Figure 6. Ratings vs. operating requirements (VCC pin)

8.2 Maximum ratings

permanent damage to the device. Table 3. Maximum ratings [1] Exceeding voltage limits on those pins may cause a malfunction or permanent damage to the device. [2] Maximum current in negative clamping for IN1:IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins. package thermal resistance is required.

8.3 Thermal characteristics

permanent damage to the device. Table 4. Thermal ratings [1] To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125 °C. or permanent damage to the device. temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [6] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. [7] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

8.4 Operating conditions

following data, unless otherwise noted. permanent damage to the device. functional. All features are operating. functional. All features are operating. Table 5. Operating conditions

8.5 Supply currents

This section describes the current consumption characteristics of the device.

Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 6. Supply currents [1] With the OUT1… OUT5 power channels grounded. [2] With the OUT1… OUT5 power channels opened.

9 General IC functional description and application information

9.1 Introduction

capability and a PWM frequency prescaler per power channel.

9.2 Features

Penta high-side switches with overload, overtemperature, and undervoltage protection
Control output for one external smart power switch
16-bit SPI communication interface with daisy chain capability
Dedicated control inputs for use in fail mode
Analog feedback pin with SPI programmable multiplexer and sync signal
Channel diagnosis by SPI communication
Advanced current sense mode for low current use
Synchronous PWM module with external clock, prescaler, and multiphase feature
Excellent EMC behavior
Power net and reverse polarity protection
Ultra low-power mode
Scalable and flexible family concept
Board layout compatible SOIC54 and SOIC32 package with exposed pad Product data sheet Rev. 5 — 21 July 2021

9.3 Block diagram

Figure 7. Functional block diagram

9.3.1 Self-protected high-side switches

9.3.2 Power supply

The device operates with supply voltages from 5.5 V to 40 V (VPWR), but is full spec.

9.3.3 MCU interface and device control

different frequencies to 400 Hz.

9.4 Functional description

In Normal mode by SPI interface. A second supply voltage (VCC) is required for bidirectional SPI communication. Product data sheet Rev. 5 — 21 July 2021

In Fail mode by the corresponding direct inputs IN1… IN4. The OUT5 and OUT6 are off in this mode.

9.5 Modes of operation

wake = (IN1_ON) or (IN2_ON) or (IN3_ON) or (IN4_ON) or (RSTB). For more details, see Section 10.3.3.2 "Logic I/O plausibility check".
fail = (SPI_fail) or (LIMP). For more details, see Section 10.3.3.1 "Loss of communication interface".

Figure 8. General IC operating modes

9.5.1 Power Off mode

by the clamping circuits in power off. See Section 10.2.3 "Supply voltage disconnection".

9.5.2 Sleep mode

the component is inactive and all outputs are disabled
the outputs are protected by the clamping circuits
the pull-up/pull-down resistors are present Sleep mode is the default mode of the device after applying the supply voltages (VPWR or VCC) prior to any wake-up condition (wake = [0]). Wake-up from sleep mode is provided by the wake signal. Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches

9.5.3 Normal mode

The Normal mode is the regular operating mode of the device. The device is in Normal mode, when the device is in the wake state (wake = [1]) and no fail condition (fail = [0]) is detected. During Normal mode:

the power outputs are under control of the SPI and its programmable PWM mode
the power outputs are protected by the overload protection circuits
the digital diagnostic feature transfers status of the smart switch via the SPI
the analog feedback output (CSNS and CSNS SYNCB) can be controlled by the SPI

9.5.4 Fail mode

The device enters the Fail mode, when:

the LIMP input pin is high (logic [1])
or a SPI failure is detected During Fail mode (wake = [1] & fail = [1]):
the OUT1… OUT4 outputs are directly controlled by the corresponding control inputs (IN1… IN4)
the OUT5… OUT6 are turned off and not controllable
the PWM module is not available
while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition): – SO reports the content of SO register defined by SOA0 to 3 bits
the outputs are fully protected in case of an overload, overtemperature, and undervoltage
no analog feedback is available
the max. output overcurrent profile is activated (OCLO and window times)
in case of an overload condition or undervoltage, the autorestart feature controls the OUT1… OUT4 outputs
in case of an overtemperature condition, OCHI1 detection, or severe short-circuit detection, the corresponding output is latched OFF until a new wake-up event

9.5.5 Mode transitions

After a wake-up:

a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])
the faults are blanked during tBLANKING The device enters in Normal mode after start-up if following sequence is provided:
VPWR and VCC power supplies must be above their undervoltage thresholds (sleep mode)
generate wake-up event (wake = 1) setting RSTB from 0 to 1 The device initialization is completed after 50 μsec (typ). During this time, the device is robust in case of VPWR interrupts higher than 150 nsec. The transition from “Normal mode” to “Fail mode” is executed immediately when a fail condition is detected. During the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared. When the Fail mode condition is a: Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches

LIMP input, WD toggle timeout, WD toggle sequence, or a SPI modulo 16 error, the SPI diagnosis is available during Fail mode
SI/SO stuck to static level, the SPI diagnosis is not available during Fail mode The transition from “Fail mode” to “Normal mode” is enabled when:
the fail condition is removed and
two SPI commands are sent within a valid watchdog cycle (first WD=[0] and then WD=[1]) During this transition:
all SPI SI and SO registers are cleared (logic[0])
the DSF (device status flag) in the registers #1… #7 and the RCF (Register Clearer flag) in the device status register #1 are set (logic[1]) To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.

9.6 SPI interface and configurations

9.6.1 Introduction

The SPI is used to:

control the device in case of Normal mode
provide diagnostics in case of Normal and Fail mode The SPI is a 16-bit full-duplex synchronous data transfer interface with daisy chain capability. The interface consists of four I/O lines with 5.0 V CMOS logic levels and termination resistors:
The SCLK pin clocks the internal shift registers of the device
The SI pin accepts data into the input shift register on the rising edge of the SCLK signal
The SO pin changes its state on the rising edge of SCLK and reads out on the falling edge
The CSB enables the SPI interface: – with the leading edge of CSB, the registers load – while CSB is logic [0], SI/SO data shifts – with the trailing edge of the CSB signal, SPI data latches into the internal registers – when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance When the RSTB input is:
low (logic [0]), the SPI and the fault registers are reset. The wake state then depends on the status of the input pins (IN_ON1… IN_ON4)
high (logic[1]), the device is in wake status and the SPI is enabled The functionality of the SPI is checked by a plausibility check. During a SPI failure, the device enters Fail mode.

9.6.2 SPI input register and bit descriptions

The first nibble of the 16-bit data word (D15… D12) serves as address bits. Product data sheet Rev. 5 — 21 July 2021

Table 7. SPI input register and bit descriptions 11 bits (D10… D0) are used as data bits. The D11 bit is the WD toggle bit. This bit has to be toggled with each write command. When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected.

Figure 9. SPI input register

NXP Semiconductors MC32XSG Multi-purpose high-side switches

9.6.3 SPI output register and bit descriptions

The first nibble of the 16-bit data word (D12… D15) serves as address bits. All register values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off/ inactive unless otherwise noted. Product data sheet Rev. 5 — 21 July 2021

Figure 10. SPI output register

9.6.4 Timing diagrams

Figure 11. Timing requirements during SPI communication

Figure 12. Timing diagram for serial output (SO) data communication

9.6.5 Electrical characterization

Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 8. Electrical characteristics

Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 8. Electrical characteristics...continued [1] Parameter is derived from simulations.

10 Functional block requirements and behaviors

10.1 Self-protected high-side switches description and application

10.1.1 Features

Up to five power outputs are foreseen to drive light as well as DC motor applications.

output pulse shaping
output protections
active clamps
output diagnostics Product data sheet Rev. 5 — 21 July 2021

10.1.2 Output pulse shaping

low switching losses
low EMC emission performance
minimum propagation delay time Depending on the programming of the prescaler setting register #12-1, #12-2, the switching speeds of the outputs are adjusted to the output frequency range of each channel. The edge shaping must be designed according to the following table. Min. on/ off duty cycle time (μs) 4 25 100 10 40 03 FB 4 252 156 2 50 200 5 20 07 F7 8 248 156 1 100 400 2.5 10 07 F7 8 248 78 The edge shaping provides full symmetry for rising and falling transition.

Figure 13. Typical power output switching (slow and fast slew rate)

10.1.2.1 SPI control and configuration

very high frequency), the output duty cycle is 100 %. Each output (OUT1:OUT6) can be controlled by an individual channel control register.

PH0x… PH1x: phase assignment of the output channel x
ONx: on/off control including overcurrent window control of the output channel x
PWM0x… PWM7x: 8-bit PWM value individually for each output channel x The ONx bits are duplicated in the output control register #8 to control the outputs with either the CHx control register or the output control register. The PRS1x… PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2. The synchronization of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2 register #1. On a SPI write into initialization 2 register (#1):
initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module are reset with the positive edge of the CSB, the phase synchronization is performed immediately within one SPI frame. It could help to synchronize different 32XSG devices in the board
when the bit D1 is logic[0], no action is executed The switching frequency can be adjusted for the corresponding channel as described in the following table: CLK freq. (kHz) prescaler setting PWN freq. (Hz) PWM resolution min. max. PRS1x PRS0x divider factor min. max. slew rate (Bit) (steps) 0 0 4 25 100 slow 0 1 2 50 200 slow 25.6 102.4

1 X 1 100 400 fast

fail mode
clock input signal failure

10.1.2.2 Global PWM control

low (logic[0]), the output is assigned to individual PWM (default status)
high (logic[1]), the output is assigned to global PWM The PWM value of the global PWM channel is controlled by the global PWM control register #9-2. When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the corresponding output channel setting. SI address SI dataRegister # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 9-1 1 0 0 1 WD 0 X X X X GPWM EN6 GPWM EN5 GPWM EN4 GPWM EN3 GPWM EN2 GPWM EN1 Global PWM control 9-2 1 0 0 1 WD 1 X X GPWM 7 GPWM6 GPWM5 GPWM4 GPWM3 GPWM2 GPWM1 GPWM0

Table 9. Global PWM Register

NXP Semiconductors MC32XSG Multi-purpose high-side switches

10.1.2.3 Incremental PWM control

To reduce the control overhead during soft start/stop of bulbs or DC motors (theatre dimming), an incremental PWM control feature is implemented. With the incremental PWM control feature the PWM values of all internal channels OUT1:OUT5 can be incremented or decremented with one SPI frame. The incremental PWM feature is not available for:

the global PWM channel
the external channel OUT6 The control is according the increment/decrement register #14:
INCR SGN: sign of incremental dimming (valid for all channels)
INCR 1x, INCR 0x increment/decrement INCR SGN Increment/decrement 0 decrement 1 increment INCR 1x INCR 0x Increment/decrement 0 0 no increment/decrement 0 1 4 1 0 8 1 1 16 This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.

10.1.2.4 Input control

Up to four dedicated control inputs (IN1:IN4) are foreseen to:

wake-up the device
fully control the corresponding output in case of Fail mode
control the corresponding output in case of Normal mode The control during Normal mode is according the INEN0x and INEN1x bits in the input enable register #11 and according to the logic in Table 9. An input deglitcher is provided at each control input to avoid high frequency control of the outputs. The internal signal is called iINx. As the input thresholds are logic level compatible, the input structure of the pin is able to withstand supply voltage levels (max. 40 V) without damage. External current limit resistors (1.0 kΩ, 10 kΩ) can be used to handle reverse current conditions. The inputs have an integrated pull-down resistor. Product data sheet Rev. 5 — 21 July 2021

10.1.2.5 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 10. Electrical characteristics

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 10. Electrical characteristics...continued [1] With nominal resistive load: 2.5 Ω and 5.0 Ω respectively for 7.0 mΩ and 17 mΩ channel.

10.1.3 Output protections

overload conditions
harness short-circuit
overcurrent and severe short-circuit
overtemperature including overtemperature warning
under and overvoltage
charge pump failure
reverse polarity In case a fault condition is detected, the corresponding output is commanded off immediately after the deglitch time tFAULT SD. The turn off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature (fast turn off). The FTO:
does not use edge shaping
is provided with high slew rate to minimize the output turn-off time tOUTPUT SD, in regards to the detected fault
uses a latch which keeps the FTO active during an undervoltage condition (0 ≤ VPWR ≤ VPWR UVF) Product data sheet Rev. 5 — 21 July 2021

Figure 14. Power output switching in nominal operation and in case of fault

the status is reported in the quick status register #1 and the corresponding channel status register #2:#6. To restart the output:
the channel must be restarted by writing the corresponding ON bit in the channel control register #2:#6 or output control register #8 Product data sheet Rev. 5 — 21 July 2021

Figure 15. Output control diagram in Normal mode controlled by the autorestart feature.

10.1.3.1 Overcurrent protections

Figure 18. Transient overcurrent profile accumulated at each On state period of the output. reported in the corresponding channel status register #2…#6, as shown in Table 11. Table 11. Channel status register #2…#6 The enabling of the high current window (OCHI1:OCHI3) is dependent on CHx signal.

NXP Semiconductors MC32XSG Multi-purpose high-side switches the ON bits inside channel control registers #2:#7 or the output control register #8. When the corresponding CHx signal is:

toggled (turn OFF and then ON), the OCHI window counter resets and the full OCHI windows is applied
rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI counter Fail mode The enabling of the high current window (OCHI1:OCHI3) is dependent on INx_ON toggle signal. The enabling of output (OUT1:5) is dependent on CHx signal.

10.1.3.2 Overcurrent control programming

OCHI On Demand (OCHI OD) In some instances, a lamp might be de-powered when its supply is interrupted by the opening of a switch (as in a door), or by disconnecting the load (as for a supply dock). In these cases, the driver should be tolerant of the inrush current occurring when the load is reconnected and the channel is already ON. The OCHI On Demand feature allows such control individually for each channel through the OCHI ODx bits inside the Initialization #2 register. When the OCHI ODx bit is:

low (logic[0]), the channel operates in its Normal, Default mode. After end of OCHI window timeout the output is protected with an OCLO threshold
high (logic[1]), the channel operates in the OCHI On Demand mode and uses the OCHI2 and OCHI3 windows and times after an OCLO event (when horizontal current threshold OCLO is crossed, a new window with OCHI2&3 is started) To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register and then turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output. The fault detection status is reported in the quick status register #1 and the corresponding channel status registers #2:#6. OCLO Threshold Setting The static overcurrent threshold can be programmed individually for each output in two levels to adapt low duty cycle dimming and a variety of loads. The CSNS recopy factor and OCLO threshold depend on OCLO and ACM settings. The OCLO setting is controlled by the OCLOx bits inside the overcurrent control register #10-1. When the OCLOx bit is:
low (logic[0]), the output is protected with the higher OCLO threshold (default status and during Fail mode)
high (logic[1]), the lower OCLO threshold is applied Short OCHI The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis and to reduce the potential stress inside the switch during an overload condition. The setting is controlled individually for each output by the SHORT OCHIx bits inside the overload control register #10-2. When the SHORT OCHIx bit is:
low (logic[0]), the default OCHI window times are applied (default status and during Fail mode) Product data sheet Rev. 5 — 21 July 2021

high (logic[1]), the short OCHI window times are applied (50 % of the regular OCHI window time) NO OCHI Depending on the type of load in the output, the OCHI windows can be suppressed with the NO OCHI feature. In that case, the output is protected with OCLO protection right after the turn On and CSNS reporting is directly available. The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis. The setting is controlled individually for each channel by the NO OCHIx bits inside the overcurrent control register #10-2. When the NO OCHIx bit is:
low (logic[0]), the regular OCHI window is applied (default status and during Fail mode)
high (logic[1]), the turn on of the output is provided without OCHI windows Thermal OCHI To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHI1 level can be automatically adjusted in regards to the control die temperature. The functionality is controlled for all channels by the OCHI THERMAL bit inside the initialization 2. When the OCHI THERMAL bit is:
low (logic[0]), the output is protected with default OCHI1 level
high (logic[1]), the output is protected with the OCHI1 level reduced by RTHERMAL OCHI = 20 % (typ) when the control die temperature is above TTHERMAL OCHI = 63 °C (typ.)

10.1.3.3 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 12. Electrical characteristics

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 12. Electrical characteristics...continued [1] Guaranteed by test mode.

10.1.3.4 Overtemperature protection

selectable overtemperature warning threshold (TOTW1, TOTW2), the output stays on and the event is reported in the SPI
overtemperature threshold (TOTS), the output is switched off immediately after the deglitch time tFAULT SD and the event is reported in the SPI after the deglitch time tFAULT SD

10.1.3.4.1 Overtemperature warning (OTW)

the output remains in current state
the status is reported in the quick status register #1 and the corresponding channel status register #2:#6 Product data sheet Rev. 5 — 21 July 2021

low (logic[0]), the high overtemperature threshold is enabled (default status)
high (logic[1]), the low overtemperature threshold is enabled To delatch the OTW bit (OTWx):
the temperature has to drop below the corresponding overtemperature warning threshold
a read command of the corresponding channel status register #2:#6 must be performed

10.1.3.4.2 Overtemperature shutdown (OTS)

the corresponding output is disabled immediately after the deglitch time tFAULT SD
the status is reported after tFAULT SD in the quick status register #1 and the corresponding channel status register #2:#6 To restart the output after an overtemperature shutdown event in Normal mode:
the overtemperature condition must be removed, and the channel must be restarted by a write command of the ON bit in the corresponding channel control register #2:#6, or in the output control register #8 To delatch the diagnosis:
the overtemperature condition must be removed
a read command of the corresponding channel status register #2:#6 must be performed To restart the output after an overtemperature shutdown event in Fail mode:
a mode transition is needed. Refer to Section 9.5.5 "Mode transitions"

10.1.3.4.3 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 13. Electrical characteristics [1] Guaranteed by test mode.

10.1.3.5 Undervoltage and overvoltage protections

10.1.3.5.1 Undervoltage

in the device status flag (DSF) in the registers #1:#7
in the undervoltage flag (UVF) inside the device status register #7 Normal mode The reactivation of the outputs is controlled by the microcontroller. To restart, the output the undervoltage condition must be removed and:
a write command of the ON Bit must be performed in the corresponding channel control register #2:#6 or in the output control register #8 To delatch the diagnosis:
the undervoltage condition must be removed
a read command of the device status register #7 must be performed Fail mode When the device is in Fail mode, the restart of the outputs is controlled by the autorestart feature.

10.1.3.5.2 Overvoltage

device status flag (DSF) in the registers #1:#7
overvoltage flag (OVF) inside the device status register #7 To delatch the diagnosis:
the overvoltage condition must be removed
a read command of the device status register #7 must be performed During an overvoltage (VPWR ≥ VPWR OVF), the output stays in the ON state.

10.1.3.5.3 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 14. Electrical characteristics

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 14. Electrical characteristics...continued

10.1.3.6 Charge pump protection

power up
failure of external capacitor
failure of charge pump circuitry When a charge pump failure occurs, output control is no longer possible, and the status reports after tFAULT SD in the register Quick status #1 bit D7 (CPF flag) and on all output registers #1…#7 (DSF flag). To delatch the diagnosis:
the charge pump failure condition must be removed
a read command of the quick status register #1 is necessary

10.1.3.6.1 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND =0 V, unless otherwise noted. Table 15. Electrical characteristics

10.1.3.6.2 Reverse supply protection

the output transistors OUT1:5 are turned ON in order to prevent the device from thermal overload
the OUT6 pin is pulled down to GND. An external current limit resistor must be added in series with OUT6 pin
no output protection is available in this condition

10.1.4 Digital diagnostics

NXP Semiconductors MC32XSG Multi-purpose high-side switches

10.1.4.1 Openload detections

The device provides smart diagnostics for openload conditions: These diagnostics are provided for each power output (OUT1…5), based on the current monitoring circuit. Openload detection is reported:

for the corresponding OUTx on the QSFx bit in the quick status register #1.
In the global openload flag OLF (register #1…#7)
In the OLON or OLOFF bit in the corresponding channel status register (#2…#6)
For LED loads type with the OLLED feature (OLLED control register #13-2) Openload detection is provided for the following output configuration:

10.1.4.1.1 Output is in the ON state

OLON flag is reported on the bit D1 of the corresponding channel status register if the output current is below the following threshold:

IOL threshold if the corresponding OLLED EN bit is low (register #13-2)
IOLLED threshold if the corresponding OLLED EN bit is high When openload detection in LED mode is enabled (OLLED ENx=1), the output current is checked differently, depending on the output operation:
When the output is fully On (100 % PWM), the comparison with IOLLED threshold is done by user's demand by setting OLLED TRIG=1 on bit D5 of register OLLED control (#13-2) When the output is in PWM operation, the comparison with IOLLED threshold is done at each Turn Off phase of each PWM cycle.
In PWM operation, the OLON diagnosis available within δPWM OLON duty cycle range.

10.1.4.1.2 Output is in the OFF state

OLOFF flag is reported on the bit D0 of the corresponding channel status register if the output current is below IOLOFF threshold. Openload OFF diagnostic is reported on at the user's demand by setting the bit OLOFF ENx of the corresponding output to high (logic[1]). Once the OLOFF ENx is set high, the corresponding output turns ON during tOLOFF and the output current is compared to IOLOFF:

If the output current goes above IOLOFF within the tOLOFF period, the output is turned back to the Off state and a logic [0] is reported on the OLOFFx bit of CHx status register #2…#6
If the output current is below IOLOFF within the tOLOFF period, a logic [1] is reported on the OLOFFx bit of CHx status register #2…#6. The output is turned OFF at the end of the tOLOFF period. To delatch the diagnosis, the openload condition must be removed and a read command of the corresponding channel status register #2…#6 must be read. Product data sheet Rev. 5 — 21 July 2021

10.1.4.1.3 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND =0 V, unless otherwise noted. Table 16. Electrical characteristics

10.1.4.2 Output shorted to VPWR in OFF state

10.1.4.2.1 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND =0 V, unless otherwise noted. Table 17. Electrical characteristics

10.1.4.3 SPI fault reporting

user wants to read. The 'quick status register' #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no action by the microcontroller is needed.

NXP Semiconductors MC32XSG Multi-purpose high-side switches SO address SO dataRegister # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 quick address 1 0 0 0 1 FM DSF OVLF OLF CPF RCF CLKF QSF5 QSF4 QSF3 QSF2 QSF1

FM: Fail mode indication. This bit is also present in all other SO data words, and indicates the fail mode by a logic[1]. When the device is in Normal mode, the bit is logic[0]
global device status flags (D10:D8): These flags are also present in the channel status registers #2:#6, the device status register #7, and are cleared when all fault bits are cleared by reading the registers #2:#7
DSF: device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the device status register #7
OVLF: over load flag (wired OR of all OC and OTS signals)
OLF: openload flag
CPF: charge pump flag
RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset
CLKF: clock fail flag. Refer to Section 10.3.3.2 "Logic I/O plausibility check"
QSF1:QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx, or OTSx, or OLONx, or OLOFFx) The SOA address #0 is also mapped to register #1 (D15…D12 bits report logic [0001]). When a fault condition is indicated by one of the quick status bits (QSF1…QSF5, OVLF, OLF), the detailed status can be evaluated by reading of the corresponding channel status registers #2…#6. SO address SO dataRegister # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH1 status 2 0 0 1 0 FM DSF OVLF OLF res OTS1 OTW1 OC21 OC11 OC01 OLON1 OLOFF1 CH2 status 3 0 0 1 1 FM DSF OVLF OLF res OTS2 OTW2 OC22 OC12 OC02 OLON2 OLOFF2 CH3 status 4 0 1 0 0 FM DSF OVLF OLF res OTS3 OTW3 OC23 OC13 OC03 OLON3 OLOFF3 CH4 status 5 0 1 0 1 FM DSF OVLF OLF res OTS4 OTW4 OC24 OC14 OC04 OLON4 OLOFF4 CH5 status 6 0 1 1 0 FM DSF OVLF OLF res OTS5 OTW5 OC25 OC15 OC05 OLON5 OLOFF5
OTSx: overtemperature shutdown flag
OTWx: overtemperature warning flag
OC0x…OC2x: overcurrent status flags
OLONx: openload in ON state flag
OLOFFx: openload in OFF state flag The most recent OC fault is reported by the OC0x…OC2x bits, if a new OC occurs before an old OC on the same output read. When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of the device status registers #7: SO address SO dataRegister # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 device status 7 0 1 1 1 FM DSF OVLF OLF res res res TMF OVF UVF SPIF iLMP
TMF: test mode activation flag. Test mode is used for manufacturing testing only. If this bit is set to logic [1], the MCU must reset the device Product data sheet Rev. 5 — 21 July 2021

OVF: overvoltage flag
UVF: undervoltage flag
SPIF: SPI fail flag
iLIMP: real time reporting after the tIN_DGL, not latched The I/O status register #8 can be used for system test, fail mode test and the power down procedure: SO address SO dataRegister # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I/O status 8 1 0 0 0 FM res TOGGLE iIN4 iIN3 iIN2 iIN1 OUT5 OUT4 OUT3 OUT2 OUT1 The register provides the status of the control inputs, the toggle signal, and the power outputs state in real time (not latched).
TOGGLE: status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or IN4_ON), reported in real time
iINx: status of iINx signal (real time reporting after the tIN_DGL, not latched)
OUTx: status of output pins OUTx (the detection threshold is VPWR/2) when undervoltage condition does not occur

10.1.5 Analog diagnostics

inside the initialization 1 register #0.

10.1.5.1 Output current monitoring

reporting channel 1…5 current feedback (IFSR). Figure 19. Output current sensing

10.1.5.2 Supply voltage monitoring

proportional to the VPWR voltage as shown in Figure 21. Figure 21. Supply voltage reporting

10.1.5.3 Temperature monitoring

feedback range, TFB, –40 °C to 150 °C. Figure 22. Temperature reporting

10.1.5.4 Analog diagnostic synchronization

available during Normal mode only Product data sheet Rev. 5 — 21 July 2021

behavior depends on the type of signal selected by the MUX2…MUX0 bits in the initialization 1 register #0. This signal is either a current proportional to an output current or a voltage proportional to temperature or the supply voltage Current sense signal When a current sense signal is selected:
the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0, SYNC EN1 bits inside the initialization 1 register #0 SYNC EN1 SYNC EN0 Setting Behavior 0 0 OFF CSNS SYNCB is inactive (high) 0 1 VALID CSNS SYNCB is active (low) when CSNS is valid. During switching the output of MUX, the CSNS SYNCB is inactive (high) 1 0 TRIG0 As in setting VALID, but after a change of the MUX, the CSNS SYNCB is inactive (high) until the next PWM cycle is started 1 1 TRIG1/2 Pulses (active low) from the middle of the CSNS pulse to its end are generated. Switching phases (output and MUX) and the time from the MUX switching to the next middle of the CSNS pulse are blanked (high)

Table 18. Current sense signal details

the CSNS SYNCB pulse is suppressed during OCHI and during OFF phase of the PWM
the CSNS SYNCB is blanked during settling time of the CSNS multiplexer and ACM switching by a fixed time of tDLY(ON) + tCSNS(SET)
when a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty cycle at a fixed period of 6.5 ms
when the output is programmed with 100 % PWM, the CSNS SYNCB delivers a logic[0] a high pulse with the length of 100 µs (typ.) during the PWM counter overflow for TRIG0 and TRIG1/2 settings
In case of an output fault, the CSNS SYNCB signal for current sensing does not deliver a trigger signal until the output is enabled again Temperature signal or VPWR monitor signal When a voltage signal (average control die temperature or supply voltage) is selected:
the CSNS SYNCB delivers a signal with 50 % duty cycle and the period of the lowest prescaler setting (fCLK/1024)
and a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty cycle at a fixed period of 6.5 ms (tSYNC DEFAULT)

10.1.5.5 Electrical characterization

approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Table 19. Electrical characteristics

approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

7.0 V < VPWR < 30 V

9.0 V ≤ VPWR ≤ 30 V

Table 19. Electrical characteristics...continued [1] Precision either OCLO and ACM setting. [2] Error of ±100 % without calibration for all modes and ±50 % with 1 calibration point done at 25 °C.

[3] Parameter is derived mainly from simulations.

10.2 Power supply functional block description and application

10.2.1 Introduction

supplies the output register of the Serial Peripheral Interface (SPI) and the OUT6 driver. IC architecture guarantees a low quiescent current in Sleep mode (wake = [0]).

10.2.2 Wake state reporting

microcontroller as long as RSTB is logic [0].

"wake state" and RSTB is inactive, the CLK pin reports a high signal (logic[1])
"sleep mode" or the device is wake by the RSTB pin, the CLK is an input pin

10.2.2.1 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 20. Electrical characteristics

10.2.3 Supply voltage disconnection

10.2.3.1 Loss of VPWR

VCC ≤ VCC POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
VCC > VCC POR: all registers and faults are maintained. OUT1:5 are shut off immediately. The ON/OFF state of OUT6 depends on the current SPI configuration. SPI reporting is available when VCC remains within its operating voltage range (4.5 V to 5.5 V) The wake-up event is not reported to the CLK pin. The clamping structures (supply clamp, negative output clamp) are available to protect the device. No current is conducted from VCC to VPWR. An external current path must be available to drain the energy from an inductive load, if a supply disconnection occurs when an output is ON. Product data sheet Rev. 5 — 21 July 2021

10.2.3.2 Loss of VCC

VPWR ≤ VPWR POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
VPWR > VPWR POR: the SPI is not available. Therefore, the device enters WD timeout The clamping structures (supply clamp, negative output clamp) are available to protect the device. No current is conducted from VPWR to VCC.

10.2.3.3 Loss of device GND

order to limit the current to ICL.

10.2.3.4 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 21. Electrical characteristics

10.3 Communication interface and device control functional block

10.3.1 Introduction

10.3.2 Fail mode input (LIMP)

input can be monitored by the LIMP IN bit inside the device status register #7.

10.3.2.1 Electrical characterization

Characteristics noted under conditions 4.5 V ≤ VPWR ≤ 5.5 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 22. Electrical characteristics [1] Parameter is derived mainly from simulations.

10.3.3 MCU communication interface protections

10.3.3.1 Loss of communication interface

the WD bit is not toggled with each SPI message or
WD timeout is reached or
protocol length error (modulo 16 check) The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by a WD toggle error. The SPI communication error is reported in:
SPI failure flag (SPIF) inside the device status register #7 in the next SPI communication As long as the device is in Fail mode, the SPIF bit retains its state. The SPIF bit is delatched during the transition from fail-to-normal modes. Product data sheet Rev. 5 — 21 July 2021

10.3.3.2 Logic I/O plausibility check

Fail mode (internal signal called iLIMP). Figure 23. LIMP and iLIMP signal channel is controlled by the direct signal (internal signal called iINx). deglitcher (at the CLK input) a very high input frequency leads to a clock fail detection.

the clock failure condition must be removed
a read command of the quick status register #1 must be performed

10.3.3.3 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 23. Electrical characteristics

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 23. Electrical characteristics...continued

10.3.4 External smart power control (OUT6)

The protection and current feedback of the external SMARTMOS device are under the responsibility of the microcontroller
The output delivers a 5.0 V CMOS logic signal from VCC The output is protected against overvoltage. An external current limit resistor (1.0 kΩ, 10 kΩ) must be used to handle negative output voltage conditions. The output has an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and Fail mode. In case of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of external smart power device and to limit possible reverse OUT6 current (resistor in series).

10.3.4.1 Electrical characterization

Characteristics noted under conditions 7.0 V ≤ VPWR ≤ 30 V, –40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Table 24. Electrical characteristics

11 Typical applications

11.1 Introduction

The 32XSG is the latest achievement in DC motors and lighting drivers.

11.1.1 Application diagram

Figure 24. Automation system application

11.1.2 Bill of materials

Table 25. 32XSG Bill of materials offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

12 Packaging

12.1 Package mechanical dimensions

Table 26. Package outline

NXP Semiconductors MC32XSG Multi-purpose high-side switches Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches Revision Date Description of changes 1.0 8/2016 • Initial release 2.0 7/2018 • Added MC17XSG500BEK part and associated 98ASA00894D package information 3.0 11/2018 • Updated as per CIN 201811005I

Added footnote [1] to Table 8
Added footnote [1] to Table 24 4.0 9/2020 • Changed document status from Advance Information to Technical Data
Added values for RPULL-CSB to Table 8
Updated the max value for ROUT6 DOWN in Table 24 (replaced 20 by 30) 5.0 7/2021 • Updated as per 202106018I – Table 1: added MC07XSG517DEK and MC17XSG500DEK parts – Section 10.1.3.2: replaced "RTHERMAL OCHI = 15 % (typ)" by "RTHERMAL OCHI = 20 % (typ)" – Table 12: updated values for High overcurrent ratio 2 (RTHERMALOCHI) – Section 12.1: updated package drawings due to migration of devices from OHT Fab to ICN8, and the change from etch to stamp lead frame Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches

14 Legal information

14.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Product data sheet Rev. 5 — 21 July 2021

NXP Semiconductors MC32XSG Multi-purpose high-side switches Tables Figures Fig. 3. Pin configuration for 32-pin SOIC-EP Fig. 4. Pin configuration for 54-pin SOIC-EP Fig. 5. Ratings vs. operating requirements (VPWR Fig. 6. Ratings vs. operating requirements (VCC Fig. 11. Timing requirements during SPI Fig. 12. Timing diagram for serial output (SO) data Fig. 13. Typical power output switching (slow and Fig. 14. Power output switching in nominal Product data sheet Rev. 5 — 21 July 2021

Product Information

MC07XSG517DEK specifications and overview.

Summary

Multi-purpose high-side switches Rev. 5-21 July 2021

Description

Multi-purpose high-side switches Rev. 5-21 July 2021

Source title MC07XSG517DEK Datasheet(PDF) - NXP Semiconductors

Related Parts

More parts from the same family.

Browse manufacturer