MC07XS6517EK

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Document overview

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• PDF pages: 73

Technical content

Features

• Triple 7.0 mΩ and dual 17 mΩ high-side switches with high transient current capability
• 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control including PWM duty-cycles, output-ON and -OFF OpenLoad detections, thermal shut-down and prewarning, and fault reporting
• Output current monitoring with programmable synchronization signal and battery voltage feedback
• Limp Home mode
• External smart power switch control
• Operating voltage is 7.0 to 18 V with sleep current < 5.0 µA, extended mode from 6.0 to 28 V
• - 1 6 V reverse polarity and ground disconnect protections
• Compatible PCB foot print and SPI software driver among the family

Figure 1. Triple 7.0 mOhm and Dual 17 mOhm Simplified Application Diagram

Applications

• Low voltage exterior lighting
• Low voltage industrial lighting
• Low voltage automation systems
• Halogen lamps
• Incandescent bulbs
• Light-emitting diodes (LEDs)
• HID Xenon ballasts
• DC motors EK SUFFIX (PB-FREE) 98ASA00367D 54-PIN SOICEP IN4 VCC SI CSB SO RSTB CLK CSNS LIMP IN1 IN2 IN3 VBAT CP OUT1 OUT2 OUT3 OUT4 OUT5 OUT6GND OUTVBAT GNDCSNS Smart Power 07XS6517 VCC SO CSB SCLK SI RSTB CLK A/D1 TRG1 A/D2 PORT PORT PORT PORT PORT GND SCLK SYNCB Main MCU VCCVBAT GND 5.0 V Regulator VBAT VBAT IN

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1 Orderable Parts

number search for the following device numbers. Table 1. Ordering Information

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

Table 2. Part Variations

• T J = 25 °C, VBAT > 12 V
• T J = 150 °C, VBAT > 12 V
• T J = 25 °C, VBAT = 7.0 V
• T J = 25 °C, VBAT = -12 V
• T J = 150 °C, VBAT = -12 V 7.0 11.9 10.5 10.5 15.7 6.0 6.0 12.9 18.7 mΩ RDS(on) ON-Resistance, Drain-to-Source for 7mΩ Power Channel
• T J = 25 °C, VBAT > 12 V
• T J = 150 °C, VBAT > 12 V
• T J = 25 °C, VBAT = 7.0 V
• T J = 25 °C, VBAT = -12 V
• T J = 150 °C, VBAT = -12 V 28.9 25.5 25.5 30.9 43.5 mΩ tDLY Turn-on and Turn-off Delay Times at VBAT = 14 V
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range 100 100 120 120 µs

• I OUT = 80% FSR with ACM = 0
• I OUT = 25% FSR with ACM = 0
• I OUT = 10% FSR with ACM = 0
• I OUT = 5.0% FSR with ACM = 0
• I OUT = 80% FSR with High OCLO and ACM = 1
• I OUT = 25% FSR with High OCLO and ACM = 1
• I OUT = 10% FSR with High OCLO and ACM = 1
• I OUT = 5.0% FSR with High OCLO and ACM = 1
• I OUT = 80% FSR with Low OCLO and ACM = 1
• I OUT = 25% FSR with Low OCLO and ACM = 1
• I OUT = 10% FSR with Low OCLO and ACM = 1
• I OUT = 5.0% FSR with Low OCLO and ACM = 1 -11 -14 -20 -29 -14 -18 -25 -40 -16 -22 -40 -60 +11 +14 +20 +29 +14 +18 +25 +40 +16 +22 +40 +60 -11 -14 -20 -29 -11 -14 -20 -29 -11 -14 -20 -29 +11 +14 +20 +29 +11 +14 +20 +29 +11 +14 +20 +29 ACC I CSNS 2 CAL Current Sense Accuracy for 9.0 V < VBAT < 18 V with 2 calibration points at 25 °C for 2.0% and 50% FSR and VBAT = 14 V for 7.0 mΩ Power Channel
• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -6.0 -6.0 -8.0 -12 +6.0 +6.0 +8.0 +12 -6.0 -6.0 -8.0 -12 +6.0 +6.0 +8.0 +12 ICSNSMIN Minimum Current Sense Reporting for 17 mΩ
• 9 . 0 V < VBAT < 12 V
• 9 . 0 V < VBAT < 18 V 2.0 3.0 1.0 1.0 ACC VBAT Battery Feedback Precision
• Default
• 1 calibration point at 25 °C and VBAT = 12 V, for 7.0 V < VBAT < 20 V
• 1 calibration point at 25 °C and VBAT = 12 V, for 6.0 V < VBAT < 7.0 V -5.0 -1.0 -2.2 +5.0 +1.0 +2.2 -5.0 -1.5 -2.2 +5.0 +1.5 +2.2

Table 2. Part Variations(continued)

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Analog Integrated Circuit Device Data Freescale Semiconductor 5 MC07XS6517 Archive Information Archive Information

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2 Internal Block Diagram

Figure 2. Simplified Internal Block Diagram (Penta version)

3 Pin Connections

3.1 Pinout Diagram

Figure 3. Pinout Diagram

3.2 Pin Definitions

Table 3. 07XS6517 Pin Definitions

3 CP Internal

Charge-pump This pin is the connection for an external capacitor for charge pump use only.

4 RSTB SPI Reset This input pin is used to initialize the device configuration and fault registers,

5 CSB SPI Chip select This input pin is connected to a chip select output of a master microcontroller

internal pull-up to VCC through a diode.

6 SCLK SPI Serial clock This input pin is connected to the MCU providing the required bit shift clock

for SPI communication. This pin has an passive internal pull-down.

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9 SO SPI Serial Output This output pin is connected to the SPI Serial Data Input pin of the MCU or

pin has a passive internal pull-down. 11, 44 GND Ground Ground These pins are the ground for the logic and analog circuitries of the device. 12, 13 OUT2 Output Channel #2 Protected high-side power output pins to the load. 14, 15, 16 OUT4 Output Channel #4 Protected high-side power output pins to the load. NC N/A Not connected These pins are not connected. 28… 37 OUT5 Output Channel #5 Protected high-side power output pins to the load. 39, 40, 41 OUT3 Output Channel #3 Protected high-side power output pins to the load. 42, 43 OUT1 Output Channel #1 Protected high-side power output pins to the load.

45 CSNS Feedback Current sense This pin reports an analog value proportional to the designated OUT[1:5]

output current or the temperature of the exposed pad or the battery voltage.

46 CSNS

This open drain output pin allows synchronizing the MCU A/D conversion. This pin requires an external pull-up resistor to VCC. Table 3. 07XS6517 Pin Definitions (continued)

52 CLK Input/Output Device mode

55 VBAT Power

operational power for the device.

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4 General Product Characteristics

4.1 Relationship Between Ratings and Operating Requirements

(logic in case of a VCC disconnect, charge pump, gate drive,...) is derived from the VBAT pin.

• the internal supply rail is protected (max. -16 V)
• the output drivers (OUT1… OUT5) ar e switched on, to reduce the power consumption in the drivers when using incandescent bulbs

Figure 4. Ratings vs. Operating Requirements (VBAT pin) protected externally in case of a reverse polarity, and in case of a high-voltage disturbance. Figure 5. Ratings vs. Operating Requirements (VCC pin)

4.2 Maximum Ratings

Table 4. Maximum Ratings

• IN1… IN4 and LIMP
• CLK, SI, SCLK, CSB, and RSTB -0.3 -0.3 V (2) VOUT Digital Output Voltage
• SO, CSNS, SYNC, OUT6, CLK -0.3 V (2) ICL Negative Digital Input Clamp Current –5 . 0 m A (3) IOUT Power Channel Current
• 7 . 0 mΩ channel
• 1 7 mΩ channel 5.5 A (4) ECL Power Channel Clamp Energy Capability
• 7 . 0 mΩ channel - Initial TJ = 25 °C
• 7 . 0 mΩ channel - Initial TJ = 150 °C
• 1 7 mΩ channel - Initial TJ = 25 °C
• 1 7 mΩ channel - Initial TJ = 150 °C 200 100 100 mJ (5) VESD ESD Voltage
• Human Body Model (HBM) - VBAT, Power Channel, and GND pins
• Human Body Model (HBM) - All other pins
• Charge Device Model (CDM) - Corner pins
• Charge Device Model (CDM) - All other pins -8000 -2000 -750 -500 +8000 +2000 +750 +500 V (6) Notes 2. Exceeding voltage limits on those pins may caus e a malfunction or permanent damage to the device. 3. Maximum current in negative clamping for IN1… IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins 4. Continuous high-side output current rating so long as maximum j unction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 5. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 Ω, VBAT = 14 V). Please refer to Output Clamps section. 6. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model.

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4.3 Thermal Characteristics

4.4 Operating Conditions

This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted. Table 5. Thermal Ratings

• Ambient
• Junction -40 -40 +125 +150 TSTG Storage Temperature -55 + 150 °C TPPRT Peak Package Reflow Temperature During Reflow – 260 °C (7) (8) THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RΘJB Junction-to-Board (1]Soldered to Board) – 2.5 °/W (9) RΘJA Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) – 17.4 °/W (10) (11) RΘJC Junction-to-Case (Case top surface) – 10.6 °/W (12) Notes 7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 10. Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 11. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

Table 6. Operating Conditions functional. All features are operating.

• Jump Start
• Load dump V Reverse Battery -16 – V VCC Functional operating supply voltage - Device is fully functional. All features are operating. 4.5 5.5 V

4.5 Supply Currents

This section describes the current consumption characteristics of the device. Table 7. Supply Currents values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• T A = 25 °C
• T A = 125 °C 1.2 5.0 µA (13) (14) IVBAT Operating mode measured at VPWR = 18 V – 7.0 8.0 mA (14) VCC CURRENT CONSUMPTIONS IQVCC Sleep mode measured at VCC = 5.5 V – 0.05 5.0 µA IVCC Operating mode measured at VPWR = 5.5 V (SPI frequency 5.0 MHz) – 2.8 4.0 mA Notes 13. With the OUT1… OUT5 power channels grounded. 14. With the OUT1… OUT5 power channels opened.

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5 General IC Functional De scription and Application

5.1 Introduction

The 07XS6517 is the latest achievement in automotive drivers for all types of centralized automotive lighting applications. It is an evolution of the successful Gen3 by providing improved features of a complete family of devices using Freescale's latest and unique technologies for the controller and the power stages. It consists of a scalable family of devices compatible in terms of software driver and package footprint. It allows diagnosing the light-emitting diodes (LEDs) with an enhanced current sense precision with synchronization pin. It combines flexibility through daisy chainable SPI 5.0 MHz, extended digital and analog feedbacks, safety, and robustness. It integrates an enhanced PWM module with 8-bit duty cycle capability and PWM frequency prescaler per power channel.

5.2 Features

The main attributes of 07XS6517 are:

• Penta high-side switches with overload, overtemperature and undervoltage protection
• control output for 1 external smart power switch
• 16 Bit SPI communication interface with daisy chain capability
• integrated Fail mode (ASIL B comp liant functional safety behavior)
• dedicated control inputs for use in Fail mode
• analog feedback pin with SPI programmable multiplexer and sync signal
• channel diagnosis by SPI communication
• advanced current sense mode for LED usage
• synchronous PWM module with external cl ock, prescaler and multiphase feature
• excellent EMC behavior
• power net and reverse polarity protection
• ultra low power mode
• scalable and flexible family concept
• board layout compatible SOIC54 package with exposed pad

5.3 Block Diagram

with Smart Power control die lead to an optimized solution. Figure 6. Functional Block Diagram

5.3.1 Self-protected High-side Switches

5.3.2 Power Supply

employed IC architecture guarantees a low quiescent current in Sleep mode.

5.3.3 MCU Interface and Device Control

ground, overcurrent, overtemperature, clock-fail, and under and overvoltage. The device allows driving loads at different frequencies up to 400 Hz.

5.4 Functional Description

• in Normal mode by SPI interface. For bidirecti onal SPI communication, a second supply voltage (VCC) is required.
• in Fail mode by the corresponding the direct inputs IN1… IN4. The OUT5 for the Penta version and the OUT6 are off in this mode. Power Supply Gen4 - Functional Block Diagram Parallel Control Inputs MCU Interface & Device Control SPI Interface Self-Protected Supply MCU Interface & Output Cont rol Self-Protected High-side Switches PWM Controller High-side Switches OUT[x] MCU Interface

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5.5 Modes of Operation

• wake = (IN1_ON) OR (IN2_ON) OR (IN3_ON) OR (IN4_ON) OR (RST\\). More details in Logic I/O Plausibility Check section.
• fail = (SPI_fail) OR (LIMP). More details in Loss of Communication Interface section.

Figure 7. General IC Operating Modes

5.5.1 Power Off Mode

The power off mode is applied when VBAT and VCC are below the power on reset threshold (VBAT POR, VCC POR).

5.5.2 Sleep Mode

• the component is inactive and all outputs are disabled
• the outputs are protected by the clamping circuits
• the pull up / pull down resistors are present The Sleep mode is the default mode of the device after applying the supply voltages (VBAT or VCC) prior to any wake-up condition (wake = [0]). The wake-up from Sleep mode is provided by the wake signal.

5.5.3 Normal Mode

state (wake = [1]) and no fail condition (fail = [0]) is detected.

• the power outputs are under control of the SPI
• the power outputs are controlled by the programmable PWM module wake = [0] wake = [0] wake = [1] fail = [1] fail = [0] and valid watchdog toggleFail Normal Sleep Power off (VBAT < VBATPOR) and (VCC < VCCPOR) (VBAT > VBATPOR) or (VCC > VCCPOR) (VBAT < VBATPOR) and (VCC < VCCPOR) (VBAT < VBATPOR) and (VCC < VCCPOR)

Analog Integrated Circuit Device Data Freescale Semiconductor 17 MC07XS6517 Archive Information Archive Information

• the power outputs are protected by the overload protection circuit
• the control of the power outputs by SPI programming
• the digital diagnostic feature transfers status of the smart switch via the SPI
• the analog feedback output (CSNS and CSNS SYNC) can be controlled by SPI The channel control (CHx) can be summarized:
• CH1… 4 controlled by ONx or iINx (if ir is programmed by SPI)
• CH5… 6 controlled by ONx
• Rising CHx by definition means star ting over current window for OUT1… 5.

5.5.4 Fail Mode

The device enters the Fail mode, when

• the LIMP input pin is high (logic [1])
• or a SPI failure is detected During Fail mode (wake = [1] & fail = [1]):
• the OUT1… OUT4 outputs are directly controlle d by the corresponding control inputs (IN1… IN4)
• the OUT5… OUT6 are turned off
• the PWM module is not available
• while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition):
• the SO shall report the content of SO register defined by SOA0 to 3 bits
• the outputs are fully protected in case of an overload, overtemperature, and undervoltage
• no analog feedback is available
• the max. output overcu rrent profile is activated (OCLO and window times)
• in case of an overload condition or undervoltage, th e autorestart feature controls the OUT1… OUT4 outputs
• in case of an overtemperature condit ion, OCHI1 detection, or severe short-circuit detection, the corresponding output is latched OFF until a new wake-up event. The channel control (CHx) can be summarized:
• CH1… 4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx
• CH5… 6 are off

5.5.5 Mode Transitions

After a wake-up:

• a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])
• the faults are blanked during t BLANKING The device enters in Normal mode after start-up if following sequence is provided:
• V BAT and VCC power supplies must be above their undervoltage thresholds (Sleep mode)
• generate wake-up event (wake =1) setting RSTB from 0 to 1 The device initialization will be completed after 50 µsec (typ). During this time, the device is robust in case of VBAT interrupts higher than 150nsec. The transition from “Normal mode” to “Fail mode” is executed immediately when a fail condition is detected. During the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared. When the Fail mode condition was a:
• LIMP input, WD toggle timeout, WD t oggle sequence, or a SPI modulo 16 error, the SPI diagnosis is available during Fail mode
• SI / SO stuck to static le vel, the SPI diagnosis is not available during Fail mode The transition from “Fail mode” to “Normal mode” is enabled, when
• the fail condition is removed and
• two SPI commands are sent within a valid watchdog cycle (first WD=[0] and then WD=[1])

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During this transition:

• all SPI SI and SO registers are cleared (logic[0])
• the DSF (device status flag) in the registers #1… #7 a nd the RCF (Register Clearer flag) in the device status register #1 are set (logic[1]) To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.

5.6 SPI Interface and Configurations

5.6.1 Introduction

• control the device in case of Normal mode
• provide diagnostics in case of Normal and Fail mode The SPI is a 16 Bit full-duplex synchronous data transfer interface with daisy chain capability. The interface consists of four I/O lines with 5.0 V CMOS logic levels and termination resistors:
• The SCLK pin clocks t he internal shift registers of the device
• The SI pin accepts data into the input shift register on the rising edge of the SCLK signal
• The SO pin changes its state on the rising edge of SCLK and reads out on the falling edge
• The CSB enables the SPI interface
• with the leading edge of CS \\ the registers are loaded
• while CSB is logic [0] SI/SO data are shifted
• with the trailing edge of the CSB signal, SPI da ta is latched into the internal registers
• when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance When the RSTB input is
• low (logic [0]), the SPI and the fault registers are reset. The Wake state then depends on the status of the input pins (IN_ON1… IN_ON4)
• high (logic[1]), the device is in Wake status and the SPI is enabled The functionality of the SPI is checked by a plausibility check. In case of a SPI failure the device enters the Fail mode.

5.6.2 SPI Input Register and Bit Descriptions

The first nibble of the 16 bit data word (D15… D12) serves as address bits. 11 bits (D10… D1) are used as data bits. The D11 bit is the WD toggle bit. This bit has to be toggled with each write command. When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected. All register values are logic [0] after a reset. The predefined value is off / inactive unless otherwise noted. # D1 5 D 14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 name WD SI data

11 Bi t d at a4 Bi t ad ress

Analog Integrated Circuit Device Data Freescale Semiconductor 19 MC07XS6517 Archive Information Archive Information # D1 5 D 1 4 D1 3 D 1 2 D 1 1 D 1 0 D9 D 8 D 7 D 6 D 5 D4 D 3 D2 D 1 D 0 In i tia li sa tio n 1 0 00 00 W D W D S E L SYNC EN 1 SY NC EN0 MU X2 M UX1 MU X0 SOA MODE SOA3 SOA2 SOA 1 SOA0 in i tia li sa tio n 2 1 00 01 W D OCHI THE RMAL OCHI T RANS IENTNO HI D1 NO HI D0 OC H I OD5 OCHI OD4 OC H I OD3 OCH I OD2 OCHI OD 1 PWM sync OT W SE L CH 1 co ntro l 2 0 0 1 0 W D PH 11 PH01 ON1 PW M71 PWM61 PW M51 PWM41 PW M31 PWM21 PWM11 PW M01 CH 2 co ntro l 3 0 0 1 1 W D PH 12 PH02 ON2 PW M72 PWM62 PW M52 PWM42 PW M32 PWM22 PWM12 PW M02 CH 3 co ntro l 4 0 1 0 0 W D PH 13 PH03 ON3 PW M73 PWM63 PW M53 PWM43 PW M33 PWM23 PWM13 PW M03 CH 4 co ntro l 5 0 1 0 1 W D PH 14 PH04 ON4 PW M74 PWM64 PW M54 PWM44 PW M34 PWM24 PWM14 PW M04 CH 5 co ntro l 6 0 1 1 0 W D PH 15 PH05 ON5 PW M75 PWM65 PW M55 PWM45 PW M35 PWM25 PWM15 PW M05 CH 6 co ntro l 7 0 1 1 1 W D PH 16 PH06 ON6 PW M76 PWM66 PW M56 PWM46 PW M36 PWM26 PWM16 PW M06 ou tp ut contr ol 8 1 0 0 0 WD PSF 5 PS F4 PSF 3 P SF 2 PSF 1 ON6 ON5 ON4 ON 3 ON2 ON1 9-1 10 01 W D 0X XXX GP WM EN6 GPWM EN 5 GPW M EN4 GPWM EN3 GPWM EN 2 GPW M EN1 9-2 1 0 0 1 WD 1 X X GPWM 7 GPWM6 GPWM 5 GPWM4 GPWM3 GP WM 2 GPWM1 GPWM 0 10-1 1 0 1 0 W D 0 OCLO5 OCLO4 OC LO 3 OCLO2 O C LO1 AC M EN 5 ACM EN4 AC M EN3 ACM EN 2 ACM EN1 10-2 10 10 W D 1 NO OCHI 5 NO OC H I 4 NO OCH I3 NO OCHI2 NO OCH I1 SH OR T OCHI5 SHORT OC HI4 SH OR T OCHI 3 SHORT OC H I 2 SH OR T OCH I1 inp ut en ab le 11 1 0 1 1 W D 0 X X I NE N14 I NEN 04 IN EN13 I NEN 03 IN EN12 I NE N02 I NEN11 I NE N01 12-1 1 1 0 0 WD 0 PRS 15 P RS05 PR S14 PRS04 PR S13 PRS0 3 P RS12 PRS 02 P RS11 PR S01 12-2 11 00 W D 1X XXX XX XX P R S 1 6 P R S 0 6 OL con trol 13-1 11 01 W D 0 OL ON DGL5 OLON DG L4 OLON DGL3 OLON DGL2 OLON DGL1 OLOFF EN 5 OLO FF EN4 OLOFF EN3 OLOF F EN 2 OLOFF EN1 OLL ED control 13-2 1 1 0 1 W D 1 res r es res res OLLED TRI G OLLED EN5 OLLED EN4 OLLED EN 3 OLLED EN2 OLLED EN 1 incr eme nt / dercrement 14 11 10 W D I NCR SG N I NC R15 I NCR05 I NC R14 I NCR 04 IN CR13 I NCR 03 IN CR12 I NC R02 I NCR11 I NC R01 testmode 15 11 11X XX XXX XX XX XX Register S I address SI data Gl obal PW M contr ol ov er curr ent contr ol pre sca le r settings #0 ~# 14 = wa tch dog tog gle bi t #0 SYNC SYNC Sync status #0 = a ddre ss of nex t SO data word EN1 EN0 #0 = s ing le read a ddre ss of nex t SO data w o rd 0 0 #0 = C SN S m ultip lexe r s etti ng 0 1 #0 = S YNC d ela y setti ng 1 0 #0 = wa tch dog tim eout sel ect 1 1 # 1 = ove r te mpe ra tu re w a rni n g th resh ol d se le cti o n #1 = r eset clock module #1 NO H I D1N O H ID 0D Selection #1 = OC H I windo w on l oad de man d 0 0 av aila ble for all c han nels #1 = H ID outpu ts s elec ti on 0 1 av aila ble for cha nne l 3 only #1 = OC H I1 le vel de pen din g o n con tro l die temp erature 1 0 av aila ble for cha nne ls 3 and 4 o nly #1 = OC H I1 le vel ad jus te d durin g OFF to ON tra nsitio n 1 1 un ava ilab le fo r a ll ch anne ls #2~ #7 = P W M val ue (8Bi t) #2~ #7 PH 1x PH 0x P hase #2~ #7 = p has e con tro l 0 0 0 ° #2~ #8 = c han nel on /o ff inc l. O C HI c ont rol 0 1 90° # 8 = pu l se ski pp i ng f e at ure f or po w e r o u tp ut cha n n el s 1 0 1 80 ° # 9-1 = g lob al PWM en abl e 1 1 27 0° #9 -2 = gl o ba l PWM val u e (8Bi t) #11 GPWM #10 -1 = a dva nce d curre nt s ense m ode e nab le EN x OUT x PW Mx OUTx PWMx #10 -1 = OC LO lev el co ntr ol 0 x x x OFF x OFF x #10 -2 = u se sh ort OC HI w i ndo w time 0 ON individua l ON individual #10-2 = st art with OCLO threshold 1 ON g l obal ON global #1 1 = i npu t en able c ontrol 0O F F individua l ON individual #1 2 = p re sca ler se tting 1O F F g l obal ON global #13 -1 = OL l oad in o ff state enab le 0 OFF individua l ON individual #13 -1 = OL ON degl itch ti me 1O F F g l obal ON global #13 -2 = OL L ED mo de en able 0O N individua l ON global #13 -2 = trig ger for OLLED detetcio n in 100 % d.c. 1 ON g l obal ON individual #1 4 = P WM inc reme nt / dec reme nt si gn #12 P RS 1x PRS 0x PRS divider #1 4 = P WM inc reme nt / dec reme nt se ttin g 0 0 /4 2 5Hz .... 10 0H z 0 1 / 2 50Hz .. .. 200Hz #0 MUX2 MUX1 MUX0 CSNS 1 x / 1 100Hz .. .. 400Hz 000 #14 inc rem e nt/decr em ent 001 010 011 #14 IN C R 1x INC R 0x inc rem e nt/decr em ent 1 0 0 0 0 no i ncrem ent/dec reme nt 101 01 110 1 111 1 1 VBAT m onitor 8 LSB con tro l die temp erature 1 6 LSB OUT2 cur rent 1 in crem ent OUT3 current OUT4 current OUT5 current 4 LSB off INCR SGN OUT1 cur rent 0 de crem ent OLL ED ENx 11 OLL ED TRIG IN CR SGN IN C R0x ~ IN C R1x IN E N0x ~ IN E N1x 01PR S0x ~ P RS 1x OLOF F ENx 10 OLO N DGLx INE N0x IN x= 0 I Nx= 1 ACM E Nx OCLOx SHOR T OCHI x NO OCHI x ONx PS Fx GPWM ENx GPWM 1 ~ G PWM 7 ONx INEN1x OCH I ODx NO HI Dx OCH I THERM AL OCHI TR A N SI ENT PWM0x ~ PWM7x PH0x ~ PH 1x SYNC EN 0~ SYN C E N1 trig0 WD SEL trig1/ 2 OT W SEL PW M S Y NC WD S O A0 ~ SOA3 SOA M OD E sy nc off MUX 0 ~ MU X2 va lid

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5.6.3 SPI Output Register and Bit Descriptions

The first nibble of the 16 Bit data word (D12… D15) serves as address bits. All register values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off / inactive unless otherwise noted. QSFx #1 = quick st at us (OC or OTW or OTS or OLON or OLOFF) #2~#6 OC 2x O C1x OC 0x ove r cur re nt st atus CLK F #1 = PWM clo ck fail flag 0 0 0 n o ove rcu rrent RC F #1 = reg ister c lea r fla g 0 0 1 OC H I1 CPF #1 = ch arge pum p fl ag 0 1 0 OC H I2 OLF #1 ~# 7 = op en lo ad flag (wi red or of all OL s ign als ) 0 1 1 OC H I3 OVLF #1 ~# 7 = ov er loa d fl ag (wire d or of all OC a nd OTS sig nal s) 1 0 0 OC LO DSF #1 ~# 7 = de vic e status flag ( UVF or OVF or CP F or R CF or CL KF o r TM F) 1 0 1 OC H IOD FM #1 ~# 8 = fail m ode fla g 11 0 S S C OLOFFx #2 ~# 6 = op en lo ad in o ff state status b it 1 1 1 n ot u sed OLONx #2 ~# 6 = op en lo ad in o n state status b it #9 DEVI D2 D EVI D 1 DEVI D0 de vi ce ty pe OTWx #2 ~# 6 = ov er te mp eratur e w a rnin g bit 0 0 0 P enta3 /2 OT Sx #2 ~# 6 = ov er te mp eratur e shu td own bit 0 0 1 P enta0 /5 iL IM P #7 = status o f LIM P i npu t after de gli tc her (re ported i n rea l tim e) 0 1 0 Qu ad2 /2 SPIF #7 = SPI f ail flag 01 1 Q u a d 0 / 4 UVF #7 = un der v oltag e fla g 1 0 0 Trip le1 /2 OVF #7 = ov er vo lta ge flag 1 0 1 Trip le0 /3 TMF #7 = testmo de a ctiva ti on flag 1 1 0 re s OUTx #8 = status o f VB AT/2 c omp arato r (re po rte d in rea l ti me) 1 1 1 re s iI Nx #8 = status o f INx p in after de glitc her (re ported i n real tim e) TOGGLE #8 = status o f INx _ON s ign als (IN 1_O N or IN2 _ON o r IN 3_ON or IN 4_ ON) D EVID0 ~ DE VID 2 #9 = de vic e ty pe D EVID3 ~ DE VID 4 #9 = de vic e fa mil y D EVID5 ~ DE VID 7 #9 = de sig n status (in cre men te d nu mbe r)

5.6.4 Timing Diagrams

Figure 8. Timing Requirements During SPI Communication Figure 9. Timing Diagram for Serial Output (SO) Data Communication

22 Freescale Semiconductor

5.6.5 Electrical Characterization

Table 8. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. Parameter is deri ved from simulations.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 MC07XS6517 Archive Information Archive Information

6 Functional Block Requirements and Behaviors

6.1 Self-protected High-side Swit ches Description and Application

6.1.1 Features

Up to five power outputs are foreseen to drive automotive light applications. The outputs are optimized for driving automotive bulbs, but also HID ballasts, LEDs, and other primarily resistive loads. The smart switches are controlled by use of high sophisticated gate drivers. The gate drivers provide:

• output pulse shaping
• output protections
• active clamps
• output diagnostics

6.1.2 Output Pulse Shaping

The outputs are controlled with a closed loop active pulse shaping to provide the best compromise between:

• low switching losses
• low EMC emission performance
• minimum propagation delay time Depending on the programming of the prescaler setting register #12-1, #12-2, the switching speeds of the outputs are adjusted to the output frequency range of each channel. The edge shaping shall be designed according the following table: The edge shaping provides full symmetry for rising and falling transition:
• the slopes for the rising and falling edge are matc hed to provide the best EMC emission performance
• the shaping of the upper edges and t he lower edges are matched to provide the best EMC emission performance
• the propagation delay time for the rising edge and the fa lling edge is matched to provide true duty cycle control of the output duty cycle error, < 1 LSB at max. frequency
• a digital regulation loop is used to mini mize the duty cycle error of the output signal divider f act or min m ax mi n max min m ax min max 4 25 100 10 40 03 FB 42 5 2 2 50 200 5 20 07 F7 82 4 8 1 100 400 2, 5 1 0 07 F7 82 4 8 PWM freq [Hz] PWM period [ms] d.c. range [hex] d.c. range [LSB] min. on/off duty cycl e t ime [ µs] 156 156

24 Freescale Semiconductor

Figure 10. Typical Power Output Switching (slow & fast slew rate)

6.1.2.1 SPI Control and Configuration

very high frequency), the output duty cycle is 100%.

• PH0x… PH1x: phase assignment of the output channel x
• ONx: on/off control including overcurrent window control of the output channel x
• PWM0x… PWM7x: 8-bit PWM value individually for each output channel x The ONx bits are duplicated in the output control register #8 to control the outputs with either the CHx control register or the output control register. The PRS1x… PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2. The following changes of the duty cycle are performed asynchronous (with pos. edge of CSB signal)
• turn on with 100% duty cycle (CHx = ON)
• change of duty cycle value to 100%
• turn off (CHx = OFF)
• phase setting (PH0x… PH1x)
• prescaler setting (PRS1x… PRS0x) A change in phase setting or prescaler setting during CHx = ON may cause an unwanted long ON-time. Therefore it is recommended to turn off the output(s) before execution of this change. The following changes of the duty cycle are performed synchronous (with the next PWM cycle)
• turn on with le ss than 100% duty cycle (OUTx = ONx)
• change of duty cycle value to less than 100% # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D 2 D 1 D0 C H x contr ol 2~ 7 WD PH1x PH0x Onx PWM7x PWM6x PWM5x PWM4x PWM3x PWM2x PWM1x PWM0xchannel address Register SI address SI data INCR SGN increment/decrement 0d e c r e m e n t 1 increment

Analog Integrated Circuit Device Data Freescale Semiconductor 25 MC07XS6517 Archive Information Archive Information A change of the duty cycle value can be achieved by a change of the

• PWM0x… PWM7x bits in individual channel control register #2… #7
• GPWM EN1… GPWM EN6 bits (change between individual PWM and global PWM settings) in global PWM control register #9-1
• incremental/decremental register #14 The synchronization of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2 register #1. On a SPI write into initialization 2 register (#1):
• initialization when the bit D1 (PWM SYNC) is logic[1], a ll counters of the PWM module are reset with the positive edge of the CSB, i.e. the phase synchronization is performed immediately within one SPI frame. It could help to synchronize different Gen4 devices in the board.
• when the bit D1 is logic[0], no action is executed The switching frequency can be adjusted for the corresponding channel as described in the following table: No PWM feature is provided in case of:
• F a i l m o d e
• clock input signal failure

6.1.2.2 Global PWM Control

In addition to the individual PWM register, each channel can be assigned independently to a global PWM register. The setting is controlled by the GPWM EN bits inside the global PWM control register #9-1. When no control by direct input pin is enabled and the GPWM EN bit is

• low (logic[0]), the output is assig ned to individual PWM (default status)
• high (logic[1]), the output is assigned to global PWM The PWM value of the global PWM channel is controlled by the global PWM control register #9-2. div ider sl ew min. max. P RS1x PRS0x factor min max rate [Bit] [steps] 00 4 25 10 0 sl ow 01 2 50 20 0 sl ow 1X 1 100 400 fas t 25, 6 102,4 PWM fr eq [Hz] PWM resoluti o n 256 CLK fr eq. [kHz] prescaler setting hex dec [%] S0 S1 S2 S3 S4 S5 S6 S7 FF 256 100,00% FF FF FF FF FF FF FF FF FE 255 99,61% F7 FF FF FF FF FF FF FF FD 254 99,22% F7 FF FF FF F7 FF FF FF FC 253 98,83% F7 FF F7 FF F7 FF FF FF FB 252 98,44% F7 FF F7 FF F7 FF F7 FF FA 251 98,05% F7 F7 F7 FF F7 FF F7 FF F9 250 97,66% F7 F7 F7 FF F7 F7 F7 FF F8 249 97,27% F7 F7 F7 F7 F7 F7 F7 FF F7 248 96,88% F6 247 96,48% F5 246 96,09% .. . .. . 03 4 1,56% 02 3 1,17% 01 2 0,78% 00 1 0,39% PWM duty cycle pulse skipping frame

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the corresponding output channel setting.

6.1.2.3 Incremental PWM Control

To reduce the control overhead during soft start/stop of bulbs (e.g. theatre dimming), an incremental PWM control feature is implemented. With the incremental PWM control feature the PWM values of all internal channels OUT1… OUT5 can be incremented or decremented with one SPI frame. The incremental PWM feature is not available for

• the global PWM channel
• the external channel OUT6 The control is according the increment/decrement register #14:
• INCR SGN: sign of incremental dimming (valid for all channels)
• INCR 1x, INCR 0x increment/decrement This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.

6.1.2.4 Pulse Skipping

Due to the output pulse shaping feature and the resulting switching delay time of the smart switches, duty cycles close to 0% resp. 100% can not be generated by the device. Therefore the pulse skipping feature (PSF) is integrated to interpolate this output duty cycle range in Normal mode. The pulse skipping provides a fixed duty cycle pattern with eight states to interpolate the duty cycle values between F7 (Hex) and FF (Hex). The range between 00 (Hex) and 07 (Hex) is not considered to be provided. The pulse skipping feature

• is available individually for the power output channels (OUT1… OUT5)
• is not available for the external channel (OUT6). The feature is enabled with the PSF bits in the output control register #8. When the corresponding PSF bit is
• low (logic[0]), the pulse skipping feature is disabled on this channel (default status)
• high (logic[1]), the pulse skipping feature is enabled on this channel GP WM ENx CHx PWMx CHx PWMx 0 x x x OF F x OFF x

0 O N individual O N individual

0 OF F individual O N individual

1 OF F global O N global

0 O N individual O N global

1 O N global O N individual1

iINx=1ONx INEN1x INEN0x iINx=0 INCR 1x INCR 0x increment/decrement 0 0 no increment/decrement 014 1 0 8 1 1 16

6.1.2.5 Input Control

• wake-up the device
• fully control the corresponding output in case of Fail mode
• control the corresponding output in case of Normal mode The control during Normal mode is according the INEN0x and INEN1x bits in the input enable register #11 and according following logic table: An input deglitcher is provided at each control input to avoid high frequency control of the outputs. The internal signal is called iINx. The channel control (CHx) can be summarized:
• Normal mode:
• CH1… 4 controlled by ONx or INx (if it is programmed by the SPI)
• CH5… 6 controlled by ONx
• Rising CHx by definition means starting overcurrent window for OUT1… 5
• F a i l m o d e :
• CH1… 4 controlled by iINx, while the over current windows are controlled by IN_ONx
• CH5… 6 are off Even so, the input thresholds are logic level compatible, the input structure of the pins shall be able to withstand battery voltage conditions. The inputs have an integrated pull-down resistor.

6.1.2.6 Electrical Characterization

Table 9. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• T J = 25 °C, VBAT > 12 V
• T J = 150 °C, VBAT > 12 V
• T J = 25 °C, VBAT = 7.0 V
• T J = 25 °C, VBAT = -12 V
• T J = 150 °C, VBAT = -12 V 7.0 11.9 10.5 10.5 15.7 mΩ RDS(on) ON-Resistance, Drain-to-Source for 17 mΩ Power Channel
• T J = 25 °C, VBAT > 12 V
• T J = 150 °C, VBAT > 12 V
• T J = 25 °C, VBAT = 7.0 V
• T J = 25 °C, VBAT = -12 V
• T J = 150 °C, VBAT = -12 V 28.9 25.5 25.5 mΩ ILEAK SLEEP Sleep Mode Output Leakage Current (Output shorted to GND) per Channel
• T J = 25 °C, VBAT = 12 V
• T J = 125 °C, VBAT = 12 V
• T J = 25 °C, VBAT = 35 V
• T J = 125 °C, VBAT = 35 V 0.5 5.0 5.0 µA

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6.1.3 Output Protections

• overload conditions
• harness short-circuit
• overcurrent protection against ultra-low resistive short- circuit conditions thanks to smart overcurrent profile & severe short-circuit protection
• overtemperature protection including overtemperature warning
• under and overvoltage protections
• charge pump monitoring
• reverse battery protection In case a fault condition is detected, the corresponding output is commanded off immediately after the deglitch time tFAULT SD. The turn off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature (fast turn off). POWER OUTPUTS OUT1… OUT5 (Continued) IOUT OFF Operational Output Leakage Current in OFF-State per Channel
• T J = 25 °C, VBAT = 18 V
• T J = 125 °C, VBAT = 18 V µA δPWM Output PWM Duty Cycle Range (measured at VOUT = VBAT/2)
• Low Frequency Range (25 to 100 Hz)
• Medium Frequency Range (50 to 200 Hz)
• High Frequency Range (100 to 400 Hz) 4.0 8.0 8.0 252 248 248 LSB SR Rising and Falling Edges Slew-Rate at V BAT = 14 V (measured from VOUT = 2.5 V to VBAT - 2.5 V)
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range 0.25 0.25 0.55 0.42 0.42 0.84 0.6 0.6 1.25 V/µs (16) ΔSR Rising and Falling Edges Slew Rate Matching at VBAT = 14 V (SRr / SRf) 0.9 1.0 1.1 (16) tDLY Turn-on and Turn-off Delay Times at VBAT = 14 V
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range 100 100 µs (16) ΔtDLY Turn-on and Turn-off Delay Times Matching at VBAT = 14 V
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range -20 -20 -10 0.0 0.0 0.0 µs (16) tOUTPUT SD Shutdown Delay Time in case of Fault 0.5 2.5 4.5 µs REFERENCE PWM CLOCK fCLK Clock Input Frequency Range 25.6 – 102.4 kHz Notes

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• does not use edge shaping
• is provided with high slew rate to minimize the output turn-off time tOUTPUT SD, in regards to the detected fault
• uses a latch which keeps the FTO active during an undervoltage condition (0 < VBAT < VBAT UVF)

Figure 11. Power Output Switching in Nominal Operation and In Case of Fault

• the status is reported in the quick status register #1 and the corresponding channel status register #2… #6. To restart the output
• the channel must be restarted by writing the corresponding ON bit in the channel control register #2… #6 or output control register #8.

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Figure 12. Output Control Diagram in Normal Mode

32 Freescale Semiconductor

6.1.3.1 Overcurrent Protections

Each output channel is protected against overload conditions by use of a multilevel overcurrent shutdown. Figure 15. Transient Overcurrent Profile The current thresholds and the threshold window times are fixed for each type of power channel.

• the clock for the t OCHI counter is activated when the output = [1] respectively CHx = 1
• the clock for the t OCHI counter is stopped when the output = [0] respectively CHx= 0

Figure 16. Transient Over Current Profile in PWM mode impedance is monitored during the output turn-on.

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6.1.3.1.1 Over Current Control Programming

OCHI2 time counter is divided by 8, when no load current is demanded from the output driver.

• the clock for the t OCHI2 counter is divided by 8 when the open load signal is high (logic[1]), to accommodate the HID ballast while in power on reset mode
• the clock for the t OCHI2 counter is connected directly to the window time counter when the OpenLoad signal is low (logic[0]), to accommodate the HID demanding load current from the output

Figure 19. HID Ballast Overcurrent Profile reset time of HID ballast. Nominal tOCHI2 duration is up to 64 ms (instead of 8.0 ms). The functionality is controlled by the NO_HID1 and NO_HID0 bits inside the initialization #2 register.

• [0 0]: smart HID feature is available for all ch annels (default status and during Fail mode)
• [0 1]: smart HID feature is available for channel 3 only
• [1 0]: smart HID feature is av ailable for channels 3 and 4 only
• [1 1]: smart HID feature is not available for any channel OCHI On Demand (OCHI OD) In some instances, a lamp might be de-powered when its supply is interrupted by the opening of a switch (as in a door), or by disconnecting the load (as in a trailer harness). In these cases, the driver should be tolerant of the inrush current that will occur when the load is reconnected. The OCHI On Demand feature allows such control individually for each channel through the OCHI ODx bits inside the Initialization #2 register. time IOCHI1 IOCHI2 IOCHI3 IOCLO current tOCHI38 x tOCHI2 tOCHI1 Over Current Threshold Profile Channel Current

• low (logic[0]), the channel operates in its Normal, Def ault mode. After end of OCHI window timeout the output is protected with an OCLO threshold
• high (logic[1], the channel operates in the OCHI On Demand mode and uses the OCHI2 and OCHI3 windows and times after an OCLO event To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register and then turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output. The fault detection status is reported in the quick status register #1 and the corresponding channel status registers #2… #6, a s presented in Figure 20.

Figure 20. OCHI On Demand Profile The CSNS recopy factor and OCLO threshold depend on OCLO and ACM settings. The OCLO setting is controlled by the OCLOx bits inside the overcurrent control register #10-1.

• low (logic[0]), the output is prot ected with the higher OCLO threshold (default status and during Fail mode)
• high (logic[1]), the lower OCLO threshold is applied SHORT OCHI The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis and to reduce the potential stress inside the switch during an overload condition. The setting is controlled individually for each output by the SHORT OCHIx bits inside the overload control register #10-2. When the SHORT OCHIx bit is
• low (logic[0]), the default OCHI window times are applied (default status and during Fail mode)
• high (logic[1]), the short OCHI window times are applied (50% of the regular OCHI window time) NO OCHI The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis. The setting is controlled individually for each channel by the NO OCHIx bits inside the overcurrent control register #10-2. When the NO OCHIx bit is
• low (logic[0]), the regular OCHI window is ap plied (default status and during Fail mode)
• high (logic[1]), the turn on of the output is provided without OCHI windows The NO OCHI bit is applied in real time. The OCHI window is left immediately when the NO OCHI is high (logic[1]). timetOCHI3 current tOCHI2 IOCHI2 IOCHI3 IOCLO OCHI2 fault reported OCHI3 fault reported OCLO fault reported OCHI OD fault reported solid line: nominal operation dotted lines: fault conditions

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• the NO OCHIx bit is set to logic [1] while CHx is ON or
• CHx turns ON if NO OCHIx is already set THERMAL OCHI To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHI1 level can be automatically adjusted in regards to the control die temperature. The functionality is controlled for all channels by the OCHI THERMAL bit inside the initialization 2. When the OCHI THERMAL bit is:
• low (logic[0]), the output is pr otected with default OCHI1 level
• high (logic[1]), the output is protec ted with the OCHI1 level reduced by RTHERMAL OCHI = 15% (typ) when the control die temperature is above TTHERMAL OCHI = 63 °C (typ) TRANSIENT OCHI To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHIx levels can be dynamically evaluated during the OFF-to-ON output transition. The functionality is controlled for all channels by the OCHI TRANSIENT bit inside the initialization 2 register. When the OCHI TRANSIENT bit is:
• low (logic[0]), the output is pr otected with default OCHIx levels
• high (logic[1]), the output is protected with an OCHIx levels depending on the output voltage (VOUT):
• OCHIx level reduced by R TRANSIENT OCHI = 50% typ for 0 < VOUT < VOUT DETECT (VBAT / 2 typ),
• Default OCHIx level for V OUT DETECT < VOUT In case the resistive load is less than VBAT/IOCHI1, the overcurrent threshold will be exceeded before output reaches VBAT / 2, and the output current reaches IOCHI1. The output is then switched off at much lower and safer currents. When the load has significant series inductance, the output current transition falls behind voltage with LLOAD/RLOAD constant time. The intermediate overcurrent threshold could not reach and the output current continues to rise up to OCHIx levels.

6.1.3.1.2 Electrical Characterization

Table 10. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

• T J = -40 °C and 25 °C
• T J = 150 °C 100 111 106 126.5 126.5 A IOCHI2 High Overcurrent Level 2 for 7.0 mΩ Power Channel
• T J = -40 °C and 25 °C
• T J = 150 °C 61.2 77.5 77.5 A IOCHI3 High Overcurrent Level 3 for 7.0 mΩ Power Channel 34 39 43.5 A IOCLO Low Overcurrent for 7.0 mΩ Power Channel
• High Level
• Low Level 17.6 8.8 21.9 10.8 26.4 13.2 A IOCLO ACM Low Overcurrent for 7.0 mΩ Power Channel in ACM Mode
• High Level
• Low Level 8.8 4.4 10.8 5.5 13.2 6.6 A IOCHI1 High Overcurrent Level 1 for 17 mΩ Power Channel
• T J = -40 °C and 25 °C
• T J = 150 °C 54.4 54.4 A

6.1.3.2 Overtemperature Protection

A dedicated temperature sensor is located on each power transistor, to protect the transistors and provide SPI status monitoring. The protection is based on a two stage strategy.

• selectable overtemperature warning threshold (T OTW1, TOTW2), the output stays on and the event is reported in the SPI
• overtemperature threshold (TOTS), the output is switched off immediately after the deglitch time tFAULT SD and the event is reported in the SPI after the deglitch time tFAULT SD. POWER OUTPUTS OUT1… OUT5 (Continued) IOCHI2 High Overcurrent Level 2 for 17 mΩ Power Channel 24.5 28.2 32.2 A IOCHI3 High Overcurrent Level 3 for 17 mΩ Power Channel 14.8 17.3 19.5 A IOCLO Low Overcurrent for 17 mΩ Power Channel
• High Level
• Low Level 8.8 4.4 10.8 5.3 13.2 6.6 A IOCLO ACM Low Overcurrent for 17 mΩ Power Channel in ACM Mode
• High Level
• Low Level 4.4 2.2 5.3 2.6 6.6 3.3 A RTRANSIENT OCHI High Overcurrent Ratio 1 0.45 0.5 0.55 RTHERMAL OCHI High Overcurrent Ratio 2 0.835 0.85 0.865 TTHERMAL OCHI Temperature Threshold for IOCHI1 Level Adjustment 50 63 70 °C tOCHI1 High Overcurrent Time 1
• Default Value
• SHORT OCHI option 1.5 0.75 2.0 1.0 2.5 1.25 ms tOCHI2 High Overcurrent Time 2
• Default Value
• SHORT OCHI option 6.0 3.0 8.0 4.0 5.0 ms tOCHI3 High Overcurrent Time 3
• Default Value
• SHORT OCHI option ms RSC MIN Minimum Severe Short-circuit Detection
• 7 . 0 mΩ Power Channel
• 1 7 mΩ Power Channel 5.0 mΩ tfault SD Fault Deglitch Time
• OCLO and OCHI OD
• OCHI1… 3 and SSC 1.0 1.0 2.0 2.0 3.0 3.0 µs (17) tautorestart Fault Autorestart Time in Fail Mode 48 64 80 ms tBLANKING Fault Blanking Time after Wake-up – 50 100 µs Notes 17. Guaranteed by testmode.

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

38 Freescale Semiconductor

6.1.3.2.1 Overtemperat ure Warning (OTW)

• the output remains in current state
• the status is reported in the quick status register #1 and the corresponding channel status register #2… #6 The OTW threshold can be selected by the OTW SEL bit inside the initialization 2 register #1. When the bit is:
• low (logic[0]), the high overtemperatur e threshold is enabled (default status)
• high (logic[1]), the low overtemperature threshold is enabled To delatch the OTW bit (OTWx):
• the temperature has to drop below the corresponding overtemperature warning threshold
• a read command of the corresponding channel status register #2… #6 must be performed

6.1.3.2.2 Overtemperat ure Shutdown (OTS)

• the corresponding output is disabled immediately after the deglitch time t FAULT SD
• the status is reported after t FAULT SD in the quick status register #1 and the corresponding channel status register #2… #6. To restart the output after an overtemperature shutdown event in Normal mode:
• the overtemperature condition must be removed, and the channel must be restarted by a write command of the ON bit in the corresponding channel control register #2… #6, or in the output control register #8 To delatch the diagnosis:
• the overtemperature condition must be removed:
• a read command of the corresponding channel status register #2… #6 must be performed To restart the output after an overtemperature shutdown event in Fail mode:
• a mode transition is needed. Refer to Mode Transitions section

6.1.3.2.3 Electrical Characterization

Table 11. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• T OW1 level
• T OW2 level 100 120 115 135 130 150 °C (18) TOTS Overtemperature Shutdown 155 170 185 °C (18) tFAULT SD Fault Deglitch Time
• O T S 2.0 5.0 10 µs Notes 18. Guaranteed by testmode.

6.1.3.3 Undervoltage and Overvoltage Protections

6.1.3.3.1 Undervoltage

• in the device status flag (DSF) in the registers #1… #7
• in the undervoltage flag (UVF) insi de the device status register #7 Normal mode The reactivation of the outputs is controlled by the microcontroller. To restart, the output the undervoltage condition must be removed and:
• a write command of the ON Bit must be performed in the corresponding channel control register #2… #6 or in the output control register #8 To delatch the diagnosis
• the undervoltage condition must be removed
• a read command of the device status register #7 must be performed Fail mode When the device is in Fail mode, the restart of the outputs is controlled by the autorestart feature.

6.1.3.3.2 Overvoltage

The device is protected against overvoltage on VBAT.

• jump start condition, the device may be oper ated, but with respect to the device limits
• load dump condition (V BAT LD MAX = 40 V) the device does not conduct energy to the loads The overvoltage condition (VBAT > VBAT OVF) is reported in the
• device status flag (DSF) in the registers #1… #7
• overvoltage flag (OVF) inside the device status register #7 To delatch the diagnosis
• the overvoltage condition must be removed
• a read command of the device status register #7 must be performed In case of an overvoltage (VBAT > VBAT HIGH), the device is not “short-circuit“ proof

6.1.3.3.3 Electrical Characterization

Table 12. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

40 Freescale Semiconductor

6.1.3.4 Charge Pump Protection

• power up
• failure of external capacitor
• failure of charge pump circuitry During power up, when the charge pump voltage has not yet settled to its nominal output voltage range, the outputs can not be turned on. Any turn on command during this phase is executed immediately after settling of the charge pump. When the charge pump voltage is not within its nominal output voltage range:
• the power outputs are disabled immediately after the deglitch time t FAULT SD
• the failure status is reported after t FAULT SD in the device status flag DSF in the registers #1… #7 and the CPF in the quick status register #1
• Any turn on command during this phase is executed in cluding the OCHI windows immediately after the charge pump output voltage has reached its valid range To delatch the diagnosis:
• the charge pump failure condition must be removed
• a read command of the quick status register #1 is necessary

6.1.3.4.1 Electrical Characterization

6.1.3.5 Reverse Battery Protection

The device is protected against reverse polarity of the VBAT line.

• the output transistors OUT1… 5 are turned ON in order to prevent the device from thermal overload
• the OUT6 pin is pulled down to GND. An external current limit resistor shall be added in series with OUT6 pin
• no output protection is available in this condition BATTERY VBAT (Continued) VBAT HIGH Maximum Battery Voltage for Short-circuit Protection 32 – – V tFAULT SD Fault Deglitch Time
• UV and OV 2.0 3.5 5.5 µs

Table 13. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• C P F –4 . 06 . 0 µs

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.1.4 Output Clamps

6.1.4.1 Negative Output Clamp

In case of an inductive load (L), the energy is dissipated after the turn-off inside the N-channel MOSFET. When tCL (=Io x L / VCL) > 1.0 ms, the turn-off waveform can be simplified with a rectangle as shown in Figure 21. Figure 21. Simplified Negative Output Clamp Waveform The energy dissipated in the N-Channel MOSFET is: ECL = 1/2 x L x Io² x (1+ VBAT / |VCL|). In the case of tCL < 1.0 ms, please contact the factory for guidance.

6.1.4.2 Battery Clamp

output transistors in order to limit the supply voltage (VDCClamp). VBAT line. The maximum VBAT voltage is limited at VDCCLAMP by active clamp circuitry through the load. are dissipated inside the load, or shall be drained by an external clamping circuit, during a high ohmic load.

6.1.4.3 Electrical Characterization

Table 14. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• 7 . 0 mΩ
• 1 7 mΩ -20.5 -21 -17.5 -18 V time Output Current Io VBAT VCL Output Voltage tCL time time

42 Freescale Semiconductor

6.1.5 Digital Diagnostics

The device offers several modes for load status detection in on state and off state through SPI.

6.1.5.1 OpenLoad Detections

6.1.5.1.1 OpenLoad in ON State

OpenLoad detection during ON state is provided for each power output (OUT1… OUT5), based on the current monitoring circuit. The detection is activated automatically when the output is in on state.

• the OLLED EN bits inside t he OLLED control register #13-2 The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (registers #1… #7)
• the OLON bit of the corresponding channel status registers #2… #6 To delatch the diagnosis:
• the openload condition must be removed
• a read command of the corresponding channel status register #2… #6 must be performed When an open load has been detected, the output remains in on state. The deglitch time of the OpenLoad in on state can be controlled individually for each output in order to be compliant with different load types. The setting is dependent on the OLON DGL bits inside the OpenLoad control register #13-1:
• low (logic[0]) the deglitch time is t OLON DGL = 64 µs typ (bulb mode)
• high (logic[1]) the deglitch time is t OLON DGL = 2.0 ms typ (converter mode) The deglitching filter is reset whenever output falls low and is only active when the output is high.

6.1.5.1.2 OpenLoad in ON State for LED

The detection principle is based on a digital decision during regular switch off of the output. Figure 22. OpenLoad in ON State Diagram for LED

in case of off-time < 2.0 ms. The detection mode is enabled individually for each channel with the OLLED EN bits inside the LED control register #13-2.

• low (logic[0]), the standard Ope nLoad in on state (OLON) is enabled
• high (logic[1]), the OLLED detection is enabled The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (register #1… #7)
• the OLON bit of the corresponding channel status register #2… #6 When an OpenLoad has been detected, the output remains in on state. When output is in PWM operation:
• the detection is performed at the end of the on time of each PWM cycle
• the detection is active during the off time of the PWM signal, up to 2.0 ms max. The current source (IOLLED) is disabled after “no OLLED” detection or after 2.0 ms.

Figure 23. OpenLoad in ON State for LED in PWM Operation (OFF time > 2.0 ms)

44 Freescale Semiconductor

Figure 24. Openload in ON State for LED in PWM Operation (OFF time < 2.0 ms)

• the detection on all outputs is triggered by setting th e OLLED TRIG bit inside the LED control register #13-2
• at the end of detection time, the current source (I OLLED) is disabled 100 µsec (typ.) after the output reactivation

Figure 25. Openload in ON State for LED in Fully ON Operation The OLLED TRIG bit is reset after the detection.

• a read command of the corresponding channel status register #2… #6 must be performed A false “open” result could be reported in the OLON bit:
• for high duty cycles, the PWM off-time becomes too short
• for capacitive load, the output voltage slope becomes too slow En_OLLed_1 hson_1 128*DCLOCK (prescaler=‘0’) VBAT-0.75OUT_1 OUT_high Analog Comparator output 0 : no olled detected 1 : olled detected check TimeOut = 2.0 msec OLLED TRIG 1 En_OLLed_1 hson_1 ONoff & PWM FF TimeOut = 2.0 msec VBAT-0.75OUT_1 OUT_high Analog Comparator output 0 : no olled detected 1 : olled detected check Check Precision ~ 9600 ns Note: OLLED TRIG bit is reset after the detection 100 ℵsec 100 ℵsec

6.1.5.1.3 OpenLoad in OFF State

An OpenLoad in off state detection is provided individually for each power output (OUT1… OUT5). The detection is enabled individually for each channel by the OLOFF EN bits inside the open load control register #13-1.

• low (logic[0]), the diagnosis mo de is disabled (default status)
• high (logic[1]), the diagnosis mode is started for t OLOFF. It is not possible to restart any OLOFF or disable the diagnosis mode during active OLOFF state This detection can be activated independently for each power output (OUT1… OUT5). When it is ac tivated, it is always activated synchronously for all selected outputs (with positive edge of CS\\). When the detection is started, the corresponding output channel is turned on with a fixed overcurrent threshold of IOLOFF threshold. When this overcurrent threshold is:
• reached within the detection timeout t OLOFF, the output is turned off and the OLOFF EN bit is reset. No OCLOx and no OLOFFx will be reported.
• not reached within the detection timeout t OLOFF, the output is turned off after tOLOFF and the OLOFF EN bit is reset. The OLOFFx will be reported. The overcurrent behavior as commanded by the overcurrent control settings (NO OCHIx, OCHI ODx, SHORTOCHIx, OCLOx, and ACM ENx) is not be affected by applying the OLOFF ENx bit. The same is true for the output current feedback and the current sense synchronization. The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (register #1… #7)
• the OLOFF bit of the corresponding channel status register #2… #6 To delatch the diagnosis, a read command of the corresponding channel status register #2… #6 must be performed. In case any fault during tOLOFF (OTS, UV, CPF,), the OpenLoad in off state detection is disabled and the output(s) is (are) turned off after the deglitch time tFAULT SD. The corresponding fault is reported in the SPI SO registers.

6.1.5.1.4 Electrical Characterization

Table 15. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• 7 . 0 mΩ Power Channel at TJ = -40 °C
• 7 . 0 mΩ Power Channel at TJ = 25 °C and 125 °C
• 1 7 mΩ Power Channel at TJ = -40 °C
• 1 7 mΩ Power Channel at TJ = 25 °C and 125 °C 100 200 200 100 100 350 300 160 150 mA δPWM OLON Output PWM Duty Cycle Range for Openload Detection in ON state
• Low Frequency Range (25 to 100 Hz)
• Medium Frequency Range (100 to 200 Hz)
• High Frequency Range (200 to 400 Hz) LSB IOLLED Openload Current Threshold in ON state / OLLED mode 2.0 4.0 5.0 mA tOLLED100 Maximum Openload Detection Time / OLLED mode with 100% duty cycle 1.5 2.0 2.6 ms tOLOFF Openload Detection Time in OFF State 0.9 1.2 1.5 ms

46 Freescale Semiconductor

6.1.5.2 Output Shorted to VBAT in OFF State

voltage comparator referenced to VBAT / 2 (VOUT DETECT) and an external pull-down circuitry. The detection result is reported in the OUTx bits of the I/O status register #8 in real time. In case of UVF, the OUTx bits are undefined.

6.1.5.2.1 Electrical Characterization

6.1.5.3 SPI Fault Reporting

Protection and monitoring of the outputs during normal mode is provided by digital switch diagnosis via the SPI. The selection of the SO data word is controlled by the SOA0… SOA3 bits inside the initialization 1 register #0. The device provides two different reading modes, depending on the SOA MODE bit.

• low (logic[0]), the programmed SO address will be used for a single read command. After the reading the SO address returns to quick status register #1 (default state)
• high (logic[1]), the programmed SO address will be used for the next and all further read commands until a new programming The “quick status register” #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no control action by the microcontroller is necessary.
• FM: Fail mode indication. This bit is also present in all other SO data words, and indicates the fail mode by a logic[1]. When the device is in Normal mode, the bit is logic[0]
• global device status flags (D10… D8): These flags are al so present in the channel status registers #2… #6, the device status register #7, and are cleared when all fault bits are cleared by reading the registers #2… #7 POWER OUTPUTS OUT1… OUT5 (Continued) tFAULT SD Fault Deglitch Time
• O L O F F
• OLON with OLON DGL = 0
• OLON with OLON DGL = 1 2.0 1.5 3.3 2.0 5.0 2.5 µs ms ms I OLOFF Openload Current Threshold in OFF state 0.385 0.55 0.715 A

Table 16. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 47 MC07XS6517 Archive Information Archive Information

• DSF = device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the device status register #7
• OVLF = over load flag (wired OR of all OC and OTS signals)
• OLF = openload flag
• CPF: charge pump flag
• RCF: registers clear flag: this flag is set (l ogic[1]) when all SI and SO registers are reset
• CLKF: clock fail flag. Refer to Logic I/O Plausibility Check section
• QSF1… QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx, or OTSx, or OLONx, or OLOFFx) The SOA address #0 is also mapped to register #1 (D15… D12 bits will report logic [0001]). When a fault condition is indicated by one of the quick status bits (QSF1… QSF5, OVLF, OLF), the detailed status can be evaluated by reading of the corresponding channel status registers #2… #6.
• OTSx: overtemperature shutdown flag
• OTWx: overtemperature warning flag
• OC0x… OC2x: overcurrent status flags
• OLONx: OpenLoad in on state flag
• OLOFFx: OpenLoad in off state flag The most recent OC fault is reported by the OC0x… OC2x bits, if a new OC occurs before an old OC on the same output that was read. When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of the device status registers #7:
• TMF: testmode activation flag. Testmode is used for manufa cturing testing only. If this bit is set to logic [1], the MCU shall reset the device.
• OVF: overvoltage flag
• UVF: undervoltage flag
• SPIF: SPI fail flag
• iLIMP (real time reporting after the t IN_DGL, not latched) The I/O status register #8 can be used for system test, fail mode test and the power down procedure: # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D 1 D0 CH 1 status 2 0 0 1 0 FM DS F OVLF OLF res OTS1 OTW1 OC21 OC11 OC01 OLON1 OLOFF1 CH 2 status 3 0 0 1 1 FM DS F OVLF OLF res OTS2 OTW2 OC22 OC12 OC02 OLON2 OLOFF2 CH 3 status 4 0 1 0 0 FM DS F OVLF OLF res OTS3 OTW3 OC23 OC13 OC03 OLON3 OLOFF3 CH 4 status 5 0 1 0 1 FM DS F OVLF OLF res OTS4 OTW4 OC24 OC14 OC04 OLON4 OLOFF4 CH 5 status 6 0 1 1 0 FM DS F OVLF OLF res OTS5 OTW5 OC25 OC15 OC05 OLON5 OLOFF5 SO dataRe giste r SO address # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D 0 devi ce sta tus 7 0111 F M D S F O V L F O L F r e s r e s r e s T M F O V F U V F S P I F i L I M P SO dataRegister SO address # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I/ O s tat us 8 1 0 0 0 FM re s TOGGLE iIN4 iIN3 iIN2 iIN1 OUT5 OUT4 OUT3 OUT2 OUT1 SO dataRegister SO address

48 Freescale Semiconductor

The register provides the status of the control inputs, the toggle signal, and the power outputs state in real time (not latched).

• TOGGLE = status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or IN4_ON), reported in real time
• iINx = status of iINx signal (real time reporting after the t IN_DGL, not latched)
• OUTx = status of output pins OUTx (the detection threshold is V BAT/2) when undervoltage condition does not occur The device can be clearly identified by the device ID register #9 when the battery voltage is within its nominal range: The register delivers DEVIDx bits = 40hex for the 07XS6517. During undervoltage condition (UVF = 1), DEVIDx bits report 00hex.

6.1.6 Analog Diagnostics

Sleep modes, the analog feedback is not available. The routing of the integrated multiplexer is controlled by MUX0… MUX2 bits in side the initialization 1 register #0.

6.1.6.1 Output Current Monitoring

delivers 1.0 mA full scale range current source reporting channel 1… 5 current feedback (I FSR). Figure 26. Output Current Sensing

001 O C H I 1

010 O C H I 2

011 O C H I 3

100 O C L O

101 O C H I O D

110 S S C

50 Freescale Semiconductor

6.1.6.2 Battery Voltage Monitoring

Figure 28. Battery Voltage Reporting

6.1.6.3 Temperature Monitoring

within the min/max range of 5.0 kΩ to 50 kΩ. Temperature feedback range, TFB, -40 °C to 150 °C. Figure 29. Temperature Reporting

6.1.6.4 Analog Diagnostic Synchronization

A current sense synchronization pin is provided to simplify the synchronous sampling of the CSNS signal. The CSNS SYNCB pin is an open drain requiring an external 5.0 kΩ (min) pull-up resistor to VCC.

• available during Normal mode only
• behavior depends on the type of signal select ed by the MUX2 … MUX0 bits in the initialization 1 register #0. This signal is either a current proportional to an output current or a voltage proportional to temperature or the battery voltage Current sense signal When a current sense signal is selected:
• the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0, SYNC EN1 bits inside the initialization 1 register #0

Figure 30. CSNS SYNC\\ Valid Setting

52 Freescale Semiconductor

Figure 31. CSNS SYNC\\ TRIG0 Setting Figure 32. CSNS SYNC\\ TRIG1/2 Setting

• the CSNS SYNC\\ pulse is suppressed duri ng OCHI and during OFF phase of the PWM
• the CSNS SYNC\\ is blanked during settling time of the CSNS multiplexer and ACM switching by a fixed time of tdly(on) + tCSNS(SET) OUT1 time OUT2 time OUT1 for CSNS selected OUT2 for CSNS selected timechange of CSNS MUX from OUT1 to OUT2 CSNS SYNC\\ CSNS SYNC\\ blanked until rising edge of the 1st complete PWM cycle OUT1 time OUT2 time OUT1 for CSNS selected OUT2 for CSNS selected timechange of CSNS MUX CSNS SYNC\\ active (low) from OUT1 to OUT2 CSNS SYNC\\ CSNS SYNC\\ blanked until 1rst valid edge generated in the middle of the OUT2 pulse

• when a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50% duty cycle at a fixed period of 6.5 ms.
• when the output is programmed with 100% PWM, the CS NS SYNCB delivers a logic[0] a high pulse with the length of 100 µs (typ.) during the PWM counter overflow for TRIG0 and TRIG1/2 settings, as shown in Figure 33.

Figure 33. CSNS SYNC\\ when the output is programmed with 100%

• In case of output fault, the CSNS SYNCB signal for cu rrent sensing does not deliver a trigger signal until the output is enabled again. Temperature signal or VBAT monitor signal When a voltage signal (average control die temperature or battery voltage) is selected:
• the CSNS SYNCB delivers a signal with 50% duty cycle and the period of the lowest prescaler setting (fCLK / 1024).
• and a PWM clock fail is detected, the CSNS SYNC\\ deliv ers a signal with 50% duty cycle at a fixed period of 6.5 ms (tSYNC DEFAULT).

6.1.6.5 Electrical Characterization

Table 17. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

54 Freescale Semiconductor

• High OCLO and ACM = 0
• Low OCLO and ACM = 0
• High OCLO and ACM = 1
• Low OCLO and ACM = 1 5.5 A ACC ICSNS Current Sense Accuracy for 9.0 V < VBAT < 18 V for 7.0 mΩ Power Channel
• I OUT = 80% FSR with ACM = 0
• I OUT = 25% FSR with ACM = 0
• I OUT = 10% FSR with ACM = 0
• I OUT = 5.0% FSR with ACM = 0
• I OUT = 80% FSR with High OCLO and ACM = 1
• I OUT = 25% FSR with High OCLO and ACM = 1
• I OUT = 10% FSR with High OCLO and ACM = 1
• I OUT = 5.0% FSR with High OCLO and ACM = 1
• I OUT = 80% FSR with Low OCLO and ACM = 1
• I OUT = 25% FSR with Low OCLO and ACM = 1
• I OUT = 10% FSR with Low OCLO and ACM = 1
• I OUT = 5.0% FSR with Low OCLO and ACM = 1 -11 -14 -20 -29 -14 -18 -25 -40 -16 -22 -40 -60 +11 +14 +20 +29 +14 +18 +25 +40 +16 +22 +40 +60 ACC ICSNS 1 CAL Current Sense Accuracy for 9.0 V < VBAT < 18 V with 1 calibration point at 25 °C for 50% FSR and VBAT = 14 V for 7.0 mΩ Power Channel
• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -7.0 -7.0 -20 -29 +7.0 +7.0 +20 +29 % (23) (21) ACC ICSNS 2 CAL Current Sense Accuracy for 9.0 V < VBAT < 18 V with 2 calibration points at 25 °C for 2.0% and 50% FSR and VBAT = 14 V for 7.0 mΩ Power Channel
• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -6.0 -6.0 -8.0 -21 +6.0 +6.0 +8.0 +21 % (23) (21) ICSNSMIN Minimum Current Sense Reporting for 17 mΩ
• 9 . 0 V < VBAT < 12 V
• 9 . 0 V < VBAT < 18 V 2.0 3.0 IFSR Current Sense Full Scale Range for 17 mΩ Power Channel
• High OCLO and ACM = 0
• Low OCLO and ACM = 0
• High OCLO and ACM = 1
• Low OCLO and ACM = 1 5.5 5.5 2.75 A

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -11 -14 -20 -29 +11 +14 +20 +29 % (19) ACC ICSNS 1 CAL Current Sense Accuracy for 9.0 V < VBAT < 18 V with 1 calibration point at 25 °C for 50% FSR and VBAT = 14 V for 17 mΩ Power Channel
• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -7.0 -7.0 -20 -29 +7.0 +7.0 +20 +29 % (19) (21) ACC ICSNS 2 CAL Current Sense Accuracy for 9.0 V < VBAT < 18 V with 2 calibration points at 25 °C for 2.0% and 50% FSR and VBAT = 14 V for 17 mΩ Power Channel
• I OUT = 80% FSR
• I OUT = 25% FSR
• I OUT = 10% FSR
• I OUT = 5.0% FSR -6.0 -6.0 -8.0 -11 +6.0 +6.0 +8.0 +11 % (19) (21) ICSNSMIN Minimum Current Sense Reporting for 17 mΩ
• f o r 9 . 0 V < VBAT < 18 V, max. = 1% ––1 . 0 % (19) (22) VBAT Battery Voltage Feedback Range VBATMAX –2 0 V ACC VBAT Battery Feedback Precision
• Default
• 1 calibration point at 25 °C and VBAT = 12 V, for 7.0 V < VBAT < 20 V
• 1 calibration point at 25 °C and VBAT = 12 V, for 6.0 V < VBAT < 7.0 V -5.0 -1.0 -2.2 +5.0 +1.0 +2.2 % (21) TFB Temperature Feedback Range -40 – 150 °C (20) VFB Temperature Feedback Voltage at 25 °C –2 . 3 1 – V COEF VFB Temperature Feedback Thermal Coefficient –7 . 7 2 – mV/°C (21) ACC TFB Temperature Feedback Voltage Precision
• Default
• 1 calibration point at 25 °C and VBAT = 7.0 V -15 -5.0 +15 +5.0 °C (21) tCSNS(SET) Current Sense Settling Time
• Current Sensing Feedback for IOUT from 75% FSR to 50% FSR
• Current Sensing Feedback for IOUT from 10% FSR to 1.0% FSR Temperature and Battery Voltage Feedbacks 260 µs (20) Notes 19. Precision either OCLO and ACM setting. 20. Parameter is derived mainly from simulations. 21. Parameter is guaranteed by design charac terization. Measurements are taken from a statistically relevant sample size across process variations. 22. Error of ±100% without calibration and ±50% with 1 calibration point done at 25 °C.

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

56 Freescale Semiconductor

6.2 Power Supply Functional Bl ock Description and Application

6.2.1 Introduction

6.2.2 Wake State Reporting

The CLK input/output pin is also used to report the wake state of the device to the microcontroller as long as RSTB is logic [0].

• “wake state” and RSTB is inactive, t he CLK pin reports a high signal (logic[1])
• “sleep mode” or the device is wake by the RSTB pin, the CLK is an input pin CURRENT SENSE CSNS (Continued) tCSNS(VAL) Current Sense Valid Time Current Sensing Feedback
• Low / Medium Frequency Ranges for IOUT > 20% FSR
• Low / Medium Frequency Ranges for IOUT < 20% FSR
• High Frequency Range for IOUT > 20% FSR
• High Frequency Range for IOUT < 20% FSR Temperature Voltage Feedback Battery Voltage Feedback 5.0 150 300 300 µs (23) tSYNC DEFAULT Current Sense Synchronization Period for PWM Clock Failure 4.8 6.5 8.2 ms CURRENT SENSE SYNCHRONIZATION CSNS SYNCB RCSNS SYNC Pull-up Current Sense Synchronization Resistor Range 5.0 – – kΩ VOL Current Sense Synchronization Logic Output Low State Level at 1.0 mA ––0 . 4 V IOUT max Current Sense Synchronization Leakage Current in Tri-state (CSNS SYNC from 0 to 5.5 V) -1.0 – +1.0 µA Notes

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.2.2.1 Electrical Characterization

6.2.3 Supply Voltages Disconnection

6.2.3.1 Loss of V BAT

• V CC < VCC POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared.
• V CC > VCC POR: all registers and faults are maintained. OUT1… 5 are shut off immediately. The ON/OFF state of OUT6 depends on the current SPI configuration. SPI reporting is available when VCC remains within its operating voltage range (4.5 to 5.5 V). The wake-up event is not reported to the CLK pin. The clamping structures (battery clamp, negative output clamp) are available to protect the device. No current is conducted from VCC to VBAT. An external current path shall be available to drain the energy from an inductive load, in case a battery disconnection occurs when an output is ON.

6.2.3.2 Loss of V CC

• V BAT < VBAT POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared.
• V BAT > VBAT POR: the SPI is not available. Therefore, the device will enter WD timeout. The clamping structures (battery clamp, negative output clamp) are available to protect the device. No current is conducted from VBAT to VCC.

6.2.3.3 Loss of Device GND

The device shall not be damaged by this failure condition. For protection of the digital inputs series resistors (1.0 kΩ typ) can be provided externally in order to limit the current to ICL. Table 18. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

58 Freescale Semiconductor

6.2.3.4 Electrical Characterization

6.3 Communication Interface and D evice Control Functional Block

6.3.1 Introduction

short-circuit to ground, overcurrent, overtemperature, clock fail, and under and overvoltage.

6.3.2 Fail Mode Input (LIMP)

The Fail mode of the component can be activated by LIMP direct input. The Fail mode is activated when the input is logic [1].

6.3.2.1 Electrical Characterization

Table 19. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Table 20. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.3.3 MCU Communication Interface Protections

6.3.3.1 Loss of Communication Interface

If a SPI communication error occurs, the device is switched into Fail mode.

• the WD bit is not toggled with each SPI message or
• WD timeout is reached or
• protocol length erro r (modulo 16 check) The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by a WD toggle error. The SPI communication error is reported in:
• SPI failure flag (SPIF) inside the device status register #7 in the next SPI communication As long as the device is in Fail mode, the SPIF bit retains its state. The SPIF bit is delatched during the transition from fail-to-normal modes.

6.3.3.2 Logic I/O Plausibility Check

The LIMP and IN1… IN4 have an input symmetrically deglitch time t IN_DGL = 200 µs (typ).

1. Parameter is derived mainly from simulations.

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

60 Freescale Semiconductor

Figure 34. LIMP and iLIMP signal signal (internal signal called iINx). Figure 35. IN, iIN and IN_ON signal The RSTB has an input deglitch time tRST_DGL = 10 µs (typ) for the falling edge only. high input frequency leads to a clock fail detection. The CLK fail detection (clock input frequency detection fCLK LOW) is started immediately with the positive edge of RSTB signal. If the CLK frequency is below fCLK LOW limit, the output state will depend on the corresponding CHx signal. As soon as the CLK signal is valid, the output duty cycle depends on the corresponding SPI configuration.

• the clock failure condition must be removed
• a read command of the quick status register #1 must be performed LIMP time iLIMP time tIN_DGL 200µs typ. tIN_DGL 200µs typ. INx time iINx time INx_ON time ttoggle tIN_DGL ttoggle 1024ms typ. tIN_DGL 200µs typ. tIN_DGL tIN_DGL tIN_DGL tIN_DGL

6.3.3.3 Electrical Characterization

6.3.4 External Smart Power Control (OUT6)

The device provides a control output to drive an external smart power device in Normal mode only. The control is according to the channel 6 settings in the SPI input data register.

• The protection and current feedback of the external SMARTMOS device are under the responsibility of the microcontroller.
• The output delivers a 5.0 V CMOS logic signal from VCC. The output is protected against overvoltage. The output has an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and Fail mode. In case of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of external smart power device and to limit possible reverse OUT6 current (i.e. resistor in series).

6.3.4.1 Electrical Characterization

Table 21. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

• WD SEL = 0
• WD SEL = 1 128 160 ms tTOGGLE Input Toggle Time for IN1… IN4 768 1024 1280 ms tDGL Input Deglitching Time
• LIMP and IN1… IN4
• C L K
• R S T \\ 150 1.5 7.5 200 2.0 250 2.5 12.5 µs fCLOCK LOW Clock Low Frequency Detection 50 100 200 Hz

Table 22. Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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7 Typical Applications

7.1 Introduction

The 07XS6517 is the latest achievement in automotive drivers for all types of centralized automotive lighting applications.

7.1.1 Application Diagram

Figure 36. Typical Automotive Front Lighting

7.1.2 Application Instructions

7.1.3 Bill of Material

Table 23. 07XS6517 Bill of Material (25)

1. Freescale does not assume liability, endorse, or warrant compon ents from external manufacturers that are referenced in circuit drawings

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7.2 EMC and EMI Considerations

7.2.1 EMC/EMI Tests

7.2.2 Fast Transient Pulse Tests

This paragraph gives the device performances.against fast transient disturbances. Table 24. 07XS6517 EMC/EMI Performances Table 25. 07XS6517 Fast Transient Capability on VBAT

7.3 Robustness Considerations

presented in Table 26. The tests are performed on 30 parts from three engineering lots (total 90 pieces). For either condition, contact our local Field Application Engineer (email: support@freescale.com). Table 26. 07XS6517 Repetitive Short-circuit Test Results at TA = 70 °C

1. The channel was loaded in the on-state with 100 mA.

Table 27. 07XS6517 AECQ100-12 Reliability Test Results at TA = 85 °C and Battery Voltage = 14 V

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7.4 PCB Layout Recommendations

Figure 37. PCB Copper Layer & Solder Stencil Opening Recommendations

7.5 Thermal Information

This section is to provide thermal information.

7.5.1 Thermal Transient

Figure 38. Transient Thermal Response Curve

7.5.2 R/C Thermal Model

Contact our local Field Application Engineer (email: support@freescale.com).

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8 Packaging

8.1 Marking Information

8.2 Package Mechanical Dimensions

www.freescale.com and perform a keyword search for the drawing’s document number. Table 28. Package Outline

Analog Integrated Circuit Device Data Freescale Semiconductor 69 MC07XS6517 Archive Information Archive Information

Analog Integrated Circuit Device Data

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Analog Integrated Circuit Device Data Freescale Semiconductor 71 MC07XS6517 Archive Information Archive Information

Analog Integrated Circuit Device Data

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9 Revision History

REVISION DATE DESCRIPTION OF CHANGES 1.0 6/2013 • Initial release 2.0 7/2013 • Changed operating voltage feature to “Operating voltage is 7.0 to 18 V with sleep current < 5.0 µA, extended mode from 6.0 to 28 V” 3.0 12/2014 • Migrating to MC12XS6D1 Data sheet

• Added Table 2 4.0 12/2017 • MC07XS6517BEK part removed from this data sheet and migrated to MC12XS6D1 data sheet

Document Number: MC07XS6517 Rev. 4.0 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP , the NXP logo, Freescale, the Freescale logo, and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP Semiconductors N.V. 2017 How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support Archive Information Archive Information