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ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet Rev. F | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

6/2019—Rev. E to Rev. F Changes to ADM3061E/ADM3062E/ADM3063E Section and Changes to ADM3065E/ADM3066E/ADM3067E/ADM3068E Added Endnote 1 to Digital Input and Output Voltage (DE, RE Changes to Digital Input and Output Voltage (DE, RE, DI, and 4/2019—Rev. D to Rev. E Changes to Figure 14, Figure 15, Figure 16, and Figure 18 Changes to Figure 19, Figure 20, Figure 23, and Figure 24 Changes to Tr ut h Tables S ec tion, Table 11, Table 12, and Changes to Isolated High Speed RS-485 Node Section and 3/2019—Rev. C to Rev. D 1/2018—Rev. B to Rev. C

Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Rev. F | Page 3 of 28 Changes to ADM3061E/ADM3062E Timing Specifications 12/2017—Rev. A to Rev. B Changes to Product Title, Features Section, Figure 1, and Table 1 ... 1 Added ADM3061E Timing Specification Section and Table 3; Changes to ADM3065E/ADM3066E Timing Specification Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter, Changes to Operating Temperature Range Parameter, Table 5 Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28 .. 14 Changed High Speed IEC ESD Protected RS-485 Section to IEC 5/2017—Rev. 0 to Rev. A 3/2017—Revision 0: Initial Version

narrow body standard small outline packages (SOIC_N). and −40°C to +85°C are available. output into a high impedance state. options. Refer to the Ordering Guide for model numbering. Table 1. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Operating

Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Rev. F | Page 5 of 28 SPECIFICATIONS VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWER SUPPLY No Load Supply Current ICC 3.5 7.5 mA DE = VIO1, RE = 0 V 3.5 7.5 mA DE = VIO, RE = VIO 3 4.5 mA DE = 0 V, RE = 0 V ADM3065E/ADM3066E/ADM3067E/ ADM3068E Supply Current, Data Rate = 50 Mbps ICC 107 172 mA Load resistance (RL) = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V) 67 75 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V) ADM3061E/ADM3062E/ADM3063E Supply Current, Data Rate = 500 kbps ICC 100 165 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V) 56 74 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V) Supply Current in Shutdown Mode ISHDN 210 450 µA DE = 0 V, RE = VIO VIO Shutdown Current2 IIOSHDN 1 50 µA DE = 0 V, RE = VIO DRIVER Differential Outputs Output Voltage, Loaded |VOD2| 2.0 2.5 VCC V VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38 |VOD2| 1.5 2.1 VCC V VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38 |VOD2| 2.1 3.5 VCC V VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38 |VOD2| 2.1 3 VCC V VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38 |VOD3| 1.5 2.1 VCC V VCC ≥ 3.0 V, −7 V ≤ common-mode voltage (VCM) ≤ +12 V, see Figure 39 |VOD3| 2.1 3 VCC V VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39 Change in Differential Input Voltage for Complementary Output States ∆|VOD| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38 Common-Mode Output Voltage VOC 1.6 3.0 V RL = 27 Ω or 50 Ω, see Figure 38 Change in Common Mode Voltage for Complementary Output States ∆|VOC| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38 Output Short-Circuit Current IOS −250 +250 mA −7 V < output voltage (VOUT) < +12 V ADM3063E/ADM3067E Output Leakage (Y, Z) IO +100 µA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, input voltage (VIN) = 12 V −100 µA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V Logic Inputs (DE, RE, DI) Input Voltage Low VIL 0.33 × VIO V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V High VIH 0.67 × VIO V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V Input Current II −2 +2 µA DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO

ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet Rev. F | Page 6 of 28 Parameter Symbol Min Typ Max Unit Test Conditions/Comments RECEIVER Differential Inputs Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VCM < +12 V Input Voltage Hysteresis VHYS 30 mV −7 V < VCM < +12 V Input Current (A, B) II 0.1 0.25 mA DE = 0 V, VCC = powered/unpowered, VIN = 12 V −0.20 −0.1 mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V Line Input Resistance RIN 48 96 kΩ −7 V ≤ VCM ≤ +12 V Logic Outputs Output Voltage Low VOL 0.4 V VIO = 3.6 V, output current (IOUT) = 2 mA, VID3 ≤ −0.2 V 0.4 V VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2 0.2 V VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V2 High VOH 2.4 V VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V 2.0 V VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2 VIO − 0.2 V VIO = 1.65 V, IOUT = −500 µA, VID ≥ −0.03 V2 Short-Circuit Current 85 mA VOUT = GND or VIO Three-State Output Leakage IOZR ±2 µA RO pin = 0 V or VIO 1 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E. 2 ADM3062E/ADM3066E/ADM3068E only. 3 VID is the receiver input differential voltage.

1. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E.

Figure 8. Receiver Enable and Disable Timing Diagram

10 Positive and 10 Negative

1 VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E. PCB thermal design is required. resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with no bias. See JEDEC JESD-51.

10 VCC

1. NIC = NO INTERNAL CONNECTION. THIS

PIN IS NOT INTERNALLY CONNECTED.

1. EXPOSED PAD. THE EXPOSED PAD

MUST BE CONNECTED TO GROUND. Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration

1. NIC = NO INTERNAL CONNECTION. THIS

PIN IS NOT INTERNALLY CONNECTED. Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration Table 8. ADM3066E/ADM3062E Pin Function Descriptions tristated when the receiver is disabled; that is, when RE is driven high. output into a high impedance state. 5 DI Transmit Data Input. Data to be transmit ted by the driver is applied to this input. 7 NIC No Internal Connection. This pin is not internally connected. put into a high impedance state to avoid overloading the bus. into a high impedance state to avoid overloading the bus. EPAD Exposed Pad. The exposed pa d must be connected to ground.

PIN IS NOT INTERNALLY CONNECTED. Figure 13. ADM3063E/ADM3067E 14-Lead SOIC Pin Configuration Table 9. ADM3063E/ADM3067E Pin Function Descriptions 1, 8 NIC No Internal Connection. This pin is not internally connected. tristated when the receiver is disabled; that is, when RE is driven high. output into a high impedance state. 5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input. impedance state to avoid overloading the bus. impedance state to avoid overloading the bus. 11 B Inverting Receiver Input. 12 A Noninverting Receiver Input.

PIN IS NOT INTERNALLY CONNECTED. Figure 14. ADM3068E 14-Lead SOIC Pin Configuration Table 10. ADM3068E Pin Function Descriptions tristated when the receiver is disabled; that is, when RE is driven high. output into a high impedance state. 5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input. 7, 13 NIC No Internal Connection. This pin is not internally connected. impedance state to avoid overloading the bus. impedance state to avoid overloading the bus. 11 B Inverting Receiver Input. 12 A Noninverting Receiver Input.

Figure 15. Shutdown Current (ISHDN) vs. Temperature Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, Figure 18. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance,

50 Mbps Models

Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance, Figure 20. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and

Table 12 and Table 13 use the abbreviations shown in Table 11. Table 11. Truth Table Abbreviations Table 12. Transmitting Truth Table

1 For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is

Table 13. Receiving Truth Table −30 m V, the RO pin is logic high. the hot swap tolerable input.

128 TRANSCEIVERS ON THE BUS

are reenabled at a temperature of 140°C.

keep stub lengths off the main line as short as possible.

1. THE MAXIMUM NUMBER OF NODES IS 128.
2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.

Figure 47. ADM3061E/ADM3065E Typical Half-Duplex RS-485 Communications Network

using Analog Devices, Inc., iCoupler® and isoPower® technology. remains within the load capability of ADuM6401 even at 25 Mbps. switching elements to transfer power through the transformers.

50 Mbps, can be implemented using the ADuM241D quad-

Figure 48. Signal and Power Isolated 25 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown) Figure 49. Signal and Power Isolated 50 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]

0.65 BSC

1.10 MAX

Figure 51. 8-Lead Mini Small Outline Package [MSOP]

0.50 BSC

Figure 52. 10-Lead Mini Small Outline Package [MSOP]

0.20 REF

0.05 MAX

0.02 NOM

0.20 MIN

Figure 53. 10-Lead Lead Frame Chip Scale Package [LFCSP]

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 54. 14-Lead Standard Small Outline Package [SOIC_N]

ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet Rev. F | Page 28 of 28 Model1 Temperature Range Package Description Package Option Marking Code ADM3066EACPZ −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MC9 ADM3066EACPZ-R7 −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MC9 ADM3066EBCPZ −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCA ADM3066EBCPZ-R7 −40°C to +125°C 10-Lead Lead Fr ame Chip Scale Package [LFCSP] CP-10-9 MCA ADM3066EARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC4 ADM3066EARMZ-R7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC4 ADM3066EBRMZ −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC5 ADM3066EBRMZ-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC5 ADM3067EARZ −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3067EARZ-R7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3067EBRZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3067EBRZ-R7 −40°C to +125°C 14-Lead Stan dard Small Outline Package [SOIC_N] R-14 ADM3068EARZ −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3068EARZ-R7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3068EBRZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADM3068EBRZ-R7 −40°C to +125°C 14-Lead Stan dard Small Outline Package [SOIC_N] R-14 EVAL-ADM3061EEBZ 8-Lead SOIC_N Evaluation Board EVAL-ADM3061EEB1Z 8-Lead MSOP Evaluation Board EVAL-ADM3062EEBZ 10-Lead MSOP Evaluation Board EVAL-ADM3062EEB1Z 10-Lead LFCSP Evaluation Board EVAL-ADM3063EEBZ 14-Lead SOIC_N Evaluation Board EVAL-ADM3065EEBZ 8-Lead SOIC_N Evaluation Board EVAL-ADM3065EEB1Z 8-Lead MSOP Evaluation Board EVAL-ADM3066EEBZ 10-Lead MSOP Evaluation Board EVAL-ADM3066EEB1Z 10-Lead LFCSP Evaluation Board EVAL-ADM3067EEBZ 14-Lead SOIC_N Evaluation Board EVAL-ADM3068EEBZ 14-Lead SOIC_N Evaluation Board 1 Z = RoHS Compliant Part. ©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D14666-0-6/19(F)