MBM30LV0032 FUJITSU | Alldatasheet

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DS05-20884-2EFUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 32M (4M · 8) BIT NAND-type MBM30LV0032 nnnn DESCRIPTION The MBM30LV0032 device is a single 3.3 V 4M · 8 bit NAND flash memory organized as 528 byte · 16 pages

  • 512 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code(Specifications indicated are on condition that ECC system would be combined.). Program and read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page can be programmed in 200 ms and an 8K byte block can be erased in 2 ms under typical conditions. An internal controller automates all program and erase operations including the verification of data margins. Data within a page can be read with a 50 ns cycle time per byte. The I/O pins are utilized for both address and data input/output as well as command inputs. The MBM30LV0032 is an ideal solution for applications requiring mass non-volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage. nnnn PRODUCT LINE UP nnnn PACKAGES Part No. MBM30LV0032 Operating Temperature –40°C to +85°C V CC +2.7 V to +3.6 V Power Dissipation (Max.) Read 72 mW Erase / Program 72 mW TTL Standby 3.6 mW CMOS Standby 0.18 mW Marking Side Marking Side (FPT -44P-M07) (Normal Bend) (FPT -44P-M08) (Reverse Bend) 44-pin plastic TSOP (II)
  • 3.3 V-only operating voltage (2.7 V to 3.6 V) Minimizes system level power requirements
  • Organization Memory Cell Array : (4M + 128K) ·8 bit Data Register : (512 + 16) ·8 bit
  • Automatic Program and Erase Page Program : (512 + 16) Byte Block Erase : (8K + 256) Byte
  • 528 Byte Page Read Operation Random Access : 7 ms (Max.) Serial Access : 35 ns (Max.)
  • Fast Program and Erase Program Time : 200 ms (T yp.) / page Block Erase Time : 2 ms (T yp.) / block
  • Command/Address/Data Multiplexed I/O Port
  • Hardware Data Protection
  • 1,000,000 write/erase cycle guaranteed (ECC system required)
  • Command Register Operation
  • Package 44(40)-pin TSOP T ype II (0.8 mm pitch) Normal/Reverse T ype
  • Data Retention: 10 years

N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq Vss CLE ALE WE WP N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss FPT-44P-M07 TOP VIEW FPT-44P-M08 TOP VIEW Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq N.C. N.C.

Pin Number Pin Name Descriptions 18 to 21 24 to 27 I/O0 to I/O7 Data Input/Output The I/O ports are used for transferring command, address, and input/output data into and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected. 2C L E Command Latch Enable The CLE signal enables the acquisition of the made command into the internal com- mand register. When CLE=“H”, command are latched into the command register from the I/O port upon the rising edge of the WE signal. 3A L E Address Latch Enable The ALE signal enables the acquisition of either address or data into the internal ad- dress/data register. The rising edge of WE latch in addresses when ALE is high and data when ALE is low. 43 CE Chip Enable The CE signal is used to select the device. When CE is high, the device enters a low power standby mode. If CE transitions high during a read operation, the standby mode will be entered. However, the CE signal is ignored if the device is in a busy state(R/B=L) during a program or erase operation. 42 RE Read Enable The RE signal controls the serial data output. The falling edge of RE drives the data onto the I/O bus and increments the column address counter by one. 4W E Write Enable The WE signal controls writes from the I/O port. Data, address, and commands on the I/O port are latched upon the rising of the WE pulse. 5W P Write Protect The WP signal protects the device against accidental erasure or programming dur- ing power up/down by disabling the internal high voltage generators. WP should be kept low when the device powers up until VCC is above 2.5 V. During power down, WP should be low when VCC falls below 2.5 V. 40 SE Spare Area Enable The SE input enables the spare area during sequential data input, page program, and Read 1.

41 R/B

The R/B output signal is used to indicate the operating status of the device. During program, erase, or read, R/B is low and will return high upon the completion of the operation. The output buffer for this signal is an open drain.

23 V CC q

Output Buffer Power Supply The VCCq input supplies the power to the I/O interface logic. This power line is elec- trically isolated from V CC for the purpose of supporting 5V tolerant I/O.

44 V CC Power Supply

1,22 V SS Ground 6 to 17 28 to 39 N.C. No Connection

I/O Register & Buffer Command Register Status Register Y-Decoder Y-Decoder Memory Array Data Register & S/A Data Register & S/A Address Register

nnnn SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT The Program operation is implemented in page units while the Erase operation is carried out in block units. A0 to A7 : column address A9 to A21 : page address (A8 is automatically set to “Low” or “High” by the “00h” command or the “01h” command in device inside.) * : X = VIH or VIL Table 1 Addressing I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 First Cycle A 0 A1 A2 A3 A4 A5 A6 A7 Second Cycle A 9 A10 A11 A12 A13 A14 A15 A16 Third Cycle A 17 A18 A19 A20 A21 X* X* X* 16512 I/O0 I/O7 16 pages fi 1 block

8 I/O

(512 blocks) Memory Cell Array Register 1) A page consists of (512+16) bytes; - 512 bytes for main memory - 16 bytes for redundancy or other use 2) A block consists of 16 pages; (8K+256) bytes. 3) Total device density = Read and Program operation are executed through Register Register = 1 page size 528 bytes · 16 pages · 512 blocks. Figure 1 Schematic Cell Layout A13 to A21 : block address A9 to A12 : Page address in block

nnnn DEVICE BUS OPERATIONS *1: H: VIH, L: VIL, X: VIH or VIL *2: WP should be biased to CMOS high or CMOS low for standby. *3: When SE is high, spare area is deselected. *4: If 50h command is input and read/program operation is executed only for spare area, SE must be low at the command/address input. *: H: VIH, L: VIL, X: VIH or VIL Table 2 Operation Table *1 Mode CLE ALE CE WE RE SE WP Read Mode Command Input H L L H X *4 X Address Input (3 clock) L H L H X *4 X During Read (Busy) L L L H H L/H *3 X Sequential Read & Data Output L L L H L/H *3 X Program/ Erase Mode Command Input H L L H X *4 H Address Input (2 or 3 clock) L H L H X *4 H Data Input L L L H L/H *3 H D u r i n g P r o g r a m ( B u s y ) XXXXX L/H *3 H D u r i n g E r a s e ( B u s y ) XXXXXXH W r i t e P r o t e c t XXXXXX L Stand-by X X H X X 0 V/VCC *2 0 V/VCC *2 Table 3 Read Mode Operation Status * Operation CLE ALE CE WE RE I/O0 to I/O7 Power Output Select L L L H L Data Output Active Output Deselect L L L H H High Impedance Active Standby X X H X X High Impedance Standby

*1: The 00h Command defines starting Address on the 1st half Page. *2: The 01h Command defines starting Address on the 2nd half Page. *3: The 50h Command is valid only When SE is low level. Table 4 Command Table Function 1st Cycle 2nd Cycle Acceptable Command During Busy State Read (1) 00h *1 — Read (2) 01h *2 — Read (3) 50h *3 — Sequential Data Input 80h — Page Program 10h — Block Erase 60h D0h Reset FFh — Status Read 70h — ID Read 90h —

nnnn FUNCTIONAL DESCRIPTION READ MODE There are three distinct commands used for the read operation: 00h, 01h, and 50h. After the command cycle, three address cycles are used to input the starting address. Upon the rising edge of the final WE pulse, there is a 7 ms latency in which the 528 byte page is transferred to the data register. The R/B signal may be used to monitor the completion of the data transfer. In the read operation, the CE signal must stay “Low” after the third address input and during Busy state. If the CE signal goes High during this period, the read operation will be terminated and then the standby mode will be entered. Once the page of data has been loaded into the data register, it may be clocked out with consecutive 50 ns RE pulses. Each RE pulse will automatically advance the column address by one. Once the last column has been read, the page address will automatically increment by one and the data register will be updated with the new page after 7 ms. The 00h Read command will set the pointer to the first half page of the array while the 01h Read command will set it in the second half. It may be logical to think of 00h as a command which sets A 8 = 0 while 01h sets A8 = 1. The 50h command set the pointer to the spare area, consisting of columns 512 to 527. During this read mode, A 3 to A0 is used to set the starting address of the spare area. As with the 00h and 01h operations, once the spare area page is loaded into the data register, it may be read out by RE pulses. Each RE pulse will increment the column address until the final column (527) is reached. At this time, the pointer will be reset to column 512 while the page address is incriminated and the data register is updated. The 00h or 01h command is required to move the pointer back into the main array area. Read (1), (2): 00h/01h The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode (00h) will be automatically selected when the device powers up. CLE CE WE ALE RE I/O0 to I/O7 Y X X R/B 00h Data OutputStarting Address Command 01h 0 255 511 527 (Column Address) Page (Row) Address X YY Figure 2 Read Mode (1), (2) Operation

Read ID: 90h This mode allows the identification of the manufacturer and product. After the 90h command cycle, one address cycle follows in which 00h is entered. The next two RE pulses will output the manufacturer and device code respectively. Status Read: 70h The Status Register may be used to determine if the device is ready, in the write protect mode, or passed program/erase operations. After the 70h command is entered, the more recent falling edge of either CE or RE will output the contents of the status register to I/O0 to 7. The status register is continually updated and does not require either CE or RE to be toggled. By utilizing the CE pin, multiple devices with R/B pins wired together may be polled to determine their specific status. Table 5 Code Table I/O7 I/O 6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Code M a n u f a c t u r e r 00000100 0 4 h D e v i c e 11100011E 3 h Table 6 Status Output Table Status Description I/O0 Program/Erase 0 = Pass; 1 = Fail I/O1 Not Used I/O2 Not Used I/O3 Not Used I/O4 Not Used I/O5 Not Used I/O6 Ready/Busy 0 = Busy; 1 = Ready I/O7 Write Protect 0 = Protected; 1 = Unprotected E3h04h90h 00h RE I/O0 to I/O7 Manufacturer Code Device Code Figure 7 Read ID Operation

When the device is busy during program, erase, or read, it can be reset by entering the command FFh. If WP = 1, the Status Register will be set to C0h. If a reset command is issued while the device is in the reset state, the command will be ignored. If the device is reset during the program or erase operations, the internal high voltages will be discharged before R/B goes high. Device(1) CE(1) Device(2) CE(2) Device(N) CE(N) 0/1 0/1 ALE CLE WE RE I/O0 to I/O7 R/B R/B ALE CLE WE CE(1) CE(N) RE I/O0 to I/O7 Status of Device(1) Status of Device(N) 70h 70h Figure 8 Status Read FFh R/B I/O0 to I/O7

nnnn ABSOLUTE MAXIMUM RATINGS *: Minimum DC voltage on input or I/O pins is -0.5V . During voltage transitions, inputs may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input pins is VCC + 0.5 V and on I/O pins are VCC q + 0.5 V . During voltage transitions,input pins may overshoot to VCC + 2.0 V for periods of up to 20ns and I/O pins may overshoot to VCC q + 2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS *: VCC q = 5.0 V – 10% can be guaranteed on VCC ‡ 3.0 V . Note: Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min. Max. Ambient Temperature with Power Applied T A –40 +85 °C Storage Temperature Tstg –55 +125 °C Voltage on a I/O pin with respect to Ground * VI/O –0.6 V CC q +0.5 V Voltage on a pin except I/O with respect to Ground * VIN –0.6 V CC +0.5 V Power Supply Voltage VCC –0.6 +5.5 V VCC q –0.6 +6.0 Parameter Symbol Value Unit Min. Max. Supply Voltages V CC +2.7 +3.6 V Supply Voltages V CC q * +2.7 +5.5 V Voltages V SS 0 V Ambient Temperature T A –40 +85 °C

nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Conditions Value Unit Min. Typ. Max. Sequential Read Current I CC1 tCYCLE = 50 ns, CE = VIL, IOUT = 0 mA —1 02 0 m A Command Address Input Current I CC3 tCYCLE = 50 ns, CE = VIL —1 02 0 m A Data Input Current I CC4 — — 10 20 mA Program Current I CC6 — — 10 20 mA Erase Current I CC7 — — 10 20 mA Stand-by Current (TTL) I SB1 CE = VIH, WP = SE = 0 V/VCC —— 1 m A Stand-by Current (CMOS) I SB2 CE = VCC –0.2 V , WP = SE = 0 V/ VCC —1 05 0 µ A Input Leakage Current I LI VIN = 0 to 3.6 V — — ±10 µA Output Leakage Current I LO VOUT = 0 to 3.6 V — — ±10 µA Input High Voltage V IH I/O pins 2.0 — V CC q +0.3 V Except I/O pins 2.0 — V CC +0.3 V Input Low Voltage V IL — –0.3 — 0.8 V Output High Voltage Level V OH IOH = –400 mA2 . 4 — — V Output Low Voltage Level V OL IOL = 2.1 mA — — 0.4 V Output Low Current (R/B)I OL VOL = 0.4 V 8 10 — mA

  1. AC Characteristics (Note 1) (Continued) Parameter Symbol Value Unit Min. Max. CLE Setup Time t CLS 0— n s CLE Hold Time t CLH 10 — ns CE Setup Time t CS 0— n s CE Hold Time t CH 10 — ns Write Pulse Width t WP 25 — ns ALE Setup Time t ALS 0— n s ALE Hold Time t ALH 10 — ns Data Setup Time t DS 20 — ns Data Hold Time t DH 10 — ns Write Cycle Time t WC 50 — ns WE High Hold Time t WH 15 — ns WP High to WE Low t WW 100 — ns Ready to RE Falling Edge t RR 20 — ns Read Pulse Width t RP 30 — ns Read Cycle Time t RC 50 — ns RE Access Time (Serial Data Access) t REA —3 5n s CE High Time for the Last Address in Serial Read Cycle (Note 3) tCEH 100 — ns RE Access Time (ID Read) t REAID —3 5n s RE High to Output High Impedance t RHZ 15 30 ns CE High to Output High Impedance t CHZ —2 0n s RE High Hold Time t REH 15 — ns Output High Impedance to RE Falling Edge t IR 0— n s RE Access Time (Status Read) t RSTO —3 5n s CE Access Time (Status Read) t CSTO —4 5n s WE High to RE Low t WHR 60 — ns ALE Low to RE Low (ID Read) t AR1 100 — ns CE Low to RE Low (ID Read) t CR 100 — ns Data T ransfer from Memory Cell Array to Register t R —7 ms WE High to Busy t WB — 100 ns

(Continued) Notes: 1. AC T est Conditions: 2. The time to go from CE high to Ready depends on the pull-up resister of the R/B pin (see Application Notes (6)) toward the end of this document. 3. In case that toggling CE to high after access to the last address (address 527) in the resister in the read mode (1), (2), and (3), the CE high time must be held for 100 ns or more when the delay time of CE with respect to RE is 0 to 200 ns (see the figure below). When the CE delay time is within 30 ns, the device is kept in the Ready state and will output no Busy signal. Parameter Symbol Value Unit Min. Max. ALE Low to RE Low (Read Cycle) t AR2 50 — ns RE Last Clock Rising Edge to Busy (in Sequential Read) t RB —1 0 0n s CE High to Ready (in Case of Interception by CE in Read Mode) (Note 2) tCRY — 50 + tr (R/B) ns Device Resetting Time (Read/Program/Erase) t RST — 5/10/500 ms Operating range V CC = 2.7 to 3.6 V VCC = 3.0 to 3.6 V Input level 2.4 V/0.4 V Input comparison level 1.5 V/1.5 V Output data comparison level 1.5 V/1.5 V Output load 1TTL Load capacitance (C L) 50 pF 100 pF T ransition time (tT)5 n s tCEH ‡ 100 ns *VIH or VIL A 527 511 526 510 525 509 Busy A : 0 to 30 ns fi Busy signal is not output. CE RE R/B

nnnn ERASE AND PROGRAMMING PERFORMANCE *1: Refer to Application Note (10) toward the end of this document. *2: Refer to Application Note (13) toward the end of this document. This specification is on conditions that ECC system would be combined. nnnn VALID BLOCKS The MBM30LV0032 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this document. nnnn PIN CAPACITANCE Notes: 1. T est conditions TA = 25 °C, f = 1.0 MHz 2. Sampled, not 100% tested. Parameter Symbol Value Unit Remarks Min. Typ. Max. Average Programming Time t PROG — 200 1000 ms Number of Programming Cycles on Same Page N — — 10 *1 Block Erasing Time t BERASE —21 0 m s Number of Program/Erase Cycles P/E 1 · 106 —— * 2 Parameter Symbol Value Unit Min. Typ. Max. Valid Block Number N VB 502 ¾ 512 Block Parameter Symbol Condition Value Unit Typ. Max. Input Capacitance C IN VIN = 0 — 10 pF Output Capacitance C OUT VOUT = 0 — 10 pF

Figure 11 Data Input Cycle Timing Diagram D INN D INN+1 CLE CE WE I/O0 to I/O7 ALE tCLH tCH tALS tWC tWP tWH tWP tWP tDS tDH tDS tDH D IN * tDS tDH * : SE = GND input : to DIN 527 = VCC input : to DIN 511 : VIH or VIL

tR tR Page M Access Page M + 1 Access 512 513 514 : VIH or VIL 512 N 512 N + 1 512 N + 2 Column Address N Page Address M = Do not input VCC **: SE = GND input : DOUT 527 A9 to A16 A17 to A21 Figure 20 Sequential Read Cycle (3) Timing Diagram Note: The CE signal must stay “Low” after the third address input and during Busy state.

Address Input Maker Code Device Code tCH : VIH or VIL Figure 23 ID Read Operation Timing Diagram

nnnn APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The operation commands are listed in T able 4. Data input as a command other than the specified commands in T able 4 is prohibited. Stored data may be corrupted if an unspecified command is entered during the command cycle. (2) Pointer Action for Program Operation The pointer action can be done for program operation as follows. Start Only 50h area Program? Start address is in 00h area? Input 01h Command Input 00h Command *2 Program Sequence Continue to Program? The pointer is 01h? Start address area (00h,01h,50h) is the same as the previous? Program Sequence Start address area is changed from 01h to 00h? Set 01h command Input read command *3 Continue to Program? End Input 50h Command *1 Yes No Yes No No Yes Yes No No Yes Yes No Yes No *1: If read operation was done setting start address in 50h area in previous use, the 50h command input can be skipped. *2: If read operation was done at 00h or (and) 01h area in previous use, the 00h command input can be skipped. *3: The read command means 00h, 01h or 50h. 0 255 511 527 00h 01h 50h Figure 24 Pointer Action Flow Chart

(8) Setup for WP Signal A Low-level WP signal will force erasing and programming to be reset. T o control, use the WP signal as shown below. WE DIN WP R/B 80 10 tWW Program 100 ns (Min.) WE DIN WP R/B 80 10 tWW Program Prohibition 100 ns (Min.) WE DIN WP R/B 60 D0 tWW Erase 100 ns (Min.) WE DIN WP R/B 60 D0 tWW Erase Prohibition 100 ns (Min.)

(14) ALE Input Condition during Address Input The ALE input must remain high once asserted until the last address byte has been written to the device. CLE CE WE ALE I/O0 to I/O7 00h, 01h or 50h Address Input Keep H Inhibit L Input Read Operation CLE CE WE ALE I/O0 to I/O7 80h Address Input Keep H Inhibit L Input Program Operation CLE CE WE ALE I/O0 to I/O7 60h Address Input Keep H Inhibit L Input D0h Erase Operation

(15) Inhibit RE Toggling during Busy State The RE input cannot be allowed to toggle during the period that a read data transfer operation is in process (busy state). If the RE input toggles during that period, the internal column address will increment. (16) Restriction on Toggling the WE The WE input cannot be allowed to toggle past the end of page (byte 511 with SE high or byte 527 with SE low) during an input data operation. If the WE input toggles past the end of page, the internal address counter will wrap around to the begging of the page and overwrite the information previously there. (17) Reading Past Last Device Page When the last byte in the last page of the device is read, the internal address counter will wrap around to the fist page in the device. CLE CE WE ALE RE I/O0 to I/O7 R/B Starting Address Y Toggling X times (fi Inhibiting) Start from column address Y + X 80h 10h 70h CLE CE WE ALE R/B RE D IN *D IN Output Status I/O0 to I/O7 *: DIN for address 511 with SE = "H" or 527 with SE = "L" Inhibit toggling : VIH or VIL : Invalid Data

(18) CE don’t care timing for read and program operation CE can be don’t-care (“H” or “L”) state during read and program operation as follows. A17 toA21 10h80h D IN 2D IN 1D IN

0 D IN

(55 ns Max.) <Read Operation> <Program Operation> : VIH or VIL A0 to A9 to A16 A17 to A21 D OUT N D OUT N+1 D OUT N+2 D OUT Note: In the read operation, the CE signal must stay “Low” after the third address input and during Busy state. If the CE signal goes High during this period, the read operation will be terminated and then the standby mode will be entered.

Figure 36 Bad Block Test Flow Test Start Page 1 & 2 Blank Check Block No. = 0 Test End Set as a bad block Yes No Yes No B No. Block No. = Block No. + 1 /K93All FFh?/K94 = 511>

Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM30LV0032 -PFTN DEVICE NUMBER/DESCRIPTION MBM30LV0032

32 Mega-bit (4M · 8-Bit) CMOS Flash Memory

2.7 V to 3.6 V Read, Write, and Erase P ACKAGE TYPE PFTN = 44-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 44-Pin Thin Small Outline Package (TSOP) Reverse Pinout Valid Combinations MBM30LV0032 -PFTN -PFTR Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

(Continued) C 2000 FUJITSU LIMITED F44016S-1C-3 Details of "A" part 0.30±0.10 (.012±.004) 18.41±0.10 (.725±.004) M0.13(.005) 0.80(.0315)TYP 16.80(.661)REF 0(0)MIN (STAND OFF) .043–.002 +.004 –0.05 +0.10 1.10 10.16±0.10 (.400±.004) 11.76±0.20 (.463±.008) 0.50±0.10 (.020±.004) 10.76±0.20 (.424±.008) 0.15±0.05 (.006±.002) 101 "A" INDEX LEAD No. 0.15(.006)MAX 0.40(.016)MAX 0.15(.006) 0.25(.010) 13 22 233244 35 (Mounting height) 0.10(.004) 44-pin plastic TSOP (II) (FPT-44P-M07) *: Resin protrusion. (Each side: 0.15(.006) Max) Dimensions in mm (inches)

(Continued) C 2000 FUJITSU LIMITED F44017S-1C -3 Details of "A" part 0.30±0.10 (.012±.004) 18.41±0.10 (.725±.004) M0.13(.005) 0.80(.0315)TYP 16.80(.661)REF 0(0)MIN (STAND OFF) .043–.002 +.004 –0.05 +0.10 1.10 10.16±0.10 (.400±.004) 11.76±0.20 (.463±.008) 0.50±0.10 (.020±.004) 10.76±0.20 (.424±.008) 0.15±0.05 (.006±.002) 101 "A" INDEX LEAD No. 0.15(.006)MAX 0.40(.016)MAX 0.15(.006) 0.25(.010) 13 22 233244 35 (Mounting height) 0.10(.004) Dimensions in mm (inches) 44-pin plastic TSOP (II) (FPT-44P-M08) *: Resin protrusion. (Each side: 0.15(.006) Max)

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