MBM29DL321BE80PBT

MBM29DL32XTE FUJITSU | Alldatasheet

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DS05-20881-3EFUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 32M (4M · 8/2M · 16) BIT Dual Operation MBM29DL32XTE/BE -80/90/12 nnnn DESCRIPTION The MBM29DL32XTE/BE are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (Continued) nnnn PRODUCT LINE UP nnnn PACKAGES Part No. MBM29DL32XTE/BE Ordering Part No. VCC = 3.3 V+0.3 V –0.3 V 80 — — VCC = 3.0 V+0.6 V –0.3 V —9 01 2 Max. Address Access Time (ns) 80 90 120 Max. CE Access Time (ns) 80 90 120 Max. OE Access Time (ns) 30 35 50 48-pin plastic TSOP (I) (FPT-48P-M19) 48-pin plastic TSOP (I) (FPT-48P-M20) 63-ball plastic FBGA (BGA-63P-M01) Marking Side Marking Side

(Continued) In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb. T o eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. T ypically, each sector can be programmed and verified in about 0.5 seconds. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the factory. Internally generated and regulated voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the T oggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

• 0 . 2 3 mm Process Technology
• Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to T able 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program
• Single 3.0 V read, program, and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E 2PROMs
• Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: TN – Normal Bend T ype, TR – Reversed Bend T ype) 63-ball FBGA (Package suffix: PBT
• Minimum 100,000 program/erase cycles
• High performance 80 ns maximum access time
• Sector erase architecture Eight 4K word and sixty-three 32K word sectors in word mode Eight 8K byte and sixty-three 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture T = T op sector B = Bottom sector
• Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)
• W P /ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC , increases program performance
• Embedded EraseTM *Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded Program TM Algorithms Automatically writes and verifies data at specified address
• D a t a Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
• L o w VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection T emporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common F lash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

Table 1 MBM29DL32XTE/BE Device Bank Divisions Device Part Number Organization Bank 1 Bank 2 Megabits Sector sizes Megabits Sector sizes MBM29DL321TE/BE

• 8/· 16 0.5 Mbit Eight 8K byte/4K word 31.5 Mbit Sixty-three 64K byte/32K word MBM29DL322TE/BE 4 Mbit Eight 8K byte/4K word, seven 64K byte/32K word28 Mbit Fifty-six 64K byte/32K word MBM29DL323TE/BE 8 Mbit Eight 8K byte/4K word, fifteen 64K byte/32K word24 Mbit Forty-eight 64K byte/32K word MBM29DL324TE/BE 16 Mbit Eight 8K byte/4K word, thirty-one 64K byte/ 32K word

16 Mbit Thirty-two

(Continued) A15 A14 A13 A12 A11 A10 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 Standard Pinout Reverse Pinout TSOP(I) A16 BYTE VSS DQ 15/A-1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 VCC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE V SS CE A CE V SS OE DQ DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 VCC DQ 4 DQ 12 DQ 5 DQ 13 DQ 6 DQ 14 DQ 7 DQ 15/A-1 VSS BYTE A A17 A18 RY/BY WP/ACC N.C. RESET WE A20 A19 A10 A11 A12 A13 A14 A15 (Marking Side) (Marking Side) FPT-48P-M19 FPT-48P-M20

(Continued) A14 A10 N.C. A18 A16 DQ 2 DQ 0 BYTE DQ 14 DQ 12 DQ 10 DQ 8 CE A15 A11 DQ 15/A-1 DQ 13 Vcc DQ 11 DQ 9 OE Vss DQ 6 DQ 4 DQ 3 DQ 1 Vss N.C. N.C. N.C. N.C. A12 RESET WP/ACC A17 N.C. N.C. N.C. N.C. A13 WE RY/BY N.C. N.C. N.C. N.C. N.C. N.C. N.C. A19 DQ 5 A20 DQ 7 * * * * * * * * * * FBGA (TOP VIEW) Marking side *: Peripheral Balls on each corner are shorted together via substrate but not connected to the die. —— C 2 A 3 C3 A 7 C4 RY/BY C5 WE C6 A 9 C7 A 13 —— —— D 2 A 4 D3 A 17 D4 WP /ACC D5 RESET D6 A 8 D7 A 12 —— ——E 2A 2 E3 A 6 E4 A 18 E5 N.C. E6 A 10 E7 A 14 —— ——F 2A 1 F3 A 5 F4 A 20 F5 A 19 F6 A 11 F7 A 15 —— —— G 2 A 0 G3 DQ 0 G4 DQ 2 G5 DQ 5 G6 DQ 7 G7 A 16 —— —— H 2 C E H3 DQ 8 H4 DQ 10 H5 DQ 12 H6 DQ 14 H7 BYTE —— ——J 2 O E J3 DQ 9 J4 DQ 11 J5 V CC J6 DQ 13 J7 DQ 15/A-1 —— ——K 2 V SS K3 DQ 1 K4 DQ 3 K5 DQ 4 K6 DQ 6 K7 V SS —— (BGA-63P-M01)

(A-1) OE BYTE WP/ACC RESET DQ 0 to DQ 15 RY/BY State Control Command Register X-Decoder X-Decoder Cell Matrix (Bank 2) Cell Matrix (Bank 1) Y-Gating & Data LatchY-Gating & Data Latch DQ 0 to DQ 15 Status Control

Table 2 MBM29DL32XTE/BE Pin Configuration Pin Function A-1, A0 to A20 Address Inputs DQ 0 to DQ15 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/T emporary Sector Group Unprotection BYTE Selects 8-bit or 16-bit mode WP /ACC Hardware Write Protection/Program Acceleration N.C. No Internal Connection VSS Device Ground VCC Device Power Supply A0 to A20 WE OE CE DQ 0 to DQ 15 16 or 8 BYTE WP/ACC RESET A-1 RY/BY

Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See T able 5. 2. Refer to the section on Sector Group Protection. 3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. VCC = 3.3 V ± 10% 5. It is also used for the extended sector group protection. Table 3 MBM29DL32XTE/BE User Bus Operations (BYTE = VIH) Operation CE OE WE A 0 A 1 A 6 A 9 DQ 0 to DQ15 RESET WP /ACC Auto-Select Manufacturer Code (1) L L H L L L V ID Code H X Auto-Select Device Code (1) L L H H L L V ID Code H X Read (3) L L H A 0 A1 A6 A9 D OUT HX S t a n d b y HXXXXXX H I G H - Z H X Output Disable L H H X X X X HIGH-Z H X Write (Program/Erase) L H L A

0 A1 A6 A9 D IN HX

Enable Sector Group Protection (2), (4) L VID LHL V ID XH X Verify Sector Group Protection (2), (4) L L H L H L V ID Code H X T emporary Sector Group Unprotection (5)XXXXXXX X V ID X R e s e t ( H a r d w a r e ) / S t a n d b y XXXXXXX H I G H - Z L X B o o t B l o c k S e c t o r W r i t e P r o t e c t i o n XXXXXXX X X L Table 4 MBM29DL32XTE/BE User Bus Operations (BYTE = VIL) Operation CE OE WE DQ 15/ A-1 A 0 A 1 A 6 A 9 DQ 0 to DQ7 RESET WP /ACC Auto-Select Manufacturer Code (1) L L H L L L L V ID Code H X Auto-Select Device code (1) L L H L H L L V ID Code H X Read (3) L L H A -1 A0 A1 A6 A9 D OUT HX S t a n d b y HXX X XXXX H I G H - Z H X Output Disable L H H X X X X X HIGH-Z H X Write (Program/Erase) L H L A -1 A0 A1 A6 A9 D IN HX Enable Sector Group Protection (2), (4) LV ID LL H L V ID XH X Verify Sector Group Protection (2), (4) LLHL LHL V ID Code H X T emporary Sector Group Unprotection (5) XXX X XXXX X V ID X Reset (Hardware) / Standby X X X X X X X X HIGH-Z L X Boot Block Sector Write Protection X X X X X X X X X X L

(Continued) Table 5 MBM29DL32XTE/BE Command Definitions Command sequence Bus write cycles req’d First bus write cycle Second bus write cycle Third bus write cycle Fourth bus read/write cycle Fifth bus write cycle Sixth bus write cycle Read/Reset Word 3 555h AAh 2AAh 55h 555h F 0 h R A R D ————Byte AAAh 555h AAAh Autoselect Word 555h AAh 2AAh 55h (BA) Byte AAAh 555h (BA) AAAh Program Word 4 555h AAh 2AAh 55h 555h A 0 h P A P D ————Byte AAAh 555h AAAh Chip Erase Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10hByte AAAh 555h AAAh AAAh 555h AAAh Sector Erase Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30hByte AAAh 555h AAAh AAAh 555h Set to Fast Mode Word 3 555h AAh 2AAh 55h 555h 2 0 h ——————Byte AAAh 555h AAAh Fast Program *1 Word 2 XXXh A 0 h P A P D ————————Byte XXXh Reset from Fast Mode *1 Word 2 BA 90h XXXh F 0 h ————————Byte BA XXXh Extended Sector Group Protection *2 Word

4 XXXh 60h SPA 60h SPA 40h SPA SD ————Byte

Query *3 Hi-ROM Entry Word 3 555h AAh 2AAh 55h 555h 8 8 h ——————Byte AAAh 555h AAAh Hi-ROM Program *4 Word 4 555h AAh 2AAh 55h 555h A 0 h P A P D ————Byte AAAh 555h AAAh Hi-ROM Erase *4 Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30hByte AAAh 555h AAAh AAAh 555h Hi-ROM Exit *4 Word 555h AAh 2AAh 55h (HRBA ) 555h 9 0 h X X X h 0 0 h ———— Byte AAAh 555h (HRBA ) AAAh

(Continued) *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: The valid addresses are A6 to A0. *4: This command is valid while Hi-ROM mode. Notes: 1. Address bits A11 to A20 = X = “H” or “L” for all address commands except or Program Address (P A), Sector Address (SA), and Bank Address (BA). 2. Bus operations are defined in T ables 3 and 4. 3. RA = Address of the memory location to be read P A = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A 15 to A20) 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location P A. Data is latched on the falling edge of write pulse. 5. SP A = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. HRA = Address of the Hi-ROM area 29DL32XTE (T op Boot T ype) Word Mode: 1F8000h to 1FFFFFh Byte Mode: 3F0000h to 3FFFFFh 29DL32XBE (Bottom Boot T ype) Word Mode: 000000h to 007FFFh Byte Mode: 000000h to 00FFFFh 7. HRBA = Bank Address of the Hi-ROM area 29DL32XTE (T op Boot T ype) :A15 = A16= A17 = A18 = A19 = A20 = 1 29DL32XBE (Bottom Boot T ype) :A15 = A16= A17 = A18 = A19 = A20 = 0 8. The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A0 to A10 Byte Mode: AAAh or 555h to addresses A–1 and A0 to A10 9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultaneous operation can not be executed. *1: A-1 is for Byte mode. *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (B) : Byte mode (W): Word mode *1: A-1 is for Byte mode. *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Table 6.1 MBM29DL321TE/BE Sector Group Protection Verify Autoselect Codes Type A 12 to A20 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacture’s Code X V IL VIL VIL VIL 04h Device Code MBM29DL321TE Byte XV IL VIL VIH VIL 59h Word X 2259h MBM29DL321BE Byte XV IL VIL VIH VIL 5Ah Word X 225Ah Sector Group Protection Sector Group Addresses VIL VIH VIL VIL 01h*2 Table 6.2 Expanded Autoselect Code Table Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacturer’s Code 04h A-1/0 00000000 0 000100 Device Code MBM29DL321TE (B) 59h A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01011001 ( W ) 2 2 5 9 h 001000100 1 011001 MBM29DL321BE (B) 5Ah A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01011010 (W) 225Ah 001000100 1 011010 Sector Group Protection 01h A-1/0 00000000 0 000001 Table 6.3 MBM29DL322TE/BE Sector Group Protection Verify Autoselect Codes Type A 12 to A20 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacture’s Code X V IL VIL VIL VIL 04h Device Code MBM29DL322TE Byte XV IL VIL VIH VIL 55h Word X 2255h MBM29DL322BE Byte XV IL VIL VIH VIL 56h Word X 2256h Sector Group Protection Sector group addresses VIL VIH VIL VIL 01h*2

(B) : Byte mode (W): Word mode *1: A-1 is for Byte mode. *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (B) : Byte mode (W): Word mode Table 6.4 Expanded Autoselect Code Table Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacturer’s Code 04h A-1/0 00000000 0 000100 Device Code MBM29DL322TE (B) 55h A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01010101 ( W ) 2 2 5 5 h 001000100 1 010101 MBM29DL322BE (B) 56h A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01010110 ( W ) 2 2 5 6 h 001000100 1 010110 Sector Group Protection 01h A-1/0 00000000 0 000001 Table 6.5 MBM29DL323TE/BE Sector Group Protection Verify Autoselect Codes Type A 12 to A20 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacture’s Code X V IL VIL VIL VIL 04h Device Code MBM29DL323TE Byte XV IL VIL VIH VIL 50h Word X 2250h MBM29DL323BE Byte XV IL VIL VIH VIL 53h Word X 2253h Sector Group Protection Sector group addresses VIL VIH VIL VIL 01h*2 Table 6.6 Expanded Autoselect Code Table Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacturer’s Code 04h A-1/0 00000000 0 000100 Device Code MBM29DL323TE (B) 50h A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01010000 (W) 2250h 001000100 1 010000 MBM29DL323BE (B) 53h A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01010011 (W) 2253h 001000100 1 010011 Sector Group Protection 01h A-1/0 00000000 0 000001

*1: A-1 is for Byte mode. *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (B) : Byte mode (W): Word mode Table 6.7 MBM29DL324TE/BE Sector Group Protection Verify Autoselect Codes Type A 12 to A20 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacture’s Code X V IL VIL VIL VIL 04h Device Code MBM29DL324TE Byte XV IL VIL VIH VIL 5Ch Word X 225Ch MBM29DL324BE Byte XV IL VIL VIH VIL 5Fh Word X 225Fh Sector Group Protection Sector group addresses VIL VIH VIL VIL 01h*2 Table 6.8 Expanded Autoselect Code Table Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacturer’s Code 04h A-1/0 00000000 0 000100 Device Code MBM29DL324TE (B) 5Ch A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01011100 ( W ) 2 2 5 C h 001000100 1 011100 MBM29DL324BE (B) 5Fh A -1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z01011111 ( W ) 2 2 5 F h 001000100 1 011111 Sector Group Protection 01h A-1/0 00000000 0 000001

nnnn FLEXIBLE SECTOR-ERASE ARCHITECTURE (Continued) Table 7.1 Sector Address Tables (MBM29DL321TE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 0 000000 XXXX 6 4 / 3 2 0 0000h to 0FFFFh 000000h to 007FFFh S A 1 000001 XXXX 6 4 / 3 2 1 0000h to 1FFFFh 008000h to 00FFFFh S A 2 000010 XXXX 6 4 / 3 2 2 0000h to 2FFFFh 010000h to 017FFFh S A 3 000011 XXXX 6 4 / 3 2 3 0000h to 3FFFFh 018000h to 01FFFFh S A 4 000100 XXXX 6 4 / 3 2 4 0000h to 4FFFFh 020000h to 027FFFh S A 5 000101 XXXX 6 4 / 3 2 5 0000h to 5FFFFh 028000h to 02FFFFh S A 6 000110 XXXX 6 4 / 3 2 6 0000h to 6FFFFh 030000h to 037FFFh S A 7 000111 XXXX 6 4 / 3 2 7 0000h to 7FFFFh 038000h to 03FFFFh S A 8 001000 XXXX 6 4 / 3 2 8 0000h to 8FFFFh 040000h to 047FFFh S A 9 001001 XXXX 6 4 / 3 2 9 0000h to 9FFFFh 048000h to 04FFFFh S A 1 0001010 XXXX 6 4 / 3 2 A 0000h to AFFFFh 050000h to 057FFFh S A 1 1001011 XXXX 6 4 / 3 2 B 0000h to BFFFFh 058000h to 05FFFFh S A 1 2001100 XXXX 6 4 / 3 2 C 0000h to CFFFFh 060000h to 067FFFh S A 1 3001101 XXXX 6 4 / 3 2 D 0000h to DFFFFh 068000h to 06FFFFh S A 1 4001110 XXXX 6 4 / 3 2 E 0000h to EFFFFh 070000h to 077FFFh S A 1 5001111 XXXX 6 4 / 3 2 F 0000h to FFFFFh 078000h to 07FFFFh S A 1 6010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 1 7010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 1 8010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 1 9010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 0010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 1010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 2010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 3010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 4011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 2 5011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 2 6011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 2 7011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 2 8011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh S A 2 9011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 0011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 1011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 2100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 3100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 4100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh

(Continued) MBM29DL321TE Top Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 51X0011XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 3 61X0100XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 3 71X0101XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 3 81X0110XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 3 91X0111XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 01X1000XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 11X1001XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 21X1010XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 31X1011XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 41X1100XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 4 51X1101XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 4 61X1110XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 4 71X1111XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 4 8110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 4 9110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 0110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 1110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 2110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 3110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 4110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 5 5110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 5 6111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 5 7111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 5 8111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 5 9111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 0111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 1111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 2111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh Bank 1 S A 6 3111111000X 8 / 4 3 F 0 0 0 0 h t o 3 F 1 F F F h 1 F 8000h to 1F8FFFh S A 6 4111111001X 8 / 4 3 F 2 0 0 0 h t o 3 F 3 F F F h 1 F 9000h to 1F9FFFh S A 6 5111111010X 8 / 4 3 F 4 0 0 0 h t o 3 F 5 F F F h1 F A 000h to 1FAFFFh S A 6 6111111011X 8 / 4 3 F 6 0 0 0 h t o 3 F 7 F F F h1 F B 000h to 1FBFFFh S A 6 7111111100X 8 / 4 3 F 8 0 0 0 h t o 3 F 9 F F F h1 F C 000h to 1FCFFFh S A 6 8111111101X 8 / 4 3 F A 0 0 0 h t o 3 F B F F F h1 F D 000h to 1FDFFFh S A 6 9111111110X 8 / 4 3 F C 0 0 0 h t o 3 F D F F F h1 F E 000h to 1FEFFFh S A 7 0111111111X 8 / 4 3 F E 0 00h to 3FFFFFh 1FF000h to 1FFFFFh

(Continued) Table 7.2 Sector Address Tables (MBM29DL321BE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 7 0111111 XXXX 6 4 / 3 2 3 F 0000h to 3FFFFFh 1F8000h to 1FFFFFh S A 6 9111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 8111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 7111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 6111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 5111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 6 4111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 6 3111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 6 2110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 6 1110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 6 0110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 9110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 8110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 7110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 6110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 5110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 5 4101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 5 3101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 5 2101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 5 1101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 5 0101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 9101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 8101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 7101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 6100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 5100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 4 4100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 4 3100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 4 2100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 4 1100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh S A 4 0100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 9100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 8011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 7011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 6011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 5011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued) MBM29DL321BE Bottom Boot Sector Architecture Note : The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 4011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 3 3011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 3 2011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 3 1011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 3 0010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 9010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 8010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 7010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 6010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 5010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 2 4010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 2 3010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 2 2001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 2 1001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 2 0001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 9001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 8001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 7001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 6001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 5001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 1 4000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 1 3000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 1 2000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 1 1000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 1 0000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 9 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 8 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh Bank 1 S A 7 000000111X 8 / 4 0 0 E 0 00h to 00FFFFh 007000h to 007FFFh S A 6 000000110X 8 / 4 0 0 C 0 0 0 h t o 0 0 D F F F h0 0 6000h to 006FFFh S A 5 000000101X 8 / 4 0 0 A 0 0 0 h t o 0 0 B F F F h 0 0 5000h to 005FFFh S A 4 000000100X 8 / 4 0 08000h to 009FFFh 004000h to 004FFFh S A 3 000000011X 8 / 4 0 06000h to 007FFFh 003000h to 003FFFh S A 2 000000010X 8 / 4 0 04000h to 005FFFh 002000h to 002FFFh S A 1 000000001X 8 / 4 0 02000h to 003FFFh 001000h to 001FFFh S A 0 000000000X 8 / 4 0 00000h to 001FFFh 000000h to 000FFFh

(Continued) Table 8.1 Sector Address Tables (MBM29DL322TE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 0 000000 XXXX 6 4 / 3 2 0 0 0000h to 00FFFFh 000000h to 007FFFh S A 1 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 2 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 3 000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 4 000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 5 000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 6 000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 7 000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 8 001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 9 001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 0001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 1001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 2001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 3001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 4001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 1 5001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 1 6010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 1 7010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 1 8010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 1 9010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 0010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 1010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 2010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 3010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 4011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 2 5011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 2 6011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 2 7011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 2 8011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh S A 2 9011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 0011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 1011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 2100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 3100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 4100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh

(Continued) MBM29DL322TE Top Boot Sector Architecture Note : The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 5100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 3 6100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 3 7100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 3 8100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 3 9100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 0101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 1101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 2101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 3101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 4101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 4 5101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 4 6101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 4 7101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 4 8110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 4 9110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 0110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 1110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 2110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 3110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 4110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 5 5110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh Bank 1 S A 5 6111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 5 7111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 5 8111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 5 9111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 0111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 1111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 2111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 3111111000X 8 / 4 3 F 0 0 0 0 h t o 3 F 1 F F F h 1 F 8000h to 1F8FFFh S A 6 4111111001X 8 / 4 3 F 2 0 0 0 h t o 3 F 3 F F F h 1 F 9000h to 1F9FFFh S A 6 5111111010X 8 / 4 3 F 4 0 0 0 h t o 3 F 5 F F F h1 F A 000h to 1FAFFFh S A 6 6111111011X 8 / 4 3 F 6 0 0 0 h t o 3 F 7 F F F h1 F B 000h to 1FBFFFh S A 6 7111111100X 8 / 4 3 F 8 0 0 0 h t o 3 F 9 F F F h1 F C 000h to 1FCFFFh S A 6 8111111101X 8 / 4 3 F A 0 0 0 h t o 3 F B F F F h1 F D 000h to 1FDFFFh S A 6 9111111110X 8 / 4 3 F C 0 0 0 h t o 3 F D F F F h1 F E 000h to 1FEFFFh S A 7 0111111111X 8 / 4 3 F E 0 00h to 3FFFFFh 1FF000h to 1FFFFFh

(Continued) Table 8.2 Sector Address Tables (MBM29DL322BE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 7 0111111 XXXX 6 4 / 3 2 3 F 0000h to 3FFFFFh 1F8000h to 1FFFFFh S A 6 9111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 8111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 7111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 6111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 5111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 6 4111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 6 3111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 6 2110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 6 1110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 6 0110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 9110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 8110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 7110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 6110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 5110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 5 4101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 5 3101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 5 2101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 5 1101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 5 0101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 9101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 8101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 7101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 6100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 5100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 4 4100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 4 3100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 4 2100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 4 1100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh S A 4 0100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 9100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 8011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 7011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 6011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 5011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued) MBM29DL322BE Bottom Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 4011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 3 3011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 3 2011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 3 1011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 3 0010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 9010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 8010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 7010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 6010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 5010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 2 4010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 2 3010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 2 2001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 2 1001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 2 0001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 9001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 8001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 7001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 6001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 5001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh Bank 1 S A 1 4000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 1 3000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 1 2000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 1 1000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 1 0000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 9 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 8 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 7 000000111X 8 / 4 0 0 E 0 00h to 00FFFFh 007000h to 007FFFh S A 6 000000110X 8 / 4 0 0 C 0 0 0 h t o 0 0 D F F F h0 0 6000h to 006FFFh S A 5 000000101X 8 / 4 0 0 A 0 0 0 h t o 0 0 B F F F h 0 0 5000h to 005FFFh S A 4 000000100X 8 / 4 0 08000h to 009FFFh 004000h to 004FFFh S A 3 000000011X 8 / 4 0 06000h to 007FFFh 003000h to 003FFFh S A 2 000000010X 8 / 4 0 04000h to 005FFFh 002000h to 002FFFh S A 1 000000001X 8 / 4 0 02000h to 003FFFh 001000h to 001FFFh S A 0 000000000X 8 / 4 0 00000h to 001FFFh 000000h to 000FFFh

(Continued) Table 9.1 Sector Address Tables (MBM29DL323TE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 0 000000 XXXX 6 4 / 3 2 0 0 0000h to 00FFFFh 000000h to 007FFFh S A 1 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 2 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 3 000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 4 000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 5 000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 6 000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 7 000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 8 001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 9 001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 0001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 1001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 2001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 3001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 4001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 1 5001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 1 6010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 1 7010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 1 8010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 1 9010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 0010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 1010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 2010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 3010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 4011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 2 5011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 2 6011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 2 7011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 2 8011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh S A 2 9011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 0011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 1011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 2100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 3100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 4100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh

(Continued) MBM29DL323TE Top Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 5100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 3 6100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 3 7100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 3 8100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 3 9100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 0101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 1101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 2101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 3101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 4101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 4 5101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 4 6101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 4 7101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh Bank 1 S A 4 8110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 4 9110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 0110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 1110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 2110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 3110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 4110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 5 5110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 5 6111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 5 7111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 5 8111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 5 9111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 0111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 1111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 2111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 3111111000X 8 / 4 3 F 0 0 0 0 h t o 3 F 1 F F F h 1 F 8000h to 1F8FFFh S A 6 4111111001X 8 / 4 3 F 2 0 0 0 h t o 3 F 3 F F F h 1 F 9000h to 1F9FFFh S A 6 5111111010X 8 / 4 3 F 4 0 0 0 h t o 3 F 5 F F F h1 F A 000h to 1FAFFFh S A 6 6111111011X 8 / 4 3 F 6 0 0 0 h t o 3 F 7 F F F h1 F B 000h to 1FBFFFh S A 6 7111111100X 8 / 4 3 F 8 0 0 0 h t o 3 F 9 F F F h1 F C 000h to 1FCFFFh S A 6 8111111101X 8 / 4 3 F A 0 0 0 h t o 3 F B F F F h1 F D 000h to 1FDFFFh S A 6 9111111110X 8 / 4 3 F C 0 0 0 h t o 3 F D F F F h1 F E 000h to 1FEFFFh S A 7 0111111111X 8 / 4 3 F E 0 00h to 3FFFFFh 1FF000h to 1FFFFFh

(Continued) Table 9.2 Sector Address Tables (MBM29DL323BE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 7 0111111 XXXX 6 4 / 3 2 3 F 0000h to 3FFFFFh 1F8000h to 1FFFFFh S A 6 9111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 8111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 7111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 6111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 5111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 6 4111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 6 3111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 6 2110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 6 1110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 6 0110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 9110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 8110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 7110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 6110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 5110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 5 4101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 5 3101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 5 2101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 5 1101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 5 0101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 9101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 8101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 7101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 6100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 5100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 4 4100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 4 3100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 4 2100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 4 1100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh S A 4 0100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 9100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 8011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 7011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 6011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 5011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued) MBM29DL323BE Bottom Boot Sector Architecture Note : The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 3 4011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 3 3011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 3 2011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 3 1011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 3 0010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 9010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 8010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 7010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 6010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 5010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 2 4010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 2 3010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh Bank 1 S A 2 2001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 2 1001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 2 0001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 9001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 8001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 7001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 6001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 5001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 1 4000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 1 3000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 1 2000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 1 1000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 1 0000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 9 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 8 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 7 000000111X 8 / 4 0 0 E 0 00h to 00FFFFh 007000h to 007FFFh S A 6 000000110X 8 / 4 0 0 C 0 0 0 h t o 0 0 D F F F h0 0 6000h to 006FFFh S A 5 000000101X 8 / 4 0 0 A 0 0 0 h t o 0 0 B F F F h 0 0 5000h to 005FFFh S A 4 000000100X 8 / 4 0 08000h to 009FFFh 004000h to 004FFFh S A 3 000000011X 8 / 4 0 06000h to 007FFFh 003000h to 003FFFh S A 2 000000010X 8 / 4 0 04000h to 005FFFh 002000h to 002FFFh S A 1 000000001X 8 / 4 0 02000h to 003FFFh 001000h to 001FFFh S A 0 000000000X 8 / 4 0 00000h to 001FFFh 000000h to 000FFFh

(Continued) Table 10.1 Sector Address Tables (MBM29DL324TE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 0 000000 XXXX 6 4 / 3 2 0 0 0000h to 00FFFFh 000000h to 007FFFh S A 1 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 2 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 3 000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 4 000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 5 000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 6 000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 7 000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 8 001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 9 001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 0001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 1001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 2001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 3001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 4001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 1 5001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 1 6010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 1 7010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 1 8010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 1 9010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 0010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 1010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 2010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 3010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 4011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 2 5011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 2 6011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 2 7011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 2 8011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh S A 2 9011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 0011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 1011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh Bank 1 S A 3 2100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh S A 3 3100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 4100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh

(Continued) MBM29DL324TE Top Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH). Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 1 S A 3 5100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 3 6100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 3 7100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 3 8100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 3 9100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 0101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 1101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 2101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 3101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 4101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 4 5101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 4 6101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 4 7101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 4 8110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 4 9110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 0110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 1110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 2110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 3110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 4110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 5 5110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 5 6111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 5 7111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 5 8111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 5 9111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 0111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 1111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 2111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 3111111000X 8 / 4 3 F 0 0 0 0 h t o 3 F 1 F F F h 1 F 8000h to 1F8FFFh S A 6 4111111001X 8 / 4 3 F 2 0 0 0 h t o 3 F 3 F F F h 1 F 9000h to 1F9FFFh S A 6 5111111010X 8 / 4 3 F 4 0 0 0 h t o 3 F 5 F F F h1 F A 000h to 1FAFFFh S A 6 6111111011X 8 / 4 3 F 6 0 0 0 h t o 3 F 7 F F F h1 F B 000h to 1FBFFFh S A 6 7111111100X 8 / 4 3 F 8 0 0 0 h t o 3 F 9 F F F h1 F C 000h to 1FCFFFh S A 6 8111111101X 8 / 4 3 F A 0 0 0 h t o 3 F B F F F h1 F D 000h to 1FDFFFh S A 6 9111111110X 8 / 4 3 F C 0 0 0 h t o 3 F D F F F h1 F E 000h to 1FEFFFh S A 7 0111111111X 8 / 4 3 F E 0 00h to 3FFFFFh 1FF000h to 1FFFFFh

(Continued) Table 10.2 Sector Address Tables (MBM29DL324BE) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 2 S A 7 0111111 XXXX 6 4 / 3 2 3 F 0000h to 3FFFFFh 1F8000h to 1FFFFFh S A 6 9111110 XXXX 6 4 / 3 2 3 E 0000h to 3EFFFFh 1F0000h to 1F7FFFh S A 6 8111101 XXXX 6 4 / 3 2 3 D 0000h to 3DFFFFh 1E8000h to 1EFFFFh S A 6 7111100 XXXX 6 4 / 3 2 3 C 0000h to 3CFFFFh 1E0000h to 1E7FFFh S A 6 6111011 XXXX 6 4 / 3 2 3 B 0000h to 3BFFFFh 1D8000h to 1DFFFFh S A 6 5111010 XXXX 6 4 / 3 2 3 A 0000h to 3AFFFFh 1D0000h to 1D7FFFh S A 6 4111001 XXXX 6 4 / 3 2 3 9 0000h to 39FFFFh 1C8000h to 1CFFFFh S A 6 3111000 XXXX 6 4 / 3 2 3 8 0000h to 38FFFFh 1C0000h to 1C7FFFh S A 6 2110111 XXXX 6 4 / 3 2 3 7 0000h to 37FFFFh 1B8000h to 1BFFFFh S A 6 1110110 XXXX 6 4 / 3 2 3 6 0000h to 36FFFFh 1B0000h to 1B7FFFh S A 6 0110101 XXXX 6 4 / 3 2 3 5 0000h to 35FFFFh 1A8000h to 1AFFFFh S A 5 9110100 XXXX 6 4 / 3 2 3 4 0000h to 34FFFFh 1A0000h to 1A7FFFh S A 5 8110011 XXXX 6 4 / 3 2 3 3 0000h to 33FFFFh 198000h to 19FFFFh S A 5 7110010 XXXX 6 4 / 3 2 3 2 0000h to 32FFFFh 190000h to 197FFFh S A 5 6110001 XXXX 6 4 / 3 2 3 1 0000h to 31FFFFh 188000h to 18FFFFh S A 5 5110000 XXXX 6 4 / 3 2 3 0 0000h to 30FFFFh 180000h to 187FFFh S A 5 4101111 XXXX 6 4 / 3 2 2 F 0000h to 2FFFFFh 178000h to 17FFFFh S A 5 3101110 XXXX 6 4 / 3 2 2 E 0000h to 2EFFFFh 170000h to 177FFFh S A 5 2101101 XXXX 6 4 / 3 2 2 D 0000h to 2DFFFFh 168000h to 16FFFFh S A 5 1101100 XXXX 6 4 / 3 2 2 C 0000h to 2CFFFFh 160000h to 167FFFh S A 5 0101011 XXXX 6 4 / 3 2 2 B 0000h to 2BFFFFh 158000h to 15FFFFh S A 4 9101010 XXXX 6 4 / 3 2 2 A 0000h to 2AFFFFh 150000h to 157FFFh S A 4 8101001 XXXX 6 4 / 3 2 2 9 0000h to 29FFFFh 148000h to 14FFFFh S A 4 7101000 XXXX 6 4 / 3 2 2 8 0000h to 28FFFFh 140000h to 147FFFh S A 4 6100111 XXXX 6 4 / 3 2 2 7 0000h to 27FFFFh 138000h to 13FFFFh S A 4 5100110 XXXX 6 4 / 3 2 2 6 0000h to 26FFFFh 130000h to 137FFFh S A 4 4100101 XXXX 6 4 / 3 2 2 5 0000h to 25FFFFh 128000h to 12FFFFh S A 4 3100100 XXXX 6 4 / 3 2 2 4 0000h to 24FFFFh 120000h to 127FFFh S A 4 2100011 XXXX 6 4 / 3 2 2 3 0000h to 23FFFFh 118000h to 11FFFFh S A 4 1100010 XXXX 6 4 / 3 2 2 2 0000h to 22FFFFh 110000h to 117FFFh S A 4 0100001 XXXX 6 4 / 3 2 2 1 0000h to 21FFFFh 108000h to 10FFFFh S A 3 9100000 XXXX 6 4 / 3 2 2 0 0000h to 20FFFFh 100000h to 107FFFh Bank 1 S A 3 8011111 XXXX 6 4 / 3 2 1 F 0000h to 1FFFFFh 0F8000h to 0FFFFFh S A 3 7011110 XXXX 6 4 / 3 2 1 E 0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 6011101 XXXX 6 4 / 3 2 1 D 0000h to 1DFFFFh 0E8000h to 0EFFFFh S A 3 5011100 XXXX 6 4 / 3 2 1 C 0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued) MBM29DL324BE Bottom Boot Sector Architecture Note : The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH) Bank Sector Sector address Sector size (Kbytes/ Kwords) (·8) Address range (·16) Address rangeBank address A 14 A 13 A 12 A 11A 20 A 19 A 18 A 17 A 16 A 15 Bank 1 S A 3 4011011 XXXX 6 4 / 3 2 1 B 0000h to 1BFFFFh 0D8000h to 0DFFFFh S A 3 3011010 XXXX 6 4 / 3 2 1 A 0000h to 1AFFFFh 0D0000h to 0D7FFFh S A 3 2011001 XXXX 6 4 / 3 2 1 9 0000h to 19FFFFh 0C8000h to 0CFFFFh S A 3 1011000 XXXX 6 4 / 3 2 1 8 0000h to 18FFFFh 0C0000h to 0C7FFFh S A 3 0010111 XXXX 6 4 / 3 2 1 7 0000h to 17FFFFh 0B8000h to 0BFFFFh S A 2 9010110 XXXX 6 4 / 3 2 1 6 0000h to 16FFFFh 0B0000h to 0B7FFFh S A 2 8010101 XXXX 6 4 / 3 2 1 5 0000h to 15FFFFh 0A8000h to 0AFFFFh S A 2 7010100 XXXX 6 4 / 3 2 1 4 0000h to 14FFFFh 0A0000h to 0A7FFFh S A 2 6010011 XXXX 6 4 / 3 2 1 3 0000h to 13FFFFh 098000h to 09FFFFh S A 2 5010010 XXXX 6 4 / 3 2 1 2 0000h to 12FFFFh 090000h to 097FFFh S A 2 4010001 XXXX 6 4 / 3 2 1 1 0000h to 11FFFFh 088000h to 08FFFFh S A 2 3010000 XXXX 6 4 / 3 2 1 0 0000h to 10FFFFh 080000h to 087FFFh S A 2 2001111 XXXX 6 4 / 3 2 0 F 0000h to 0FFFFFh 078000h to 07FFFFh S A 2 1001110 XXXX 6 4 / 3 2 0 E 0000h to 0EFFFFh 070000h to 077FFFh S A 2 0001101 XXXX 6 4 / 3 2 0 D 0000h to 0DFFFFh 068000h to 06FFFFh S A 1 9001100 XXXX 6 4 / 3 2 0 C 0000h to 0CFFFFh 060000h to 067FFFh S A 1 8001011 XXXX 6 4 / 3 2 0 B 0000h to 0BFFFFh 058000h to 05FFFFh S A 1 7001010 XXXX 6 4 / 3 2 0 A 0000h to 0AFFFFh 050000h to 057FFFh S A 1 6001001 XXXX 6 4 / 3 2 0 9 0000h to 09FFFFh 048000h to 04FFFFh S A 1 5001000 XXXX 6 4 / 3 2 0 8 0000h to 08FFFFh 040000h to 047FFFh S A 1 4000111 XXXX 6 4 / 3 2 0 7 0000h to 07FFFFh 038000h to 03FFFFh S A 1 3000110 XXXX 6 4 / 3 2 0 6 0000h to 06FFFFh 030000h to 037FFFh S A 1 2000101 XXXX 6 4 / 3 2 0 5 0000h to 05FFFFh 028000h to 02FFFFh S A 1 1000100 XXXX 6 4 / 3 2 0 4 0000h to 04FFFFh 020000h to 027FFFh S A 1 0000011 XXXX 6 4 / 3 2 0 3 0000h to 03FFFFh 018000h to 01FFFFh S A 9 000010 XXXX 6 4 / 3 2 0 2 0000h to 02FFFFh 010000h to 017FFFh S A 8 000001 XXXX 6 4 / 3 2 0 1 0000h to 01FFFFh 008000h to 00FFFFh S A 7 000000111X 8 / 4 0 0 E 0 00h to 00FFFFh 007000h to 007FFFh S A 6 000000110X 8 / 4 0 0 C 0 0 0 h t o 0 0 D F F F h0 0 6000h to 006FFFh S A 5 000000101X 8 / 4 0 0 A 0 0 0 h t o 0 0 B F F F h 0 0 5000h to 005FFFh S A 4 000000100X 8 / 4 0 08000h to 009FFFh 004000h to 004FFFh S A 3 000000011X 8 / 4 0 06000h to 007FFFh 003000h to 003FFFh S A 2 000000010X 8 / 4 0 04000h to 005FFFh 002000h to 002FFFh S A 1 000000001X 8 / 4 0 02000h to 003FFFh 001000h to 001FFFh S A 0 000000000X 8 / 4 0 00000h to 001FFFh 000000h to 000FFFh

Table 11.1 Sector Group Addresses (MBM29DL32XTE) (Top Boot Block) Sector group A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors S G A 0 000000XXX S A 0 S G A 1 0000 XXX S A 1 t o S A 310 S G A 2 0001XXXXX S A 4 t o S A 7 S G A 3 0010XXXXXS A 8 t o S A 1 1 S G A 4 0011XXXXX S A 1 2 t o S A 1 5 S G A 5 0100XXXXX S A 1 6 t o S A 1 9 S G A 6 0101XXXXX S A 2 0 t o S A 2 3 S G A 7 0110XXXXX S A 2 4 t o S A 2 7 S G A 8 0111XXXXX S A 2 8 t o S A 3 1 S G A 9 1000XXXXX S A 3 2 t o S A 3 5 S G A 1 0 1001XXXXX S A 3 6 t o S A 3 9 S G A 1 1 1010XXXXX S A 4 0 t o S A 4 3 S G A 1 2 1011XXXXX S A 4 4 t o S A 4 7 S G A 1 3 1100XXXXX S A 4 8 t o S A 5 1 S G A 1 4 1101XXXXX S A 5 2 t o S A 5 5 S G A 1 5 1110XXXXX S A 5 6 t o S A 5 9 SGA16 1 1 1 1 X X X SA60 to SA6201 S G A 1 7 111111000 S A 6 3 S G A 1 8 111111001 S A 6 4 S G A 1 9 111111010 S A 6 5 S G A 2 0 111111011 S A 6 6 S G A 2 1 111111100 S A 6 7 S G A 2 2 111111101 S A 6 8 S G A 2 3 111111110 S A 6 9 S G A 2 4 111111111 S A 7 0

Table 11.2 Sector Group Addresses (MBM29DL32XBE) (Bottom Boot Block) Sector group A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors S G A 0 000000000 S A 0 S G A 1 000000001 S A 1 S G A 2 000000010 S A 2 S G A 3 000000011 S A 3 S G A 4 000000100 S A 4 S G A 5 000000101 S A 5 S G A 6 000000110 S A 6 S G A 7 000000111 S A 7 S G A 8 0000 X X X SA8 to SA1010 S G A 9 0001XXXXX S A 1 1 t o S A 1 4 S G A 1 0 0010XXXXX S A 1 5 t o S A 1 8 S G A 1 1 0011XXXXX S A 1 9 t o S A 2 2 S G A 1 2 0100XXXXX S A 2 3 t o S A 2 6 S G A 1 3 0101XXXXX S A 2 7 t o S A 3 0 S G A 1 4 0110XXXXX S A 3 1 t o S A 3 4 S G A 1 5 0111XXXXX S A 3 5 t o S A 3 8 S G A 1 6 1000XXXXX S A 3 9 t o S A 4 2 S G A 1 7 1001XXXXX S A 4 3 t o S A 4 6 S G A 1 8 1010XXXXX S A 4 7 t o S A 5 0 S G A 1 9 1011XXXXX S A 5 1 t o S A 5 4 S G A 2 0 1100XXXXX S A 5 5 t o S A 5 8 S G A 2 1 1101XXXXX S A 5 9 t o S A 6 2 S G A 2 2 1110XXXXX S A 6 3 t o S A 6 6 SGA23 1 1 1 1 X X X SA67 to SA6901 S G A 2 4 111111XXX S A 7 0

Description A 0 to A6 DQ 0 to DQ15 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 2h: AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended T able 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended T able 19h 1Ah 0000h 0000h V CC Min. (write/erase) D7-4: V , D3-0: 100 mV 1Bh 0027h VCC Max. (write/erase) D7-4: V , D3-0: 100 mV 1Ch 0036h VPP Min. voltage 1Dh 0000h VPP Max. voltage 1Eh 0000h T ypical timeout per single byte/word write 2N ms 1Fh 0004h T ypical timeout for Min. size buffer write 2N ms 20h 0000h T ypical timeout per individual block erase 2N ms 21h 000Ah T ypical timeout for full chip erase 2N ms 22h 0000h Max. timeout for byte/word write 2N times typical 23h 0005h Max. timeout for buffer write 2N times typical 24h 0000h Max. timeout per individual block erase 2N times typical 25h 0004h Max. timeout for full chip erase 2N times typical 26h 0000h Device Size = 2N byte 27h 0016h Flash Device Interface

description

Max. number of byte in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0002h Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 003Eh 0000h 0000h 0001h Table 12 Common Flash Memory Interface Code Description A 0 to A6 DQ 0 to DQ15 Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0032h Address Sensitive Unlock 0h = Required 1h = Not Required 45h 0000h Erase Suspend 0h = Not Supported 1h = T o Read Only 2h = T o Read & Write 46h 0002h Sector Protection 0h = Not Supported X = Number of sectors in per group 47h 0001h Sector T emporary Unprotection 00h = Not Supported 01h = Supported 48h 0001h Sector Protection Algorithm 49h 0004h Number of Sector for Bank 2 00h = Not Supported 3Fh = MBM29DL321TE 38h = MBM29DL322TE 30h = MBM29DL323TE 20h = MBM29DL324TE 3Fh = MBM29DL321BE 38h = MBM29DL322BE 30h = MBM29DL323BE 20h = MBM29DL324BE 4Ah 00XXh Burst Mode T ype 00h = Not Supported 4Bh 0000h Page Mode T ype 00h = Not Supported 4Ch 0000h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-4: V , D3-0: 100 mV 4Dh 0085h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-4: V , D3-0: 100 mV 4Eh 0095h Boot T ype 02h = MBM29DL32XBE 03h = MBM29DL32XTE 4Fh 00XXh Program Suspend 00h = Not Supported, 01h = Supported 50h 0001h

nnnn FUNCTIONAL DESCRIPTION

• Simultaneous Operation MBM29DL32XTE/BE have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A 15 to A20) with zero latency. The MBM29DL321TE/BE have two banks which contain Bank 1 (8KB · eight sectors) and Bank 2 (64KB · sixty-three sectors). The MBM29DL322TE/BE have two banks which contain Bank 1 (8KB · eight sectors, 64KB · seven sectors) and Bank 2 (64KB · fifty-six sectors). The MBM29DL323TE/BE have two banks which contain Bank 1 (8KB · eight sectors, 64KB · fifteen sectors) and Bank 2 (64KB · forty-eight sectors). The MBM29DL324TE/BE have two banks which contain Bank 1 (8KB · eight sectors, 64KB · thirty-one sectors) and Bank 2 (64KB · thirty-two sectors). The simultaneous operation can not execute multi-function mode in the same bank. T able 13 shows combination to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.) *: An erase operation may also be supended to read from or program to a sector not being erased.
• R e a d M o d e The MBM29DL32XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC ) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE ) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC -tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L” Table 13 Simultaneous Operation Case Bank 1 status Bank 2 status

1 Read Mode Read Mode

2 Read Mode Autoselect Mode

3 Read Mode Program Mode

4 Read Mode Erase Mode *

5 Autoselect Mode Read Mode

6 Program Mode Read Mode

7 Erase Mode * Read Mode

• Standby Mode There are two ways to implement the standby mode on the MBM29DL32XTE/BE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V . Under this condition the current consumed is less than 5 mA Max. During Embedded Algorithm operation, VCC active current (ICC2 ) is required even CE = “H”. The device can be read with standard access time (tCE ) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”). Under this condition the current is consumed is less than 5 mA Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
• Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29DL32XTE/BE data. This mode can be used effectively with an application requested low power con- sumption such as handy terminals. T o activate this mode, MBM29DL32XTE/BE automatically switch themselves to low power mode when MBM29DL32XTE/BE addresses remain stably during access fine of 150 ns. It is not necessary to control CE WE , and OE on the mode. Under the mode, the current consumed is typically 1 mA (CMOS Level). During simultaneous operation, VCC active current (ICC2 ) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29DL32XTE/BE read-out the data for changed addresses.
• Output Disable With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
• Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. T o activate this mode, the programming equipment must force V ID (11.5 V to 12.5 V) on address pin A9. T wo identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See T ables 3 and 4.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29DL32XTE/BE are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in T able 5. (Refer to Autoselect Command section.) Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code (MBM29DL321TE = 59h and MBM29DL321BE = 5Ah for ·8 mode; MBM29DL321TE = 2259h and MBM29DL321BE = 225Ah for ·16 mode). (MBM29DL322TE = 55h and MBM29DL322BE = 56h for ·8 mode; MBM29DL322TE = 2255h and MBM29DL322BE = 2256h for ·16 mode). (MBM29DL323TE = 50h and MBM29DL323BE = 53h for ·8 mode; MBM29DL323TE = 2250h and MBM29DL323BE = 2253h for ·16 mode). (MBM29DL324TE = 5Ch and MBM29DL324BE = 5Fh for ·8 mode; MBM29DL324TE = 225Ch and MBM29DL324BE = 225Fh for ·16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See T ables 6.1 to 6.8.)

• W r i t e Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The com- mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
• Sector Group Protection The MBM29DL32XTE/BE feature hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See T ables 11.1 and 11.2). The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. T o activate this mode, the programming equipment must force V ID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. T ables 7.1 to 10.2 define the sector address for each of the seventy one (71) individual sectors, and tables 11.1 and 11.2 define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm. T o verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A 0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See T ables 6.1 to 6.8 for Autoselect codes.
• Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTE/BE devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 19 and 27.

• RESET Hardware Reset The MBM29DL32XTE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP ” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “t READY ” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional “tRH ” before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing diagram. Refer to T emporary Sector Group Unprotection for additional functionality.
• Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. (MBM29DL32XTE: SA69 and SA70, MBM29DL32XBE: SA0 and SA1) If the system asserts V IH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector protection/unprotection”.
• Accelerated Program Operation MBM29DL32XTE/BE offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing V ACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See Figure 21.

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. Some commands are required Bank Address (BA) input. When command sequences are inputted to bank being read, the commands have priority than reading. T able 5 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ 0 to DQ7 and DQ8 to DQ15 bits are ignored.

• Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro- processor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
• Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM pro- grammers typically access the signature codes by raising A 9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming method- ology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read cycle from address (BA)01h for ·16((BA)02h for ·8) returns the device code (MBM29DL321TE = 59h and MBM29DL321BE = 5Ah for ·8 mode; MBM29DL321TE = 2259h and MBM29DL321BE = 225Ah for ·16 mode). (MBM29DL322TE = 55h and MBM29DL322BE = 56h for ·8 mode; MBM29DL322TE = 2255h and MBM29DL322BE = 2256h for ·16 mode). (MBM29DL323TE = 50h and MBM29DL323BE = 53h for ·8 mode; MBM29DL323TE = 2250h and MBM29DL323BE = 2253h for ·16 mode). (MBM29DL324TE = 5Ch and MBM29DL324BE = 5Fh for ·8 mode; MBM29DL324TE = 225Ch and MBM29DL324BE = 225Fh for ·16 mode). (See T ables 6.1 to 6.8.) All manufacturer and device codes will exhibit odd parity with DQ 7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA)02h for ·16 ((BA)04h for ·8). Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See T ables 10 and 11.) The manufacture and device codes can be allowed reading from selected bank. T o read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu- facture codes should be read from the other bank where is not contain the software.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on T able 5. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “t TOW ” otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t TOW ” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW ” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ 3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ 7 (Data Polling), DQ6 (T oggle Bit), or RY/BY. The sector erase begins after the “tTOW ” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the devices return to the read mode. Data polling and T oggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] · Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. Figure 23 illustrates the Embedded Erase TM Algorithm using typical command strings and bus operations.

• Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONL Y during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “t SPD ” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro- gramming in this mode is the same as programming in the regular Program mode except that the data must be

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase- suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the T oggle Bit I (DQ 6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. T o resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

• Extended Command (1) Fast Mode MBM29DL32XTE/BE has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. T o exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to the Figure 28.) The V CC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (P A/PD). (Refer to the Figure 28.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29DL32XTE/BE has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing V ID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set- up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 ms. T o verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector group protection command (60h) again. T o terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the Figures 20 and 29.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interro- gation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ 8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. T o terminate operation, it is necessary to write the read/reset command sequence into the register. (See T able 12.)

• Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modifi- cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB ·8 sectors. The MBM29DL32XTE occupies the address of the byte mode 3F0000h to 3FFFFFh (word mode 1F8000h to 1FFFFFh) and the MBM29DL32XBE type occupies the address of the byte mode 000000h to 00FFFFh (word mode 000000h to 007FFFh). After the system has written the Enter Hi-ROM command sequence, the system may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
• Hidden ROM (Hi-ROM) Entry Command MBM29DL32XTE/BE has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 3F0000h to 3FFFFFh at byte mode (1F8000h to 1FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh at byte mode (000000h to 007FFFh at word mode). These areas are normally the boot block area (8KB ·8 sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears. Sector other than the boot block area could be read during Hidden ROM mode. Read/program/erase of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset command sequence. In case of MBM29DL321TE/BE, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute multi-function mode between the Hidden ROM area and Bank 2 Region.
• Hidden ROM (Hi-ROM) Program Command T o program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is same as the program command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, the data of the address will be changed.
• Hidden ROM (Hi-ROM) Erase Command T o erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode. This command is same as the sector erase command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ 7 data poling, DQ 6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address other than the Hidden ROM area is selected, the data of the sector will be changed.

• Hidden ROM (Hi-ROM) Protect Command There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup com- mand(60h), set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0), and write the sector group protect command(60h) during the Hidden ROM mode. The same command sequence could be used because except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is the same as the extension sector group protect in the past. Please refer to “Function Explanation Extended Command (3) Extended Sector Group Protection” for details of extension sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0), and apply the write pulse during the Hidden ROM mode. T o verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and read. When “1” appears to DQ0, the protect setting is completed. “0” will appear to DQ0 if it is not protected. Please apply write pulse again. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to “Function Explanation Sector Group Protection” for details of sector group protect setting Other sector group will be effected if the address other than the Hidden ROM area is selected for the sector group address, so please be careful. Once it is protected, protection can not be cancelled, so please pay closest attention.
• Write Operation Status Detailed in T able 14 are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ 2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>, [2] <non-busy bank>, [3] <busy bank>, the DQ 6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted.

*: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. Notes :1.DQ0 and DQ1 are reserve pins for future use. 2.DQ4 is Fujitsu internal use only.

• D Q7 Data Polling The MBM29DL32XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ 7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 24. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 ms, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 ms, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. Table 14 Hardware Sequence Flags Status DQ 7 DQ 6 DQ 5 DQ 3 DQ 2 In Progress Embedded Program Algorithm DQ 7 Toggle 0 0 1 Embedded Erase Algorithm 0 Toggle 0 1 Toggle* Erase Suspended Mode Erase Suspend Read (Erase Suspended Sector) 110 0 T o g g l e Erase Suspend Read (Non-Erase Suspended Sector) Data Data Data Data Data Erase Suspend Program (Non-Erase Suspended Sector) DQ 7 Toggle 0 0 1* Exceeded Time Limits Embedded Program Algorithm DQ 7 Toggle 1 0 1 Embedded Erase Algorithm 0 Toggle 1 1 N/A Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) DQ

7 Toggle 1 0 N/A

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See T able 14.) See Figure 9 for the Data Polling timing specifications and diagrams.

• D Q6 Toggle Bit I The MBM29DL32XTE/BE also feature the “T oggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the T oggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the T oggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The T oggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 ms and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ 6 to toggle. T o operate toggle bit function properly, CE or OE must be high when bank address is changed. See Figure 10 for the T oggle Bit I timing specifications and diagrams.
• D Q5 Exceeded Timing Limits DQ 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in T ables 3 and 4. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ 7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ 5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence.
• D Q3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and T oggle Bit are valid after the initial sector erase command sequence. If Data Polling or the T oggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or T oggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. T o insure the command has been accepted, the system software should check the status of DQ 3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See T able 14: Hardware Sequence Flags.

• D Q2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ 2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ 6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ 2 toggles while DQ6 does not.) See also T able 15 and Figure 12. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. T o operate toggle bit function properly, CE or OE must be high when bank address is changed. Table 15 Toggle Bit Status Note: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non- erase suspend sector address will indicate logic “1” at the DQ2 bit.
• R Y / B Y Ready/Busy The MBM29DL32XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/ write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29DL32XTE/BE are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC . Mode DQ 7 DQ 6 DQ 2 Program DQ 7 Toggle 1 Erase 0 Toggle Toggle (Note) Erase-Suspend Read (Erase-Suspended Sector) 11 T o g g l e Erase-Suspend Program DQ 7 Toggle 1 (Note)

• Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to Figures 15, 16 and 17 for the timing diagram.
• Data Protection The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automat- ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form V CC power-up and power-down transitions or system noise.
• L o w VCC Write Inhibit T o avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min.). If VCC < VLKO , the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V CC level is greater than VLKO . It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min.). If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
• Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
• Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. T o initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
• Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.

nnnn ABSOLUTE MAXIMUM RATINGS (See WARNING) Notes : 1. Minimum DC voltage on input or I/O pins is -0.5 V . During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V . During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE and RESET pins is -0.5 V . During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC ) does not exceed +9.0 V . Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. 3. Minimum DC input voltage on WP/ACC pin is -0.5 V . During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Conditions Rating Unit Min. Max. Storage T emperature Tstg ¾ –55 +125 °C Ambient T emperature with Power Applied TA ¾ –40 +85 °C Voltage with Respect to Ground All pins except A9, OE , RESET (Note 1) VIN, VOUT ¾ –0.5 V CC +0.5 V Power Supply Voltage (Note 1) VCC ¾ –0.5 +4.0 V A9, OE, and RESET (Note 2) VIN ¾ –0.5 +13.0 V WP /ACC (Note 3) V IN ¾ –0.5 +10.5 V Parameter Symbol Conditions Value Unit Min. Max. Ambient T emperature T A MBM29DL32XTE/BE-80 –20 +70 °C MBM29DL32XTE/BE-90/12 –40 +85 °C Power Supply Voltage V CC MBM29DL32XTE/BE-80 +3.0 +3.6 V MBM29DL32XTE/BE-90/12 +2.7 +3.6 V

nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. Applicable for only VCC applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz) Parameter Symbol Conditions Value Unit Min. Max. Input Leakage Current I LI VIN = VSS to VCC , VCC = VCC Max. –1.0 +1.0 mA Output Leakage Current I LO VOUT = VSS to VCC , VCC = VCC Max. –1.0 +1.0 mA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max. A9, OE, RESET = 12.5 V —3 5 mA VCC Active Current (Note 1) I CC1 CE = VIL, OE = VIH, f = 5 MHz Byte mA Word 18 CE = VIL, OE = VIH, f = 1 MHz Byte mA Word 7 VCC Active Current (Note 2) I CC2 CE = VIL, OE = VIH —3 5 m A VCC Current (Standby) I CC3 VCC = VCC Max., CE = VCC ± 0.3 V , RESET = VCC ± 0.3 V —5 mA VCC Current (Standby, Reset) I CC4 VCC = VCC Max.,WE/ACC = VCC ± 0.3 V , RESET = VSS ± 0.3 V —5 mA VCC Current (Automatic Sleep Mode) (Note 3) ICC5 VCC = VCC Max., CE = VSS ± 0.3 V , RESET = VCC ± 0.3 V VIN = VCC ± 0.3 V or VSS – 0.3 V —5 µ A VCC Active Current (Note 5) (Read-While-Program) ICC6 CE = VIL, OE = VIH Byte — 51 mA Word — 53 VCC Active Current (Note 5) (Read-While-Erase) ICC7 CE = VIL, OE = VIH Byte — 51 mA Word — 53 VCC Active Current (Erase-Suspend-Program) ICC8 CE = VIL, OE = VIH —3 5 m A ACC Accelerated Program Current I ACC VCC = VCC Max. WP /ACC = VACC Max. —2 0 m A Input Low Level V IL — –0.5 0.6 V Input High Level V IH —2 . 0 V CC +0.3 V Voltage for WP/ACC Sector Protection/ Unprotection and Program AccelerationVACC —8 . 5 9 . 5 V Voltage for Autoselect and Sector Protection (A9, OE, RESET) (Note 4) VID — 11.5 12.5 V Output Low Voltage Level V OL IOL = 4.0 mA, VCC = VCC Min. — 0.45 V Output High Voltage Level VOH1 IOH = –2.0 mA, VCC = VCC Min. 2.4 — V VOH2 IOH = –100 mAV CC –0.4 — V Low VCC Lock-Out Voltage V LKO —2 . 3 2 . 5 V

1. AC Characteristics

• Read Only Operations Characteristics Note: T est Conditions: Output Load: 1 TTL gate and 30 pF (MBM29DL32XTE/BE-80)

1 TTL gate and 100 pF (MBM29DL32XTE/BE-90/12)

Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V Parameter symbols Description Test setup 80 (Note) (Note) (Note) Unit JEDEC Standard t AVAV tRC Read Cycle Time — Min. 80 90 120 ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL Max. 80 90 120 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 80 90 120 ns tGLQV tOE Output Enable to Output Delay — Max. 30 35 50 ns tEHQZ tDF Chip Enable to Output High-Z — Max. 25 30 30 ns tGHQZ tDF Output Enable to Output High-Z — Max. 25 30 30 ns tAXQX tOH Output Hold Time from Addresses, CE or OE, Whichever Occurs First — M i n . 000 n s —t READY RESET Pin Low to Read Mode — Max. 20 20 20 ms — tELFL tELFH CE or BYTE Switching Low or High — Max. 5 5 5 ns C L 3.3 V Diodes = IN3064 or Equivalent 2.7 kW Device Under Test IN3064 or Equivalent 6.2 kW Figure 4 Test Conditions

• Write/Erase/Program Operations (Continued) Parameter symbols Description 80 90 12 Unit JEDEC Standard tAVAV tWC Write Cycle Time Min. 80 90 120 ns tAVWL tAS Address Setup Time Min. 0 0 0 ns —t ASO Address Setup Time to OE Low During T oggle Bit Polling Min. 12 15 15 ns tWLAX tAH Address Hold Time Min. 45 45 50 ns —t AHT Address Hold Time from CE or OE High During T oggle Bit Polling Min. 0 0 0 ns tDVWH tDS Data Setup Time Min. 30 35 50 ns tWHDX tDH Data Hold Time Min. 0 0 0 ns —t OEH Output Enable Hold Time Read Min. 0 0 0 ns T oggle and Data Polling Min. 10 10 10 ns —t CEPH CE High During T oggle Bit Polling Min. 20 20 20 ns —t OEPH OE High During T oggle Bit Polling Min. 20 20 20 ns tGHWL tGHWL Read Recover Time Before Write Min. 0 0 0 ns tGHEL tGHEL Read Recover Time Before Write Min. 0 0 0 ns tELWL tCS CE Setup Time Min. 0 0 0 ns tWLEL tWS WE Setup Time Min. 0 0 0 ns tWHEH tCH CE Hold Time Min. 0 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 0 ns tWLWH tWP Write Pulse Width Min. 35 35 50 ns tELEH tCP CE Pulse Width Min. 35 35 50 ns tWHWL tWPH Write Pulse Width High Min. 25 30 30 ns tEHEL tCPH CE Pulse Width High Min. 25 30 30 ns tWHWH1 tWHWH1 Byte Programming Operation Typ. 8 8 8 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ. 1 1 1 s —t VCS VCC Setup Time Min. 50 50 50 µs —t VIDR Rise Time to VID (Note 2) Min. 500 500 500 ns —t VACCR Rise Time to VID (Note 2) Min. 500 500 500 ns —t VLHT Voltage T ransition Time (Note 2) Min. 4 4 4 µs —t WPP Write Pulse Width (Note 2) Min. 100 100 100 µs —t OESP OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs

(Continued) Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Group Protection operation. Parameter symbols Description 80 90 12 Unit JEDEC Standard —t CSP CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs —t RB Recover Time from RY/BY Min. 0 0 0 ns —t RP RESET Pulse Width Min. 500 500 500 ns —t RH RESET High Level Period before Read Min. 200 200 200 ns —t FLQZ BYTE Switching Low to Output High-Z Max. 30 30 40 ns —t FHQV BYTE Switching High to Output Active Max. 80 90 120 ns —t BUSY Program/Erase Valid to RY/BY Delay Max. 90 90 90 ns —t EOE Delay Time from Embedded Output Enable Max. 80 90 120 ns —t TOW Erase Time-Out Time Min. 50 50 50 µs —t SPD Erase Suspend T ransition Time Max. 20 20 20 µs

nnnn ERASE AND PROGRAMMING PERFORMANCE nnnn PIN CAPACITANCE Note: T est conditions TA = 25°C, f = 1.0 MHz Parameter Limits Unit Comments Min. Typ. Max. Sector Erase Time — 1 10 s Excludes programming time prior to erasure Word Programming Time — 16 360 ms Excludes system-level overheadByte Programming Time — 8 300 ms Chip Programming Time — — 100 s Excludes system-level overhead Program/Erase Cycle 100,000 — — cycle — Parameter symbol Parameter description Test setup Typ. Max. Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 8 11 pF C IN3 WP /ACC Pin Capacitance V IN = 0 21.5 22.5 pF

• Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady May Change from H to L May Change from L to H “H” or “L” Any Change Permitted Does Not Apply Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is High- Impedance “Off” State WE OE CE tACC tDF tCE tOE Outputs tRC Address Address Stable High-Z Output Valid High-Z tOEH tOH Figure 5.1 AC Waveforms for Read Operations

Figure 5.2 AC Waveforms for Hardware Reset/Read Operations

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations Notes: 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations Notes: 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

555h 2AAh 555h 555h 2AAh SA* tDS tCH tAS tAH tCS tWPH tDH tGHWL tVCS tWC 55h55h 80h AAhAAh 10h/ 30h Figure 8 AC Waveforms for Chip/Sector Erase Operations *: SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase. Note: These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

DQ 7 = Valid Data DQ 0 to DQ6 Valid Data DQ 7 DQ 7 DQ 0 to DQ6 RY/BY Data DQ 0 to DQ6 = Output Flag Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations * : DQ7 = Valid Data (The device has completed the Embedded operation).

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations * : DQ6 stops toggling (The device has completed the Embedded operation).

Figure 18 AC Waveforms for Sector Group Protection SGAX: Sector Group Address for initial sector SGAY : Sector Group Address for next sector Note: A -1 is VIL on byte mode. tVLHT SGAX A20, A19, A18 A17, A16, A15 A14, A13, A12 SGAY VID 3 V tVLHT OE VID 3 V tVLHTtVLHT tOESP tWPP tCSP WE CE tOE 01hData VCC tVCS

tVLHT Program or Erase Command Sequence 3 V tVLHT tVCS tVIDR VID tVLHT Unprotection period Figure 19 Temporary Sector Group Unprotection Timing Diagram

Figure 20 Extended Sector Group Protection Timing Diagram SGAX: Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 ms (Min.)

tVLHT Program or Erase Command Sequence 3 V tVLHT tVCS tVACCR VACC tVLHT Acceleration period Figure 21 Accelerated Program Timing Diagram

Program Command Sequence* (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Write Program Command Sequence (See below) Data Polling Device Increment Address Last Address Program Address/Program Data Start Programming Completed Figure 22 Embedded ProgramTM Algorithm EMBEDDED ALGORITHMS * : The sequence is applied for · 16 mode. The addresses differ from · 8 mode.

are optional. Write Erase Command Sequence (See below) Data Polling or Toggle Bit Successfully Completed Chip Erase Command Sequence* (Address/Command): Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): Sector Address/30h Sector Address/30h Sector Address/30h Erasure Completed Start Figure 23 Embedded EraseTM Algorithm EMBEDDED ALGORITHMS * : The sequence is applied for · 16 mode. The addresses differ from · 8 mode.

DQ 7 = Data? No No DQ 7 = Data? DQ 5 = 1? Yes Yes No Read (DQ 0 to DQ 7) Addr. = VA Read (DQ 0 to DQ 7) Addr. = VA Yes Start Fail Pass Figure 24 Data Polling Algorithm Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase

DQ 6 = Toggle Yes No DQ 6 = Toggle DQ 5 = 1? Yes No No Yes Read (DQ 0 to DQ 7) Addr. = VA Read (DQ 0 to DQ 7) Addr. = VA Start PassFail Figure 25 Toggle Bit Algorithm Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ 5 changing to “1”. VA = Bank address being executed Embedded Algorithm.

Setup Sector Group Addr. (A20, A19, A18, A17, A16, A15, A14, A13, A12) Activate WE Pulse WE = V IH, CE = OE = V IL (A 9 should remain V ID) Yes Yes No No OE = V ID, A 9 = V ID, A 6 = CE = V IL, RESET = V IH A 0 = V IL, A 1 = V IH PLSCNT = 1 Time out 100 ms Read from Sector Group (Addr. = SGA, A 0 = V IL, A 1 = V IH, A 6 = V IL)* Remove V ID from A 9 Write Reset Command Increment PLSCNT No Yes Protect Another Sector Group ? Data = 01H?PLSCNT = 25? Device Failed Remove V ID from A 9 Write Reset Command Start Sector Group Protection Completed Figure 26 Sector Group Protection Algorithm * : A-1 is V IL on byte mode.

RESET = VID (Note 1) Perform Erase or Program Operations RESET = VIH Start Temporary Sector Group Unprotection Completed (Note 2) Figure 27 Temporary Sector Group Unprotection Algorithm Notes: 1. All protected sector groups are unprotected. 2. All previously protected sector groups are protected once again.

Figure 28 Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h XXXh/A0h 555h/20h Verify Byte? No Program Address/Program Data Data Polling Device Last Address Programming Completed (BA) XXXh/90h XXXh/F0h Increment Address No Yes Yes Set Fast Mode In Fast Program Reset Fast Mode Note: The sequence is applied for · 16 mode. The addresses differ from · 8 mode.

Figure 29 Extended Sector Group Protection Algorithm To Sector Group Protection Yes No No PLSCNT = 1 Protection Other Sector Start Sector Group Protection Extended Sector Group Completed Remove VID from RESET Write Reset Command RESET = VID Wait to 4 ms Protection Entry? To Setup Sector Group Protection Write XXXh/60h Write SGA/60h (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 ms To Verify Sector Group Protection Write SGA/40h (A0 = VIL, A1 = VIH, A6 = VIL) Data = 01h? Group ? Device is Operating in Temporary Sector Group Read from Sector Group (A0 = VIL, A1 = VIH, A6 = VIL) Increment PLSCNT No Yes Yes Unprotection Mode Address Setup Next Sector Group Address No Yes PLSCNT = 25? Device Failed Remove V ID from RESET Write Reset Command

Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29DL32X T E 80 TN DEVICE NUMBER/DESCRIPTION MBM29DL32X 32Mega-bit (4M · 8-Bit or 2M · 16-Bit) CMOS Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PBT = Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = T op sector B = Bottom sector Valid Combinations MBM29DL321TE/BE TN TR PBT MBM29DL322TE/BE MBM29DL323TE/BE MBM29DL324TE/BE Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

C 2000 FUJITSU LIMITED F48029S-3c-4 Details of "A" part 0.15(.006) MAX 0.35(.014) MAX INDEX "A" 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 19.00±0.20 (.748±.008) 0.50±0.10 (.020±.004) 0.15±0.05 (.006±.002) 11.50REF (.453) 0.50(.0197) TYP 0.20±0.10 (.008±.004) 0.10±0.05 .043–.002 +.004 –0.05 +0.10 1.10 M0.10(.004) (.004±.002) 24 25 LEAD No. * 12.00±0.20 (.472±.008) (Mounting height) 0.10(.004) (STAND OFF) Dimensions in mm (inches) 48-pin plastic TSOP(I) (FPT -48P-M19) * Resin Protrusion. (Each Side: 0.15 (.006)Max) (Continued) C 2000 FUJITSU LIMITED F48030S-3c-4 Details of "A" part 0.15(.006) MAX 0.35(.014) MAX INDEX "A" 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 19.00±0.20 (.748±.008) 0.50±0.10 (.020±.004) 0.15±0.05 (.006±.002) 11.50(.453)REF 0.50(.020) TYP 0.20±0.10 (.008±.004) .043–.002 +.004 –0.05 +0.10 1.10 M0.10(.004) 24 25 LEAD No. (Mounting height) 0.10(.004) 0.10±0.05 (.004±.002) (STAND OFF) 48-pin plastic TSOP(I) (FPT -48P-M20) Dimensions in mm (inches) * Resin Protrusion. (Each Side: 0.15 (.006)Max)

(Continued) 63-pin plastic FBGA (BGA-63P-M01) C 1999 FUJITSU LIMITED B63001S-1C-1 .041–.004 +.006 –0.10 +0.15 1.05 (Mounting height) ABCDEFGH 0.80(.031)TYP (5.60(.220)) (5.60(.220)) INDEX BALL M0.08(.003) 0.10(.004) INDEX AREA 7.00±0.10 (.276±.004) (7.20(.283)) JK (63-Ø0.18±.002) 63-Ø0.45±0.05 ML (8.80(.346)) (4.00(.157)) 0.38±0.10 (.015±.004) (Stand off) Dimensions in mm (inches)

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