MBM29BT32LF18PBT

MBM29BS32LF18 SPANSION | Alldatasheet

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DS05-20913-2EFUJITSU SEMICONDUCTOR DATA SHEET BURST MODE FLASH MEMORY CMOS 32M (2M · 16) BIT MBM29BS/BT32LF 18/25 nnnn GENERAL DESCRIPTION The MBM29BS/BT32LF is a 32M bit, 1.8 Volt-only, Burst mode and dual operation Flash memory organized as 2M words of 16 bits each. The device offered in a 60-ball FBGA package. This device is designed to be programmed in-system with the standard system 1.8V V CC supply. (Continued) nnnn PRODUCT LINE UP nnnn PACKAGE Part No. MBM29BS/ BT32LF-25 MBM29BT32LF-18 MBM29BS32LF-18 VCC 1.8 V 1.8 V 1.8 V VCCQ 1.8 V/3.0 V 3.0 V 1.8 V Clock Rate 40 MHz ( - 25) 54 MHz ( - 18) 54 MHz ( - 18) Synchronous/Burst Max Latency Time (ns) 120 106.5 106 Max Burst Access Time (ns) 20 14 13.5 Max OE Access Time (ns) 20 14 13.5 Asynchronous Max Address Access Time (ns) 70 70 70 Max CE Access Time (ns) 70 70 70 Max OE Access Time (ns) 20.5 20 20 +0.15 V –0.15 V +0.15 V –0.15 V +0.15 V –0.15 V +0.15 V –0.30 V +0.15 V –0.15 V 60-ball plastic FBGA (BGA-60P-M05)

(Continued) The device supports Enhanced VCCQ to offer up to 3 V compatible inputs and outputs(MBM29BS32LF:1.8V VCCQ , can also be programmed in standard EPROM programmers. The device provides truly high performance non-volatile memory solution. The device offers fast burst access frequency of 54MHz with initial access times of 106ns, allowing operation of high-speed microprocessors without wait states. T o eliminate bus connection the device has separate chip enable (CE), write enable (WE), address valid (AVD) and output enable (OE) controls. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/ microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space. At 54 MHz, the device provides a burst access of 13.5 ns with a latency of 106 ns at 30 pF . The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E 2PROMs. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state- machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0V and 12.0V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. T ypically, each 32K words sector can be programmed and verified in about 0.3 second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.2 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The Enhanced V I/O (VCCQ ) feature allows the output voltage generated on the device to be determined based on the VI/O level. This feature allows this device to operate in the 1.8 V and 3.0 V I/O environment, driving and receiving signals to and from other 1.8 V and 3.0 V devices on the same bus. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the T oggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

• 0 . 1 7 mmmmm process technology
• Single 1.8 volt read, program and erase (1.65 V to 1.95 V)
• Simultaneous Read/Write operation (Dual Bank)
• All Sectors Being Protected Upon Power-up The device aims for high-speed read of stored codes, thus to fully prevent it from much anticipated wrong operational procedures, programming and erasure, it adopts All-Sectors Lock for ultimate all sector protection by default upon power-up.
• FlexBank TM *1 Bank A: 8M bit (8K words · 4 and 32K words · 15) Bank B: 8M bit (32K words · 16) Bank C: 8M bit (32K words · 16) Bank D: 8M bit (8K words · 4 and 32K words · 15)
• Enhanced I/OTM *2 (VCCQ ) Feature Input/ Output voltage generated on the device is determined based on the VI/O level (MBM29BS32LF: 1.8V VCCQ and MBM29BT32LF: 3.0V VCCQ )
• High Performance Burst frequency reach at 54MHz Burst access times of 13.5 ns @ 30 pF at industrial temperature range Asynchronous random access times of 70 ns (at 30 pF) Synchronous latency of 106 ns with 1.8 V V CCQ , and 106.5 ns with 3.0 V VCCQ (at 30 pF)
• Programmable Burst Read Interface Linear Burst: 8, 16, and 32 words with wrap-around
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Minimum 100,000 program/erase cycles
• Sector Erase Architecture Eight 8K words, sixty-two 32K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Write Protect Pin (WP) At VIL, allows protection of “outermost” 2 · 8K words on low end of boot sectors(SA0 and SA1), regardless of sector protection/unprotection status
• Accelerate Pin (ACC) At VACC , increases program performance. At VIL, hardware protect method to lock all sectors.
• Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector
• Embedded Program TM *2 Algorithms Automatically writes and verifies data at specified address
• D a t a Polling and Toggle Bit feature for detection of program or erase cycle completion
• Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• In accordance with CFI (Common Flash Interface)
• Hardware reset pin (RESET) Hardware method to reset the device for reading array data T o avoid initiation of a write cycle during Vcc power-up/down, Reset must be VIL for defined time. (Continued)

(Continued)

• Protection Software command sector locking WP protects the outermost two boot sectors(SA0 and SA1) ACC protects all sector at VIL. Should be at VIH for all other conditions.
• CMOS compatible inputs, CMOS compatible outputs *1: FlexBank TM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM , Embedded ProgramTM and Enhanced VI/OTM are trademarks of Advanced Micro Devices, Inc. nnnn PIN ASSIGNMENT (BGA-60P-M05) FBGA (TOP VIEW) Marking Side N.C. A13 VCC VSSQ B8 C8 D8 E8 F8 G8 A12 A14 A15 A16 N.C. DQ 15 VSS A7 B7 C7 D7 E7 F7 G7 H7 A8 A10 A11 DQ 7 DQ 14 DQ 13 DQ 6 A6 B6 C6 D6 E6 F6 G6 H6 WE RESET N.C. DQ 12 VCC DQ 4 A5 B5 C5 F5 G5 H5 DQ 10A18RDY ACC DQ 11 DQ 3 B4 C4A4 F4 G4 H4 A17 A6 A5 DQ 0 DQ 8 DQ 9 DQ 1 A3 B3 C3 D3 E3 F3 G3 H3 A2 A1 A0 CE OE V SS A2 B2 C2 D2 E2 F2 G2 H2 CLK WP AVD VCCQ B1 G1C1 D1 E1 F1 A19 DQ 5 A20 DQ 2 Index

DQ 15 to DQ0 Data Inputs/Outputs CLK CLK Input CE Chip Enable OE Output Enable WE Write Enable AVD Address Valid Input RDY Ready Output RESET Hardware Reset WP Hardware Write Protection ACC Program Acceleration N.C. Pin Not Connected Internally VSS Device Ground VCC Device Power Supply VSSQ Input & Output Buffer Ground VCCQ Input & Output Buffer Power Supply

16 Mbit

(Bank A) X-Decoder Y -Gating Cell Matrix (Bank D) X-Decoder Y -Gating Cell Matrix (Bank B) X-Decoder Y -Gating Cell Matrix (Bank C) X-Decoder Y -Gating VSSQ VSS VCCQ CLK ACC A20 to A0 OE ACC CE WP CLK DQ 15 to DQ0 WE RDY RESET AVD

nnnn DEVICE BUS OPERATIONS MBM29BS/BT32LF User Bus Operations Table Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1: Default active edge of CLK is the rising edge. *2: Autoselect code can be read both Asynchronous and Synchronous Read operation *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: For four program operations, enable to input the same program command. *5: Protect “outermost” 2 · 8K words on low end of the boot block sectors.(SA0 and SA1) Operation CE OE WE WP A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 DQ 15 to DQ0 CLK *1 AVD RESET ACC Auto-Select Manufacturer Code *2 L L H X LHLLLLLLC o d e X HH Auto-Select Device Code *2 L L H X HLLLLLLLC o d e X HH Extended Auto-Select Device Code *2 L L H X LH H HLLLLC o d e X HH L L H X H H H HLLLLC o d e X HH Asynchronous Read - Addresses Latched *3 LLH X A 0 A1 A2 A3 A4 A5 A6 A7 D OUT X HH Asynchronous Read - Addresses Steady State *

3 LLH X A 0 A1 A2 A3 A4 A5 A6 A7 D OUT XL HH

Load Starting Burst Address (CLK latch) *

3 LXH X A 0 A1 A2 A3 A4 A5 A6 A7 XH H

Load Starting Burst Address (AVD latch) *3 LXH X A 0 A1 A2 A3 A4 A5 A6 A7 X H/L HH Advance Burst to next address *

3 L L H X XXXXXXXX D OUT H HH

T erminate Burst read H X H X XXXXXXXX High-Z X HH T erminate Burst read and start new Burst read LXH X A 0 A1 A2 A3 A4 A5 A6 A7 D OUT HH T erminate Burst read via RESET X X H X XXXXXXXX High-Z XX LH Standby H X X X XXXXXXXX High-Z XX HH Output Disable L H H X XXXXXXXX High-Z XX HH Program 1 - Addresses Latched (WE) *4 LH L XA 0 A1 A2 A3 A4 A5 A6 A7 D IN LL HH Program 1 - Addresses Latched (CLK) *

4 LH L X A 0 A1 A2 A3 A4 A5 A6 A7 D IN L HH

Latched (CLK) *

4 LH L X A 0 A1 A2 A3 A4 A5 A6 A7 D IN HH

Latched (AVD ) *4 LH L X A 0 A1 A2 A3 A4 A5 A6 A7 D IN H/L HH Boot Block Sector Write Protection *

5 X X X L XXXXXXXX X XX HH

All Sector Lock L X X X XXXXXXXX X XX HL RESET X X X X XXXXXXXX High-Z XX LH

MBM29BS/BT32LF Command Definitions Table Legend: RA = Address of the memory location to be read. P A = Address of the memory location to be programmed. Address latches on the rising edge of AVD pulse or active CLK edge while AVD=V IL or falling edge of write pulse while AVD=V IL SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14 and A13 will uniquely select any sector. BA = Bank Address. Address setted by A20, A19 will select Bank A, Bank B, Bank C and Bank D. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. RD = Data read from location RA during read operation. PD = Data to be programmed at location P A. Data latches on the rising edge of write pulse. CR = Configuration Register address bits A 19 to A12. *1: This command is valid during Fast Mode. *2: The data “00h” is also acceptable. Notes:• Address bits A20 to A11 = X = “H” or “L” for all address commands except for P A, SA, BA.

• Bus operations are defined in “MBM29BS/BT32LF User Bus Operations T able” (in n DEVICE BUS OPERA TIONS).
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Write Cycle Third Write Cycle Fourth Write Cycle Fifth Write Cycle Sixth Write Cycle Asynchronous Read / Reset 1 X X X h F 0 h R A R D ———————— Asynchronous Read / Reset 3 555h AAh 2AAh 55h 555h F0h RA RD — — — — Autoselect 3 555h AAh 2AAh 55h (BA) Program 4 555h AAh 2AAh 55h 555h A0h PA PD — — — — Chip Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h Fast Program 2 XXXh A0 PA PD Set to Fast Mode 3 555h AAh 2AAh 55h 555h 20h — — — — — — Reset from Fast Mode * Sector Lock/Unlock (Sector Command Locking)

3 XXXh 60h XXXh 60h SLA 60h — — — — — —

3 555h AAh 2AAh 55h (CR) Query 1 (BA)

MBM29BS/BT32LF Sector Protection Verify Autoselect Codes Table *1: A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh. *2: 2223h for V CCQ : 1.8 V(MBM29BS32LF), 2234h for VCCQ : 3.0 V(MBM29BT32LF). *3: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Expanded Autoselect Code Table Type A 20, A19 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Code (HEX) Manufacture’s Code BA* 2 VIL VIL VIL VIL VIL VIL VIL VIL 04h Device Code BA* 2 VIL VIL VIL VIL VIL VIL VIL VIH 227Eh Extended Device Code*1 BA V IL VIL VIL VIL VIH VIH VIH VIL 2223h*2 2234h*2 BA V IL VIL VIL VIL VIH VIH VIH VIH 2200h Sector lock/ unlock Sector Addresses VIL VIL VIL VIL VIL VIL VIH VIL 01h*3 Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacture’s Code 0 4 h 0000000000000100 Device Code 227Eh 0010001001111110 Extended Device Code 2 2 2 3 h 0010001000100011 2 2 3 4 h 0010001000110100 2 2 0 0 h 0010001000000000 Sector Lock/ Unlock 0 0 h 0000000000000000 0 1 h 0000000000000001

nnnn FLEXIBLE SECTOR ERASE ARCHITECTURE Sector Address Table (Bank A, B) Bank Sector Sector Address Sector Size (Kwords) Address RangeBank Address A 18 A 17 A 16 A 15 A 14 A 13 A 20 A 19 Bank A S A 000000000 8 000000h to 001FFFh S A 100000001 8 002000h to 003FFFh S A 200000010 8 004000h to 005FFFh S A 300000011 8 006000h to 007FFFh S A 4000001XX 3 2 008000h to 00FFFFh S A 5000010XX 3 2 010000h to 017FFFh S A 6000011XX 3 2 018000h to 01FFFFh S A 7000100XX 3 2 020000h to 027FFFh S A 8000101XX 3 2 028000h to 02FFFFh S A 9000110XX 3 2 030000h to 037FFFh S A 1 0 000111XX 3 2 038000h to 03FFFFh S A 1 1 001000XX 3 2 040000h to 047FFFh S A 1 2 001001XX 3 2 048000h to 04FFFFh S A 1 3 001010XX 3 2 050000h to 057FFFh S A 1 4 001011XX 3 2 058000h to 05FFFFh S A 1 5 001100XX 3 2 060000h to 067FFFh S A 1 6 001101XX 3 2 068000h to 06FFFFh S A 1 7 001110XX 3 2 070000h to 077FFFh S A 1 8 001111XX 3 2 078000h to 07FFFFh Bank B S A 1 9 010000XX 3 2 080000h to 087FFFh S A 2 0 010001XX 3 2 088000h to 08FFFFh S A 2 1 010010XX 3 2 090000h to 097FFFh S A 2 2 010011XX 3 2 098000h to 09FFFFh S A 2 3 010100XX 3 2 0 A 0 0 00h to 0A7FFFh S A 2 4 010101XX 3 2 0 A 8 0 00h to 0AFFFFh S A 2 5 010110XX 3 2 0 B 0 0 00h to 0B7FFFh S A 2 6 010111XX 3 2 0 B 8 0 00h to 0BFFFFh S A 2 7 011000XX 3 2 0 C 0 0 00h to 0C7FFFh S A 2 8 011001XX 3 2 0 C 8 0 00h to 0CFFFFh S A 2 9 011010XX 3 2 0 D 0 0 00h to 0D7FFFh S A 3 0 011011XX 3 2 0 D 8 0 00h to 0DFFFFh S A 3 1 011100XX 3 2 0 E 0 0 00h to 0E7FFFh S A 3 2 011101XX 3 2 0 E 8 0 00h to 0EFFFFh S A 3 3 011110XX 3 2 0 F 0 0 00h to 0F7FFFh S A 3 4 011111XX 3 2 0 F 8 0 00h to 0FFFFFh

Sector Address Table (Bank C, D) Bank Sector Sector Address Sector Size (Kwords) Address RangeBank Address A 18 A 17 A 16 A 15 A 14 A 13 A 20 A 19 Bank C S A 3 5 100000XX 3 2 100000h to 107FFFh S A 3 6 100001XX 3 2 108000h to 10FFFFh S A 3 7 100010XX 3 2 110000h to 117FFFh S A 3 8 100011XX 3 2 118000h to 11FFFFh S A 3 9 100100XX 3 2 120000h to 127FFFh S A 4 0 100101XX 3 2 128000h to 12FFFFh S A 4 1 100110XX 3 2 130000h to 137FFFh S A 4 2 100111XX 3 2 138000h to 13FFFFh S A 4 3 101000XX 3 2 140000h to 147FFFh S A 4 4 101001XX 3 2 148000h to 14FFFFh S A 4 5 101010XX 3 2 150000h to 157FFFh S A 4 6 101011XX 3 2 158000h to 15FFFFh S A 4 7 101100XX 3 2 160000h to 167FFFh S A 4 8 101101XX 3 2 168000h to 16FFFFh S A 4 9 101110XX 3 2 170000h to 177FFFh S A 5 0 101111XX 3 2 178000h to 17FFFFh Bank D S A 5 1 110000XX 3 2 180000h to 187FFFh S A 5 2 110001XX 3 2 188000h to 18FFFFh S A 5 3 110010XX 3 2 190000h to 197FFFh S A 5 4 110011XX 3 2 198000h to 19FFFFh S A 5 5 110100XX 3 2 1 A 0 0 00h to 1A7FFFh S A 5 6 110101XX 3 2 1 A 8 0 00h to 1AFFFFh S A 5 7 110110XX 3 2 1 B 0 0 00h to 1B7FFFh S A 5 8 110111XX 3 2 1 B 8 0 00h to 1BFFFFh S A 5 9 111000XX 3 2 1 C 0 0 00h to 1C7FFFh S A 6 0 111001XX 3 2 1 C 8 0 00h to 1CFFFFh S A 6 1 111010XX 3 2 1 D 0 0 00h to 1D7FFFh S A 6 2 111011XX 3 2 1 D 8 0 00h to 1DFFFFh S A 6 3 111100XX 3 2 1 E 0 0 00h to 1E7FFFh S A 6 4 111101XX 3 2 1 E 8 0 00h to 1EFFFFh S A 6 5 111110XX 3 2 1 F 0 0 00h to 1F7FFFh S A 6 6 11111100 8 1 F 8 0 00h to 1F9FFFh S A 6 7 11111101 8 1 F A 0 00h to 1FBFFFh S A 6 8 11111110 8 1 F C 0 00h to 1FDFFFh S A 6 9 11111111 8 1 F E 000h to 1FFFFFh

Common Flash Memory Interface Code Table (CFI) (Continued) Description A 6 to A0 DQ 15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 2h: AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended T able 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended T able 19h 1Ah 0000h 0000h V CC Min (write/erase) DQ 7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 1Bh 0017h VCC Max (write/erase) DQ 7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 1Ch 0019h VPP Min voltage 1Dh 0000h VPP Max voltage 1Eh 0000h T ypical timeout per single byte/word write 2N ms 1Fh 0004h T ypical timeout for Min size buffer write 2N ms 20h 0000h T ypical timeout per individual block erase 2N ms 21h 0009h T ypical timeout for full chip erase 2N ms 22h 0000h Max timeout for byte/word write 2N times typical 23h 0004h Max timeout for buffer write 2N times typical 24h 0000h Max timeout per individual block erase 2N times typical 25h 0004h Max timeout for full chip erase 2N times typical 26h 0000h Device Size = 2N byte 27h 0016h Flash Device Interface description 28h 29h 0001h 0000h Max number of byte in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0003h Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0003h 0000h 0040h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 003Dh 0000h 0000h 0001h Erase Block Region 3 Information 35h 36h 37h 38h 0003h 0000h 0040h 0000h

(Continued) Description A 6 to A0 DQ 15 to DQ0 Erase Block Region 4 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0033h Address Sensitive Unlock 0h = Required 1h = Not Required 45h 0004h Erase Suspend 0h = Not Supported 1h = T o Read Only 2h = T o Read & Write 46h 0002h Sector Protection 0h = Not Supported X = Number of sectors in per group 47h 0001h Sector T emporary Unprotection 00h = Not Supported 01h = Supported 48h 0000h Sector Protection Algorithm 49h 0005h Simultaneous Operation 00h = Not Supported, X = T otal number of sectors in all Banks except Bank A 4Ah 0033h Burst Mode T ype 00h = Not Supported 4Bh 0001h Page Mode T ype 00h = Not Supported 4Ch 0000h ACC (Acceleration) Supply Minimum 00h = Not Supported, DQ 7 to DQ 4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 4Dh 00B5h ACC (Acceleration) Supply Maximum 00h = Not Supported, DQ 7 to DQ 4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 4Eh 00C5h Boot T ype 02h = Bottom Boot 03h = T op Boot 4Fh 0002h Program Suspend 00h = Not Supported, 01h = Supported 50h 0000h Bank Organization 57h 0004h Bank A Region Information 58h 0013h Bank B Region Information 59h 0010h Bank C Region Information 5Ah 0010h Bank D Region Information 5Bh 0013h

nnnn FUNCTIONAL DESCRIPTION Asynchronous Read Operation (Non-Burst) Mode When the device first powers up, it is enabled for asynchronous read operation. CLK is ignored in this operation. T o read data from the memory array, the system must first assert a valid address on A20 to A0, while driving AVD and CE to VIL. WE should remain at VIH. The rising edge of AVD latches the address or while AVD=V IL, address is latched by address change timing. The data will appear on DQ15 to DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC ) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE ) is the delay from the stable addresses and stable CE to valid data at the outputs. The output enable access time (tOE ) is the delay from the falling edge of OE to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. During power transition, RESET must be held low(Refer to "Power On/Off Timing Dia- gram").This ensures that no spurious alteration of the memory content occurs during the power transition. Synchronous (Burst) Read Operation Mode The device is capable of continuous sequential burst operation and linear burst operation of a preset length. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register set command sequence. See "Configuration Register Set Command" and "Command Definitions" for further details. Once the system has written the "Configuration Register Set" command sequence, the device Read mode is enabled for synchronous reads only. However Program operation is independent of the Configuration Register status. The initial word is output t IACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. The device will continue to output sequential burst data, wrapping around to address after it reaches the highest addressable memory location in group address range, until the system drives CE to VIH, RESET to VIL, or AVD to VIL in conjunction with a new address. See “MBM29BS/BT32LF User Bus Operations T able” in n DEVICE BUS OPERA TIONS. If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY indicates the length of the latency by pulsing low. 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see “MBM29BS/BT32LF User Bus Operations T able” in n DEVICE BUS OPERA TIONS). As an example: if the starting address in the 8-word with wrap-around mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group.

In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. The RDY pin indicates when data is valid on the bus in both asnchronous and synchronous read mode. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Simultaneous Operation The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A 20, A19)with zero latency. The device consists of the following four banks : Bank A : 4 X 8K word and 15 X 32K word; Bank B : 16 X 32K word; Bank C : 16 X 32K word; Bank D : 4 X 8K word and 15 X 32K word. The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. (See “FlexBank TM Architecture T able”.) This is what we call a “FlexBank”, for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or erase) operation. However, the different types of operations for the three banks are impossible, e.g. Bank A writing, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in “Example of Virtual Banks Combination T able”, the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multi-function mode in the same bank. “Simultaneous Operation T able” shows the possible combinations for simultaneous operation. (Refer to “(20) Bank-to-Bank Read/Write Cycle Timings” in n TIMING DIAGRAMS.) Burst Address Groups Table Mode Group Size Group Address Ranges 8-word with wrap-around 8 words 0-7h, 8-Fh, 10-17h, ... 16-word with wrap-around 16 words 0-Fh, 10-1Fh, 20-2Fh, ... 32-word with wrap-around 32 words 00-1Fh, 20-3Fh, 40-5Fh, ... FlexBank TM Architecture Table Bank Splits Bank 1 Bank 2 Volume Combination Volume Combination 1 8M bit Bank A 24M bit Remainder (Bank B, C, D) 2 16M bit Bank A, B 16M bit Remainder (Bank C, D)

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the Banks. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC ±0.2 V . Under this condition the current consumed is less than 5µA Max. During Embedded Algorithm operation, VCC active current (ICC2 ) is required even if CE=“H”. The device can be read with standard access time (tCE ) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE=“H” or “L”) . Under this condition the current consumed is less than 5µA Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of OE input. ICC3 in the DC Characteristics table represents the standby current specification. Example of Virtual Banks Combination Table Bank Splits Bank 1 Bank 2 Megabits Combination of Memory Bank Sector Sizes Megabits Combination of Memory Bank Sector Sizes 1 8M bit Bank A Four 8K word, fifteen 32K word 24M bit Bank B Bank C Bank D Four 8K word, forty-seven 32K word 2 16M bit Bank A Bank D Eight 8K word, thirty 32K word 16M bit Bank B Bank C thirty-two 32K word Simultaneous Operation Table Case Bank 1 Status Bank 2 Status

1 Read mode Read mode

2 Read mode Autoselect mode

3 Read mode Program mode

4 Read mode Erase mode

5 Autoselect mode Read mode

6 Program mode Read mode

7 Erase mode Read mode

Automatic sleep mode works to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC +60 ns. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. A new burst operations is required to provid new data. It is not necessary to control CE, WE, and OE on this mode. Under the mode, the current consumed is typically 0.2 mA (CMOS Level)(ICC5 ). During simultaneous operation, VCC active current (ICC2 ) is required. Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. Output Disable When the OE input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Autoselect Mode The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. Autoselect may only be entered and used when in the asynchronous mode. The manufacturer and device codes can be read via the command register, Three identifier bytes may then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A 7 to A0. (See “MBM29BS/BT32LF User Bus Operations T able” in n DEVICE BUS OPERA TIONS.) The command sequence is illustrated in “MBM29BS/BT32LF Command Definitions T able” (in n DEVICE BUS OPERA TIONS). (Refer to Autoselect Command section.) In the command Autoselect mode, the bank addresses BA; (A20, A19)must point to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank. A read cycle from address 00h returns the manufacturer’s code (Fujitsu=04h) . A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh and 0Fh. (Refer to “MBM29BS/BT32LF Sector Protection Verify Autoselect Codes T able” and “Expanded Autoselect Code T able” in n DEVICE BUS OPERA TIONS. ) Write Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine output dictates the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The device has the capability of performing programming operations. It has inputs/outputs that accept both address and data information. During a program operation(AVD latched address)(Program2), the command register is written by bringing active CLK edge while AVD and CE to VIL, and OE to VIH when providing an address to the device, addresses are latched on the CLK active edge or AVD rising edge(when CLK active edge doesn’t appear while AVD=VIL) and drive WE and CE to VIL, and OE to VIH, data is latched on the rising edge of WE. During a program operation(WE latched address)(Program1), the command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever

happens later, while data is latched on the rising edge of WE or CE(whichever happensfirst). Standard microprocessor write timings are used. The programming operations are independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. RESET (Hardware Reset) The RESET input provides a hardware method of re-setting the device to reading array data. When RESET is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS –0.2 V , the device draws CMOS standby current (ICC4 ). If RESET is held at VIL but not within VSS –0.2 V , the standby current will be greater. RESET may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (during Embedded Algorithms) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. Note that sectors must be unlocked by sector unlock command sequence(xxxh/60h, xxxh/60h, SLA/60h), prior to raising ACC to V ACC. When at VIL, ACC locks all sectors. Should be at VIH for all other conditions. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from ACC pin while programming. See “(15) Accelerated Fast mode Programming Timing” in n TIMING DIAGRAMS. <Protection> The MBM29BS/BT32LF features several levels of sector protection, which can disable both the program and erase operations (1) Write Protect (WP) [Hardware Protection] The device features a hardware protection option using a write protect pin that prevents programming or erasing. The WP pin is associated with the “outermost” 2 · 8K words on low end of boot sectors. The WP pin has no effect on any other sector. When WP is taken to VIL, programming and erase operations of the “outermost” 2 · · · · 8K words sectors are disabled. By taking WP back to VIH, the “outermost” 2 · 8K words sectors are enabled for program and erase operations, The user must hold the WP pin at either VIH or VIL during the entire program or erase operation of the “outermost” two sectors on low end of boot sectors(SA0 and SA1).

(2) ACC Protect (ACC) [Hardware Protection2] The device has also hardware protect feature by ACC pin. When ACC is VIL, all sectors are locked. Should be at VIH for all other condition (3) Software Command Locking(SCL) [Software Protection] The sector lock/unlock feature allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. T o unlock a sector, the system must write the sector lock/unlock command. Enhanced I/O (VCCQ ) Control The Enhanced I/O (VCCQ ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VCCQ pin. This allows the device to operate in 1.8 V and 3 V system environments as required. For example, a VCCQ of 2.70 V to 3.15 V allows for I/O at the 3-volt level, driving and receiving signals to and from other 3 V devices on the same bus.

Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the reading. “MBM29BS/BT32LF Command Definitions T able” in n DEVICE BUS OPERA TIONS shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ 7 to DQ0 and DQ15 to DQ8 bits are ignored. Asynchronous Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, verify mode of secter protect commands the Reset operation is initiated by writing the Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Asynchronous Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. While AVD = VIL, asynchronous read operation is same as conventional Fujitsu Flash memory. Addresses are latched by the rising edge of AVD or address change timing. tACC defined from address change timing or AVD falling edge, because addresses are input to internal circuit while AVD = VIL. If the device is used by AVD ratch asynchronous read operation, addresses should be kept from AVD falling edge to AVD rising edge or tACC defined by address change timing, not AVD falling edge. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Synchronous (Burst) Read Command This operation is enable after configuratrion register command is issued (A19 = 0). Addresses are latched by the AVD rising edge or CLK active edge while AVD = VIL. Configuration Register Set Command The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode(burst length), active clock edge, RDY configuration, and synchronous Read mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C0h, address bits A 11 to A0 should be 555h, address bits A19 to A12 set the code to be latched, and address bit A20 is Don’t care. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: "1’ for asynchronous mode, "0" for synchronous mode. Programmable Wait State Configuration Setting The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14 to A12 determine the setting (see “Third Cycle Address/Data T able”).The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency.

It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. “Wait State T able” describes the typical number of clock cycles (wait states) for conditions.The host system must set the appropriate number of wait states in the flash device depending on the clock frequency and the presence of a boundary crossing. Burst Read Mode Configuration Setting(Burst Length) The device supports three different burst read modes: 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then advances to the next 8-word boundary. The address pointer then returns to the 1st word after the previous eight-word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. “Burst Read Mode Settings T able” shows the address bits and settings for the three burst read modes. Third Cycle Address/Data Table A

14 A 13 A 12 Total Initial Access Cycles

Typical No. of Clock Cycles after AVD Low

40 MHz 54 MHz

Wait state for initial access 5 6 Burst Read Mode Settings Table Burst Modes Address Bits A 16 A 15 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1

Active Clock Edge Configuration Setting By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. Address bit A 17 determines this setting; "1" for rising active, "0" for falling active. RDY Configuration Setting By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; "1" for RDY active with data, "0" for RDY active one clock cycle before valid data. “Hardware Sequence Flags T able” shows the address bits that determine the configuration register settings for various device functions. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore, manufacture and device codes must be accessible while the device resides in the target system. PROM pro- grammers typically access the signature codes by raising A 9 to a higher voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming method- ology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. The higher order address (A 20, A19) required for reading out the manufacture and device codes demands the bank address (BA) set at the third write cycle. Following the command write, a read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu=04h). And a read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that two Configuration Register Table Address BIt Function Settings (Binary) A19 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) A18 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data A17 Clock 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK A16 Burst Read Mode 00 = Reserved 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around A A14 Programmable Wait State 000 = Data is valid on the 2th active CLK edge after AVD transition to VIH 001 = Data is valid on the 3th active CLK edge after AVD transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD transition to VIH 110 = Reserved 111 = Reserved A13 A12

additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. (Refer to “MBM29BS/ BT32LF Sector Protection Verify Autoselect Codes T able” and “Expanded Autoselect Code T able” in n DEVICE BUS OPERA TIONS. ) The sector state will be informed by address (SA)02h. Scanning the sector addresses (A 20, A19, A18, A17, A16, A15, A14, and A13) while(A7,A6, A5, A4, A3, A2, A1,A0) = (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verifying sector group protection on the protected sector. (See “MBM29BS/BT32LF User Bus Operations T able” in n DEVICE BUS OPERA TIONS.) The manufacture and device codes can be read from the selected bank. T o read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command sequence into the register. Autoselect command should then be written into the bank to be read. If the software (program code) for Autoselect command is stored in the Flash memory, the device and manu- facture codes should be read from the other bank, which does not contain the software. No subsequent data will be made available if the autoselect data is read in synchronous mode. T o terminate the operation, it is necessary to write the Read/Reset command sequence into the register. T o execute the Autoselect command during the operation, Read/Reset command sequence must be written before the Autoselect command. Word Programming Command The device is programmed on word-by-word basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. During a programming operation(AVD latched address)(Program2), the command register is written by bringing active CLK edge while AVD and CE to VIL, and OE to VIH when providing an address to the device, addresses are latched on the CLK active edge or AVD rising edge(when CLK active edge doesn’t appear while AVD=VIL). and drive WE and CE to VIL, and OE to VIH, data is latched on the rising edge of WE. During a programming operation(WE latched address)(Program1), the command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE(whichever happens first). Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ 7 (Data Polling), DQ6 (T oggle Bit). The Data Polling and T oggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see “Hardware Sequence Flags T able”). Therefore, the device requires that a valid address to the device be supplied by the system in this particular instance. Hence, Data Polling must be performed at the memory location which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert from “0”s to “1”s. “(2) Embedded Program TM Algorithm” in n FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Command Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. T wo more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ 7 (Data Polling), or DQ6 (T oggle Bit). The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time · All sectors + Chip Program Time (Preprogramming) “(3) Embedded EraseTM Algorithm” in n FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Command Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. T wo more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW ” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29BS/BT32LF Command Definitions T able” (in n DEVICE BUS OPERA TIONS). This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW ” otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t TOW ” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW ” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors. Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ 7 (Data Polling), or DQ6 (T oggle Bit). The sector erase begins after the “tTOW ” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to the read mode. Data polling and T oggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] · Number of Sector Erase. In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed.

“(3) Embedded EraseTM Algorithm” in n FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume Command The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONL Y during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CARES” when writting the Erase Suspend or Erase Resume command.When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “t SPD ” to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the Data polling of DQ7 or by the T oggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. T o resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Sector Lock/Unlock Command(Software Command Locking(SCL)) The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. T o unlock a sector, the system must write the sector lock/unlock command sequence. T wo cycles are first written: addresses are don’t care and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) is written, while specifying with address A 6 whether that sector should be locked (A6 = VIL) or unlocked (A6 = VIH). After the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing F0h (reset command). Note that the last two outermost boot sectors can be locked by taking the WP signal to VIL.

(1) Fast Mode The device has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. T o exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to “(6) Embedded Programming Algorithm for Fast Mode” in n FLOW CHART .) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (P A/PD). (Refer to “(6) Embedded Programming Algorithm for Fast Mode” in n FLOW CHART .) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward- compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ 15 to DQ8) is “0” in word mode (16 bit) read. Refer to the CFI code table. T o terminate operation, it is necessary to write the Read/Reset command sequence into the register. WRITE OPERATION STATUS Detailed in “Hardware Sequence Flags T able” are all the status flags which can determine the status of the bank for the current mode operation. The read operation from the bank which doesn’t operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The information on DQ 2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1] and [3].

*1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. *3: When the device is set to Asynchronus mode, these status flags should be read by CE toggle. Notes:• DQ 0 and DQ1 are reserve pins for future use.

• DQ4 is limited to Fujitsu internal use. DQ 7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a complement of data last written to DQ 7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “(4) Data Polling Algorithm” (in n FLOW CHART). For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro- tected sectors. Otherwise the status may become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 ms, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 ms, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information Hardware Sequence Flags Table Status DQ 7 DQ 6 DQ 5 DQ 3 DQ 2 In Progress Embedded Program Algorithm DQ 7 Toggle 0 0 No toggle Embedded Erase Algorithm Erase Sector

0 Toggle 0 1

Toggle * Non-Erase Sector No toggle Erase Suspended Mode Erase Suspend Read (Erase Suspended Sector) 1 No toggle *3 0 0 Toggle Erase Suspend Read (Non-Erase Suspended Sector) Data Data Data Data Data Erase Suspend Program (Non-Erase Suspended Sector) DQ 7 Toggle 0 0 1 * 2,*3 Exceeded Time Limits Embedded Program Algorithm DQ 7 Toggle 1 0 No toggle Embedded Erase Algorithm 0 Toggle 1 1 N/A Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) DQ 7 Toggle 1 0 N/A

on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to DQ 7 will be read on successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See “T oggle Bit Status T able”.) See “(14) Chip/Sector Erase Command Sequence”, “(16) Data Polling Timings (During Embedded Algorithm)” in n TIMING DIAGRAMS for the Data Polling timing specifications and diagrams. DQ 6 T oggle Bit I The device also features the “T oggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the T oggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the T oggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The T oggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 ms and then stop toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data kept remained. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ 6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. T o operate toggle bit function properly, CE or OE must be high when bank address is changed. See “(15) Accelerated Fast mode Programming Timing”, “(16) Data Polling Timings (During Embedded Algorithm)” in n TIMING DIAGRAMS for the T oggle Bit I timing specifications and diagrams. DQ 5 Exceeded Timing Limits DQ 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in “MBM29BS/BT32LF User Bus Operations T able” in n DEVICE BUS OPERA TIONS. The DQ 5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset device with the command sequence.

After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain low until the time-out is completed. Data Polling and T oggle Bit are valid after the initial sector erase command sequence. If Data Polling or the T oggle Bit I indicates that a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. T o insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags T able” DQ 2 T oggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ 2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ 6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ 2 toggles while DQ6 does not.) See also “T oggle Bit Status T able”. Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. T o operate toggle bit function properly, CE or OE must be high when bank address is changed. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. T ypically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ 7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ 5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to “(5) T oggle Bit Algorithm” in n FLOW CHART .)

*: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. RDY: Ready The RDY is a dedicated output that, by default, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. RDY functions only while reading data in burst mode. The following condition causes the RDY output to be low: during the initial access (in burst mode). Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequence. Device also incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. T o initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. Toggle Bit Status Table Mode DQ 7 DQ 6 DQ 2 Program DQ 7 Toggle 1 Erase 0 Toggle Toggle * Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle Erase-Suspend Program DQ

7 Toggle 1 *

nnnn ABSOLUTE MAXIMUM RATINGS *1: Minimum DC voltage on input or l/O pins are –0.5 V . During voltage transitions, inputs may underrshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and l/O pins are VCC +0.5 V . During voltage transitions, outputs may overshoot to VCC +2.0 V for periods of up to 20 ns. *2: Minimum DC input voltage on ACC pin is –0.5 V . During voltage transitions, ACC pin may undershoot VSS to – 2.0 V for periods of up to 20 ns. Maximum DC input voltage on ACC pin is +10.5 V which may overshoot to +12.5 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (V IN - VCC ) do not exceed 9 V . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS Note: Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating UnitMin Max Storage Temperature Tstg –55 +125 °C Ambient Temperature with Power Applied T A –40 +85 °C Voltage with Respect to Ground All inputs and I/Os pins except as noted below *1 VIN, VOUT –0.5 V CCQ +0.5 V Power Supply Voltage *1 VCC –0.5 +2.5 V I/O’s Power Supply Voltage V CCQ –0.5 +3.5 V ACC *2 VACC –0.5 +10.5 V Parameter Symbol Part No. Value UnitMin Max Ambient Temperature T A MBM29BS/BT32LF 18/25 –40 +85 °C Power Supply Voltage V CC MBM29BS/BT32LF 18/25 +1.65 +1.95 V VCCQ Supply Voltage V CCQ MBM29BS32LF 18/25 +1.65 Vcc V MBM29BT32LF 18/25 +2.70 +3.15 V

*1: The lCC current listed includes both the DC operating current and the frequency dependent component. *2: lCC active while Embedded Algorithm (Program or Erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remain stable for tACC + 60 ns. *4: Embedded Algorithm (Program or Erase) is in progress.(@5 MHz) *5: Applicable for only Vcc. Parameter Description Symbol Conditions Value Unit Min Typ Max Input Leakage Current I LI VIN = VSS to Vcc, VCC = Vcc Max — — –1.0 µA Output Leakage Current I LO VOUT = VSS to Vcc, VCC = Vcc Max — — –1.0 µA VCC Active Burst Read Current ICCB CE = VIL, OE = VIH, WE =VIH (54MHz) ——2 5 m A VCC Active Asynchronous Read Current*1 ICC1 CE = VIL, OE = VIH, WE = VIH

5 MHz

1 MHz 3.3 5 VCC Active Current*2 ICC2 CE = VIL, OE = VIH, VPP = VIH —1 54 0 m A VCC Current (Standby) I CC3 CE = RESET = VCC –0.2 V , VIN £0.2V VCCQ = 1.8 V — 0.2 10 µA VCCQ = 3.0 V — 0.2 10 µA VCC Current (Standby, Reset)*3 ICC4 RESET = VIL, CLK = VIL VCCQ = 1.8 V — 0.2 10 µA VCCQ = 3.0 V — 0.2 10 µA VCC Current (Automatic Sleep Mode)*3 ICC5 Vcc=Vcc Max, CE = VSSQ – 0.2 V , RESET = VCCQ –

0.2 V , VIN = VCCQ –

0.2 V or VSSQ – 0.2 V VCCQ = 1.8 V — 0.2 10 µA VCCQ = 3.0 V — 0.2 10 µA VCC Active Current (Read-While-Program )*4 ICC6 CE = VIL, OE = VIH —2 56 0 m A VCC Active Current (Read-While-Erase )*4 ICC7 CE = VIL, OE = VIH —2 56 0 m A Input Low Level V IL — VCCQ = 1.8 V –0.5 — 0.2 V VCCQ = 3.0 V –0.5 — 0.4 V Input High Level V IH — VCCQ = 1.8 V VCCQ –0.2 — V CCQ +0.2 V VCCQ = 3.0 V VCCQ –0.4 — V CCQ +0.4 V Output Low Voltage Level V OL IOL = 100 µA, VCC = VCC Min = VCCQ —— 0 . 1V Output High Voltage Level V OH IOH = –100 µA, VCC = VCC Min = VCCQ VCCQ –0.1 — — V Voltage for ACC Program Acceleration*5 VACC —8 . 5 — 9 . 5 V

• Synchronous/Burst Read *: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD. Note: T est Conditions: Output Load: VCCQ =1.65 V to 1.95 V :30 pF(MBM29BS32LF) VCCQ =2.7 V to 3.15 V : 30 pF(MBM29BT32LF) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCQ Timing measurement reference level Input: 0.5 · VCCQ Output: 0.5 · VCCQ Parameter Symbol BS32LF BT32LF Unit-25 (40 MHz) -18 (54 MHz) -25 (40 MHz) -18 (54 MHz) JEDEC Standard Min Max Min Max Min Max Min Max Latency — t IACC ¾ 120 ¾ 106 ¾ 120 ¾ 106.5 ns Burst Access Time Valid Clock to Output Delay —t BACC ¾ 20 ¾ 13.5 ¾ 20 ¾ 14 ns AVD Setup Time to CLK — t AVDS 5 ¾ 5 ¾ 5 ¾ 5 ¾ ns Address Setup Time to CLK * —t ACS 5 ¾ 5 ¾ 5 ¾ 5 ¾ ns Address Hold Time from CLK * — t ACH 7 ¾ 7 ¾ 7 ¾ 7 ¾ ns Data Hold Time from Next Clock Cycle —t BDH ¾ 4 ¾ 4 ¾ 4 ¾ 4n s Output Enable to Output Valid — t OE ¾ 20 ¾ 13.5 ¾ 20 ¾ 14 ns Chip Enable to High-Z — t CEZ ¾ 10 ¾ 10 ¾ 10.5 ¾ 10.5 ns Output Enable to High-Z — t OEZ ¾ 10 ¾ 10 ¾ 10.5 ¾ 10.5 ns CE Setup Time to CLK — t CES 5 ¾ 5 ¾ 5 ¾ 5 ¾ ns RDY Setup Time to CLK — t RDYS 5 ¾ 5 ¾ 4.5 ¾ 4.5 ¾ ns Ready Access Time from CLK — t RACC ¾ 20 ¾ 13.5 ¾ 20 ¾ 14 ns Address Setup Time to AVD *—t AAS 5 ¾ 5 ¾ 5 ¾ 5 ¾ ns Address Hold Time to AVD *— t AAH 7 ¾ 7 ¾ 7 ¾ 7 ¾ ns CE Setup Time to AVD —t CAS 0 ¾ 0 ¾ 0 ¾ 0 ¾ ns AVD Low to CLK — t AVC 5 ¾ 5 ¾ 5 ¾ 5 ¾ ns AVD Pulse — t AVD 12 ¾ 12 ¾ 12 ¾ 12 ¾ ns Access Time — t ACC ¾ 70 ¾ 70 ¾ 70 ¾ 70 ns

• Asynchronous Read *1: Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD. *2: Addresses are latched on the rising edge of AVD or Address change timing.
• Hardware Reset (RESET) Parameter Symbol BS32LF BT32LF Unit JEDEC Standard Min Max Min Max Access Time from CE Low — t CE ¾ 70 ¾ 70 ns Asynchronous Access Time *1 —t ACC ¾ 70 ¾ 70 ns AVD Low Time — t AVDP 12 ¾ 12 ¾ ns Address Setup Time to Rising Edge of AVD — t AAVDS 5 ¾ 5 ¾ ns Address Hold Time from Rising Edge of AVD — t AAVDH 7 ¾ 7 ¾ ns Output Enable to Output Valid — t OE ¾ 20 ¾ 20.5 ns Output Enable Hold Time Read —t OEH 0 ¾ 0 ¾ ns T oggle and Data Polling 10 ¾ 10 ¾ ns Output Enable to High-Z *2 —t OEZ ¾ 10 ¾ 10.5 ns CE Setup Time to AVD —t CAS 0 ¾ 0 ¾ ns Parameter Symbol All Speed Options Unit JEDEC Standard Min Max RESET Pin Low (During Embedded Algorithms) to Read Mode —t READY ¾ 20 µs RESET Pulse Width — t RP 500 ¾ ns Reset High Time Before Read — t RH 200 ¾ ns Power On/Off Time — t PS 0 ¾ ns

• Write (Erase/Program) Operations *1: In Program 1 timing, addresses are latched on the falling edge of WE. In Program 2 timing, addresses are latched on the first of either the rising edge of AVD or the active edge of CLK. *2: See the "Erase and Programming Performance" section for more information. *3: Does not include the preprogramming time. Parameter Symbol All Speed Options Unit JEDEC Standard Min Typ Write Cycle Time t AVAV tWC 80 ¾ ns Address Setup Time Program 1(WEor CLK) tAVWL tAS 0 ¾ ns Program 2(AVD or CLK) 5 ¾ Address Hold Time *1 Program 1(WE or CLK) tWLAX tAH 45 ¾ ns Program 2(AVD or CLK) 7 ¾ AVD Low Time — t AVDP 12 ¾ ns Data Setup Time t DVWH tDS 45 ¾ ns Data Hold Time t WHDX tDH 0 ¾ ns Read Recovery Time Before Write t GHWL tGHWL 0 ¾ ns CE Setup Time to AVD —t CAS 0 ¾ ns CE Hold Time t WHEH tCH 0 ¾ ns Write Pulse Width t EHWH tWP 50 ¾ ns Write Pulse Width High t WHWL tWPH 30 ¾ ns Latency Between Read and Write Operations — t SR/W 0 ¾ ns Programming Operation *2 tWHWH1 tWHWH1 ¾ 8µ s Accelerated Programming Operation *2 tWHWH1 tWHWH1 ¾ 2.5 µs Sector Erase Operation *2, *3 tWHWH2 tWHWH2 ¾ 0.5 s Chip Erase Operation *2, *3 ¾ 35.0 VACC Rise and Fall Time — t VID 500 ¾ ns VACC Setup Time (During Accelerated Programming) —t VIDS 1 ¾ µs VCC Setup Time — t VCS 50 ¾ µs CE Setup Time to WE tELWL tCS 0 ¾ ns AVD Setup Time to WE —t ASW 5 ¾ ns AVD Hold Time to WE —t AHW 5 ¾ ns Address Setup Time to CLK *1 —t ACS 5 ¾ ns Address Hold Time to CLK *1 —t ACH 7 ¾ ns AVD Hold Time to CLK — t AVCH 5 ¾ ns WE Low to CLK — t WLC 0 ¾ ns CLK to WE Low — t CWL 5 ¾ ns

nnnn ERASE AND PROGRAMMING PERFORMANCE Note : T est conditions TA = +25°C, T ypical Erase conditions TA = +25°C, VCC = 1.8 V T ypical Program conditions TA = +25°C, VCC = 1.8 V , Data = checker nnnn FBGA PIN CAPACITANCE Note : T est conditions TA = +25°C, f = 1.0 MHz Parameter Limit Unit Comments Min Typ Max Sector Erase Time — 0.5 2.0 s Excludes programming prior to erasure Word Programming Time — 6 100 µs Excludes system level overhead Chip Programming Time — 25.2 95 s Excludes system level overhead Erase/Program Cycle 100,000 cycle — Parameter Symbol Test Setup Typ Max Unit Input Capacitance C IN VIN = 0 TBD TBD pF Output Capacitance C OUT VOUT = 0 TBD TBD pF Control Pin Capacitance C IN2 VIN = 0 TBD TBD pF

• Key to Switching Wavwforms (1) Synchronous Burst Mode Read (Latched By Rising Active CLK) Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High-Z) Da Da + 1 Da + n OE DQ 15 to DQ 0 A20 to A0 Aa AVD RDY CLK CE tCES tACS tAVDS tAVD tACH tOE tRACC tOEZ tCEZ tIACC tACC tBDH 7 cycles for initial access shown. High-Z High-Z High-Z 1234567 tRDYS tBACC Notes:• Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles.
• The device is in synchronous mode.

(2) Synchronous Burst Mode Read (Latched By Falling Active CLK) (3) Synchronous Burst Mode Read(Latched By AVD Active Edge) Notes:• Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge.

• The device is in synchronous mode. Da Da + 1 Da + n OE DQ 15 to DQ0 A20 to A0 Aa AVD RD Y CLK CE tCES tACS tAVDS tAVD tACH tOE tOEZ tCEZ tIACC tACC tBDH 4 cycles for initial access shown. tRACC High-Z High-Z High-Z 1234 5 tRDYS tBACC Da Da + 1 Da + n OE DQ 15 to DQ0 A20 to A0 Aa AVD RDY CLK CE tCAS tAAS tAVC tAVD tAAH tOE tRACC tOEZ tCEZ tIACC tBDH 7 cycles for initial access shown. High-Z High-Z High-Z 1234567 tRDYS tBACC tACC Notes:• Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge.
• The device is in synchronous mode.

(4) 8-word Linear Burst With Wrap Around (5) Burst with RDY Set One Cycle Before Data D6 D7 OE DQ 15 to DQ0 A20 to A0 Aa AVD RDY CLK CE tCES tACS tAVDS tAVD tACH tOE tIACC tBDH D0 D1 D5 D6 7 cycles for initial access shown. 18.5 ns Typ (54 MHz) High-Z tRACC 12 34567 tRDYS tBACC tACC Note: Figure assumes 7 wait states for initial access, 54 MHz clock, synchronous read. D0 to D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A 6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command se- quence has been written with A 18 = 1; device will output RDY with valid data. D1D0 D2 D3 Da + n OE DQ 15 to DQ0 A20 to A0 Aa AVD RDY CLK CE tCES tACS tAVDS tAVD tACH tOE tRACC tOEZ tCEZ tIACC tBDH 6 wait cycles for initial access shown. 25 ns Typ (40 MHz) High-Z High-Z High-Z 12 3456 tRDYS tBACC tACC Note: Figure assumes 6 wait states for initial access, 40 MHz clock, and synchronous read. The Set Configuration Register command sequence has been written with A18 = 0; device will output RDY one cycle before valid data.

(6) Asynchronous Mode Read With AVD Latched (7) Asynchronous Mode Read With AVD Stable Low tCEWE A20 to A0 CE OE Valid RD tACC tOEH tOE DQ 15 to DQ0 tOEZ tAAVDH tAVDP tAAVDS AVD RA tCAS Note: RA = Read Address, RD = Read Data. tCEWE A20 to A0 CE OE Valid RD tACC tOEH tOE DQ 15 to DQ0 tOEZ AVD RA tCAS Note: RA = Read Address, RD = Read Data.

(8) Reset Timings (9) Power On/Off Timings RESET tRP Reset Timings NOT during Embedded Algorithms tREADY CE, OE tRH CE, OE Reset Timings during Embedded Algorithms RESET tRP RESET Data Address Valid Data Out tPS tPS VCC Valid Data In Vcc Min 1.65 V tRH tACC 0 V 1.65 V

(10) Programming Operation Timings (WE latched address at CLK=VIL) (Program1 WE) OE CE Data Address AVD WE CLK VCC 555h PD tAS tASW tAHW tAH tWC tWPH PA tVCS tWP tDH tCH InProgress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS VIL tAVDP A0h tCS Notes:• P A = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

• “In progress” and “complete” refer to status of program operation.
• A20 to A12 are don’t care during command sequence unlock cycles.
• CLK must be fixed at VIL.(Don’t be fixed at VIH)
• Either CE or AVD is required to go from low to high in between programming command sequences.
• The Programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register.

(11) Programming Operation Timings (AVD latched address at CLK=VIL) (Program1 AVD) Notes:• P A = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

• “In progress” and “complete” refer to status of program operation.
• A20 to A12 are don’t care during command sequence unlock cycles.
• CLK must be fixed at VIL.(Don’t be fixed at VIH)
• Either CE or AVD is required to go from low to high in between programming command sequences.
• The programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. OE CE Data Address AVD WE CLK VCC 555h PD tAS tAH tWC tWPH PA tVCS tWP tDH tCH InProgress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS VIL tAVDP A0h tCS

(12) Programming Operation Timings (WE or CLK latched address) (Program1 WE or CLK ) OE CE Data Address AVD WE CLK VCC 555h PD tWP tWC tWPH PA tVCS tDH tCH InProgress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS tAVDP A0h tWLC tACS tCAS tACH tAVCH Notes:• P A = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

• “In progress” and “complete” refer to status of program operation.
• A20 to A12 are don’t care during command sequence unlock cycles.
• Addresses are latched on the first of either the rising edge of WE or the active edge of CLK. If CLK active edge will not appear until WE falling edge, program timing become programming operation (WE latched address).
• Either CS or AVD is required to go from low to high inbetween programming command sequences.
• The programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register.

(13) Programming Operation Timings (AVD or CLK latched address) (Program2 AVD or CLK) Notes:• P A = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

• “In progress” and “complete” refer to status of program operation.
• A20 to A12 are don’t care during command sequence unlock cycles.
• Addresses are latched on the first of either the rising edge of AVD or the active edge of CLK. If CLK active edge will appear while AVD=V IL, program timing become Program operation (CLK latched address).
• Either CS or AVD is required to go from low to high inbetween programming command sequences.
• The Program operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. OE CE Data Address AVD WE CLK 555h PD tWP tWC tWPH PA tAS tDH tCH InProgress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS tAVDP A0h tCWL tAVCH tAH tVCS Vcc tCAS

(14) Chip/Sector Erase Command Sequence OE CE Data Address AVD WE CLK VCC tAS tWP tAH tWC tWPH SA tVCS tCS tDH tCH In Progress tWHWH2 VA Complete VA Erase Command Sequence (last two cycles) Read Status Data tDS 10h for chip erase 555h for chip erase VIH VIL tAVDP 55h 2AAh 10h/30h Notes:• SA is the sector address for Sector Erase.

• Address bits A20 to A12 are don’t cares during unlock cycles in the command sequence.

(15) Accelerated Fast mode Programming Timing (16) Data Polling Timings (During Embedded Algorithm) CE AVD WE Address Data OE ACC Don't Care Don't CareA0h Don't Care PA PD VID 1ms VIL or VIH tVID tVIDS Note: Use setup and hold times from conventional program operation. WE CE OE tOE Address AVD tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Notes:• Status reads in figure are shown as asynchronous.

• VA = Valid Address. T wo read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data Polling will output true data.

(17) Toggle Bit Timings (During Embedded Algorithm) (18) Synchronous Read Data Polling Timings/Toggle Bit Timings WE CE OE tOE Address AVD tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Notes:• Status reads in figure are shown as asynchronous.

• VA = Valid Address. T wo read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. CE CLK AVD Address OE Data RDY Status Data Status Data VA VA tIACC tIACC Notes:• The timings are similar to synchronous read timings.
• VA = Valid Address. T wo read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
• RDY is active with data (A18 = 1in the Burst Mode Configuration Register). When A18 = 0 in the Burst Mode Configuration Register, RDY is active one clock cycle before data.

(19) Example of Wait States Insertion Data AVD OE CLK 12345 D0 D1 total number of clock cycles following AVD falling edge Rising edge of next clock cycle following last wait state triggers next burst data Wait State Decoding Addresses: A14, A13, A12 = "101" Þ 7 cycles A14, A13, A12 = "100" Þ 6 cycles A14, A13, A12 = "011" Þ 5 cycles A14, A13, A12 = "010" Þ 4 cyclesl A14, A13, A12 = "001" Þ 3 cycles A14, A13, A12 = "000" Þ 2 cycles Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.

(20) Bank-to-Bank Read/Write Cycle Timings OE CE WE tOEH Data Address AVD PD/30h AAh RAPA/SA tWC tDS tDH tRC tRC tOE tAS tAH tACC tOEH tWP tGHWL tOEZ tWC tSR/W Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence RD RA 555h RD tWPH Note: Break points in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

(1) Synchronous/Asynchronous State Diagram (Read Mode) Power-up/ Hardware Reset Asynchronous Read Mode Only Synchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (A19 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (A19 = 1)

(2) Embedded ProgramTM Algorithm No Yes Start Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Write Program Command Sequence (See Below) Data Polling Device Increment Address Verify Data Program Address/Program Data Programming Completed Last Address Yes No EMBEDDED ALGORITHM Embedded Program Algorithm in progress

(3) Embedded EraseTM Algorithm 555h/AAh 2AAh/55h 555h/AAh 555h/80h 555h/10h 2AAh/55h 555h/AAh 2AAh/55h 555h/AAh 555h/80h 2AAh/55h Additional sector erase commands are optional. Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): Sector Address/30h Sector Address/30h Sector Address/30h Start Data = FFh No Yes EMBEDDED ALGORITHM Embedded Erase Algorithm in progress Notes:• See “MBM29BS/BT32LF Command Definitions T able” in n DEVICE BUS OPERA TIONS for erase command sequence.

• See the section on DQ3 for information on the sector erase timer.

(4) Data Polling Algorithm *: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Fail DQ 7 = Data? No No DQ 7 = Data? DQ 5 = 1? Pass Yes Yes No Start Read Byte (DQ 7 to DQ0) Addr. = VA Read Byte (DQ 7 to DQ0) Addr. = VA Yes

(5) Toggle Bit Algorithm Toggle Bit = Toggle? Yes No Toggle Bit = Toggle? DQ 5 = 1? Yes No No Yes Read (DQ 7 to DQ 0) Addr. = VA Read (DQ 7 to DQ 0) Addr. = VA Read (DQ 7 to DQ 0) Addr. = VA Start *1, *2 Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Read (DQ 7 to DQ 0) Addr. = VA *1, *2 VA = Bank address being executed Embeded Algorithm. *1 : Read toggle bit twice to determine whether or not it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.

(6) Embedded Programming Algorithm for Fast Mode Yes No 555h/AAh Verify Data? Start FAST MODE ALGORITHM 555h/20h 2AAh/55h XXXXh/A0h Program Address/Program Data Data Polling Device Last Address Programming Completed XXXXh/90h XXXXh/F0h Increment Address Yes No Set Fast Mode In Fast Program Reset Fast Mode

Part No. Package Access Time(ns) Remarks MBM29BS32LF18PBT MBM29BS32LF25PBT 60-pin plastic FBGA (BGA-60P-M05) MBM29BT32LF18PBT MBM29BT32LF25PBT MBM29BS/BT32 L F XX XXX DEVICE NUMBER/DESCRIPTION MBM29BS32

32 Mega-bit (2M · 16-Bit) Burst Mode Flash Memory

1.8 V-only Read, Write, and Erase with 1.8V V CCQ MBM29BT32

32 Mega-bit (2M · 16-Bit) CMOS Burst Mode Flash Memory

1.8 V-only Read, Write, and Erase with 3.0 V VCCQ PAC K AG E T Y P E PBT= 60-Ball Fine Pitch Ball Grid Array Package (FBGA) for Engineering Sample SPEED OPTION See Product Selector Guide 18=54MHz, 25=40MHz DEVICE REVISION SECTOR PROTECTION L = Lower Sector Address

C 2003 FUJITSU LIMITED B60005S-c-1-1 .043–.005 +.005 –0.13 +0.12 1.08 (Mounting height) 0.38±0.10 (.015±.004)(Stand off) ABCDEFGH A 0.40(.016) REF 0.80(.031) REF B 0.10(.004) (.315±.004) 8.00±0.10 S 60-ø0.45±0.05 (INDEX AREA)(INDEX AREA) 60-ball plastic FBGA (BGA-60P-M05) Dimensions in mm (inches) . Note : The values in parentheses are reference values.

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