MBM2212-20 FUJITSU | Alldatasheet

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1024-BIT NON-VOLATILE STATIC RANDOM Edition 3.0 ACCESS MEMORY ‘The Fujitsu MBM 2212 is a 1024-bit non-volatile static random access memory (NVRAM) combined 1024 bit static random access memory (SRAM) and electrically erasable programmable read only memory (EEPROM) on one-chip. It is designed for applications such as system potentiometer or electrical switch to memorize the system condition etc. The MBM 2212 is organized as 256 words by 4 bit. Each one word is con: stituted with a pair of SRAM and EEPROM cell. The read and write operations are performed on the SRAM cell, The data transfer between SRAM and EEPROM is performed using two control pins. The store mode (transfering SRAM data to EEPROM) is executed with one shot pulse applied to ST pin in 10ms. The recall mode (transfering EEPROM data to SRAM) is executed with one shot pulse applied to RC pin in 1.2us. Both store and recall opera CERAMIC PACKAGE tions are completed all bits at one time (CERDIP) ‘The MBM 2212 is fabricated using N-MOS silicon gate technology with floating DIP-18C-Cor gate cells. Single +5V supply and TTL input/output level operations greatly facilitate microprocessor applications. ‘© 256 words x 4 bit organization, fully decoded y © 10ms self-timed auto store ‘© 10 years data retention for each store ‘© Unlimited endurance for recall PuAeasnene ‘© TTL compatible inputs/outputs piraispnge © Tristate output 7 ‘© Write protection on power-on/off and surge pulse ‘© Low power consumption; ‘Active: 330mW max PIN ASSIGNMENT Standby: 165mW max. © Fast access time; 200ns max. (MBM 2212-20) ach 181) Vee 250ns max, (MBM 2212-25) A «C]2 7 ‘© Standard 18 pin CERAMIC DIP package: Suffix:Z q pas ‘© Standard 18 pin PLASTIC DIP package: Suffix-P AaoC]3 re As © Pin compatible with Xicor X2212 AoCla 1504 ABSOLUTE MAXIMUM RATINGS (See NOTE) Ai({s Tor view r4f 1/03 ‘Supply Voltage with Respect to GND Veo Vv sd; 210, aputl wit H No} We Ail Input/Output Voltage with Vw. Vour |-1.000070| v Ce utwe Respect to GND #I _ {| — — Ce ld Output Current with Respect to GND. lout +50 | ma | Temperature under Bias Taras | 1010 +85 | °C Storage Temperature Tera | 6510 +125 | °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM [This device contains circuitry to protect the RATINGS are exceeded, Functional operation should be restricted to | Inputs auhinst damage due to high static olt, | the conditions as detailed in the operational sections of this data that normal precautions be taken to avoid sheet. Exposure to absolute maximum rating conditions for extended | application of any voltage higher than maxi: periods may affect device reliability. | i,t woes oe hah edn ee 7-3

Fig. 1 — MBM 2212 BLOCK DIAGRAM. / | EPROM CELL ARRAY /” ——~ end Ago am — GHA store) |—ost ° CALL rs CE now sy cau array | ee seveer Zoot CELL MATRIC A20 te As0 te a | Vv0z0 (> INPUT No ciRcuIT | fe ona. COLUMN SELECT vose— Ht @ i ire | VO4e > T TI } u RAAL | | | <q | Bo tT) WG Ir 5 Wo <] rT) Y | ‘incur CAPACITANCE (tq = 25°c, = 1 mie) a a

170 Capacitance Wp = OV) a

MBM2212-25 _ ili ee ee wie [ve va | vw | vm fey | | oe | aoe | Vie Vin High-2 sv Vow Vi High-Z 5V Active [vm | x | Note: X Can be either Vi_ or Ving (Referenced to GND) Suoeiy Vale ve | 48 | so [oss [ov | [reine wf ee tees ec Note: * For less than 50ns undershoot, but ~0.5V for DC. (Recommended operating conditions unless otherwise noted.) Input Leakage Current Vw = GND 10 5.5V 1/0 Leakage Current CS = Vin, Vyo = GND to 5.5V 110 uA Voc Standby Current CS = Vin. Veo = 4.5V to 5.5V, Io = OMA"? {30 mA Vee Active Current CS = Vin. Vee = 5.5V, Iyo = OMA‘? lee 60 | ma Output Low Level lou = 4.2m Vou oa Output High Level low = =2.0mA Von | 24 Store Inhibit Vee Voltage Vier lor Note: *1 Supply current increases to loc while store mode regardless of GS level. *2. Supply current reduces to Isq while recall mode regardless of CS level. 7-5

‘ea FUJITSU MBM2212-20 i) MBM2212-25 (Recommended operating conditions unless otherwise noted.) READ MODE (WE =ST=RC= Vi) mo A re Note: * Transition is measured at point of +500mV from steady state voltage. READ CYCLE TIMING DIAGRAM (WE = V,,, for Read Cycle) ADDRESS CONTROL MODE] (CS = V,., WE = Vi) tre. Vw tsa— ton: Vou~ DATA PREVIOUS DATA DATA VALIO Vou. CS CONTROL MODE" ] (WE =v...) = Via S va- tz tacs Vor AT nich 4 Co ncetined ate Note: “Address valid prior to or coincident with CS transition low. 7-6

‘reat MBM2212-20 FUJITSU MBM2212-25 _ WNASII/I/IN| WRITE MODE (ST = RC = Vy) Pee | ome | |e — a [wiemomtas em P [omviewencorme ee ef Note: *1 twa is defined from the end point of write. *2. Transition is measured at point of $600mV from steady state voltage *3. If CS goes high coincident with WE high transition, DATA OUT remains in a high impedance state. WRITE CYCLE TIMING DIAGRAM WE CONTROL MODE we: Vin~ Vu ss we Sw eh ——tas: twp] twa: we Vin Vim DATA IN q DATA VALID , vi twz tow: pata our Yow NGHZ You- Note: + 1f CS goes high simultaneously with WE high transition, OATA OUT remains ina high impedance state

WRITE CYCLE TIMING DIAGRAM ES CONTROL MODE ee Yim b+—<tas- ad wr a Vine ss Yum we: we Yin me VOM MVILLLLLL tow ——~| 4:0 Vie vim biel DATA OUT OH Ze You- AC TEST CONDITIONS (including EEPROM mode) Input Pulse Levels: 0.6V to24V Input Rise/Falt Times: <10ns “D> Input Reference Levels: 0.8V,2.2V cL Output Reference Levels: 0.8V, 2.2V J Output Load 1 TTL gate and C, = 100pF 7-8

MBM2212-25,_ lili ‘The MBM 2212 can not read or write EEPROM data externally and it must be transferred from/to SRAM cell array corre- sponding to each EEPROM bit. RC and ST pins are assigned to execute these operation easily. RECALL MODE ‘The recali mode is initiated when negative pulse (Lr) is applied to RC pin while either CS = V,4, or WE = V\\,, and is completed within 1.2us. The supply current is reduced to standby current automatically. Please notice that the SRAM data is replaced by the EEPROM data after the execution of this operation. STORE MODE The store mode is initiated when negative pulse (LF) is applied to ST pin while either CS = Vij, or WE = Viyy and is completed automatically be the on-chip timer. During this operation mode, all input and output pins are inhibited. The original SRAM data remains after the store mode. The MBM 2212 has two protection circuits to prevent a erroneous store mode. Noise filter circuit for duration of less than 20ns negative pulse on ST pin is on the chip. Auto-standby circuit prevents the store data on the EEPROM cell array from the destruction when Veg is less than +3V. When Voc power is ON or OFF, the Vi input level must be applied to ST pin before or while Veg is greater than +3V. These operation modes as store mode, recall mode and SRAM write mode have the same logical priority. Normally the first set logical condition determines the following operation mode among ST, RC and WE pins. STORE CYCLE TIMING WAVEFORM Se iste ae we By var tsr2 tost Vou RECALL CYCLE TIMING WAVEFORM tae: ve K cow ME snoness vats IK ooness YOO XK cowreane yf sooness van K - Yaw Re Yur aa ane = Vin & VO LLLLLL, _ tacz onc Vou ‘OUTPUT SSS Du netined Data 7-9

‘ima FUJITSU MBM2212-20 QOS «~MBM2212-25 EEPROM READ/WRITE INFORMATION (cont'd) AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) RECALL MODE (WE =ST = Via) Pm | om | | po a a a a a Note: * Transition is measured at point of *500mV from steady state voltage. STORE MODE (WE = AC = Vin) werent Pome ee ere | a [owavnatertasis | wr | f= [|= | Note: *1 It is protected to enter into the store mode by less than 20ns pulse width. "2. Transition is measured at point of *500mV from steady state voltage. ENDURANCE ee 7-10

MBM2212-25 _ HlllA/INON Standard 18-pin Ceramic DIP (Suffix: -2) 18-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE (CASE No. : DIP-18C-C01) "oF 1015" 0251064) melons REF. 7.32638) “3:10! 319.006 48.1040.15) 30017-6217 YP 70.10 7 056(1.42IMAX (0.2579.05) 2006.08) MAX 1342.014 | (3.492038) i r ye 32:.012 (2.582025) TP OEY, BoomOTAREF soos 52,010 i Dimension in 7 11.3220.25) (0469933) inches (millimeters) OFUNTSU LIMITED 1987 D180055-4c 7-11

‘atime, FUJITSU MBM2212-20 AHCI ~-MBM2212-25 PACKAGE DIMENSIONS ‘Standard 18-pin Plastic DIP (Suffix: -P) 18LEAD PLASTIC DUAL-IN-LINE PACKAGE (CASE No.: DIP-18P-M02) Hot AAA tte 1S MAX >) tA O08 300",010 i O (EJECTOR MARK) “01 | { FT a a | CT rT Cy a i .197(6.00)MAX 10012.54) | .oartig!? —onss.002 || | ea) cagiasy ea nt 7-12