MBL8048

MBL82C43 FUJITSU | Alldatasheet

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April 1966. Edition 2.1 CMOS INPUT/OUTPUT EXPANDER The Fujitsu MBL 62C43 is an input/output expander designed specifically to provide alow cost means of I/O expansion for the MBL 8048 series of single-chip microcomputers. Fabricated in 5 volts CMOS, the MBL 82C-43 combines low cost ‘single supply voltage and high drive current capability. Also, the MBL 82C43 is packaged in a 24-pin cerdip, plastic DIP, or plastic flat package (SOP). The MBL 82C43 consists of four 4-bit bidirectional static I/O ports and one CERAMIC DIP 4-bit port which serves as an interface to the MBL 8048 series microcomputers. ‘DIP-24C-CO1 ‘The 4-bit interface requires that only 4 I/O lines of the MBL 8048/8049/ 80C49/8749 be used for I/O expansion, and also allows multiple MBL 82C43’s to be added to the same bus. The I/O ports of the MBL 82C43 serve as a direct extension of the resident (/O facilities of the MBL 8048 series microcomputers and are accessed by their own MOVD, ANLD, and ORLD instructions. PLASTIC DIP DIP-24P-M01 FEATURES y a © CMOS Version of Fujitsu MBL 8243. : " n PLASTIC SOP © Simple Interface to Fujitsu MBL 8048 Series and Intel MCS-48° FPr-2a4i02 © Four 4-Bit 1/0 Ports. - © AND and OR Directly to Ports. PIN ASSIGNMENT © High Current Drive: 5 mA at 0.45 V 20 mA at 1.0V poo] at) vec a pao] 2 23.) Ps1 © On-Chip Power-On Reset Circuit pats 22H ese © Single +5 V Power Supply. raat ds 2D ess © Silicon-gate CMOS Process pass 20} P60 we 19) P61 © Three Package Options: prost7 “PY 18 p62 —Standard 24-pin Cerdip (Suffix:-CZ) rats 17 Hees —Standard 24-pin Plastic DIP (Suffix-P) p22Co set pra —Standard 24-pin Plastic SOP (Suffix:-PF) P21 Chto aster © Pin-Compatible with Fujitsu MBL 8243 and intel 8243. Poot |1 seen ono[] 12 13[ P70 {This device contains circuitry to protect the | ayes or electric fields. However, it is advised that normal. precautions be taken to avord + Trade Mark of Intel Corporation aoplication of any voltage higher than max! Portions Reprinted by permission of Intel Corporation | mrurm rated voltages to. this high impedance © Intel Corporation, 1980 circult 2124 ‘

Fig. 1 — LOGIC SYMBOL INTERPACE “sv To PORTS. Veo cs KZ paa.pao Pros K=> 59.760 23-920 C2 >) MBL 82043 Ka P63-P60 KZ prs.e70 ono Fig. 2 - BLOCK DIAGRAM feo 2 —— aay Le a ieo LET no +! Hfaxey 1 eter] B E pes C3 — fase] | Tie] Shem ——— = Al ena ia 2125

MBL 82C43_ i/MiliUeilll PIN DESCRIPTION ‘The MBL 82C43 has two interfaces: One is the processor interface; CS, PROG, and Port 2, which are used for the processor to communicate with the MBL 82C43 device. Another is the expansion I/O ports; Ports 4, 5, 6, and 7, which serve as an expansion of the processor's 1/0. Table 1-Pin Description fom fom foe [mm a Oa a a Chip Select input: A high on CS inhibits any change of output or 7 ‘Clock input: A high-to-low transition on PROG signifies that address: ‘and control are available on P20-P23, and a low-to-high transition signifies that data is available on P20-P23. vo Port 2: Four (4) bit bi-directional port contains the address and control bits on a high-to-low transition of PROG. During a low-to-high transition contains the data for a selected output port if a write operation, or the data from a selected port before the low-to-high transition if aread P40 — P43 2t05 vo Ports 4, 5, 6, and 7: Four (4) bit bi-directional |/O ports. May be P50 — P53 1,23 to 21 programmed to be input (during read), low impedance latched output P60 — P63 2010 17 (after write), or a tri-state (after read). Data on pins P20-P23 may be P70 — P73 13 to 16 directly written, ANDed or ORed with previous data. 2-126 F

GENERAL OPERATION is twansferred to the logic block of the specified port. After the logic manipulation is performed, the data is latched The MBL 82C43 contains four 4:bit 1/0 ports which serve ang outputed, The old data remains latched until new valid as an extension of the on-chip 1/0 and are addressed as ports Gutputs are entered. 4-7. The following operations may be performed on these . Borts: READ MODE © Transfer Accumulator to Port. © Transfer Port to Accumulator. The device has one read mode. The operation code and port address ‘© AND Accumulator to Port. Aare latched from the input port 2 on the high-to-low transition of the © OR Accumulator to Port. PROG pin. As soon as the read operation and port address are decoded, the appropriate outputs are tri-stated, and the input buffers All communication between the MBL 8048 series and the switched on. The read operation is terminated by a low-to-high MBL 82C43 occurs over Port 2 (P20 — P23) with timing pro- transition of the PROG pin. The port (4, 5, 6 or 7) that was selected is vided by an output pulse on the PROG pin of the processor. switched to the tr-stated mode while port 2 is returned to the input Each transfer consists of two 4-bit nibbles: mode. The first containing the “op code” and port address and the second containing the actual 4-bits of data. A high-to-iow Normally, a port will be in an output (write mode) or input transition of the PROG line indicates that address is present while {read mode). If modes are changed during operation, the a low-to-high transition indicates the presence of data. Additional first read following a write should be ignored; al! following MBL 82C43's may be added to the 4-bit bus and chip selected reads are valid. This is to allow the external driver on the using additional output lines from the MBL 8048 series port to settle after the first read instruction removes the low microcomputers. impedance drive from the MBL 82C43 output. A read of any Port will leave that port in a high impedance state. POWER ON INITIALIZATION SINK CAPABILITY Initia! application of power to the device forces input/output ports 4,5, 6, and 7 to the tri-state and port 2 to the input mode. The The MBL 82C43 can sink § mA at 0.45 V on each of its 16 PROG pin may be either high or low when power is applied. The 1/0 lines simultaneously. If, however, all lines are nat sinking first high-to-low transition of PROG causes device to exit power simultaneously or all lines are not fully loaded, the drive con mode. The power on sequence is initiated if Vcc drops below _caPability of any individual line increases as is shown by the 1v. accompanying curve, Address | Instruction “ Fig. 3— 00 | rona | oo | few Saat | | | It | 1 o | pone | 1 o | orto 2 soo, 1S N 1 1 Port 7 1 1 ANLD = |] { WRITE MODES 3 a \\ 7 tow dam toh ones pot ae ole st ORD Ps 2a NS new data into the selected port and old data is lost. ORLD Fi, A 2 a \\ takes new data, OR's it with the old data and then writes it to the 3 Lf} ES] port. ANLD Pi, A takes new data, AND’s it with the old data and a a or Se Ra! then writes it to the port. Operation code and port address are latched from the input port 2 on the high-tolow transition of the Largest LoL of any one pin (mA at Vo. < 0.45V) PROG pin. On the low-to-high transition of PROG data on port 2 2127 ’

MBL 82C43_ FIVIISHNRIH For example, if only 5 of the 16 lines are to sink current at ‘one time, the curve shows that each of those 5 lines is capable of sinking 9 mA at 0.45 V (if any lines are to sink 9 mA the total Io, must not exceed 45 mA or five o9mA loads). Example: How many pins can drive 5 TTL loads (1.6 mA) assuming remaining pins are unloaded? lop =5 x 1.6mA=8mA Eloy = 60 mA from curve # pins = 60 mA +8 mA/pin =7.5=7 In this case, 7 lines can sink 8 mA for a total of 56 mA. This leaves 4mA sink current capability which can be divided in any way among the remaining 8 1/0 lines of the MBL 82C43. Example: This example shows how the use of the 20mA sink capability of Port 7 affects the sinking capa- bility of the other 1/0 lines. An MBL82C43 will drive the following loads simultaneously. 2 loads — 20 mA at 1 V (port 7 only) B loads — 4 mA at 0.45 V 6 loads — 3.2 mA at 0.45 V Is this within the specified limits? From the curve: for lo, = 4 MA. Dio. = 93 mA. since 91.2mA < 93mA the loads are within specified limits. Although the 20 mA at 1 V loads are used in cal- culating Eloz, it is the largest current required at 0.45 V which determines the maximum allow- able Zlo,- 2128 :

Fig. 4 — 1/0 EXPANDER INTERFACE. MBL 80049 MBL 82643 p87-vB0K 8 1/0 paz-raoK 4» P17-P10K Bo Ps3-Ps0K a) P27-P24K 4) 1/0 To TEST r 7 ma INPUTS es-reok 3) ras-p20K 4 ___p23-P20 cs Fig. 5 MULTIPLE 1/0 EXPANDER INTERFACE met ezces aL €2C49 MBL 62c43 MBL 82c43 FROG PROG FAOG FROG MBL 8049 pak a> pak a i) oak a> ona» roK-a > rebKa» eka» weKa»> nk ay 52S 2S 2 2 i a |) r2s| - | we St 2-129 ’

i FUJITSU MBL 82C43_ /Mimiili itl ABSOLUTE MAXIMUM RATINGS Permanent device damage may occur if Supply Voltage GND-0.310+7.0 | | | ABSOLUTE MAXIMUM RATINGS are 7) exceeded. Functional operation should be GND -0310+7.0 resisted to the conditions oy deaed fn the 1 f thi sheet. T © | RATINGS conditions for extended periods Storage Temperature ba may affect device reliability. RECOMMENDED OPERATING CONDITIONS [Prana eno Vee v 5, [ao fo Pv ea DC CHARACTERISTICS (Voc = +5V +10%, GND =0V, Ta = —40°C to +85°C) rameter ditions ni ee a Ports 4 to 7 [ve [ees fT ew | ts 4 Port 2 [vas [Teton | | | ow |v Ports 4 t07 [vom [tomtiaa [oe [| | | Output High Voltage v, Port 2 Vv One lon = 100A Ports 4to7 Input Leakage Current fo te PROG A uz GND < Vin S$ Vec 7 lour = 5mA at each Total lo. of 16 Outputs Blow sour pam toy Alloutputs open, | wa | [te | Meta | | me | om | om Supply Current TAloupute oper Pe [eee | 24130 .

(oo = +5V +10%, GND =OV, Ta = —40°C to +85°C) Parameter Symbol Condition [wm [te [| Unit [Cosa seuptine | te) eater fo | [Considine to emer | [-ron2 Fomine Tine mf etme 0 |e | ES Setup/Hold Times [ws [we fe [ost 7 Oust aay Tine | wo] en oon ee | | [rer zoupoeuy Time | tase | Gace [| ef Fig. 6 —TIMING DIAGRAM tes "tk tes Era] 7av pros av ogy : ae - a 2av ADDRESS) 22 WRITE MODE | PORT2 Tak, OPERATION Dosv Sak INPUT DATA Ppa | ey a 2av # ADDRESS R22¥_24V cururoma p 24v | [READ MODE | PORT2 OUTPUT DATA i b—teo— TaV\\ /—New [WRITE MODE | PORTS 4107 OLD OUTPUT DATA ous vino v ROR eeuT tu hetces oe av Ta 2131 .

CERAMIC DIP (Suffix:-CZ) 24-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE (CASE No.: DIP-24C-CO1) XL ot018 F.025(0.64) REF ‘841(13.751 {625(15.87) 600116 24) REF 1,200(30.48) Sa 0080.20) 1¥,300(33.02) we + 10012.54)MAX 230(5,84)MAX -12013.05) 150(3.81) .990(2.29) 93210.81) ooclosty 110(2.79) Te 2201051) 1.100(27.94)REF .042(1.06) .015(0.38) Dimensions in Ugo aasOGaT inches (enltimeters) © 1985 FUJITSU LIMITED 0240088-26 2192 .

PLASTIC DIP (Suffix:-P) 24-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-24P-M01) \\ 15° MAX Om Mmmm fifi fi Fa | INDEX OOoWIUOUOOoOoSoOUooo 220/008) 05011.27) MAX ae .195(4,96)MAX 059(1.50) Dimensions in 079(2.00) Rihes tniieeters) © 1986 FUJITSU LIMITED 0240098-1C 2 | 24133 ’

MBL 82C43 _ DIIiNilllsiiti PACKAGE DIMENSIONS PLASTIC SOP (Suffix:-PF) 24-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-24P-M02) 1002(0.05) MIN AARARAAARAAR 7 (STAND OFF) HhHnnHHHRHAS ar7a08) fies 5018.9) INDEX 287173) 374195) 311(79) | po PHAAAAAHAHAS HHBUBUUEBEBSE y __582(14.79) 051013) 012103) Detail of "A" part (00810.2) O02 —t (EAA te 96011.27), 014(0.35) catio.s) 024106) TYP (0210.55) oar) 9071018) 0271068) Dimensions in MAX inches (millimeters) © 1088 FUJITSU LIMITED F240006-16 2-134 .