MB9D560

SPANSION

This document states the current technical specifications regarding

Manufacturer: SPANSION

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The following document contains information on Cypress products. Although the document is marked with the name “Spansion”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing custom ers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, wher e supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress (NASDAQ: CY) delivers high -performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes NOR flash memories, F -RAM™ and SRAM, Trav eo™ microcontrollers, the industry’s only PSoC ® programmable system -on-chip solutions, analog and PMIC Power Management ICs, CapSense ® capacitive touch-sensing controllers, and Wireless BLE Bluetooth ® Low-Energy and USB connectivity solutions, Cypress is committed to providing its customers worldwide with consistent innovation, best - in-class support and exceptional system value.

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Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.

Spansion® TraveoTM Family MB9DF564MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE MB9DF565MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE MB9DF566MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE Data Sheet (Full Production) Publication Number MB9D560_DS708-00001 Revision 3.0 Issue Date May 15, 2015 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. 1. Description MB9D560 series has SPANSION 32-bit microcontrollers for automobile motor control. They use the ARM® Cortex-R5 MPCoreTM CPU that is compatible with the ARM family. Notes: − ARM, Cortex, Thumb are the registered trademarks of ARM Limited in the EU and other countries. − MPCore, CoreSight are the trademarks of ARM Limited in the EU and other countries.

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May 15, 2015, MB9D560_DS708-00001-3v0-E 5 CONFIDENTIAL 2. Features Function Description Technology − CMOS 90nm technology CPU − ARM Cortex®-R5F − 32-bit ARM architecture − 2-instruction issuance super scalar − 8-stage pipeline − ARMv7 / Thumb®-2 instruction set − Floating-Point Unit (FPU) Double precision − Memory protection Unit (MPU) 16 area − ECC support for the TCM port 1-bit error correction, 2-bit error detection ECC (SEC-DED) − TCM port

2 TCM ports

− ATCM port − BTCM 2 ports (B0TCM, B1TCM) − VIC port Low latency interrupt − AXI master interface 64-bit AXI interface (instruction / data access) 32-bit AXI interface (I/O access) − AXI slave interface 64-bit AXI interface (accessible to TCM port) − CPU configuration

2 CPUs (AMP operation)

− Operating frequency Maximum 200 MHz − Trace with ETM-R5 Debugging − ARM CoreSightTM Technology Each CPU embedded Embedded Trace Macro (ETM), trace support of CPU operation − Debugging interface JTAG (5 pin ) Support clock : maximum 20 MHz − Debugging security support 128-bit security key (Device security key) − Wakeup function on JTAG Operation mode − User mode Normal mode (internal memory activation) − Serial writer mode Clock control − Internal clock source Fast-CR oscillation (8 MHz) Slow-CR oscillation (100 kHz) − External oscillation input Main clock input − Embedded PLL Main PLL (Multiplying clock of main oscillation ) − Oscillator stabilized timer Support oscillator stabilized timer for all clock source independently After a lapse of oscillator stabilized time, it is able to use source clock timer (Except PLL for FlexRay/RDC)

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− Reset level Hardware reset (system initialization) Software reset (programing initialization) − Reset factor (Hardware reset ) Power-on reset (PONR), external reset input (RSTX, NMIX+RSTX), clock stop waiting with time-out reset, low-voltage detection reset (internal low-voltage detection reset, 5V external low-voltage detection reset ), watchdog reset (hardware watchdog reset, software watchdog reset ), clock supervisor reset (main clock monitor, PLL clock monitor), software trigger hardware reset , profile error reset − Reset factor (software reset ) Software reset Low power consumption control − Device state RUN (Run State, CPU is operation status) PSS (Power Saving State, CPU wait event from WFI) − Setting parameter of each devise state Clock (clock source enable, clock source selection, clock divider, clock domain enable) Clock monitor Low-voltage detection Memory protection unit (MPU) − Memory protection as master except processor − Target master DMA controller − 8 area − NMI generation when violation detection Timing protection unit (TPU) − TPU 1 unit as CPU 1 unit − 24-bit timer x 8 channels per unit − Support execution time protection, locking time protection, inter-arrival time protection, deadline protection − Support normal mode and over flow mode − Prescaler of each channels Timer clock divider (1/1 to 1/64) − Independent prescaler of each channels Timer clock divider (1/1, 1/2, 1/4, 1/16) Clock supervisor (CSV) − Monitor target clock Main oscillation input , main PLL output − Monitor method Monitor of frequency range − Operation after error detection Reset or NMI Watchdog timer (WDT) − Watchdog timer embedded Hardware watchdog timer Software watchdog timer − Hardware watchdog timer 1 unit per system 32-bit watchdog timer with window function Clock source: fast-CR or slow-CR Set by boot program (BootROM maker) Not set by user program − Software watchdog timer 1 unit per CPU 32-bit watchdog timer with window function Clock source: fast-CR, slow-CR, main clock One time set on user program (not set again)

May 15, 2015, MB9D560_DS708-00001-3v0-E 7 CONFIDENTIAL Function Description Low-voltage detection (LVD) − Select voltage monitor External low-voltage detection (5V power line monitor): 3.9V, 4.1V, 4.3V Internal low-voltage detection (1.2V power line monitor): 0.9V − Internal low-voltage detection: always valid − External low-voltage detection: valid/invalid set − External low-voltage detection: set threshold voltage independently on RUN / PSS − Output when low-voltage detection External low-voltage detection: reset or NMI Internal low-voltage detection: reset Main Flash memory (TCFLASH) − Cortex-R5F ATCM connection

1 Main Flash memory as CPU 1 unit

− HPM connection with 64-bit AXI − Flash memory configuration Interleave with 64-bit Flash 2 units − 2 address areas TCM (read only) AXI (read / write) − ECC support (SEC-DED) − Parallel programming support − Flash security Work Flash memory (WorkFLASH) − 2 Work Flash memories

1 Work Flash memory as CPU 1 unit

− ECC support (SEC-DED) − Parallel programming support − Flash security Main SRAM (TCRAM) − BTCM connection of Cortex-R5F 1 main SRAM as CPU 1 unit Interleave with 2 ports of B0TCM and B1TCM − ECC support (SEC-DED) BootROM − Size: 16K byte − Boot operation support − Serial writer program support DMA controller (DMAC) − 16 channels − Transfer mode Block transfer, Burst transfer − Addressing mode Fixed, increment − Priority between channels Fixed, Dynamic, Round robin Interrupt control (IRC) − Support normal interrupt (IRQ) and non-maskable interrupt (NMI) − Normal interrupt (IRQ) Use Interrupt Request (IRQ) of Cortex-R5F 512 channels 32 level for priority − Support low latency interrupt response from VIC port of Cortex-R5F − Non-maskable interrupt (NMI) Use fast interrupt request (FIQ) of Cortex-R5F 32 channels 16 level for priority − Support software interrupt generation

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External interrupt (EXT-IRQ) − Input Normal interrupt (IRQ): 8 input Non-maskable interrupt (NMI): 1 input − Detection method H level , L level , rise edge, fall edge, both edge Inter-processor communications unit (IPCU) − Mailbox function Data communication for CPU core communication by 8 Mailbox Support of interrupt between CPU core Exclusion access memory (EAM) − Small size memory to support exclusion control on exclusion access instruction − Use for semaphore − Size: 48 byte Bit-band unit (BBU) − The bit operation of specified register bit on Bit band area, it is mapping 1 bit of bit band area to support bit band alias area for 1 byte. The target of bit band access is specified register bit on I/O area CRC − Output to register of CRC code according real time writing to input register Base timer − 16-bit timer Any of four PWM/PPG/reload/PWC timer functions can be selected and used. A 32-bit timer can be used in 2 channels of cascade mode as reload/PWC timer. 16-bit free-run timer (FRT) − 16 bit up/down counter (2 channels for motor control only) 32-bit free-run timer − 32 bit up/down counter 16-bit input capture (ICU) − Input capture 16-bit capture register that detects rise edge, Fall edge, both edge Generate interrupt request after latch of counter number of 16 bit Free-run timer with edge detection of pin input 32-bit input capture − Input capture 32-bit capture register that detects rise edge, fall edge, both edge Generate interrupt request after latch of counter number of 32 bit Free-run timer with edge detection of pin input − LIN sync break/sync field relation is following. Input capture ch.0 → Multi-function serial interface ch.0 Input capture ch.1 → Multi-function serial interface ch.1 Input capture ch.2 → Multi-function serial interface ch.2 Input capture ch.3 → Multi-function serial interface ch.3 Input capture ch.4 → Multi-function serial interface ch.4 16-bit output compare (OCU) − Output interrupt signal when compare with 16-bit free-run timer

May 15, 2015, MB9D560_DS708-00001-3v0-E 9 CONFIDENTIAL Function Description Waveform generator (WFG) − Generate variable output Real time output 16-bit PPG waveform output PPG uses 16-bit PPG timer of base timer The relation is following WFG(ch.0 to ch.5) Base timer ch.0 → PPG0 Base timer ch.2 → PPG2 Base timer ch.4 → PPG4 WFG(ch.6 to ch.11) Base timer ch.6 → PPG6 Base timer ch.8 → PPG8 Base timer ch.10 → PPG10 Non overlap three-phase waveform output (inverter control) DC chopper waveform output − Dead time timer function − GATE function − DTTI function A/D converter (ADC) − 12-bit resolution A/D converter: 1 unit (32 channels) − Sampling analog value from input port of 32 channels − Conversion time: 1 µs − External trigger activation (ADTG) − Activation from internal timer (base timer) 4ch sample-hold A/D converter − 12 bit resolution A/D converter: 2 units (8 channels ) Multi-function serial interface (MFS) − UART / CSIO / LIN interface (v2.1) communication available by selecting the function − Transmission FIFO: 64 Byte, reception FIFO: 64 Byte − Reception interrupt factor (3 types) Reception error detection (parity, over run, frame error) Reception to FIFO for data of setting value Reception data under setting value in FIFO, idle term detection of over 8 clocks with baud rate clock − Transmission interrupt factor (2 types) No transmission operation Transmission FIFO empty (contain transmission operation) − SPI (serial peripheral interface) support − LIN protocol revision 2.1 support Up/Down counter (UDC) − 8/16-bit up/down counter (2 channels uses for R/D converter) CAN interface − The CAN is based on the CAN protocol ver. 2.0A/B − 64 message buffers x 3 channels − An identification mask is applied to each message object − Up to 1Mbps support − Clock support CAN prescaler − CAN wakeup functions FlexRay controller − Supports FlexRay protocol specification v2.1 − Maximum 128 message buffers − 8K Byte message RAM − Variable length of message buffers − Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception FIFO − Host access to the message buffer via input and output buffers − Filtering for slot counter, cycle counter and channels − Maskable interrupts are supported R/D converter (RDC) − Connect to resolver interface D/A converter (DAC) − 10-bit resolution

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Motor vector operation accelerator (MVA) − Assist for three-phase current normalizing, three-phase to two-phase DC conversion / two-phase to three- phase AC conversion, angler calculation, PID control calculation. − Error detection in processing (overflow/under flow/non normalizing error of FLOP) − Amplitude diagnosis /angle diagnosis function of R/D converter − Error current diagnosis function Key code − Key code supports A part of General-purpose I/O (GPIO) register Port pin configuration (PPC) register Analog input control register (ADER) 4ch ADC analog input control register (ADER4CH_1, ADER4CH_0) Analog output control register (DAC00_DAER, DAC01_DAER)

May 15, 2015, MB9D560_DS708-00001-3v0-E 11 CONFIDENTIAL 3. Product Lineup Memory Size Parameter MB9DF564 MB9DF565 MB9DF566 FLASH size (program) (512KB+128KB)2 (768KB+128KB)2 (1024KB+128KB)2 FLASH size (Work) 64KB2 64KB2 64KB2 RAM size 64KB2 96KB2 128KB2 Functions Pin number 208 pin 176 pin System clock On-chip PLL clock multiplication system Minimum instruction execution time :5 ns (200 MHz) CR oscillator (fast/slow) Yes DMAC 16 channels Base timer 12 channels (0 to 11) 6 channels (0 to 3, 6, 7) 32-bit free-run timer 5 channels 32-bit input capture 3 units (6 channels) 16-bit free-run timer 20 channels*1 16-bit input capture 8 units (0 to 7) (15 channels (0 to 14)) 7 units (0 to 6) (13 channels (0 to 12)) 16-bit output compare 12 units (0 to 11) (24 channels (0 to 23)) 9 units (0 to 5, 9 to 11) (18 channels (0 to 11, 18 to 23)) Waveform generator 4 units (0 to 3) (24 channels (0 to 23)) 3 units (0, 1, 3) (18 channels (0 to 11, 18 to 23)) External interrupt 8 channels (0 to 7) 6 channels (0 to 4, 7) A/D converter 1 unit (32 channels) 4ch sample-hold A/D converter 2 units (8 channels) R/D converter 2 units*2 D/A converter 2 channels*2 Up/Down counter 4 channels Motor vector operation accelerator 2 units Multi-function serial interface 5 channels (0 to 4) 3 channels (0, 1, 4) CAN 3 channels FlexRay 128 msb x 1 unit (ch.A / ch.B)*2 Inter-processor communications unit Yes Exclusive access memory Yes Software watchdog timer Yes Hardware watchdog timer Yes CRC 2 channels Internal power supply low-voltage detection Yes External power supply low-voltage detection Yes Key code Yes*2 Debugging interface JTAG interface *1: 2 channels for motor control *2: The function is different according to the part number. See "15. Part Number Option".

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Pin Assignment

208 Pin Part Number with RDC

FRCK0 P305 3 154 P423 SCK3 FRCK10 IN14 FRCK1 P306 4 153 P422 SOT3 FRCK9 IN13 4ADTG0 DTTI0 P000 5 152 P421 SIN3 INT6 FRCK8 RTO0 P001 6 151 P100 DTTI1 4ADTG1 RTO1 P002 7 150 P101 RTO6 RTO2 P003 8 149 P102 RTO7 RTO3 P004 9 148 P103 RTO8 RTO4 P005 10 147 P104 RTO9 RTO5 P006 11 146 P105 RTO10 VCC5 12 145 P106 RTO11 VSS 13 144 VCC5 4AN0 P007 14 143 VSS 4AN1 P008 15 142 P107 4AN4 4AN2 P009 16 141 P108 4AN5 4AN3 P010 17 140 P109 4AN6 AVRH0 18 139 P110 4AN7 AVRL0 19 138 AVRH1 AVR0 20 137 AVRL1 AVSS0 21 136 AVR1 AVCC0 22 135 AVSS1 ZIN0 RDC_W0 P011 23 134 AVCC1 BIN0 RDC_V0 P012 24 133 P111 RDC_W1 ZIN2 AIN0 RDC_U0 P013 25 132 P112 RDC_V1 BIN2 ZIN1 RDC_Z0 P014 26 131 P113 RDC_U1 AIN2 BIN1 RDC_B0 P015 27 130 P114 RDC_Z1 ZIN3 AIN1 RDC_A0 P016 28 129 P115 RDC_B1 BIN3 AREF20 29 128 P116 RDC_A1 AIN3 SIN_IN0 30 127 AREF21 COS_IN0 31 126 SIN_IN1 SIN_OUT0 32 125 COS_IN1 SIN_MINUS0 33 124 SIN_OUT1 SIN_PLUS0 34 123 SIN_MINUS1 COS_PLUS0 35 122 SIN_PLUS1 COS_MINUS0 36 121 COS_PLUS1 COS_OUT0 37 120 COS_MINUS1 RVRH0 38 119 COS_OUT1 RVRL0 39 118 ＲＶＲＨ1 RVR0 40 117 RVRL1 RVSS0 41 116 RVR1 RVCC0 42 115 RVSS1 P026 RDC_ACT0 43 114 RVCC1 MAG_MINUS0 44 113 RDC_ACT1 P126 MAG_PLUS0 45 112 MAG_MINUS1 MAG_OUT0 46 111 MAG_PLUS1 ERDS0 P430 47 110 MAG_OUT1 FRCK12 DTTI2 P030 48 109 P431 ERDS1 FRCK13 RTO12 P031 49 108 P131 SCK2 FRCK14 RTO13 P309 50 107 P420 SOT2 FRCK15 RTO14 P310 51 106 P419 SIN2 INT5 VCC5 52 105 VCC5 100 101 102 103 104 VSS VCC12 P311 P312 P313 P314 P315 P316 P317 P318 P319 P320 P321 P322 P323 VCC12 VSS P324 P325 P326 P327 P328 P329 P330 NMIX RSTX MD1 MD0 VSS TRSTX TCK TDO TDI TMS nSRST P406 P407 P408 P409 P410 P411 P412 P413 P414 P415 P416 P417 P418 VCC12 VSS RTO15 RTO16 RTO17 DTTI3 RTO18 RTO19 RTO20 RTO21 RTO22 RTO23 SIN0 SOT0 SCK0 STOPWT RXDA TXDA TXENA RXDB TXDB TXENB SIN1 SOT1 SCK1 RX0 TX0 RX1 TX1 RX2 TX2 TIOA4 TIOB4 TIOA5 TIOB5 INT3 IN6 IN7 IN8 IN9 IN10 IN11 IN12 INT4 INT0 INT1 INT2 FRCK16 FRCK17 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 IN16 IN17 IN18 IN19 IN20 IN21 TOP VIEW LER208

May 15, 2015, MB9D560_DS708-00001-3v0-E 13 CONFIDENTIAL

208 Pin Part Number without RDC

FRCK0 P305 3 154 P423 SCK3 FRCK10 IN14 FRCK1 P306 4 153 P422 SOT3 FRCK9 IN13 4ADTG0 DTTI0 P000 5 152 P421 SIN3 INT6 FRCK8 RTO0 P001 6 151 P100 DTTI1 4ADTG1 RTO1 P002 7 150 P101 RTO6 RTO2 P003 8 149 P102 RTO7 RTO3 P004 9 148 P103 RTO8 RTO4 P005 10 147 P104 RTO9 RTO5 P006 11 146 P105 RTO10 VCC5 12 145 P106 RTO11 VSS 13 144 VCC5 4AN0 P007 14 143 VSS 4AN1 P008 15 142 P107 4AN4 4AN2 P009 16 141 P108 4AN5 4AN3 P010 17 140 P109 4AN6 AVRH0 18 139 P110 4AN7 AVRL0 19 138 AVRH1 AVR0 20 137 AVRL1 AVSS0 21 136 AVR1 AVCC0 22 135 AVSS1 ZIN0 P011 23 134 AVCC1 BIN0 P012 24 133 P111 ZIN2 AIN0 P013 25 132 P112 BIN2 ZIN1 P014 26 131 P113 AIN2 BIN1 P015 27 130 P114 ZIN3 AIN1 P016 28 129 P115 BIN3 P017 29 128 P116 AIN3 P018 30 127 P117 P019 31 126 P118 P020 32 125 P119 P021 33 124 P120 P022 34 123 P121 P023 35 122 P122 P024 36 121 P123 P025 37 120 P124 RVRH0 38 119 P125 RVRL0 39 118 RVRH1 RVR0 40 117 RVRL1 RVSS0 41 116 RVR1 RVCC0 42 115 RVSS1 P026 43 114 RVCC1 P027 44 113 P126 P028 45 112 P127 DAOUT0 P029 46 111 P128 ERDS0 P430 47 110 P129 DAOUT1 FRCK12 DTTI2 P030 48 109 P431 ERDS1 FRCK13 RTO12 P031 49 108 P131 SCK2 FRCK14 RTO13 P309 50 107 P420 SOT2 FRCK15 RTO14 P310 51 106 P419 SIN2 INT5 VCC5 52 105 VCC5 100 101 102 103 104 VSS VCC12 P311 P312 P313 P314 P315 P316 P317 P318 P319 P320 P321 P322 P323 VCC12 VSS P324 P325 P326 P327 P328 P329 P330 NMIX RSTX MD1 MD0 VSS TRSTX TCK TDO TDI TMS nSRST P406 P407 P408 P409 P410 P411 P412 P413 P414 P415 P416 P417 P418 VCC12 VSS RTO15 RTO16 RTO17 DTTI3 RTO18 RTO19 RTO20 RTO21 RTO22 RTO23 SIN0 SOT0 SCK0 STOPWT RXDA TXDA TXENA RXDB TXDB TXENB SIN1 SOT1 SCK1 RX0 TX0 RX1 TX1 RX2 TX2 TIOA4 TIOB4 TIOA5 TIOB5 INT3 IN6 IN7 IN8 IN9 IN10 IN11 IN12 INT4 INT0 INT1 INT2 FRCK16 FRCK17 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 IN16 IN17 IN18 IN19 IN20 IN21 TOP VIEW LER208

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176 Pin Part Number with RDC

4ADTG0 DTTI0 P000 3 130 P100 DTTI1 4ADTG1 RTO0 P001 4 129 P101 RTO6 RTO1 P002 5 128 P102 RTO7 RTO2 P003 6 127 P103 RTO8 RTO3 P004 7 126 P104 RTO9 RTO4 P005 8 125 P105 RTO10 RTO5 P006 9 124 P106 RTO11 4AN0 P007 10 123 P107 4AN4 4AN1 P008 11 122 P108 4AN5 4AN2 P009 12 121 P109 4AN6 4AN3 P010 13 120 P110 4AN7 AVRH0 14 119 AVRH1 AVRL0 15 118 AVRL1 AVR0 16 117 AVR1 AVSS0 17 116 AVSS1 AVCC0 18 115 AVCC1 ZIN0 RDC_W0 P011 19 114 P111 RDC_W1 ZIN2 BIN0 RDC_V0 P012 20 113 P112 RDC_V1 BIN2 AIN0 RDC_U0 P013 21 112 P113 RDC_U1 AIN2 ZIN1 RDC_Z0 P014 22 111 P114 RDC_Z1 ZIN3 BIN1 RDC_B0 P015 23 110 P115 RDC_B1 BIN3 AIN1 RDC_A0 P016 24 109 P116 RDC_A1 AIN3 AREF20 25 108 AREF21 SIN_IN0 26 107 SIN_IN1 COS_IN0 27 106 COS_IN1 SIN_OUT0 28 105 SIN_OUT1 SIN_MINUS0 29 104 SIN_MINUS1 SIN_PLUS0 30 103 SIN_PLUS1 COS_PLUS0 31 102 COS_PLUS1 COS_MINUS0 32 101 COS_MINUS1 COS_OUT0 33 100 COS_OUT1 RVRH0 34 99 RVRH1 RVRL0 35 98 RVRL1 RVR0 36 97 RVR1 RVSS0 37 96 RVSS1 RVCC0 38 95 RVCC1 P026 RDC_ACT0 39 94 RDC_ACT1 P126 MAG_MINUS0 40 93 MAG_MINUS1 MAG_PLUS0 41 92 MAG_PLUS1 MAG_OUT0 42 91 MAG_OUT1 ERDS0 P430 43 90 P431 ERDS1 VCC5 44 89 VCC5 VSS P314 P315 P316 P317 P318 P319 P320 P321 P322 P323 VCC12 VSS P324 P325 P326 P327 P328 P329 P330 NMIX RSTX MD1 MD0 VSS TRSTX TCK TDO TDI TMS nSRST P406 P407 P408 P409 P410 P411 P412 P413 P414 VCC12 VSS DTTI3 RTO18 RTO19 RTO20 RTO21 RTO22 RTO23 SIN0 SOT0 SCK0 STOPWT RXDA TXDA TXENA RXDB TXDB TXENB SIN1 SOT1 SCK1 RX0 TX0 RX1 TX1 RX2 TX2 INT3 IN6 IN7 IN8 IN9 IN10 IN11 IN12 INT4 INT0 INT1 INT2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 IN16 IN17 IN18 IN19 IN20 IN21 TOP VIEW LEP176

May 15, 2015, MB9D560_DS708-00001-3v0-E 15 CONFIDENTIAL

176 Pin Part Number without RDC

4ADTG0 DTTI0 P000 3 130 P100 DTTI1 4ADTG1 RTO0 P001 4 129 P101 RTO6 RTO1 P002 5 128 P102 RTO7 RTO2 P003 6 127 P103 RTO8 RTO3 P004 7 126 P104 RTO9 RTO4 P005 8 125 P105 RTO10 RTO5 P006 9 124 P106 RTO11 4AN0 P007 10 123 P107 4AN4 4AN1 P008 11 122 P108 4AN5 4AN2 P009 12 121 P109 4AN6 4AN3 P010 13 120 P110 4AN7 AVRH0 14 119 AVRH1 AVRL0 15 118 AVRL1 AVR0 16 117 AVR1 AVSS0 17 116 AVSS1 AVCC0 18 115 AVCC1 ZIN0 P011 19 114 P111 ZIN2 BIN0 P012 20 113 P112 BIN2 AIN0 P013 21 112 P113 AIN2 ZIN1 P014 22 111 P114 ZIN3 BIN1 P015 23 110 P115 BIN3 AIN1 P016 24 109 P116 AIN3 P017 25 108 P117 P018 26 107 P118 P019 27 106 P119 P020 28 105 P120 P021 29 104 P121 P022 30 103 P122 P023 31 102 P123 P024 32 101 P124 P025 33 100 P125 RVRH0 34 99 RVRH1 RVRL0 35 98 RVRL1 RVR0 36 97 RVR1 RVSS0 37 96 RVSS1 RVCC0 38 95 RVCC1 P026 39 94 P126 P027 40 93 P127 P028 41 92 P128 DAOUT0 P029 42 91 P129 DAOUT1 ERDS0 P430 43 90 P431 ERDS1 VCC5 44 89 VCC5 VSS P314 P315 P316 P317 P318 P319 P320 P321 P322 P323 VCC12 VSS P324 P325 P326 P327 P328 P329 P330 NMIX RSTX MD1 MD0 VSS TRSTX TCK TDO TDI TMS nSRST P406 P407 P408 P409 P410 P411 P412 P413 P414 VCC12 VSS DTTI3 RTO18 RTO19 RTO20 RTO21 RTO22 RTO23 SIN0 SOT0 SCK0 STOPWT RXDA TXDA TXENA RXDB TXDB TXENB SIN1 SOT1 SCK1 RX0 TX0 RX1 TX1 RX2 TX2 INT3 IN6 IN7 IN8 IN9 IN10 IN11 IN12 INT4 INT0 INT1 INT2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 IN16 IN17 IN18 IN19 IN20 IN21 TOP VIEW LEP176

16 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Description Part Number with RDC Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 3 - P305 FRCK0 E General-purpose I/O port 16-bit free-run timer ch.0 external clock input pin 4 - P306 FRCK1 E General-purpose I/O port 16-bit free-run timer ch.1 external clock input pin 5 3 P000 DTTI0 4ADTG0 E General-purpose I/O port Waveform generator output stop signal input pin 0 4ch sample-hold A/D converter unit0 external trigger input pin 6 4 P001 RTO0 E General-purpose I/O port Waveform generator ch.0 output pin 7 5 P002 RTO1 E General-purpose I/O port Waveform generator ch.1 output pin 8 6 P003 RTO2 E General-purpose I/O port Waveform generator ch.2 output pin 9 7 P004 RTO3 E General-purpose I/O port Waveform generator ch.3 output pin 10 8 P005 RTO4 E General-purpose I/O port Waveform generator ch.4 output pin 11 9 P006 RTO5 E General-purpose I/O port Waveform generator ch.5 output pin 14 10 P007 4AN0 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 0 input pin 15 11 P008 4AN1 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 1 input pin 16 12 P009 4AN2 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 2 input pin 17 13 P010 4AN3 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 3 input pin 23 19 P011 RDC_W0 ZIN0 E General-purpose I/O port R/D converter unit0 W-phase output pin Up/Down counter ch.0 ZIN input pin 24 20 P012 RDC_V0 BIN0 E General-purpose I/O port R/D converter unit0 V-phase output pin Up/Down counter ch.0 BIN input pin 25 21 P013 RDC_U0 AIN0 E General-purpose I/O port R/D converter unit0 U-phase output pin Up/Down counter ch.0 AIN input pin 26 22 P014 RDC_Z0 ZIN1 E General-purpose I/O port R/D converter unit0 Z-phase output pin Up/Down counter ch.1 ZIN input pin 27 23 P015 RDC_B0 BIN1 E General-purpose I/O port R/D converter unit0 B-phase output pin Up/Down counter ch.1 BIN input pin 28 24 P016 RDC_A0 AIN1 E General-purpose I/O port R/D converter unit0 A-phase output pin Up/Down counter ch.1 AIN input pin 29 25 AREF20 L R/D converter unit0 Aref output pin(RVCC0/2)

May 15, 2015, MB9D560_DS708-00001-3v0-E 17 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 30 26 SIN_IN0 K R/D converter unit0 SIN coil earth leakage detection input pin 31 27 COS_IN0 K R/D converter unit0 COS coil earth leakage detection input pin 32 28 SIN_OUT0 L R/D converter unit0 SIN output pin 33 29 SIN_MINUS0 K R/D converter unit0 SIN input pin- 34 30 SIN_PLUS0 K R/D converter unit0 SIN input pin+ 35 31 COS_PLUS0 K R/D converter unit0 COS input pin+ 36 32 COS_MINUS0 K R/D converter unit0 COS input pin- 37 33 COS_OUT0 L R/D converter unit0 COS output pin 43 39 RDC_ACT0 P026 E R/D converter unit0 operation status output pin General-purpose I/O port 44 40 MAG_MINUS0 K R/D converter unit0 excitation external input pin- 45 41 MAG_PLUS0 K R/D converter unit0 excitation external input pin+ 46 42 MAG_OUT0 L R/D converter unit0 excitation signal output pin 47 43 P430 ERDS0 E General-purpose I/O port Error detection output pin ch.0 48 - P030 DTTI2 FRCK12 E General-purpose I/O port Waveform generator output stop signal input pin 2 16-bit free-run timer ch.12 external clock input pin 49 - P031 RTO12 FRCK13 E General-purpose I/O port Waveform generator ch.12 output pin 16-bit free-run timer ch.13 external clock input pin 50 - P309 RTO13 FRCK14 E General-purpose I/O port Waveform generator ch.13 output pin 16-bit free-run timer ch.14 external clock input pin 51 - P310 RTO14 FRCK15 E General-purpose I/O port Waveform generator ch.14 output pin 16-bit free-run timer ch.15 external clock input pin 55 - P311 RTO15 FRCK16 E General-purpose I/O port Waveform generator ch.15 output pin 16-bit free-run timer ch.16 external clock input pin 56 - P312 RTO16 FRCK17 E General-purpose I/O port Waveform generator ch.16 output pin 16-bit free-run timer ch.17 external clock input pin 57 - P313 RTO17 E General-purpose I/O port Waveform generator ch.17 output pin 58 46 P314 DTTI3 TIOA0 E General-purpose I/O port Waveform generator output stop signal input pin 3 Base timer ch.0 TIOA output pin 59 47 P315 RTO18 TIOB0 E General-purpose I/O port Waveform generator ch.18 output pin Base timer ch.0 TIOB input pin 60 48 P316 RTO19 TIOA1 E General-purpose I/O port Waveform generator ch.19 output pin Base timer ch.1 TIOA I/O pin 61 49 P317 RTO20 TIOB1 E General-purpose I/O port Waveform generator ch.20 output pin Base timer ch.1 TIOB input pin 62 50 P318 RTO21 TIOA2 E General-purpose I/O port Waveform generator ch.21 output pin Base timer ch.2 TIOA output pin

18 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 63 51 P319 RTO22 TIOB2 E General-purpose I/O port Waveform generator ch.22 output pin Base timer ch.2 TIOB input pin 64 52 P320 RTO23 TIOA3 E General-purpose I/O port Waveform generator ch.23 output pin Base timer ch.3 TIOA I/O pin 65 53 P321 SIN0 INT3 TIOB3 E General-purpose I/O port Multi-function serial interface ch.0 serial data input pin INT3 external interrupt input pin Base timer ch.3 TIOB input pin 66 54 P322 SOT0 E General-purpose I/O port Multi-function serial interface ch.0 serial data output pin 67 55 P323 SCK0 E General-purpose I/O port Multi-function serial interface ch.0 clock I/O pin 70 58 P324 STOPWT IN6 IN16 E General-purpose I/O port FlexRay stop watch input pin 16-bit input capture ch.6 external pulse input pin 32-bit input capture ch.0 external pulse input pin 71 59 P325 RXDA IN7 IN17 H General-purpose I/O port FlexRay ch.A data input pin 16-bit input capture ch.7 external pulse input pin 32-bit input capture ch.1 external pulse input pin 72 60 P326 TXDA IN8 IN18 H General-purpose I/O port FlexRay ch.A data output pin 16-bit input capture ch.8 external pulse input pin 32-bit input capture ch.2 external pulse input pin 73 61 P327 TXENA IN9 IN19 H General-purpose I/O port FlexRay ch.A operation enable output pin 16-bit input capture ch.9 external pulse input pin 32-bit input capture ch.3 external pulse input pin 74 62 P328 RXDB IN10 IN20 H General-purpose I/O port FlexRay ch.B data input pin 16-bit input capture ch.10 external pulse input pin 32-bit input capture ch.4 external pulse input pin 75 63 P329 TXDB IN11 IN21 H General-purpose I/O port FlexRay ch.B data output pin 16-bit input capture ch.11 external pulse input pin 32-bit input capture ch.5 external pulse input pin 76 64 P330 TXENB IN12 H General-purpose I/O port FlexRay ch.B operation enable output pin 16-bit input capture ch.12 external pulse input pin 77 65 NMIX B Non-maskable interrupt input pin 78 66 RSTX B External reset input pin 79 67 MD1 C Mode pin 1 (with high-voltage control) 80 68 MD0 C Mode pin 0 (with high-voltage control) 81 69 X0 A Main clock oscillation input pin 82 70 X1 Main clock oscillation output pin 84 72 TRSTX J JTAG test reset input 85 73 TCK J JTAG test clock input 86 74 TDO I JTAG test data output

May 15, 2015, MB9D560_DS708-00001-3v0-E 19 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 87 75 TDI J JTAG test data input 88 76 TMS J JTAG test mode status input 89 77 nSRST J System reset input for debugger 90 78 P406 SIN1 INT4 E General-purpose I/O port Multi-function serial interface ch.1 serial data input pin INT4 external interrupt input pin 91 79 P407 SOT1 E General-purpose I/O port Multi-function serial interface ch.1 serial data output pin 92 80 P408 SCK1 E General-purpose I/O port Multi-function serial interface ch.1 clock I/O pin 93 81 P409 RX0 INT0 E General-purpose I/O port CAN ch.0 reception data input pin INT0 external interrupt input pin 94 82 P410 TX0 E General-purpose I/O port CAN ch.0 transmission data output pin 95 83 P411 RX1 INT1 E General-purpose I/O port CAN ch.1 reception data input pin INT1 external interrupt input pin 96 84 P412 TX1 E General-purpose I/O port CAN ch.1 transmission data output pin 97 85 P413 RX2 INT2 E General-purpose I/O port CAN ch.2 reception data input pin INT2 external interrupt input pin 98 86 P414 TX2 E General-purpose I/O port CAN ch.2 transmission data output pin 99 - P415 TIOA4 E General-purpose I/O port Base timer ch.4 TIOA output pin 100 - P416 TIOB4 E General-purpose I/O port Base timer ch.4 TIOB input pin 101 - P417 TIOA5 E General-purpose I/O port Base timer ch.5 TIOA I/O pin 102 - P418 TIOB5 E General-purpose I/O port Base timer ch.5 TIOB input pin 106 - P419 SIN2 INT5 E General-purpose I/O port Multi-function serial interface ch.2 serial data input pin INT5 external interrupt input pin 107 - P420 SOT2 E General-purpose I/O port Multi-function serial interface ch.2 serial data output pin 108 - P131 SCK2 E General-purpose I/O port Multi-function serial interface ch.2 clock I/O pin 109 90 P431 ERDS1 E General-purpose I/O port Error detection output pin ch.1 110 91 MAG_OUT1 L R/D converter unit1excitation signal output pin 111 92 MAG_PLUS1 K R/D converter unit1excitation external input pin+ 112 93 MAG_MINUS1 K R/D converter unit1excitation external input pin- 113 94 RDC_ACT1 P126 E R/D converter unit1 operation status output pin General-purpose I/O port 119 100 COS_OUT1 L R/D converter unit1 COS output pin 120 101 COS_MINUS1 K R/D converter unit1 COS input pin- 121 102 COS_PLUS1 K R/D converter unit1 COS input pin+

20 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 122 103 SIN_PLUS1 K R/D converter unit1 SIN input pin+ 123 104 SIN_MINUS1 K R/D converter unit1 SIN input pin- 124 105 SIN_OUT1 L R/D converter unit1 SIN output pin 125 106 COS_IN1 K R/D converter unit1 COS coil earth leakage detection input pin 126 107 SIN_IN1 K R/D converter unit1 SIN coil earth leakage detection input pin 127 108 AREF21 L R/D converter unit1 Aref output pin(RVCC1/2) 128 109 P116 RDC_A1 AIN3 E General-purpose I/O port R/D converter unit1 A phase output pin Up/Down counter ch.3 AIN input pin 129 110 P115 RDC_B1 BIN3 E General-purpose I/O port R/D converter unit1 B phase output pin Up/Down counter ch.3 BIN input pin 130 111 P114 RDC_Z1 ZIN3 E General-purpose I/O port R/D converter unit1 Z phase output pin Up/Down counter ch.3 ZIN input pin 131 112 P113 RDC_U1 AIN2 E General-purpose I/O port R/D converter unit1 U phase output pin Up/Down counter ch.2 AIN input pin 132 113 P112 RDC_V1 BIN2 E General-purpose I/O port R/D converter unit1 V phase output pin Up/Down counter ch.2 BIN input pin 133 114 P111 RDC_W1 ZIN2 E General-purpose I/O port R/D converter unit1 W phase output pin Up/Down counter ch.2 ZIN input pin 139 120 P110 4AN7 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 7 input pin 140 121 P109 4AN6 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 6 input pin 141 122 P108 4AN5 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 5 input pin 142 123 P107 4AN4 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 4 input pin 145 124 P106 RTO11 E General-purpose I/O port Waveform generator ch.11 output pin 146 125 P105 RTO10 E General-purpose I/O port Waveform generator ch.10 output pin 147 126 P104 RTO9 E General-purpose I/O port Waveform generator ch.9 output pin 148 127 P103 RTO8 E General-purpose I/O port Waveform generator ch.8 output pin 149 128 P102 RTO7 E General-purpose I/O port Waveform generator ch.7 output pin 150 129 P101 RTO6 E General-purpose I/O port Waveform generator ch.6 output pin 151 130 P100 DTTI1 4ADTG1 E General-purpose I/O port Waveform generator output stop signal input pin1 4ch sample-hold A/D converter unit1 external trigger input pin

May 15, 2015, MB9D560_DS708-00001-3v0-E 21 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 152 - P421 SIN3 INT6 FRCK8 E General-purpose I/O port Multi-function serial interface ch.3 serial data input pin INT6 external interrupt input pin 16-bit free-run timer ch.8 external clock input pin 153 - P422 SOT3 FRCK9 IN13 E General-purpose I/O port Multi -function serial interface ch.3 serial data output pin 16-bit free-run timer ch.9 external clock input pin 16-bit input capture ch.13 external pulse input pin 154 - P423 SCK3 FRCK10 IN14 E General-purpose I/O port Multi-function serial interface ch.3 clock I/O pin 16-bit free-run timer ch.10 external clock input pin 16-bit input capture ch.14 external pulse input pin 158 - P425 TIOA8 E General-purpose I/O port Base timer ch.8 TIOA output pin 159 - P426 TIOB8 E General-purpose I/O port Base timer ch.8 TIOB input pin 160 - P427 TIOA9 E General-purpose I/O port Base timer ch.9 TIOA I/O pin 161 - P428 TIOB9 E General-purpose I/O port Base timer ch.9 TIOB input pin 162 134 P429 MONCLK MM E General-purpose I/O port Clock monitor output pin Clock supervisor main clock error detection output pin 163 135 P200 AN0 F General-purpose I/O port A/D converter analog 0 input pin 164 136 P201 AN1 F General-purpose I/O port A/D converter analog 1 input pin 165 137 P202 AN2 F General-purpose I/O port A/D converter analog 2 input pin 166 138 P203 AN3 F General-purpose I/O port A/D converter analog 3 input pin 167 139 P204 AN4 F General-purpose I/O port A/D converter analog 4 input pin 168 140 P205 AN5 F General-purpose I/O port A/D converter analog 5 input pin 169 141 P206 AN6 F General-purpose I/O port A/D converter analog 6 input pin 170 142 P207 AN7 F General-purpose I/O port A/D converter analog 7 input pin 173 145 P208 AN8 F General-purpose I/O port A/D converter analog 8 input pin 174 146 P209 AN9 F General-purpose I/O port A/D converter analog 9 input pin 175 147 P210 AN10 F General-purpose I/O port A/D converter analog 10 input pin 176 148 P211 AN11 F General-purpose I/O port A/D converter analog 11 input pin 177 149 P212 AN12 F General-purpose I/O port A/D converter analog 12 input pin

22 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 178 150 P213 AN13 F General-purpose I/O port A/D converter analog 13 input pin 179 151 P214 AN14 F General-purpose I/O port A/D converter analog 14 input pin 180 152 P215 AN15 F General-purpose I/O port A/D converter analog 15 input pin 185 157 P216 AN16 F General-purpose I/O port A/D converter analog 16 input pin 186 158 P217 AN17 F General-purpose I/O port A/D converter analog 17 input pin 187 159 P218 AN18 F General-purpose I/O port A/D converter analog 18 input pin 188 160 P219 AN19 F General-purpose I/O port A/D converter analog 19 input pin 189 161 P220 AN20 TIOA6 F General-purpose I/O port A/D converter analog 20 input pin Base timer ch.6 TIOA output pin 190 162 P221 AN21 TIOB6 F General-purpose I/O port A/D converter analog 21 input pin Base timer ch.6 TIOB input pin 191 163 P222 AN22 TIOA7 F General-purpose I/O port A/D converter analog 22 input pin Base timer ch.7 TIOA I/O pin 192 164 P223 AN23 TIOB7 F General-purpose I/O port A/D converter analog 23 input pin Base timer ch.7 TIOB input pin 195 167 P224 AN24 F General-purpose I/O port A/D converter Analog 24 input pin 196 168 P225 AN25 SIN4 INT7 F General-purpose I/O port A/D converter analog 25 input pin Multi-function serial interface ch.4 serial data input pin INT7 external interrupt input pin 197 169 P226 AN26 SOT4 IN0 F General-purpose I/O port A/D converter analog 26 input pin Multi-function serial interface ch.4 serial data output pin 16-bit input capture ch.0 external pulse input pin 198 170 P227 AN27 SCK4 IN1 F General-purpose I/O port A/D converter analog 27 input pin Multi-function serial interface ch.4 clock I/O pin 16-bit input capture ch.1 external pulse input pin 199 171 P228 AN28 SCS40 IN2 F General-purpose I/O port A/D converter analog 28 input pin Multi-function serial interface ch.4 serial chip select 0 I/O pin 16-bit input capture ch.2 external pulse input pin 200 172 P229 AN29 SCS41 IN3 F General-purpose I/O port A/D converter analog 29 input pin Multi-function serial interface ch.4 serial chip select 1 I/O pin 16-bit input capture ch.3 external pulse input pin

May 15, 2015, MB9D560_DS708-00001-3v0-E 23 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 201 173 P230 AN30 SCS42 IN4 F General-purpose I/O port A/D converter analog 30 input pin Multi-function serial interface ch.4 serial chip select 2 I/O pin 16-bit input capture ch.4 external pulse input pin 202 174 P231 AN31 SCS43 IN5 F General-purpose I/O port A/D converter analog 31 input pin Multi-function serial interface ch.4 serial chip select 3 I/O pin 16-bit input capture ch.5 external pulse input pin 203 175 P300 ADTG0 E General-purpose I/O port A/D converter external trigger input pin 204 - P301 TIOA10 FRCK4 E General-purpose I/O port Base timer ch.10 TIOA output pin 16-bit free-run timer ch.4 external clock input pin 205 - P302 TIOB10 FRCK5 E General-purpose I/O port Base timer ch.10 TIOB input pin 16-bit free-run timer ch.5 external clock input pin 206 - P303 TIOA11 FRCK6 E General-purpose I/O port Base timer ch.11 TIOA I/O pin 16-bit free-run timer ch.6 external clock input pin 207 - P304 TIOB11 FRCK7 E General-purpose I/O port Base timer ch.11 TIOB input pin 16-bit free-run timer ch.7 external clock input pin 18 14 AVRH0 - 4ch sample-hold A/D converter unit0 upper limit reference voltage 19 15 AVRL0 - 4ch sample-hold A/D converter unit0 lower limit reference voltage 20 16 AVR0 - 4ch sample-hold A/D converter unit0 reference voltage 21 17 AVSS0 - 4ch sample-hold A/D converter unit0 analog GND 22 18 AVCC0 - 4ch sample-hold A/D converter unit0 analog power supply 134 115 AVCC1 - 4ch sample-hold A/D converter unit1 analog power supply 135 116 AVSS1 - 4ch sample-hold A/D converter unit1 analog GND 136 117 AVR1 - 4ch sample-hold A/D converter unit1 reference voltage 137 118 AVRL1 - 4ch sample-hold A/D converter unit1 lower limit reference voltage 138 119 AVRH1 - 4ch sample-hold A/D converter unit1 upper limit reference voltage 38 34 RVRH0 - R/D converter unit0 upper limit reference voltage 39 35 RVRL0 - R/D converter unit0 lower limit reference voltage 40 36 RVR0 - R/D converter unit0 reference voltage 41 37 RVSS0 - R/D converter unit0 analog GND 42 38 RVCC0 - R/D converter unit0 analog power supply 114 95 RVCC1 - R/D converter unit1 analog power supply 115 96 RVSS1 - R/D converter unit1 analog GND 116 97 RVR1 - R/D converter unit1 reference voltage 117 98 RVRL1 - R/D converter unit1 lower limit reference voltage 118 99 RVRH1 - R/D converter unit1 upper limit reference voltage 181 153 AVCC2 - A/D converter analog power supply 182 154 AVSS2 - A/D converter analog GND 183 155 AVRL2 - A/D converter lower limit reference voltage 184 156 AVRH2 - A/D converter upper limit reference voltage

24 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208 pin 176 pin 103 155 172 193 131 144 165 VCC12 - 1.2V power supply 105 144 157 208 133 176 VCC5 - 5.0V power supply 104 143 156 171 194 132 143 166 VSS - GND

May 15, 2015, MB9D560_DS708-00001-3v0-E 25 CONFIDENTIAL Part Number without RDC Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 3 - P305 FRCK0 E General-purpose I/O port 16-bit free-run timer ch.0 external clock input pin 4 - P306 FRCK1 E General-purpose I/O port 16-bit free-run timer ch.1 external clock input pin 5 3 P000 DTTI0 4ADTG0 E General-purpose I/O port Waveform generator output stop signal input pin 0 4ch sample-hold A/D converter unit0 external trigger input pin 6 4 P001 RTO0 E General-purpose I/O port Waveform generator ch.0 output pin 7 5 P002 RTO1 E General-purpose I/O port Waveform generator ch.1 output pin 8 6 P003 RTO2 E General-purpose I/O port Waveform generator ch.2 output pin 9 7 P004 RTO3 E General-purpose I/O port Waveform generator ch.3 output pin 10 8 P005 RTO4 E General-purpose I/O port Waveform generator ch.4 output pin 11 9 P006 RTO5 E General-purpose I/O port Waveform generator ch.5 output pin 14 10 P007 4AN0 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 0 input pin 15 11 P008 4AN1 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 1 input pin 16 12 P009 4AN2 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 2 input pin 17 13 P010 4AN3 F General-purpose I/O port 4ch sample-hold A/D converter unit0 analog 3 input pin 23 19 P011 ZIN0 E General-purpose I/O port Up/Down counter ch.0 ZIN input pin 24 20 P012 BIN0 E General-purpose I/O port Up/Down counter ch.0 BIN input pin 25 21 P013 AIN0 E General-purpose I/O port Up/Down counter ch.0 AIN input pin 26 22 P014 ZIN1 E General-purpose I/O port Up/Down counter ch.1 ZIN input pin 27 23 P015 BIN1 E General-purpose I/O port Up/Down counter ch.1 BIN input pin 28 24 P016 AIN1 E General-purpose I/O port Up/Down counter ch.1 AIN input pin 29 25 P017 E General-purpose I/O port 30 26 P018 E General-purpose I/O port 31 27 P019 E General-purpose I/O port 32 28 P020 E General-purpose I/O port 33 29 P021 E General-purpose I/O port 34 30 P022 E General-purpose I/O port 35 31 P023 E General-purpose I/O port 36 32 P024 E General-purpose I/O port 37 33 P025 E General-purpose I/O port 43 39 P026 E General-purpose I/O port

26 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 44 40 P027 E General-purpose I/O port 45 41 P028 E General-purpose I/O port 46 42 P029 DAOUT0 G General-purpose I/O port D/A converter ch.0 analog output pin 47 43 P430 ERDS0 E General-purpose I/O port Error detection output pin ch.0 48 - P030 DTTI2 FRCK12 E General-purpose I/O port Waveform generator output stop signal input pin 2 16-bit free-run timer ch.12 external clock input pin 49 - P031 RTO12 FRCK13 E General-purpose I/O port Waveform generator ch.12 output pin 16-bit free-run timer ch.13 external clock input pin 50 - P309 RTO13 FRCK14 E General-purpose I/O port Waveform generator ch.13 output pin 16-bit free-run timer ch.14 external clock input pin 51 - P310 RTO14 FRCK15 E General-purpose I/O port Waveform generator ch.14 output pin 16-bit free-run timer ch.15 external clock input pin 55 - P311 RTO15 FRCK16 E General-purpose I/O port Waveform generator ch.15 output pin 16-bit free-run timer ch.16 external clock input pin 56 - P312 RTO16 FRCK17 E General-purpose I/O port Waveform generator ch.16 output pin 16-bit free-run timer ch.17 external clock input pin 57 - P313 RTO17 E General-purpose I/O port Waveform generator ch.17 output pin 58 46 P314 DTTI3 TIOA0 E General-purpose I/O port Waveform generator output stop signal input pin 3 Base timer ch.0 TIOA output pin 59 47 P315 RTO18 TIOB0 E General-purpose I/O port Waveform generator ch.18 output pin Base timer ch.0 TIOB input pin 60 48 P316 RTO19 TIOA1 E General-purpose I/O port Waveform generator ch.19 output pin Base timer ch.1 TIOA I/O pin 61 49 P317 RTO20 TIOB1 E General-purpose I/O port Waveform generator ch.20 output pin Base timer ch.1 TIOB input pin 62 50 P318 RTO21 TIOA2 E General-purpose I/O port Waveform generator ch.21 output pin Base timer ch.2 TIOA output pin 63 51 P319 RTO22 TIOB2 E General-purpose I/O port Waveform generator ch.22 output pin Base timer ch.2 TIOB input pin 64 52 P320 RTO23 TIOA3 E General-purpose I/O port Waveform generator ch.23 output pin Base timer ch.3 TIOA I/O pin

May 15, 2015, MB9D560_DS708-00001-3v0-E 27 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 65 53 P321 SIN0 INT3 TIOB3 E General-purpose I/O port Multi-function serial interface ch.0 serial data input pin INT3 external interrupt input pin Base timer ch.3 TIOB input pin 66 54 P322 SOT0 E General-purpose I/O port Multi-function serial interface ch.0 serial data output pin 67 55 P323 SCK0 E General-purpose I/O port Multi-function serial interface ch.0 clock I/O pin 70 58 P324 STOPWT IN6 IN16 E General-purpose I/O port FlexRay stop watch input pin 16-bit input capture ch.6 external pulse input pin 32-bit input capture ch.0 external pulse input pin 71 59 P325 RXDA IN7 IN17 H General-purpose I/O port FlexRay ch.A data input pin 16-bit input capture ch.7 external pulse input pin 32-bit input capture ch.1 external pulse input pin 72 60 P326 TXDA IN8 IN18 H General-purpose I/O port FlexRay ch.A data output pin 16-bit input capture ch.8 external pulse input pin 32-bit input capture ch.2 external pulse input pin 73 61 P327 TXENA IN9 IN19 H General-purpose I/O port FlexRay ch.A operation enable output pin 16-bit input capture ch.9 external pulse input pin 32-bit input capture ch.3 external pulse input pin 74 62 P328 RXDB IN10 IN20 H General-purpose I/O port FlexRay ch.B data input pin 16-bit input capture ch.10 external pulse input pin 32-bit input capture ch.4 external pulse input pin 75 63 P329 TXDB IN11 IN21 H General-purpose I/O port FlexRay ch.B data output pin 16-bit input capture ch.11 external pulse input pin 32-bit input capture ch.5 external pulse input pin 76 64 P330 TXENB IN12 H General-purpose I/O port FlexRay ch.B operation enable output pin 16-bit input capture ch.12 external pulse input pin 77 65 NMIX B Non-maskable interrupt input pin 78 66 RSTX B External reset input pin 79 67 MD1 C Mode pin 1 (with high-voltage control) 80 68 MD0 C Mode pin 0 (with high-voltage control) 81 69 X0 A Main clock oscillation input pin 82 70 X1 Main clock oscillation output pin 84 72 TRSTX J JTAG test reset input 85 73 TCK J JTAG test clock input 86 74 TDO I JTAG test data output 87 75 TDI J JTAG test data input 88 76 TMS J JTAG test mode status input 89 77 nSRST J System reset input for debugger 90 78 P406 SIN1 INT4 E General-purpose I/O port Multi-function serial interface ch.1 serial data input pin INT4 external interrupt input pin

28 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 91 79 P407 SOT1 E General-purpose I/O port Multi-function serial interface ch.1 serial data output pin 92 80 P408 SCK1 E General-purpose I/O port Multi-function serial interface ch.1 clock I/O pin 93 81 P409 RX0 INT0 E General-purpose I/O port CAN ch.0 reception data input pin INT0 external interrupt input pin 94 82 P410 TX0 E General-purpose I/O port CAN ch.0 transmission data output pin 95 83 P411 RX1 INT1 E General-purpose I/O port CAN ch.1 reception data input pin INT1 external interrupt input pin 96 84 P412 TX1 E General-purpose I/O port CAN ch.1 transmission data output pin 97 85 P413 RX2 INT2 E General-purpose I/O port CAN ch.2 reception data input pin INT2 external interrupt input pin 98 86 P414 TX2 E General-purpose I/O port CAN ch.2 transmission data output pin 99 - P415 TIOA4 E General-purpose I/O port Base timer ch.4 TIOA output pin 100 - P416 TIOB4 E General-purpose I/O port Base timer ch.4 TIOB input pin 101 - P417 TIOA5 E General-purpose I/O port Base timer ch.5 TIOA I/O pin 102 - P418 TIOB5 E General-purpose I/O port Base timer ch.5 TIOB input pin 106 - P419 SIN2 INT5 E General-purpose I/O port Multi-function serial interface ch.2 serial data input pin INT5 external interrupt input pin 107 - P420 SOT2 E General-purpose I/O port Multi-function serial interface ch.2 serial data output pin 108 - P131 SCK2 E General-purpose I/O port Multi-function serial interface ch.2 clock I/O pin 109 90 P431 ERDS1 E General-purpose I/O port Error detection output pin ch.1 110 91 P129 DAOUT1 G General-purpose I/O port D/A converter ch.1 analog output pin 111 92 P128 E General-purpose I/O port 112 93 P127 E General-purpose I/O port 113 94 P126 E General-purpose I/O port 119 100 P125 E General-purpose I/O port 120 101 P124 E General-purpose I/O port 121 102 P123 E General-purpose I/O port 122 103 P122 E General-purpose I/O port 123 104 P121 E General-purpose I/O port 124 105 P120 E General-purpose I/O port 125 106 P119 E General-purpose I/O port 126 107 P118 E General-purpose I/O port 127 108 P117 E General-purpose I/O port

May 15, 2015, MB9D560_DS708-00001-3v0-E 29 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 128 109 P116 AIN3 E General-purpose I/O port Up/Down counter ch.3 AIN input pin 129 110 P115 BIN3 E General-purpose I/O port Up/Down counter ch.3 BIN input pin 130 111 P114 ZIN3 E General-purpose I/O port Up/Down counter ch.3 ZIN input pin 131 112 P113 AIN2 E General-purpose I/O port Up/Down counter ch.2 AIN input pin 132 113 P112 BIN2 E General-purpose I/O port Up/Down counter ch.2 BIN input pin 133 114 P111 ZIN2 E General-purpose I/O port Up/Down counter ch.2 ZIN input pin 139 120 P110 4AN7 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 7 input pin 140 121 P109 4AN6 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 6 input pin 141 122 P108 4AN5 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 5 input pin 142 123 P107 4AN4 F General-purpose I/O port 4ch sample-hold A/D converter unit1 analog 4 input pin 145 124 P106 RTO11 E General-purpose I/O port Waveform generator ch.11 output pin 146 125 P105 RTO10 E General-purpose I/O port Waveform generator ch.10 output pin 147 126 P104 RTO9 E General-purpose I/O port Waveform generator ch.9 output pin 148 127 P103 RTO8 E General-purpose I/O port Waveform generator ch.8 output pin 149 128 P102 RTO7 E General-purpose I/O port Waveform generator ch.7 output pin 150 129 P101 RTO6 E General-purpose I/O port Waveform generator ch.6 output pin 151 130 P100 DTTI1 4ADTG1 E General-purpose I/O port Waveform generator output stop signal input pin 1 4ch sample-hold A/D converter unit1 external trigger input pin 152 - P421 SIN3 INT6 FRCK8 E General-purpose I/O port Multi-function serial interface ch.3 serial data input pin INT6 external interrupt input pin 16-bit free-run timer ch.8 external clock input pin 153 - P422 SOT3 FRCK9 IN13 E General-purpose I/O port Multi -function serial interface ch.3 serial data output pin 16-bit free-run timer ch.9 external clock input pin 16-bit input capture ch.13 external pulse input pin 154 - P423 SCK3 FRCK10 IN14 E General-purpose I/O port Multi-function serial interface ch.3 clock I/O pin 16-bit free-run timer ch.10 external clock input pin 16-bit input capture ch.14 external pulse input pin 158 - P425 TIOA8 E General-purpose I/O port Base timer ch.8 TIOA output pin

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Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 159 - P426 TIOB8 E General-purpose I/O port Base timer ch.8 TIOB input pin 160 - P427 TIOA9 E General-purpose I/O port Base timer ch.9 TIOA I/O pin 161 - P428 TIOB9 E General-purpose I/O port Base timer ch.9 TIOB input pin 162 134 P429 MONCLK MM E General-purpose I/O port Clock monitor output pin Clock supervisor main clock error detection output pin 163 135 P200 AN0 F General-purpose I/O port A/D converter analog 0 input pin 164 136 P201 AN1 F General-purpose I/O port A/D converter analog 1 input pin 165 137 P202 AN2 F General-purpose I/O port A/D converter analog 2 input pin 166 138 P203 AN3 F General-purpose I/O port A/D converter analog 3 input pin 167 139 P204 AN4 F General-purpose I/O port A/D converter analog 4 input pin 168 140 P205 AN5 F General-purpose I/O port A/D converter analog 5 input pin 169 141 P206 AN6 F General-purpose I/O port A/D converter analog 6 input pin 170 142 P207 AN7 F General-purpose I/O port A/D converter analog 7 input pin 173 145 P208 AN8 F General-purpose I/O port A/D converter analog 8 input pin 174 146 P209 AN9 F General-purpose I/O port A/D converter analog 9 input pin 175 147 P210 AN10 F General-purpose I/O port A/D converter analog 10 input pin 176 148 P211 AN11 F General-purpose I/O port A/D converter analog 11 input pin 177 149 P212 AN12 F General-purpose I/O port A/D converter analog 12 input pin 178 150 P213 AN13 F General-purpose I/O port A/D converter analog 13 input pin 179 151 P214 AN14 F General-purpose I/O port A/D converter analog 14 input pin 180 152 P215 AN15 F General-purpose I/O port A/D converter analog 15 input pin 185 157 P216 AN16 F General-purpose I/O port A/D converter analog 16 input pin 186 158 P217 AN17 F General-purpose I/O port A/D converter analog 17 input pin 187 159 P218 AN18 F General-purpose I/O port A/D converter analog 18 input pin 188 160 P219 AN19 F General-purpose I/O port A/D converter analog 19 input pin

May 15, 2015, MB9D560_DS708-00001-3v0-E 31 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 189 161 P220 AN20 TIOA6 F General-purpose I/O port A/D converter analog 20 input pin Base timer ch.6 TIOA output pin 190 162 P221 AN21 TIOB6 F General-purpose I/O port A/D converter analog 21 input pin Base timer ch.6 TIOB input pin 191 163 P222 AN22 TIOA7 F General-purpose I/O port A/D converter analog 22 input pin Base timer ch.7 TIOA I/O pin 192 164 P223 AN23 TIOB7 F General-purpose I/O port A/D converter analog 23 input pin Base timer ch.7 TIOB input pin 195 167 P224 AN24 F General-purpose I/O port A/D converter analog 24 input pin 196 168 P225 AN25 SIN4 INT7 F General-purpose I/O port A/D converter analog 25 input pin Multi-function serial interface ch.4 serial data input pin INT7 external interrupt input pin 197 169 P226 AN26 SOT4 IN0 F General-purpose I/O port A/D converter analog 26 input pin Multi-function serial interface ch.4 serial data output pin 16-bit input capture ch.0 external pulse input pin 198 170 P227 AN27 SCK4 IN1 F General-purpose I/O port A/D converter analog 27 input pin Multi-function serial interface ch.4 clock I/O pin 16-bit input capture ch.1 external pulse input pin 199 171 P228 AN28 SCS40 IN2 F General-purpose I/O port A/D converter analog 28 input pin Multi-function serial interface ch.4 serial chip select 0 I/O pin 16-bit input capture ch.2 external pulse input pin 200 172 P229 AN29 SCS41 IN3 F General-purpose I/O port A/D converter analog 29 input pin Multi-function serial interface ch.4 serial chip select 1 I/O pin 16-bit input capture ch.3 external pulse input pin 201 173 P230 AN30 SCS42 IN4 F General-purpose I/O port A/D converter analog 30 input pin Multi-function serial interface ch.4 serial chip select 2 I/O pin 16-bit input capture ch.4 external pulse input pin 202 174 P231 AN31 SCS43 IN5 F General-purpose I/O port A/D converter analog 31 input pin Multi-function serial interface ch.4 serial chip select 3 I/O pin 16-bit input capture ch.5 external pulse input pin 203 175 P300 ADTG0 E General-purpose I/O port A/D converter external trigger input pin 204 - P301 TIOA10 FRCK4 E General-purpose I/O port Base timer ch.10 TIOA output pin 16-bit free-run timer ch.4 external clock input pin 205 - P302 TIOB10 FRCK5 E General-purpose I/O port Base timer ch.10 TIOB input pin 16-bit free-run timer ch.5 external clock input pin

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Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 206 - P303 TIOA11 FRCK6 E General-purpose I/O port Base timer ch.11 TIOA I/O pin 16-bit free-run timer ch.6 external clock input pin 207 - P304 TIOB11 FRCK7 E General-purpose I/O port Base timer ch.11 TIOB input pin 16-bit free-run timer ch.7 external clock input pin 18 14 AVRH0 - 4ch sample-hold A/D converter unit0 upper limit reference voltage 19 15 AVRL0 - 4ch sample-hold A/D converter unit0 lower limit reference voltage 20 16 AVR0 - 4ch sample-hold A/D converter unit0 reference voltage 21 17 AVSS0 - 4ch sample-hold A/D converter unit0 analog GND 22 18 AVCC0 - 4ch sample-hold A/D converter unit0 analog power supply 134 115 AVCC1 - 4ch sample-hold A/D converter unit1 analog power supply 135 116 AVSS1 - 4ch sample-hold A/D converter unit1 analog GND 136 117 AVR1 - 4ch sample-hold A/D converter unit1 reference voltage 137 118 AVRL1 - 4ch sample-hold A/D converter unit1 lower limit reference voltage 138 119 AVRH1 - 4ch sample-hold A/D converter unit1 upper limit reference voltage 38 34 RVRH0 - *1 39 35 RVRL0 - *2 40 36 RVR0 - *2 41 37 RVSS0 - *2 42 38 RVCC0 - *1 114 95 RVCC1 - *1 115 96 RVSS1 - *2 116 97 RVR1 - *2 117 98 RVRL1 - *2 118 99 RVRH1 - *1 181 153 AVCC2 - A/D converter analog power supply 182 154 AVSS2 - A/D converter analog GND 183 155 AVRL2 - A/D converter lower limit reference voltage 184 156 AVRH2 - A/D converter upper limit reference voltage 103 155 172 193 131 144 165 VCC12 - 1.2V power supply 105 144 157 208 133 176 VCC5 - 5.0V power supply

May 15, 2015, MB9D560_DS708-00001-3v0-E 33 CONFIDENTIAL Pin Number Pin Name I/O Circuit Type Functions 208pin 176pin 104 143 156 171 194 132 143 166 VSS - GND *1: The part number without RDC does not use this pin. Connect it with the VCC5 pin. *2: The part number without RDC does not use this pin. Connect it with the VSS pin.

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I/O Circuit Type Type Circuit Remarks A − Oscillation feedback resistor: Approx. 1 MΩ B − CMOS hysteresis input − With 50 kΩ pull-up resistor C − Schmitt input − With high withstand voltage control D − CMOS level output IOH=-1/-2 mA, IOL=1/2 mA E − General-purpose I/O port − CMOS level output IOH=-1/-2 mA, IOL=1/2 mA − With 50 kΩ pull-up resistor − CMOS hysteresis input (0.7Vcc/0.3Vcc) − Automotive input (0.8Vcc/0.5Vcc) Clock input St andby cont rol signal CMOS hysteresis input Pull-up resistor Mode input High withstand voltage control High withstand voltage mode input N-ch N-ch N-ch N-ch Digital out put N-ch P-ch Pull-up control Digital output Standby control CMOS hysteresis input Automotive input N-ch P-chP-ch R

May 15, 2015, MB9D560_DS708-00001-3v0-E 35 CONFIDENTIAL Type Circuit Remarks F − With Analog input, General-purpose I/O port − CMOS level output IOH=-1/-2 mA, IOL=1/2 mA − With 50 kΩ pull-up resistor − CMOS hysteresis input (0.7Vcc/0.3Vcc) During standby, the input value retains the previous value. − Automotive input (0.8Vcc/0.5Vcc) During standby, the input value retains the previous value. G − With Analog output , General-purpose I/O port − CMOS level output IOH=-1/-2 mA, IOL=1/2 mA − With 50 kΩ pull-up resistor − CMOS hysteresis input (0.7Vcc/0.3Vcc) During standby, the input value retains the previous value. − Automotive input (0.8Vcc/0.5Vcc) During standby, the input value retains the previous value. H − General-purpose I/O port − CMOS level output IOH=-1/-2/-4 mA, IOL=1/2/4 mA − With 50 kΩ pull-up resistor − FlexRay input (0.7Vcc/0.3Vcc) During standby, the input value retains the previous value. − Automotive input (0.8Vcc/0.5Vcc) During standby, the input value retains the previous value. Pull-up control Digital output Standby control CMOS hysteresis input Automotive input N-ch P-chP-ch Analog input R Pull-up control Digital output Standby control CMOS hysteresis input Automotive input N-ch P-chP-ch Analog output R Pull-up control Digital output Standby control FlexRay input Automotive input N-ch P-chP-ch R

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I − CMOS level output IOH=-5 mA, IOL=5 mA J − TTL hysteresis input (2V/0.8V) K − Analog input L − Analog output Digital out put N-ch P-ch TTL hyster esi s i nput Analog input Analog output

May 15, 2015, MB9D560_DS708-00001-3v0-E 37 CONFIDENTIAL 7. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices.

7.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.

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Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

7.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion’s recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.

May 15, 2015, MB9D560_DS708-00001-3v0-E 39 CONFIDENTIAL Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C and 30 ˚C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125 ˚C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

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7.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

May 15, 2015, MB9D560_DS708-00001-3v0-E 41 CONFIDENTIAL 8. Handling Devices For Latch-up Prevention If a voltage higher than VCC5 or VCC12, or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied between VCC5 to VSS and VCC12 to VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings in device application. Also, the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0, RVEH1) and analog input must not exceed the digital power supply (VCC5) when the power supply to the analog system is turned on or off. In the correct power-on sequence, turn on the digital power supply voltage (VCC5, VCC12) and analog power supply voltages (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0, RVRH1) simultaneously. Alternatively, turn on the digital power supply voltage (VCC5) first, and then turn on the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0, RVRH1). Treatment of Unused Pins If unused input pins are left open, they may cause a permanent damage to the device due to device malfunction or latch-up. Connect a 2 kΩ or higher resistor to each of unused input pins for pull-up or pull-down processing. Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins.

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The device is designed to ensure that if the device contains multiple VCC5, VCC12 and VSS pins, the pins that should be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown below, all VSS power supply pins must be treated in the similar way. If multiple VCC5 or VCC12 or VSS systems are connected, the device cannot operate correctly even within the guaranteed operating range. Power Supply Input Pin The power supply pins should be connected to VCC5, VCC12 and VSS of this device at the low impedance from the power supply source. In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to use as a bypass capacitor between VCC5, VCC12 and VSS pins Crystal Oscillation Circuit An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the device. The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits. Mode Pin (MD1, MD0) Connect the MD1, MD0 mode pin to the VCC5 or VSS pin directly. To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and VCC5 or VSS pin on the printed circuit board. Also, use the low-impedance pin connection. Notes during PLL Clock Operation When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self oscillator circuit built in the PLL. This operation is not guaranteed. VCC12 VSS VCC5 VSS VCC5 VCC12 VSS VCC VDD VCC5 VCC12 VSS VSS VCC5 VCC12

May 15, 2015, MB9D560_DS708-00001-3v0-E 43 CONFIDENTIAL Treatment of R/D Converter and A/D Converter Power Supply Pins If unuse R/D converter and A/D converter, needs connection as follows. − AVCC0 = AVCC1= AVCC2 = AVRH0= AVRH1 = AVRH2 = RVCC0 = RVCC1 = RVRH0 =RVRH1 = VCC5 − AVSS0 = AVSS1 = AVSS2 = AVRL0 = AVRL1 = AVRL2 = AVR0 = AVR1 = RVSS0 = RVSS1 = RVRL0 = RVRL1 = RVR0 = RVR1 = VSS Note on Using External Clock The external clock is unsupported. External direct clock input cannot use. Power-on Sequence of R/D Converter and A/D Converter Power Supply Analog Inputs Be sure to turn on the digital power supply (VCC5, VCC12) first, and then turn on the R/D converter and A/D converter power supplies*1 and analog inputs*2. Also, turn off the R/D converter and A/D converter power supplies*1 and analog inputs*2 first, and then turn off the digital power supply (VCC5, VCC12). When the AVRH0, AVRH1, AVRH2, RVRH0 and RVRH1 pin voltages are turned on or off, they must not exceed AVCC0, AVCC1, AVCC2, RVCC0 and RVCC1. Even if a common analog input pin is used as an input port, its input voltage must not exceed AVCC0, AVCC1 or AVCC2. (However, the analog power supply voltage and digital power supply voltage can be turned on or off simultaneously.) *1: AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, AVRL0, AVRL1, AVRL2, RVCC0, RVCC1, RVRH0, RVRH1, RVRL0, RVRL1 *2: MAG_PLUS0, MAG_MINUS0, COS_PLUS0, COS_MINUS0, SIN_PLUS0, SIN_MINUS0, COS_IN0, SIN_IN0, MAG_PLUS1, MAG_MINUS1, COS_PLUS1, COS_MINUS1, SIN_PLUS1, SIN_MINUS1, COS_IN1, SIN_IN1, 4AN0 to 4AN7, AN0 to AN31 Notes When Writing Data in a Register Having the Status Flag When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, take care not to clear its status flag erroneously. The program must be written not to clear the flag to the status bit, and to set the control bits to have the desired value. Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.) The Byte, Half-word, or Word access must be used to write data in the control bits and status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. Note: − These points can be ignored because the bit instructions already take the points into consideration for registers that are supported by bit-band unit. These points must be considered when using the bit instruction for registers that are not supported by bit-band unit.

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Block Diagram Note: − In the block diagram, block name (Config, Slave) describe bus connection for register setting of control block. AHB-32 AXI2AHB AHB-32 AXI2AHB AHB-32 AHB-32 CLK_PERI0 CLK_PERI0 CLK_PERI5 CLK_PERI4 Core Group (2-Core) TCFLASH TCRAM #0TCRAM #1 SecurityTCFLASH #1 Security ETM ETM Debug Group (CoreSightTM) Debug I/F (JTAG) AHB-MAPB-SAPB-M Security JTAG Wakeup APB-32 Trace Group Debug APB ETB (Trace Buffer) AHB2APB (Priviledge Protection) Security Checker JTAG_SWCLKTCK CLK_DBG Common Peripheral Group CAN Prescaler 16-bit Base Timer [PWM/PPG/RLT/PWC] (ch.0 to 11) MPU AHB (Config, Slave) AHB-32 CAN (ch.0 to 2) RAM AHB2APB 32-bit FRT (ch.0 to 4) 32-bit ICU (unit0 to 2, ch.0 to 5) MFS (ch.0 to 4) CRC (ch.0 to 1) CR Calibration APB-32 DMAC (Config, Slave) BBU GPIO Port Pin Config (Config, Slave) Resource Input Config (Config, Slave) CLK_PERI0 CLK_PERI1 AXI2AHB High Performance Matrix (HPM) AXI2AHB AXI2AHB AXI-64 AXI2AHB MPU AHB AHB2AXI DMAC (ch.0 to 15) Exclusive Access M emory (EAM) AXI-SAHB2AXI AHB-64 CLK_DMA CLK_HPM Memory & Config Group AHB-64 BBU TCRAM #0 (Config, Slave) TCFLASH #0 (Config, Slave) TCRAM #1 (Config, Slave) TCFLASH #1 (Config, Slave) WorkFLASH BootROM TPU#0 IRC #0 RAM Security Protection TPU#1 IRC #1 RAM WorkFLASH Security IPCU NMI distribution Wakeup Request #0 Wakeup Request #1 CLK_MEMC MCU Config Group AHB-32 HW-WDT EXT-IRQ (NMI) SW-WDT #0 System Controller (SYSC) RST manage Clock Mode control State SCT LVD Wakeup detect Clock output PONR CSV Fast-CR PLL Slow-CR SW-WDT #1 BBU CLK_SYSC_PD1 Application Specific Peripheral Group PORT MUX (Port Pin Config) I/O Resource Input Configuration BBU BBU CLK_PERI6CLK_PERI7 FlexRay (A+Bch) WFG (unit0, ch.0 to 5) 16-bit FRT for RDC (ch.18) 16-bit OCU (unit0 to 2, ch.0to 5) 4ch-SH ADC (unit0, ch.0 to 3) MVA (unit 0) 8/16bit UDC (ch.0 to 1) 16-bit ICU (unit0 to 1, ch.0 to 3) 16-bit FRT (ch.0 to 5) RDC (unit 0) DAC (ch.0) FlexRay/RDC Clock Control Clock Monitor RDC (unit 1) DAC (ch.1) WFG (unit1, ch.6 to 11) 16-bit FRT for RDC (ch.19) 16-bit OCU (unit3 to 5, ch.6 to 11) 4ch-SH ADC (unit1, ch.4 to 7) MVA (unit 1) 8/16bit UDC (ch.2 to 3) 16-bit ICU (unit2 to 3, ch.4 to 7) 16-bit FRT (ch.6 to 11) 16-bit FRT (ch.12 to 17) 16bit OCU (unit6 to 11, ch.12 to 23) 16-bit ICU (unit4 to 7, ch.8to 14) WFG (unit2 to 3, ch.12 to 23) 12-bit A/D Converter (ch.0 to 31) AHB2RBus AHB2APB Application Specific Peripheral Group A Application Specific Peripheral Group B AHB-M Processor B0TCM ATCM MPU B1TCM AXI-S ATCM B0TCM B1TCM LLPP(AXI32-M)AXI-M AXI-M AXI-SLLPP(AXI32-M) CPU #0CPU #1 MPU CLK_CPU0CLK_CPU1 CortexTM -R5F CortexTM -R5F DAP Debug APB ATB ATB CLK_ATBCLK_ATB AHB-MAPB-SAPB-M Security

May 15, 2015, MB9D560_DS708-00001-3v0-E 45 CONFIDENTIAL Group Group Name Description Core Group − CPU and TCM connected memory group Debug Group − CoreSight of Debugging group MCU Config Group − System control and supervision IP group Memory & Config Group _ − CPU related function and memory group Common Peripheral Group − Common peripheral IP group for vehicle application Application Specific Peripheral Group − Product specified peripheral group Independent IP Name Description HPM − Bus matrix of AXI − Bus bridge (AXI-to-AHB, AHB-to-AXI) DMAC − DMA controller EAM − Exclusive access memory Resource input configuration − Input selection circuit of MCU peripheral Port MUX − Port MUX circuit I/O − I/O circuit Note: − Each master connects to HPM. Each master has different transaction ID on AXI, Out-Of-Order for transaction completion.

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Memory Map Address Block Start End Overview Function 0x0000_0000 64KB: 0x0000_FFFF 96KB: 0x0001_7FFF 128KB: 0x0001_FFFF Memory (Each CPU exclusive space) TCRAM 0x0002_0000 0x007F_FFFF Reserved 0x0080_0000 512KB: 0x0087_FFFF 768KB: 0x008B_FFFF 1024KB: 0x008F_FFFF TCFLASH large sector area (TCM connection) 0x0090_0000 0x00FD_FFFF Reserved 0x00FE_0000 0x00FF_FFFF TCFLASH small sector area (TCM connection) 0x0100_0000 512KB: 0x0107_FFFF 768KB: 0x010B_FFFF 1024KB: 0x010F_FFFF TCFLASH large sector area (AXI connection) 0x0110_0000 0x01FD_FFFF Reserved 0x01FE_0000 0x01FF_FFFF TCFLASH small sector area (AXI connection) 0x0200_0000 0x027F_FFFF Memory (Common space) Reserved 0x0280_0000 0x0280_0FFF EAM 0x0280_1000 0x03FF_FFFF Reserved 0x0400_0000 64KB: 0x0400_FFFF 96KB: 0x0401_7FFF 128KB: 0x0401_FFFF CPU0 space TCRAM 0x0402_0000 0x047F_FFFF Reserved 0x0480_0000 512KB: 0x0487_FFFF 768KB: 0x048B_FFFF 1024KB: 0x048F_FFFF CPU0 space TCFLASH large sector area (TCM connection) 0x0490_0000 0x04FD_FFFF Reserved 0x04FE_0000 0x04FF_FFFF CPU0 space TCFLASH small sector area (TCM connection) 0x0500_0000 512KB: 0x0507_FFFF 768KB: 0x050B_FFFF 1024KB: 0x050F_FFFF CPU0 space TCFLASH large sector area (AXI connection) 0x0510_0000 0x05FD_FFFF Reserved 0x05FE_0000 0x05FF_FFFF CPU0 space TCFLASH small sector area (AXI connection) 0x0600_0000 64KB: 0x0600_FFFF 96KB: 0x0601_7FFF 128KB: 0x0601_FFFF CPU1 space TCRAM 0x0602_0000 0x067F_FFFF Reserved 0x0680_0000 512KB: 0x0687_FFFF 768KB: 0x068B_FFFF 1024KB: 0x068F_FFFF CPU1 space TCFLASH large sector area (TCM connection) 0x0690_0000 0x06FD_FFFF Reserved

May 15, 2015, MB9D560_DS708-00001-3v0-E 47 CONFIDENTIAL Address Block Start End Overview Function 0x06FE_0000 0x06FF_FFFF Memory (Common space) CPU1 space TCFLASH small sector area (TCM connection) 0x0700_0000 512KB: 0x0707_FFFF 768KB: 0x070B_FFFF 1024KB: 0x070F_FFFF CPU1 space TCFLASH large sector area (AXI connection) 0x0710_0000 0x07FD_FFFF Reserved 0x07FE_0000 0x07FF_FFFF CPU1 space TCFLASH small sector area (AXI connection) 0x0800_0000 0x0DFF_FFFF Reserved 0x0E00_0000 0x0E00_FFFF WorkFLASH0 mirror area 1 0x0E01_0000 0x0E01_FFFF WorkFLASH1 mirror area 1 0x0E02_0000 0x0E0F_FFFF Reserved 0x0E10_0000 0x0E10_FFFF WorkFLASH0 Reserved mirror area 2 0x0E11_0000 0x0E11_FFFF WorkFLASH1 Reserved mirror area 2 0x0E12_0000 0x0E1F_FFFF Reserved 0x0E20_0000 0x0E20_FFFF WorkFLASH0 mirror area 3 0x0E21_0000 0x0E21_FFFF WorkFLASH1 mirror area 3 0x0E22_0000 0x0FFF_FFFF Reserved 0x1000_0000 0x9FFF_FFFF Reserved Reserved 0xA000_0000 0xA1FF_FFFF Bit band alias area Reserved 0xA200_0000 0xA27F_FFFF Bit band alias area (Memory & Config Group) 0xA280_0000 0xA2FF_FFFF Reserved 0xA300_0000 0xA37F_FFFF Bit band alias area (MCU Config Group) 0xA380_0000 0xA47F_FFFF Bit band alias area (Common Peripheral Group) 0xA480_0000 0xA7FF_FFFF Reserved 0xA800_0000 0xA87F_FFFF Bit band alias area (Application Specific Peripheral Group A) 0xA880_0000 0xA8FF_FFFF Bit band alias area (Application Specific Peripheral Group B) 0xA900_0000 0xAFFF_FFFF Reserved 0xB000_0000 0xBFFF_FFFF I/O area (Bit band area) I/O 0xC000_0000 0xEFFF_FFFF Reserved Reserved 0xF000_0000 0xFFFE_DFFF BootROM area Reserved 0xFFFE_E000 0xFFFE_FFFF Error Config 0xFFFF_0000 0xFFFF_FFFF BootROM

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Notes: − Each CPU exclusive space define memory space for each CPU specified. The other master cannot access (Reserved area). If the other master access to each CPU exclusive space, access from common space. − Reserved area access cause bus error. − However, following access of reserved area will be not bus error. 0x0090_0000 to 0x00FD_FFFF 0x0110_0000 to 0x01FD_FFFF 0x0490_0000 to 0x04FD_FFFF 0x0510_0000 to 0x05FD_FFFF 0x0690_0000 to 0x06FD_FFFF 0x0710_0000 to 0x07FD_FFFF 0x1000_0000 to 0x1FFF_FFFF 0x2000_0000 to 0x2FFF_FFFF − The following area should be set device attribution or strongly ordered attribution as core access. 1. I/O area 2. Bit band alias area 3. Error Config (BootROM area) 4. WorkFLASH (when program) 5. TCFLASH (when program) About device attribute and Strongly Ordered attribute, see "ARM®Architecture Reference Manual ARM®v7-A and ARM®v7-R edition (ARM DDI 0406B)". − TCFLASH has a TCM-connected region and an AXI-connected region. AXI-connected region is dedicated for flash memory programming/erasing. When read operation in user mode, use TCM-connected region.

May 15, 2015, MB9D560_DS708-00001-3v0-E 49 CONFIDENTIAL 11. I/O Map I/O Address Map (HPM, etc.) Address Area Start End Overview Function 0xB000_0000 0xB03F_FFFF Reserved Reserved I/O Address Map (Memory & Config Group) Address Area Start End Overview Function 0xB040_0000 0xB040_0FFF Memory & Config Group IRC0 0xB040_1000 0xB040_1FFF IRC1 0xB040_2000 0xB040_6FFF Reserved 0xB040_7000 0xB040_73FF NMI distributor 0xB040_7400 0xB040_7FFF Reserved 0xB040_8000 0xB040_83FF TPU0 0xB040_8400 0xB040_8FFF Reserved 0xB040_9000 0xB040_93FF TPU1 0xB040_9400 0xB040_FFFF Reserved 0xB041_0000 0xB041_03FF TCRAM0 IF 0xB041_0400 0xB041_07FF TCRAM1 IF 0xB041_0800 0xB041_0FFF Reserved 0xB041_1000 0xB041_13FF TCFLASH0 IF 0xB041_1400 0xB041_17FF TCFLASH1 IF 0xB041_1800 0xB041_1FFF Reserved 0xB041_2000 0xB041_23FF WorkFLASH0 IF 0xB041_2400 0xB041_27FF WorkFLASH1 IF 0xB041_2800 0xB041_4FFF Reserved 0xB041_5000 0xB041_5FFF IPCU 0xB041_6000 0xB04F_FFFF Reserved

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I/O Address Map (Debug Group) Address Area Start End Overview Function 0xB050_0000 0xB050_0FFF Debug Group DAPROM 0xB050_1000 0xB050_1FFF ETB 0xB050_2000 0xB050_2FFF CTI4 0xB050_3000 0xB050_3FFF TPIU 0xB050_4000 0xB050_4FFF TRACE_FUNNEL 0xB050_5000 0xB057_FFFF Reserved 0xB058_0000 0xB058_0FFF CORTEXROM0 0xB058_1000 0xB058_FFFF Reserved 0xB059_0000 0xB059_0FFF CORE0 0xB059_1000 0xB059_1FFF Reserved 0xB059_2000 0xB059_2FFF CORE1 0xB059_3000 0xB059_7FFF Reserved 0xB059_8000 0xB059_8FFF CTI0 0xB059_9000 0xB059_9FFF CTI1 0xB059_A000 0xB059_BFFF Reserved 0xB059_C000 0xB059_CFFF ETM0 0xB059_D000 0xB059_DFFF ETM1 0xB059_E000 0xB05F_FFFF Reserved

May 15, 2015, MB9D560_DS708-00001-3v0-E 51 CONFIDENTIAL I/O Address Map (MCU Config Group) Address Area Start End Overview Function 0xB060_0000 0xB060_07FF MCU Config Group SYSC 0xB060_0800 0xB060_0FFF MODEC 0xB060_1000 0xB060_7FFF Reserved 0xB060_8000 0xB060_83FF SW-WDT0 0xB060_8400 0xB060_8FFF Reserved 0xB060_9000 0xB060_93FF SW-WDT1 0xB060_9400 0xB060_BFFF Reserved 0xB060_C000 0xB060_C3FF HW-WDT 0xB060_C400 0xB061_FFFF Reserved 0xB062_0000 0xB062_03FF EXT-IRQ 0xB062_0400 0xB06F_FFFF Reserved I/O Address Map (Common Peripheral Group) Address Area Start End Overview Function 0xB070_0000 0xB070_3FFF Common Peripheral Group (AHB32) DMAC 0xB070_4000 0xB070_FFFF Reserved 0xB071_0000 0xB071_0FFF MPU AHB 0xB071_1000 0xB071_7FFF Reserved 0xB071_8000 0xB071_87FF CRC (ch.0 to 1) 0xB071_8800 0xB071_FFFF Reserved 0xB072_0000 0xB072_0BFF CAN (ch.0 to 2) 0xB072_0C00 0xB072_7FFF Reserved 0xB072_8000 0xB072_83FF CAN prescaler 0xB072_8400 0xB072_FFFF Reserved 0xB073_0000 0xB073_03FF CR calibration 0xB073_0400 0xB073_7FFF Reserved 0xB073_8000 0xB073_8FFF GPIO 0xB073_9000 0xB073_FFFF Reserved 0xB074_0000 0xB074_3FFF PPC 0xB074_4000 0xB074_7FFF Reserved 0xB074_8000 0xB074_8FFF RIC 0xB074_9000 0xB07F_FFFF Reserved 0xB080_0000 0xB080_13FF Common Peripheral Group (APB) MFS (ch.0 to 4) 0xB080_1400 0xB080_7FFF Reserved 0xB080_8000 0xB080_AFFF Base timer (ch.0 to 11) 0xB080_B000 0xB081_FFFF Reserved 0xB082_0000 0xB082_13FF 32-bit FRT (ch.0 to 4) 0xB082_1400 0xB082_7FFF Reserved 0xB082_8000 0xB080_8BFF 32-bit ICU (ch.0 to 5) 0xB082_8C00 0xB08F_FFFF Reserved

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I/O Address Map (Product Specified Peripheral Bus) Address Area Start End Overview Function 0xB090_0000 0xB0FF_FFFF Reserved Reserved 0xB100_0000 0xB100_00FF Application Specific Peripheral Group A (AHB-32) 16-bit FRT (ch.6 to 11) 0xB100_0100 0xB100_01FF 16-bit OCU (ch.6 to 11) 0xB100_0200 0xB100_02FF 16-bit ICU (ch.4 to 7) 0xB100_0300 0xB100_03FF 4ch-SH ADC (unit1) 0xB100_0400 0xB100_04FF WFG (ch.6 to 11) 0xB100_0500 0xB100_05FF UDC (ch.2 to 3) 0xB100_0600 0xB100_07FF Reserved 0xB100_0800 0xB100_09FF MVA (unit1) 0xB100_0A00 0xB100_0BFF Reserved 0xB100_0C00 0xB100_0CFF RDC (unit1) 0xB100_0D00 0xB100_0DFF DAC (ch.1) 0xB100_0E00 0xB100_0FFF Reserved 0xB101_0000 0xB101_00FF Application Specific Peripheral Group A (APB) 16-bit FRT (ch.12 to 17) 0xB101_0100 0xB101_01FF 16-bit OCU (ch.12 to 23) 0xB101_0200 0xB101_02FF 16-bit ICU (ch.8 to 14) 0xB101_0300 0xB101_03FF Reserved 0xB101_0400 0xB101_05FF 12-bit ADC (ch.0 to 31) 0xB101_0600 0xB101_06FF WFG(ch.12 to 23) 0xB101_0700 0xB101_0FFF Reserved 0xB101_1000 0xB101_2FFF Other (WFG) 0xB101_3000 0xB101_3FFF Other (ADC, CSV) 0xB101_4000 0xB1FF_FFFF Reserved Reserved 0xB200_0000 0xB200_00FF Application Specific Peripheral Group B (AHB-32) 16-bit FRT (ch.0 to 5) 0xB200_0100 0xB200_01FF 16-bit OCU (ch.0 to 5) 0xB200_0200 0xB200_02FF 16-bit ICU (ch.0 to 3) 0xB200_0300 0xB200_03FF 4ch-SH ADC (unit0) 0xB200_0400 0xB200_04FF WFG (ch.0 to 5) 0xB200_0500 0xB200_05FF UDC (ch.0 to 1) 0xB200_0600 0xB200_07FF Reserved 0xB200_0800 0xB200_09FF MVA (unit0) 0xB200_0A00 0xB200_0BFF Reserved 0xB200_0C00 0xB200_0CFF RDC (unit0) 0xB200_0D00 0xB200_0DFF DAC (ch.0) 0xB200_0E00 0xB200_0EFF Reserved 0xB200_0F00 0xB200_0FFF Reserved 0xB200_1000 0xB200_17FF FlexRay (ch.A/ch.B) 0xB200_1800 0xB200_FFFF Reserved 0xB201_0000 0xB201_00FF Application Specific Peripheral Group B (R-Bus) FlexRay/RDC clock control 0xB201_0100 0xB201_01FF Clock monitor 0xB201_0200 0xBFFF_FFFF Reserved Reserved

May 15, 2015, MB9D560_DS708-00001-3v0-E 53 CONFIDENTIAL I/O address Map (Error Config) Address Area Start End Overview Function 0xFFFE_E000 0xFFFE_E3FF Error Config IRC0 (NMIVASBR) 0xFFFE_E400 0xFFFE_E7FF IRC1 (NMIVASBR) 0xFFFE_E800 0xFFFE_F7FF Reserved 0xFFFE_F800 0xFFFE_FBFF IRC (NMIVASBR) mirror* 0xFFFE_FC00 0xFFFE_FFFF BootROM IF *: CPU0 is IRC0, CPU1 is IRC1 able to access this area. The master of excepted CPU is reserved area. Notes: − I/O address map shows maximum area for possibility. It depends on functions. The detail information, see each address map. − It causes bus error to access to reserved area. However, following reserved area access is not generation of bus error. 0xB018_0000 to 0xB018_03FF 0xB05C_0000 to 0xB05C_0FFF 0xB05E_0000 to 0xB05E_03FF 0xB05E_0400 to 0xB05E_07FF 0xB05E_0800 to 0xB05E_0BFF 0xB05E_0C00 to 0xB05E_0FFF

54 MB9D560_DS708-00001-3v0-E, May 15, 2015

Pin Statuses in CPU Status Pin Statuses (1/2) External factor generation in progress 208 pin 176 pin Internal reset issuance in progress Internal reset issuance in progress After internal reset issuance (Before GPORT setting) Before internal reset issuance Internal reset issuance in progress Internal reset issuance in progress After internal reset issuance (Before GPORT setting) CPU sleep High impedance disabled (SYSC_SSPECFGR: PSSPADCTRL=0) High impedance enabled (SYSC_SSPECFGR: PSSPADCTRL=1) High impedance disabled (SYSC_SSPECFGR: PSSPADCTRL=0) High impedance enabled (SYSC_SSPECFGR: PSSPADCTRL=1) 3 - P305/FRCK0 4 - P306/FRCK1 5 3 P000/DTTI0/4ADTG0 6 4 P001/RTO0 7 5 P002/RTO1 8 6 P003/RTO2 9 7 P004/RTO3 10 8 P005/RTO4 11 9 P006/RTO5 14 10 P007/4AN0 15 11 P008/4AN1 16 12 P009/4AN2 17 13 P010/4AN3 23 19 P011/RDC_W0/ZIN0 24 20 P012/RDC_V0/BIN0 25 21 P013/RDC_U0/AIN0 26 22 P014/RDC_Z0/ZIN1 27 23 P015/RDC_B0/BIN1 28 24 P016/RDC_A0/AIN1 29 25 AREF20 Analog output 30 26 SIN_IN0 31 27 COS_IN0 32 28 SIN_OUT0 Analog output 33 29 SIN_MINUS0 34 30 SIN_PLUS0 35 31 COS_PLUS0 36 32 COS_MINUS0 37 33 COS_OUT0 Analog output 43 39 RDC_ACT0/P026 L*5 L H/L L*5 L*5 L H/L L H/L H/L 44 40 MAG_MINUS0 45 41 MAG_PLUS0 46 42 MAG_OUT0 Analog output 47 43 P430/ERDS0 48 - P030/DTTI2/FRCK12 49 - P031/RTO12/FRCK13 50 - P309/RTO13/FRCK14 51 - P310/RTO14/FRCK15 55 - P311/RTO15/FRCK16 56 - P312/RTO16/FRCK17 57 - P313/RTO17 58 46 P314/DTTI3/TIOA0 59 47 P315/RTO18/TIOB0 60 48 P316/RTO19/TIOA1 61 49 P317/RTO20/TIOB1 62 50 P318/RTO21/TIOA2 63 51 P319/RTO22/TIOB2 64 52 P320/RTO23/TIOA3 65 53 P321/SIN0/INT3/TIOB3 66 54 P322/SOT0 67 55 P323/SCK0 70 58 P324/STOPWT/IN6/IN16 71 59 P325/RXDA/IN7/IN17 72 60 P326/TXDA/IN8/IN18 73 61 P327/TXENA/IN9/IN19 74 62 P328/RXDB/IN10/IN20 75 63 P329/TXDB/IN11/IN21 76 64 P330/TXENB/IN12 77 65 NMIX 78 66 RSTX 79 67 MD1 80 68 MD0 81 69 X0 82 70 X1 84 72 TRSTX 85 73 TCK 86 74 TDO - 87 75 TDI 88 76 TMS 89 77 nSRST 90 78 P406/SIN1/INT4 Hi-Z/Input blocked*4 Hi-Z/Input blocked*4 91 79 P407/SOT1 92 80 P408/SCK1 93 81 P409/RX0/INT0 Hi-Z/Input blocked*4 Hi-Z/Input blocked*4 94 82 P410/TX0 Hi-Z/Input blocked Hi-Z/Input blocked 95 83 P411/RX1/INT1 Hi-Z/Input blocked*4 Hi-Z/Input blocked*4 96 84 P412/TX1 Hi-Z/Input blocked Hi-Z/Input blocked 97 85 P413/RX2/INT2 Hi-Z/Input blocked*4 Hi-Z/Input blocked*4 98 86 P414/TX2 99 - P415/TIOA4 100 - P416/TIOB4 101 - P417/TIOA5 102 - P418/TIOB5 106 - P419/SIN2/INT5 Hi-Z/Input blocked*4 Hi-Z/Input blocked*4 107 - P420/SOT2 108 - P131/SCK2 109 90 P431/ERDS1 Hi-Z/Input blocked Hi-Z/Last status retained Last status retained*6 Hi-Z/Input blocked Last status retained GPORTEN control External reset factor*1 Pin Name Analog output Analog input After external factor releasing Pin No. Analog input Analog output With controlWithout controlWith controlWith control Input enabled After external factor releasing Input enabled Input enabled Hi-Z/Input blocked Hi-Z/Last status retained Hi-Z/ Input blocked Analog output Analog output Analog output Analog output L Hi-Z/ Input blocked Analog output Analog input Hi-Z/Input blocked Analog output Analog input Last status retained Analog input Hi-Z/ Last status retained Analog output Input enabledInput enabled Hi-Z/Input blocked Last status retained Hi-Z/Input blocked Analog output Analog input Analog output Analog input Input enabled Input enabled Hi-Z/Input blocked Analog input Analog output Last status retained Input enabled Analog output Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Last status retained Hi-Z/Input blocked Hi-Z/Input blocked Input enabled Last status retained*6 Last status retained Input enabled Analog input Analog output Analog input Analog output L Input enabled Internal reset issuance in progress Hi-Z/Input blocked Input enabled Watch mode Hi-Z/Input blocked Input enabled Analog output Analog output Analog input Analog output Hi-Z/Input blocked Analog input External factor generation in progress External reset factor*2 Stop mode Last status retained Hi-Z/Input blocked Internal reset factor*3 Hi-Z/Input blocked Analog input After internal reset issuance (Before GPORT setting) Sleep mode Analog input Analog output Analog input Analog output Last status retained*6 Analog input Analog input Hi-Z/Input blocked Hi-Z/Input blocked Input enabled Input enabled Input enabled Hi-Z/Input blocked Last status retained Hi-Z/Input blocked Analog input Last status retained*6 Hi-Z/Input blocked Last status retained*6 Last status retained Input enabled Hi-Z/Input blocked Without control With control With control - - - - - Last status retained Last status retained*6 Hi-Z/Input blocked Input enabled Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Last status retained Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked - - ---- Hi-Z/Input blocked

May 15, 2015, MB9D560_DS708-00001-3v0-E 55 CONFIDENTIAL Pin Statuses (2/2) *1: Power-on reset, internal power supply low-voltage detection and NMIX + RSTX pin are factors. *2: External power supply low-voltage detection and external reset are factors. *3: Software reset and software/hardware watchdog reset are factors. *4: When external interrupt is valid, input blocked is invalid. *5: When I/O is initialized, "L" is output. *6: Operation is continued according to the peripheral function. *7: If GPORTEN bit is 0 and CPORTEN bit is 1, input is enabled. *8: When clock monitor output pin (MONCLK) is selected, pin state becomes high impedance. External factor generation in progress 208 pin 176 pin Internal reset issuance in progress Internal reset issuance in progress After internal reset issuance (Before GPORT setting) Before internal reset issuance Internal reset issuance in progress Internal reset issuance in progress After internal reset issuance (Before GPORT setting) CPU sleep High impedance disabled (SYSC_SSPECFGR: PSSPADCTRL=0) High impedance enabled (SYSC_SSPECFGR: PSSPADCTRL=1) High impedance disabled (SYSC_SSPECFGR: PSSPADCTRL=0) High impedance enabled (SYSC_SSPECFGR: PSSPADCTRL=1) 110 91 MAG_OUT1 Analog output 111 92 MAG_PLUS1 112 93 MAG_MINUS1 113 94 RDC_ACT1/P126 L*5 L H/L L*5 L*5 L H/L L H/L H/L L L L L 119 100 COS_OUT1 Analog output 120 101 COS_MINUS1 121 102 COS_PLUS1 122 103 SIN_PLUS1 123 104 SIN_MINUS1 124 105 SIN_OUT1 Analog output 125 106 COS_IN1 126 107 SIN_IN1 127 108 AREF21 Analog output 128 109 P116/RDC_A1/AIN3 129 110 P115/RDC_B1/BIN3 130 111 P114/RDC_Z1/ZIN3 131 112 P113/RDC_U1/AIN2 132 113 P112/RDC_V1/BIN2 133 114 P111/RDC_W1/ZIN2 139 120 P110/4AN7 140 121 P109/4AN6 141 122 P108/4AN5 142 123 P107/4AN4 145 124 P106/RTO11 146 125 P105/RTO10 147 126 P104/RTO9 148 127 P103/RTO8 149 128 P102/RTO7 150 129 P101/RTO6 151 130 P100/DTTI1/4ADTG1 152 - P421/SIN3/INT6/FRCK8 Hi-Z/ Last status retained Hi-Z/Input blocked Last status retained*6 Last status retained Hi-Z/Input blocked*4 Last status retained Hi-Z/Input blocked*4 153 - P422/SOT3/FRCK9/IN13 154 - P423/SCK3/FRCK10/IN14 158 - P425/TIOA8 159 - P426/TIOB8 160 - P427/TIOA9 161 - P428/TIOB9 162 134 P429/MONCLK/MM Hi-Z/ Last status retained Hi-Z/Input blocked Last status retained*6 Last status retained*8 Hi-Z/Input blocked Last status retained*8 Hi-Z/Input blocked 163 135 AN0/P200 164 136 AN1/P201 165 137 AN2/P202 166 138 AN3/P203 167 139 AN4/P204 168 140 AN5/P205 169 141 AN6/P206 170 142 AN7/P207 173 145 AN8/P208 174 146 AN9/P209 175 147 AN10/P210 176 148 AN11/P211 177 149 AN12/P212 178 150 AN13/P213 179 151 AN14/P214 180 152 AN15/P215 185 157 AN16/P216 186 158 AN17/P217 187 159 AN18/P218 188 160 AN19/P219 189 161 AN20/P220/TIOA6 190 162 AN21/P221/TIOB6 191 163 AN22/P222/TIOA7 192 164 AN23/P223/TIOB7 195 167 AN24/P224 196 168 AN25/P225/SIN4/INT7 Hi-Z/Last status retained Hi-Z/Input blocked Last status retained*6 Last status retained Hi-Z/Input blocked*4 Last status retained Hi-Z/Input blocked*4 197 169 AN26/P226/SOT4/IN0 198 170 AN27/P227/SCK4/IN1 199 171 AN28/P228/SCS40/IN2 200 172 AN29/P229/SCS41/IN3 201 173 AN30/P230/SCS42/IN4 202 174 AN31/P231/SCS43/IN5 203 175 P300/ADTG0 204 - P301/TIOA10/FRCK4 205 - P302/TIOB10/FRCK5 206 - P303/TIOA11/FRCK6 207 - P304/TIOB11/FRCK7 Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Last status retained Hi-Z/Input blocked Hi-Z/Input blocked Last status retained*6 Last status retained*6 Hi-Z/Input blocked Last status retained Hi-Z/Last status retained Hi-Z/Input blocked Hi-Z/Last status retained Hi-Z/Input blocked Hi-Z/Input blocked Analog output Hi-Z/Input blocked Analog output Analog input Hi-Z/Input blocked Last status retained Last status retained Analog output Analog output Analog input- Hi-Z/Input blocked Last status retained*6 Hi-Z/ Last status retained Hi-Z/Input blocked Hi-Z/Input blocked Analog input Analog output Analog input Analog input Analog input Analog output Analog inputAnalog inputAnalog input Analog output Analog output Analog input Analog outputAnalog output Analog outputAnalog output Analog input Analog outputAnalog output Analog output Analog input Sleep Mode Stop mode Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Hi-Z/Input blocked Analog output Analog output Analog input Analog output Pin Name GPORTEN control External reset factor*1 External reset factor*2 Internal reset factor*3 After external factor releasing External factor generation in progress After external factor releasing Pin No. Hi-Z/Input blockedHi-Z/Input blockedHi-Z/Input blocked Last status retained Last status retained Last status retained Last status retainedHi-Z/Input blocked Hi-Z/ Last status retained Hi-Z/Input blocked Hi-Z/Input blockedHi-Z/Input blocked Hi-Z/Input blocked Last status retained*6 Internal reset issuance in progress Watch mode After internal reset issuance (Before GPORT setting) Analog input Analog input Hi-Z/Input blocked Analog input Analog output Analog output Analog input Analog input With control

56 MB9D560_DS708-00001-3v0-E, May 15, 2015

Electrical Characteristics

13.1 Absolute Maximum Ratings

Power supply voltage*1, *2 VCC VSS-0.3 VSS+6.0 V Analog power supply voltage*1, *2 VDD VSS-0.3 VSS+1.8 V Analog reference voltage*1 AVCC VSS-0.3 VSS+6.0 V AVCC≤VCC Input voltage*1 RVCC VSS-0.3 VSS+6.0 V RVCC≤VCC Analog pin input voltage*1 AVRH VSS-0.3 VSS+6.0 V AVRH≤AVCC RVRH VSS-0.3 VSS+6.0 V RVRH≤RVCC Input voltage*1 VI VSS-0.3 VCC+0.3 V Analog pin input voltage*1 VIA VSS-0.3 VCC+0.3 V Output voltage*1 VO VSS-0.3 VCC+0.3 V Max clamp current ICLAMP - 4 mA *8 Max total clamp current Σ|ICLAMP| - 20 mA *8 "L" level Max output current*3 IOL1 - 3.5 mA When setting to 1 mA*6 IOL2 - 7 mA When setting to 2 mA IOL3 - 14 mA When setting to 4 mA*7 "L" level average output current*4 IOLAV1 - 1 mA When setting to 1 mA*6 IOLAV2 - 2 mA When setting to 2 mA IOLAV3 - 4 mA When setting to 4 mA*7 "L" level total output current*5 ΣIOL - 40 mA *6 "H" level Max output current*3 IOH1 - -3.5 mA When setting to 1 mA*6 IOH2 - -7 mA When setting to 2 mA IOH3 - -14 mA When setting to 4 mA*7 "H" level average output current*4 IOHAV1 - -1 mA When setting to1 mA*6 IOHAV2 - -2 mA When setting to 2 mA IOHAV3 - -4 mA When setting to 4 mA*7 "H" level total output current*5 ΣIOH - -40 mA *6 Power consumption PD - 1500 mW Operating temperature TA -40 +125 °C *9 Storage temperature Tstg -55 +150 °C *1: These parameters are based on the condition that VSS=AVSS=0.0V. *2: Caution must be taken that AVCC does not exceed VCC. *3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The average value is the operation current  the operation ratio. *5: The total output current is defined as the maximum current value flowing through all of corresponding pins. *6: Corresponding pins: general-purpose ports *7: Corresponding pins: general-purpose ports of P325 to P330 *8: Corresponding pins: all general-purpose ports and analog input pin − Use the devices within recommended operating conditions. − Use the devices with direct voltage (current). − The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.

May 15, 2015, MB9D560_DS708-00001-3v0-E 57 CONFIDENTIAL − The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input. − Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. − Note that if the + B signal is input when the microcontroller is off (not fixed at 0V), since the power is supplied through the pin, the microcontroller may operate incompletely. − Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. − Do not leave + B input pins open. Sample Recommended Circuit MB9D560 series +Ｂ input(12 to 16V) Protective diode Limiting resistor current *9: To use this product at TA=125°C, equip this on a multilayer board with four or more layers. To equip this on a single-layer board, change the operating conditions (operating frequency, power supply voltage, etc.) to use this at the power consumption PD=780mW or lower, or use this at TA=100°C or lower. Warning: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

58 MB9D560_DS708-00001-3v0-E, May 15, 2015

13.2 Recommended Operating Conditions

(VSS=AVSS-RVSS=0.0V) Parameter Symbol Value Unit Remarks Min Max Power supply voltage VCC 4.5 5.5 V Recommended operation guarantee range VDD 1.1 1.3 V AVCC 4.5 5.5 V RVCC 4.5 5.5 V VCC 3.7 5.5 V Operation guarantee range VDD 1.09 1.3 V AVCC 3.7 5.5 V RVCC 3.7 5.5 V Smoothing capacitor* CREF 0.33 1.0 µF Tolerance within ±40% Operating temperature TA -40 +125 °C * : For connection of smoothing capacitor CREF, see the figure below. − CREF pin connection CREF AVR0 AVRL0 AVRH0 MB9D560 series Pin AVCC0 AVSS0 Wire Decoupling capacitor (0.01µF to 1µF) It should be used smoothing capacitor for between AVR1 to AVRL1, RVR0 to RVRL0, RVR1 to RVRL1 as well. − CREF capacitor size and A/D converter activation time It depends on activation time of A/D converter with R/D converter and activation time of 4 channels same time sampling A/D converter by CREF capacitor seize. The computation expression of activation time is as follows. Activation time = 9 × CREF × 1.2k + 1μ [s] Activation time relate with following time from activation trigger, please use smoothing capacitor with system operation conditions. If A/D converter of 4 channels same time sampling, Set to "1" for ENBL bit of A/D enable setting register. If A/D converter with R/D converter, Set to "1" for RDCEN bit of operation control register 1.

May 15, 2015, MB9D560_DS708-00001-3v0-E 59 CONFIDENTIAL Warning: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. − Any use of semiconductor devices will be under their recommended operating condition. − Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. − No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

60 MB9D560_DS708-00001-3v0-E, May 15, 2015

13.3 DC Characteristics

Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "H" level input voltage VIH1 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P324, P406 to P423, P425 to P431 When CMOS schmitt input level is selected 0.7VCC - Vcc+0.3 V VIH2 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 to P306, P309 to P330, P406 to P423, P425 to P431 When automotive input level is selected 0.8VCC - Vcc+0.3 V VIH3 P325 to P330 When FlexRay input level is selected 0.7VCC - Vcc+0.3 V VIH4 RSTX, NMIX - 0.7VCC - Vcc+0.3 V VIH5 MD0, MD1 - 0.7VCC - Vcc+0.3 V VIH6 TRSTX, TCK, TDI, TMS, nSRST - 2.3 - Vcc+0.3 V

May 15, 2015, MB9D560_DS708-00001-3v0-E 61 CONFIDENTIAL Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "L" level input voltage VIL1 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P324, P406 to P423, P425 to P431 When CMOS schmitt input level is selected VSS-0.3 - 0.3VCC V VIL2 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 to P306, P309 to P330, P406 to P423, P425 to P431 When automotive input level is selected VSS-0.3 - 0.5VCC V VIL3 P325 to P330 When FlexRay input level is selected VSS-0.3 - 0.3VCC V VIL4 RSTX, NMIX - VSS-0.3 - 0.3VCC V VIL5 MD0, MD1 - VSS-0.3 - 0.3VCC V VIL6 TRSTX, TCK, TDI, TMS, nSRST - VSS-0.3 - 0.8 V

62 MB9D560_DS708-00001-3v0-E, May 15, 2015

Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "H" level output voltage VOH1 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P330, P406 to P423, P425 to P431 VCC=4.5V IOH=-2.0mA VCC-0.5 - VCC V VOH2 P325 to P330 VCC=4.5V IOH=-4.0mA VCC-0.5 - VCC V When FlexRay selected VOH3 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P330, P406 to P423, P425 to P431 VCC=4.5V IOH=-1.0mA VCC-0.5 - VCC V VOH4 TDO VCC=4.5V IOH=-5mA VCC-0.5 - VCC V

May 15, 2015, MB9D560_DS708-00001-3v0-E 63 CONFIDENTIAL Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "L" level output voltage VOL1 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P330, P406 to P423, P425 to P431 VCC=4.5V IOL=2.0mA 0 - 0.4 V VOL2 P325 to P330 VCC=4.5V IOL=4.0mA 0 - 0.4 V When FlexRay selected VOL3 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 toP306, P309 to P330, P406 to P423, P425 to P431 VCC=4.5V IOL=1.0mA 0 - 0.4 V VOL4 TDO VCC=4.5V IOL=5mA 0 - 0.4 V

64 MB9D560_DS708-00001-3v0-E, May 15, 2015

Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Input leakage current IIL All input pin VCC=AVCC=RVCC=5.5V VSS < VI < VCC -5 - +5 µA Pull-up resistance RUP1 RSTX, NMIX - 25 - 100 kΩ RUP2 P000 to P016, P026, P030 to P031, P100 to P116, P126, P131, P200 to P231, P300 to P306, P309 to P330, P406 to P423, P425 to P431 When pull-up resistance is selected 25 - 100 kΩ Input capacitor CIN Other than VCC, VSS, AVCC, AVSS, RVCC, RVSS - - 5 15 pF

May 15, 2015, MB9D560_DS708-00001-3v0-E 65 CONFIDENTIAL Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply current ICC5 VCC5 Normal operations 200MHz - 104 115 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz Normal operations 160MHz - 105 116 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz Flash write/erase* 200MHz - 115 126 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz Flash write/erase* 160MHz - 116 127 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz *: This series has 2 types of flash; TCFLASH (4) and WorkFLASH (2); however, this is the specification when only one of those is written/erased.

66 MB9D560_DS708-00001-3v0-E, May 15, 2015

Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply current ICC12 VCC12 Normal operations 200MHz - 310 510 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz Normal operations 160MHz - 290 490 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz Flash write/erase* 200MHz - 312 512 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz Flash write/erase* 160MHz - 292 492 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz *: This series has 2 types of flash; TCFLASH (4) and WorkFlash (2); however, this is the specification when only one of those is written/erased.

May 15, 2015, MB9D560_DS708-00001-3v0-E 67 CONFIDENTIAL Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current ICCS5 VCC5 CPU sleep mode 200MHz - 40 42 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz CPU sleep mode 160MHz - 30 32 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz ICCT5 Watch mode, 4MHz source oscillation - 390 1030 µA When using crystal TA=25°C ICCH5 Stop mode - 380 1010 µA TA=25°C

68 MB9D560_DS708-00001-3v0-E, May 15, 2015

Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply current ICCS12 VCC12 CPU sleep mode 200MHz - 220 410 mA FCD0_CLK=200 MHz FCLK_CPUx=200 MHz, FCLK_TFCLKx=66 MHz, FCLK_HPMPD2=200 MHz, FCLK_DMA=200 MHz, FCLK_MEMC=100 MHz, FCLK_WFCLKx=200 MHz, FCLK_SYSCPD1=100 MHz, FCLK_PERIy=100 MHz, FCLK_PERIz=50 MHz CPU sleep mode 160MHz - 180 360 mA FCD0_CLK=160 MHz FCLK_CPUx=160 MHz, FCLK_TFCLKx=80 MHz, FCLK_HPMPD2=160 MHz, FCLK_DMA=160 MHz, FCLK_MEMC=80 MHz, FCLK_WFCLKx=160 MHz, FCLK_SYSCPD1=80 MHz, FCLK_PERIy=80 MHz, FCLK_PERIz=40 MHz ICCT12 Watch mode, 4MHz source oscillation - 1280 9730 µA When using crystal TA=25°C ICCH12 Stop mode - 860 9530 µA TA=25°C

May 15, 2015, MB9D560_DS708-00001-3v0-E 69 CONFIDENTIAL

13.4 AC Characteristics

(1) Source Clock Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Source oscillation clock frequency FC X0, X1 - 4 - 20 MHz Source oscillation clock cycle time tCYL X0, X1 - 50 - 250 ns CAN PLL jitter (during lock) tPJ - - -10 - +10 ns Built-in slow-CR oscillation frequency FCRS - - 50 100 150 kHz Built-in fast-CR oscillation frequency FCRF - - 4 8 12 MHz Without calibration 7.2 8 8.8 MHz With calibration − X0, X1 clock timing tCYL − CAN PLL jitter Deviation time from the ideal clock is assured per cycle out of 20,000 cycles. t1 t2 t3 t1 t2 tn-1 tn tn-1 tn Ideal clock Slow Fast PLL output

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(2) Internal Clock Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Internal clock frequency FCD0_CLK - - 0 - 200 MHz CD0_CLK FCD4_CLK - - 0 - 200 MHz CD4_CLK FCLK_CPU0 - - 0 - 200 MHz CLK_CPU0 FCLK_CPU1 - - 0 - 200 MHz CLK_CPU1 FCLK_TFCLK0 - - 0 - 80 MHz CLK_TFCLK0 FCLK_TFCLK1 - - 0 - 80 MHz CLK_TFCLK1 FCLK_ATB - - 0 - 100 MHz CLK_ATB FCLK_DBG - - 0 - 50 MHz CLK_DBG FCLK_HPMPD2 - - 0 - 200 MHz CLK_HPMPD2 FCLK_DMA - - 0 - 200 MHz CLK_DMA FCLK_MEMC - - 0 - 200 MHz CLK_MEMC FCLK_WFCLK0 - - 0 - 80 MHz CLK_WFCLK0 FCLK_WFCLK1 - - 0 - 80 MHz CLK_WFCLK1 FCLK_SYSCPD1 - - 0 - 100 MHz CLK_SYSCPD1 FCLK_PERI0 - - 0 - 100 MHz CLK_PERI0 FCLK_PERI1 - - 0 - 50 MHz CLK_PERI1 FCLK_PERI4 - - 0 - 100 MHz CLK_PERI4 FCLK_PERI5 - - 0 - 100 MHz CLK_PERI5 FCLK_PERI6 - - 0 - 50 MHz CLK_PERI6 FCLK_PERI7 - - 0 - 50 MHz CLK_PERI7 FCLK_CLKO - - 0 - 200 MHz CLK_CLKO Internal clock cycle time tCD0_CLK - - 5 - - ns CD0_CLK tCD4_CLK - - 5 - - ns CD4_CLK tCLK_CPU0 - - 5 - - ns CLK_CPU0 tCLK_CPU1 - - 5 - - ns CLK_CPU1 tCLK_TFCLK0 - - 12.5 - - ns CLK_TFCLK0 tCLK_TFCLK1 - - 12.5 - - ns CLK_TFCLK1 tCLK_ATB - - 10 - - ns CLK_ATB tCLK_DBG - - 20 - - ns CLK_DBG tCLK_HPMPD2 - - 5 - - ns CLK_HPMPD2 tCLK_DMA - - 5 - - ns CLK_DMA tCLK_MEMC - - 5 - - ns CLK_MEMC tCLK_WFCLK0 - - 12.5 - - ns CLK_WFCLK0 tCLK_WFCLK1 - - 12.5 - - ns CLK_WFCLK1 tCLK_SYSCPD1 - - 10 - - ns CLK_SYSCPD1 tCLK_PERI0 - - 10 - - ns CLK_PERI0 tCLK_PERI1 - - 20 - - ns CLK_PERI1 tCLK_PERI4 - - 10 - - ns CLK_PERI4 tCLK_PERI5 - - 10 - - ns CLK_PERI5 tCLK_PERI6 - - 20 - - ns CLK_PERI6 tCLK_PERI7 - - 20 - - ns CLK_PERI7 tCLK_CLKO - - 5 - - ns CLK_CLKO

May 15, 2015, MB9D560_DS708-00001-3v0-E 71 CONFIDENTIAL − Guaranteed operation range Internal operation clock frequency vs. Power supply voltage Internal operation clock frequency FCD0_CLK(MHz) 200 4 2 3.7 5.5 Power supply voltage VCC (V) 4.5 1.3 1.1 Power supply voltage VDD (V) Recommended guaranteed operation range: Guaranteed operation range: PLL guaranteed operation range: 1.09 Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less. − Oscillation clock frequency vs. Internal operation clock frequency Oscillation Clock Frequency Main Clock PLL Multiplying Setting PLL Output Divider Setting PLL Clock

4 MHz 4 MHz 100 2 200 MHz

8 MHz 8 MHz 50 2 200 MHz

8 MHz 4 MHz 100 2 200 MHz

16 MHz 16 MHz 25 2 200 MHz

16 MHz 8 MHz 50 2 200 MHz

− Example of oscillation circuit Note: when configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator manufacturers for the design. R C C

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AC characteristics are specified by the following measurement reference voltage values. Input signal waveform Output signal waveform Hysteresis input pin (Automotive) 0.5Vcc 0.8Vcc Output pin 0.8V 2.4V Hysteresis input pin (CMOS schmitt) 0.3Vcc 0.7Vcc Hysteresis input pin (FlexRay) 0.3Vcc 0.7Vcc Hysteresis input pin (TTL) 0.8V 2.0V

May 15, 2015, MB9D560_DS708-00001-3v0-E 73 CONFIDENTIAL (3) Reset Input Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Reset input time tRSTL RSTX - 10 - µs Width for reset input removal 1 - µs RSTX 0.2Vcc 0.2Vcc tRSTL

74 MB9D560_DS708-00001-3v0-E, May 15, 2015

(4) Power-on Conditions (TA: Recommended operating conditions, VSS=0.0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Level detection voltage - VCC5 - 2.0 2.2 2.4 V When turning on power - VCC12 - 0.4 - 0.7 V Level detection hysteresis width - VCC5 - - - 150 mV During voltage drop - VCC12 - - - 50 mV Level detection time - - - - - 30 µs *1 Power-on time tR5 VCC5 - 0.11 - 30 ms tR12 VCC12 - 0.05 - 0.6 ms Power-off time tOFF VCC5 - 1 - - ms *2 *1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: This time is to start the slope detection at next power on after power down and internal charge loss. − Power-on , Power-off sequence 0.2Vcc 0.2Vcc VCC5 VCC12 tR5 tR12 tOFF 2.0V 1.1V NMIX + RSTX Notes: − Power supply input procedure Power supply should input same time VCC5 and VCC12, or VCC5 to up step. Also, when power supply input, VCC12 is not over voltage of VCC5. − Power supply shutdown procedure Power supply should shutdown same time VCC5 and VCC12, or VCC12 to up step. Also, when power supply shutdown, VCC12 is not over voltage of VCC5. − Notes: When power supply input and power supply shutdown When power supply input, power supply voltage until achieve to recommend operation guarantee area, same time input for NMIX pin + RSTX pin. When power supply shutdown, power supply voltage until achieve to recommend operation guarantee area, same time input for NMIX pin + RSTX pin.

May 15, 2015, MB9D560_DS708-00001-3v0-E 75 CONFIDENTIAL (5) Multi-Function Serial Interface (5-1) CSIO Timing (SMR:MD[2:0]=0b010) (5-1-1) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "H" (SMR:SCINV=0) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 4tCLK_PERI1 - ns SCK↓→SOT delay time tSLOVI SCK0 to SCK4, SOT0 to SOT4 -30 +30 ns Valid SIN→SCK↑ setup time tIVSHI SCK0 to SCK4, SIN0 to SIN4 30 - ns SCK↑→Valid SIN hold time tSHIXI 0 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns Serial clock "L" pulse width tSLSH 2tCLK_PERI1-10 - ns SCK↓→SOT delay time tSLOVE SCK0 to SCK4, SOT0 to SOT4 - 30 ns Valid SIN→SCK↑ setup time tIVSHE SCK0 to SCK4, SIN0 to SIN4 10 - ns SCK↑→Valid SIN hold time tSHIXE 20 - ns SCK fall time tF SCK0 to SCK4 - 5 ns SCK rise time tR SCK0 to SCK4 - 5 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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May 15, 2015, MB9D560_DS708-00001-3v0-E 77 CONFIDENTIAL (5-1-2) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "L" (SMR:SCINV=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 4tCLK_PERI1 - ns SCK↑→SOT delay time tSHOVI SCK0 to SCK4, SOT0 to SOT4 -30 +30 ns Valid SIN→SCK↓ setup time tIVSLI SCK0 to SCK4, SIN0 to SIN4 30 - ns SCK↓→valid SIN hold time tSLIXI 0 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns Serial clock "L" pulse width tSLSH 2tCLK_PERI1-10 - ns SCK↑→SOT delay time tSHOVE SCK0 to SCK4, SOT0 to SOT4 - 30 ns valid SIN→SCK↓ setup time tIVSLE SCK0 to SCK4, SIN0 to SIN4 10 - ns SCK↓→valid SIN hold time tSLIXE 20 - ns SCK fall time tF SCK0 to SCK4 - 5 ns SCK rise time tR SCK0 to SCK4 - 5 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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May 15, 2015, MB9D560_DS708-00001-3v0-E 79 CONFIDENTIAL (5-1-3) SPI Compatible (SCR:SPI=1) and Serial Clock Output Signal Detect Level "H" (SMR:SCINV=0) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 4tCLK_PERI1 - ns SCK↑→SOT delay time tSHOVI SCK0 to SCK4, SOT0 to SOT4 -30 +30 ns Valid SIN→SCK↓ setup time tIVSLI SCK0 to SCK4, SIN0 to SIN4 30 - ns SCK↓→valid SIN hold time tSLIXI 0 - ns SOT→SCK↓ delay time tSOVLI SCK0 to SCK4, SOT0 to SOT4 2tCLK_PERI1-30 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns Serial clock "L" pulse width tSLSH 2tCLK_PERI1-10 - ns SCK↑→SOT delay time tSHOVE SCK0 to SCK4, SOT0 to SOT4 - 30 ns valid SIN→SCK↓ setup time tIVSLE SCK0 to SCK4, SIN0 to SIN4 10 - ns SCK↓→valid SIN hold time tSLIXE 20 - ns SCK fall time tF SCK0 to SCK4 - 5 ns SCK rise time tR SCK0 to SCK4 - 5 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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*: Changes when writing to TDR register Slave mode

May 15, 2015, MB9D560_DS708-00001-3v0-E 81 CONFIDENTIAL (5-1-4) SPI Compatible (SCR:SPI=1) and Serial Clock Output Signal Detect Level "L" (SMR:SCINV=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 4tCLK_PERI1 - ns SCK↓→SOT delay time tSLOVI SCK0 to SCK4, SOT0 to SOT4 -30 +30 ns Valid SIN→SCK↑ setup time tIVSHI SCK0 to SCK4, SIN0 to SIN4 30 - ns SCK↑→valid SIN hold time tSHIXI 0 - ns SOT→SCK↑ Delay time tSOVHI SCK0 to SCK4, SOT0 to SOT4 2tCLK_PERI1-30 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4, SOT0 to SOT4 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns Serial clock "L" pulse width tSLSH 2tCLK_PERI1-10 - ns SCK↓→SOT delay time tSLOVE SCK0 to SCK4, SOT0 to SOT4 - 30 ns valid SIN→SCK↑ setup time tIVSHE SCK0 to SCK4, SIN0 to SIN4 10 - ns SCK↑→valid SIN hold time tSHIXE 20 - ns SCK fall time tF SCK0 to SCK4 - 5 ns SCK rise time tR SCK0 to SCK4 - 5 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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*: Changes when writing to TDR register Slave mode

May 15, 2015, MB9D560_DS708-00001-3v0-E 83 CONFIDENTIAL (5-1-5) When the Serial Chip Select is Used (SCSCR:CSEN=1) − Serial clock output signal detect level "H" (SMR, SCSFR:SCINV=0) − Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max SCS↓→SCK↓ setup time tCSSI SCK4, SCS40 to SCS43 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCSSU *1-50 - ns SCK↑→SCS↑ hold time tCSHI tCSHD *2+0 - ns SCS deselect time tCSDI SCS40 to SCS43 tCSDS *3-50 +5 tCLK_PERI1 - ns SCS↓→SCK↓ setup time tCSSE SCK4, SCS40 to SCS43 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - ns SCS deselect time tCSDE SCS40 to SCS43 3tCLK_PERI1+30 - ns SCS↓→SOT delay time tDSE SCS40 to SCS43, SOT4 - 40 ns SCS↑→SOT delay time tDEE 0 - ns SCK↓→SCS↓ clock switch time tSCC SCK4, SCS40 to SCS43 Master mode, Round operation (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+0 3tCLK_PERI1 +50 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps *1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock *2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock *3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock For details of *1, *2 and *3 above, see Hardware Manual. Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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(Normal Sync transfer) SOT (SPI compatible) tCSSI SCS output tCSHI tCSDI VOL VOL VOL VOH VOH VOH Master mode SCK input SOT (Normal Sync transfer) SOT (SPI compatible) tCSSE SCS input tCSHE tCSDE tDSE tDEE VIL VIL VIH VIH VIH VOL VOL VOH Slave mode SCSy output SCK output SCSx output tSCC VOL VOL Clock switching example by master mode round operation (x, y = 40, 41, 42, 43: x and y are different value)

May 15, 2015, MB9D560_DS708-00001-3v0-E 85 CONFIDENTIAL (5-1-6) When the Serial Chip Select is Used (SCSCR:CSEN=1) − Serial clock output signal detect level "L"(SMR, SCSFR:SCINV=1) − Serial chip select inactive level "H"(SCSCR, SCSFR:CSLVL=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max SCS↓→SCK↑ setup time tCSSI SCK4, SCS40 to SCS43 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCSSU *1-50 - ns SCK↓→SCS↑ hold time tCSHI tCSHD *2+0 - ns SCS deselect time tCSDI SCS40 to SCS43 tCSDS *3-50 +5tCLK_PERI1 - ns SCS↓→SCK↑ setup time tCSSE SCK4, SCS40 to SCS43 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - ns SCS deselect time tCSDE SCS40 to SCS43 3tCLK_PERI1+30 - ns SCS↓→SOT delay time tDSE SCS40 to SCS43, SOT4 - 40 ns SCS↑→SOT delay time tDEE 0 - ns SCK↑→SCS↓ clock switch time tSCC SCK4, SCS40 to SCS43 Master mode, Round operation (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+0 3tCLK_PERI1+50 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps *1: tCSSU =SCSTR:CSSU[7:0]  serial Chip select timing operation clock *2: tCSHD=SCSTR:CSHD[7:0]  serial Chip select timing operation clock *3: tCSDS=SCSTR:CSDS[15:0]  serial Chip select timing operation clock For details of *1, *2 and *3 above, see Hardware Manual. Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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(Normal Sync transfer) SOT (SPI compatible) tCSSI SCS output tCSHI tCSDI VOL VOL VOH VOH VOH VOL Master mode SCK input SOT (Normal Sync transfer) SOT (SPI compatible) tCSSE SCS input tCSHE tCSDE tDSE tDEE Slave mode VOL VIL VIL VIH VIH VOL VOH VIL VIH SCSy output SCK output SCSx output tSCC VOH VOL Clock switching example by master mode round operation (x, y = 40, 41, 42, 43: x and y are different value)

May 15, 2015, MB9D560_DS708-00001-3v0-E 87 CONFIDENTIAL (5-1-7) When the Serial Chip Select is Used (SCSCR:CSEN=1) − Serial clock output signal detect level "H"(SMR, SCSFR:SCINV=0) − Serial Chip select inactive level "L"(SCSCR, SCSFR:CSLVL=0) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max SCS↑→SCK↓ setup time tCSSI SCK4, SCS40 to SCS43 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCSSU *1-50 - ns SCK↑→SCS↓ hold time tCSHI tCSHD *2+0 - ns SCS deselect time tCSDI SCS40 to SCS43 tCSDS *3-50 +5tCLK_PERI1 - ns SCS↑→SCK↓ setup time tCSSE SCK4, SCS40 to SCS43 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+30 - ns SCK↑→SCS↓ hold time tCSHE 0 - ns SCS deselect time tCSDE SCS40 to SCS43 3tCLK_PERI1+30 - ns SCS↑→SOT delay time tDSE SCS40 to SCS43, SOT4 - 40 ns SCS↓→SOT delay time tDEE 0 - ns SCK↓→SCS↑ clock switch time tSCC SCK4, SCS40 to SCS43 Master mode, round operation (CL=50pF, IOL=-2mA,IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+0 3tCLK_PERI1 +50 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps *1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock *2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock *3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock For details of *1, *2 and *3 above, see Hardware Manual. Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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(Normal Sync transfer) SOT (SPI compatible) tCSSI SCS output tCSHI tCSDI VOH VOH VOH VOL VOL Master mode SCK input SOT (Normal Sync transfer) SOT (SPI compatible) tCSSE SCS input tCSHE tCSDE tDSE tDEE VIH VIH VIH VOL VIL VIL VOL VOH Slvae mode SCSy output SCK output SCSx output tSCC VOL VOH Clock switching example by master mode round operation (x, y = 40, 41, 42, 43: x and y are different value)

May 15, 2015, MB9D560_DS708-00001-3v0-E 89 CONFIDENTIAL (5-1-8) When the Serial Chip Select is Used (SCSCR:CSEN=1) − Serial clock output signal detect level "L"(SMR, SCSFR:SCINV=1) − Serial Chip select inactive level "L"(SCSCR, SCSFR:CSLVL=0) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max SCS↑→SCK↑ setup time tCSSI SCK4, SCS40 to SCS43 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCSSU *1-50 - ns SCK↓→SCS↓ hold time tCSHI tCSHD *2+0 - ns SCS deselect t time tCSDI SCS40 to SCS43 tCSDS *3-50 +5tCLK_PERI1 - ns SCS↑→SCK↑ setup time tCSSE SCK4, SCS40 to SCS43 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+30 - ns SCK↓→SCS↓ hold time tCSHE 0 - ns SCS deselect time tCSDE SCS40 to SCS43 3tCLK_PERI1+30 - ns SCS↑→SOT delay time tDSE SCS40 to SCS43, SOT4 - 40 ns SCS↓→SOT delay time tDEE 0 - ns SCK↑→SCS↑ clock switch time tSCC SCK4, SCS40 to SCS43 Master mode, Round operation (CL=50pF, IOL=-2mA,IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 3tCLK_PERI1+0 3tCLK_PERI1 +50 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps *1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock *2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock *3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock For details of *1, *2 and *3 above, see Hardware Manual. Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details.

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(Normal Sync transfer) SOT (SPI compatible) tCSSI SCS output tCSHI tCSDI VOHVOH VOH VOL VOL Master mode SCK input SOT (Normal Sync transfer) SOT (SPI compatible) tCSSE SCS input tCSHE tCSDE tDSE tDEE VOL VOL VOH VIH VIH Slave mode VIL VILVIL VIH SCSy output SCK output SCSx output tSCC VOH VOH Clock switching example by master mode round operation (x, y = 40, 41, 42, 43: x and y are different value)

May 15, 2015, MB9D560_DS708-00001-3v0-E 91 CONFIDENTIAL (5-2) UART (Async Serial Interface) Timing (SMR:MD[2:0]=0b000, 0b001) (5-2-1) When the External Clock is Selected (BGR:EXT=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max serial clock "L" pulse width tSLSH SCK0 to SCK4 (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns serial clock "H" pulse width tSHSL tCLK_PERI1+10 - ns SCK fall time tF - 5 ns SCK rise time tR - 5 ns (5-3) LIN Interface (v2.1) (LIN Communication Control Interface (v2.1)) Timing (SMR:MD[2:0]=0b011) (5-3-1) When the External Clock is Selected (BGR:EXT=1) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max serial clock "L" pulse width tSLSH SCK0 to SCK4 (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns serial clock "H" pulse width tSHSL tCLK_PERI1+10 - ns SCK fall time tF - 5 ns SCK rise time tR - 5 ns SCK tSHSL VIL VIH VIH tR tSLSH tF VIL VIH VIL When the external clock is selected SCK tSHSL VIL VIH VIH tR tSLSH tF VIL VIH VIL When the external clock is selected

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(6) Timer Input Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL IN16 to IN21, TIOA0 to TIOA11, TIOB0 to TIOB11 - 4tCLK_PERI1 - ns IN4 to IN14, FRCK6 to FRCK10, FRCK12 to FRCK17 4tCLK_PERI4 - ns 4tCLK_PERI4≥70ns 70 4tCLK_PERI4<70ns IN0 to IN3, FRCK0 to FRCK1, FRCK4 to FRCK5 4tCLK_PERI5 - ns 4tCLK_PERI5≥70ns 70 4tCLK_PERI5<70ns AIN0, BIN0, ZIN0 - 4tCLK_PERI5 - ns 4tCLK_PERI5≥70ns 70 4tCLK_PERI5<70ns AIN2, BIN2, ZIN2 - 4tCLK_PERI4 - ns 4tCLK_PERI4≥70ns 70 4tCLK_PERI4<70ns − Timer input timing VIH VIL INx tTIWL tTIWH VIH VIL FRCKx TIOAx,TIOBx AINx,BINx,ZINx

May 15, 2015, MB9D560_DS708-00001-3v0-E 93 CONFIDENTIAL (7) Trigger Input Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL INT0 to INT7 - 200 - ns RX0 to RX2 - 5tCLK_SYSCPD1 - ns ADTG0, DTTI2 to DTTI3 - 5tCLK_PERI6 - ns 4ADTG0, DTTI0 5tCLK_PERI5 - ns 5tCLK_PERI5≥70ns 70 5tCLK_PERI5<70ns 4ADTG1, DTTI1 5tCLK_PERI4 - ns 5tCLK_PERI4≥70ns 70 5tCLK_PERI4<70ns INT0 to INT7, ADTG0, 4ADTG0, 4ADTG1, RX0 to RX2, DTTI0 to DTTI3 - 1 - µs When stop mode − Trigger input timing VIH VIL ADTGx tTRGL tTRGH VIH VIL INTx RXx 4ADTGx DTTIx

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(8) NMI Input Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tNMIL NMIX - 200 - ns − NMIX input timing V IH NMIX tNMIL V IH VIL VIL

May 15, 2015, MB9D560_DS708-00001-3v0-E 95 CONFIDENTIAL (9) External Low-Voltage Detection (TA: Recommended operating conditions, VSS=AVSS=RVSS=0.0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply voltage range VDP5 VCC5 - - - 5.5 V Detection voltage VDL VCC5 *1 3.7 3.9 4.1 V − When power supply voltage falls − The original setting of detection level is 4.1V±0.2V Hysteresis width VHYS VCC5 - 75 100 150 mV − When power supply voltage rises Low voltage detection time Td - - - - 30 µs Power supply voltage fluctuation rate - VCC5 - -4 - - V/ms *2 *1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage detection time (Td), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation of the power supply within the limits of the power supply voltage fluctuation rate. (10) Internal Low-Voltage Detection (TA: Recommended operating conditions, VSS=AVSS=RVSS=0.0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply voltage range VRDP5 VCC12 - - - 1.3 V Detection voltage VRDL VCC12 *1 0.8 0.9 1.0 V − When power supply voltage falls Hysteresis width VRHYS VCC12 - 20 30 50 mV − When power supply voltage rises Low voltage detection time TRd - - - - 30 µs Power supply voltage fluctuation rate - VCC12 - -4 - - V/ms *2 *1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage detection time (TRd), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: In order to perform the low-voltage detection at the detection voltage (VRDL), be sure to suppress fluctuation of the power supply within the limits of the power supply voltage fluctuation rate.

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13.5 A/D Converter

(1) Electrical Characteristics Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Non linearity error - - -4.0 - +4.0 LSB Differential linearity error Zero transition voltage VZT AN0 to AN31 AVRL +0.5LSB-20 AVRL +0.5LSB+20 mV 1LSB=(VFST-VZT)/4094 Full-scale transition voltage VFST AN0 to AN31 AVRH -1.5LSB-20 AVRH -1.5LSB+20 mV Sampling time tSMP - 0.3 - 12 µs *1 Compare time tCMP - 0.7 - 28 µs *1 A/D conversion time tCNV - 1.0 - 40 µs *1 Analog port input current IAIN AN0 to AN31 -2.0 - 2.0 µA VAVSS≤VAIN≤VAVCC Analog input voltage VAIN AN0 to AN31 AVSS - AVRH V Reference voltage AVRH AVRH2 4.5 - 5.5 V AVCC≥AVRH AVRL AVRL2 - 0.0 - V Power supply current IA AVCC2 - 500 680 µA IAH - - 17.7 µA *2 IR AVRH2 - 1 2 mA IRH - - 2.16 µA *2 Variation between channels - AN0 to AN31 - - 4 LSB *1: Time for each channel. *2: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU is stopped. (2) Notes on Using A/D Converter <About the output impedance of the analog input of external circuit> When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin. − Analog input circuit model R C 12bit A/D 3.0kΩ (max) 8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V) Note: Listed values must be considered as reference values. R C Sampling ON Comparator Analog input

May 15, 2015, MB9D560_DS708-00001-3v0-E 97 CONFIDENTIAL 13.6 4 Channels Same Time Sampling A/D Converter (1) Electrical Characteristics Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Non linearity error - - -4.0 - +4.0 LSB Differential linearity error Zero transition voltage VZT 4AN0 to 4AN7 AVRL +0.5LSB-20 AVRL +0.5LSB+20 mV 1LSB=(VFST-VZT)/4094 Full-scale transition voltage VFST 4AN0 to 4AN7 AVRH -1.5LSB-20 AVRH -1.5LSB+20 mV Sampling time tSMP - 0.6 - 1.2 µs *1 Compare time tCMP - 1.4 - 5.6 µs *2 A/D conversion time tCNV - 2 - 6.8 µs *3 Analog port input current IAIN 4AN0 to 4AN7 -0.7 - 0.7 µA VAVSS≤VAIN≤VAVCC Analog input voltage VAIN 4AN0 to 4AN7 AVSS - AVRH V Reference voltage AVRH AVRH0, AVRH1 4.5 - 5.5 V AVCC≥AVRH AVRL AVRL0, AVRL1 - 0.0 - V Power supply current IA AVCC0, AVCC1 - 1.0 1.5 mA 1 unit operation IAH - - 27.5 µA 1 unit operation*4 IR AVRH0, AVRH1 - 0.5 4.0 mA 1 unit operation IRH - - 4.5 µA 1 unit operation*4 Variation between channels - 4AN0 to 4AN3 - - 20 mV - 4AN4 to 4AN7 - - 20 mV *1: 4 channels same time sampling time. *2: Compare time for 4 channels. *3: Conversion time for 4 channels. *4: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU is stopped.

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(2) Notes on Using A/D converter <About the output impedance of the analog input of external circuit> When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin. − Analog input circuit model R C 4-SH 12bit A/D 3.8kΩ (max) 8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V) Note: Listed values must be considered as reference values. R C Sampling ON Comparator Analog input

May 15, 2015, MB9D560_DS708-00001-3v0-E 99 CONFIDENTIAL (12-3) Definition of Terms Resolution: Analog variation that is recognized by an A/D converter. Linearity error: Deviation of the actual conversion characteristics from a straight line that connects the zero transition point ("0000 0000 0000" ←→ "0000 0000 0001") to the full-scale transition point ("1111 1111 1110" Differential linearity error: Deviation of the input voltage from the ideal value that is required to change the output code by 1LSB. Linearity error Differential linearity error Linearity error of digital output N = VNT - {1LSB×(N-1) + VZT} [LSB]1LSB Differential linearity error of digital output N = V(N + 1)T - VNT -1 LSB [LSB]1LSB 1LSB = VFST - VZT [V]4094 VZT: Voltage at which the digital output changes from "0x000" to "0x001". VFST: Voltage at which the digital output changes from "0xFFE" to "0xFFF". AVSS (AVRL) AVRH AVRH Actual conversion characteristics {1 LSB (N - 1) + VZT} AVSS (AVRL) VFST VNT VZT (Actually-measured value) V(N+1)T VNT Ideal characteristics Actual conversion characteristics Actual conversion characteristics Actual conversion characteristics Ideal characteristics Digital output (Actually-measured value) (Actually- measured value) (Actually-measured value) Analog input Analog input (Actually-measured value) Digital output N - 1 N - 2 N N + 1 FFF FFE FFD 004 003 002 001

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13.7 Flash Memory

200 800 ms 8K Byte sector*1 Excluding internal preprogramming time - 300 1100 ms 8K Byte sector *1 Including internal preprogramming time - 400 2000 ms 64K Byte sector *1 Excluding internal preprogramming time - 700 3700 ms 64K Byte sector *1 Including internal preprogramming time 8bit writing time - 9 288 µs Excluding overhead time at system level*1 16bit writing time - 12 384 µs Excluding overhead time at system level*1 ECC writing time - 9 288 µs Excluding overhead time at system level*1 Erase cycle *2/ Data retention time 1,000 times /20 years, 10,000 times /10 years, 100,000 times / 5 years - - - Temperature at writing/erasing Average temperature TA=+85°C*3 *1: The guaranteed value for erase up to 100,000 cycles *2: Number of erase cycles for each sector *3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85°C). Notes: − While the Flash memory is written or erased, shutdown of the external power supply (VCC, VDD) is prohibited. − In the application system where VCC or VDD might disappear while writing, be sure to turn the power off by using an external low-voltage detector and NMIX pin + RSTX pin for reset input at same time. Concretely, please execute two of the following. 1. After simultaneous input from the NMIX and RSTX pins while VDD is within the recommended operating range, maintain VDD within the recommended operating range for at least 60 µs. 2. After simultaneous input from the NMIX and RSTX pins while VCC is within the recommended operating range, power off VCC in observance of the standard regarding the supply voltage fluctuation rate of the external low-voltage detector.

May 15, 2015, MB9D560_DS708-00001-3v0-E 101 CONFIDENTIAL

13.8 R/D Converter

Output voltage(amplitude) 0.4VCC-1% 0.4VCC 0.4VCC+1% V Output voltage(displacement) -0.4VCC+(VCC/2) - 0.4VCC+(VCC/2) V output current - - 1 mA Frequency - 10 or 20 - kHz Setting with the register Resolver response signal*1 Amplitude AREF20-2.0 - AREF20+2.0 V Unit0 AREF21-2.0 - AREF21+2.0 V Unit1 Maximum input frequency - - 24 kHz Excitation input signal*2 Amplitude 0 - RVCC0 V Unit0 More than 2Vp-p 0 - RVCC1 V Unit1 More than 2Vp-p Phase difference from resolver detection signal -45 - 45 ° Angle output Angle accuracy (conversion accuracy) -4 - 4 LSB Variation when Pausing: ±1LSB Resolution - 12 - bit Output delay 1.1 - 2.1 µs Angular velocity output Maximum Angular velocity - - 4000 rps When bandwidth 1.8 kHz mode - - 3000 rps When bandwidth 600 kHz mode Resolution - 0.261 - rps/LSB Reference output voltage AREF2 output voltage RVCC0/2-3% - RVCC0/2+3% V Unit0 RVCC1/2-3% - RVCC1/2+3% V Unit1 Operating characteristics Tracking loop characteristics (0dB cross frequency) - - 1.2 kHz When bandwidth 1.8 kHz mode*3 - - 400 Hz When bandwidth

600 Hz mode*3

Tracking loop characteristics (-3dB cross frequency) - - 1.8 kHz When bandwidth 1.8 kHz mode*3 - - 600 Hz When bandwidth

- 4000 rps When bandwidth 1.8 kHz mode - - 3000 rps When bandwidth

600 Hz mode

Settling time (179 degree step) - - 4 ms When bandwidth 1.8 kHz mode - - 12 ms When bandwidth

- 1,000,000 rad/s2 When bandwidth 1.8 kHz mode - - 150,000 rad/s2 When bandwidth

*1: Corresponding pin: COS_PLUS, COS_MINUS, SIN_PLUS, SIN_MINUS *2: Corresponding pin: MAG_PLUS, MAG_MINUS *3: When signal amplitude is nominal

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Ordering Information Part Number Package MB9DF564MxEEQ-GTE1 208-pin plastic TEQFP (LER208) MB9DF565MxEEQ-GTE1 MB9DF566MxEEQ-GTE1 MB9DF564LxEEQ-GTE1 176-pin plastic TEQFP (LEP176) MB9DF565LxEEQ-GTE1 MB9DF566LxEEQ-GTE1 Notes: − "x" is option number. This option is following table. The detail of package, see "16. Package Dimensions". 15. Part Number Option Part Number Option R/D Converter FlexRay Key Code A  - - G   - L - - - Q -  - : Supported

May 15, 2015, MB9D560_DS708-00001-3v0-E 103 CONFIDENTIAL 16. Package Dimensions

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May 15, 2015, MB9D560_DS708-00001-3v0-E 105 CONFIDENTIAL 17. Major Changes Page Section Change Results Revision 1.0 - - Initial release Revision 2.0 11 3. Product Lineup Add 176 pin product 14, 15 4. Pin Assignment Add 176 pin product 16 to 33 5. Pin Description Add 176 pin product 46, 47 10. Memory Map Add address information of MB9DF564 and MB9DF565 54, 55 12. Pin Statuses in CPU Status Add 176 pin product 102 14. Ordering Information Change package name Add 176 pin product 103, 104 16. Package Dimensions Change package dimensions Add 176 pin product Revision 3.0 102 15. Part Number Option Add part number option L, Q

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May 15, 2015, MB9D560_DS708-00001-3v0-E 107 CONFIDENTIAL

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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2014-2015 Cypress All rights reserved. Spansion ®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

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MB9D560 specifications and overview.

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This document states the current technical specifications regarding

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This document states the current technical specifications regarding

Source title MB9D560 Datasheet(PDF) - SPANSION

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