MB9BD10T

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32-bit ARM® Cortex®-M3 based Microcontroller MB9BFD16S/T, MB9BFD17S/T, MB9BFD18S/T Data Sheet (Full Production) Publication Number MB9BD10T-DS706-00031 Revision 2.0 Issue Date February 10, 2015 CONFIDENTIAL Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.

MB9BD10T-DS706-00031-2v0-E, February 10, 2015 CONFIDENTIAL Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.

32-bit ARM® Cortex®-M3 based Microcontroller MB9BFD16S/T, MB9BFD17S/T, MB9BFD18S/T Data Sheet (Full Production) Publication Number MB9BD10T-DS706-00031 Revision 2.0 Issue Date February 10, 2015 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.  Description The MB9BD10T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN, Ethernet-MAC). The products which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family PERIPHERAL MANUAL". Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

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 Features  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 144MHz Frequency Operation  Memory Protection Unit (MPU): improves the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory]  Up to 1Mbyte  Built-in Flash Accelerator System with 16Kbyte trace buffer memory The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.  Security function for code protection [SRAM] This Series contain a total of up to 128Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0 : Up to 64 Kbyte  SRAM1 : Up to 64 Kbyte  USB Interface (Max 2 channels) USB interface is composed of Function and Host. PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock. [USB function]  USB2.0 Full-Speed supported  Max 6 EndPoint supported  EndPoint 0 is control transfer  EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer  EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer  EndPoint 1 to 5 is comprised Double Buffer  EndPoint 0, 2 to 5:64 bytes  EndPoint 1: 256 bytes [USB host]  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer support  USB Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported  CAN Interface (Max 2 channels)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32 message buffer

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 3 CONFIDENTIAL  Ethernet - MAC (Max 2 channels)  Compliant with IEEE802.3 specification  10 Mbps / 100 Mbps data transfer rates supported  MII/RMII for external PHY device supported.  MII: Max 1channel  RMII: Max 2channels  Full-Duplex and Half-Duplex mode supported.  Wake-ON-LAN supported  Built-in dedicated descriptor-system DMAC  Built-in 2 Kbyte Transmit FIFO and 2 Kbyte Receive FIFO.  Compliant IEEE1558-2008 (PTP) PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock.  Multi-function Serial Interface (Max 8 channels)  4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available [LIN]  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generate (can be changed 13 to 16-bit length)  LIN break delimiter generate (can be changed 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C] Standard-mode (Max 100kbps) / Fast-mode (Max 400kbps) supported  External Bus Interface  Supports SRAM, NOR and NAND Flash device  Up to 8 chip selects  8-/16-bit Data width  Up to 25-bit Address bit  Maximum area size : Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY input

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 DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbyte)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536  A/D Converter (Max 32 channels) [12-bit A/D Converter]  Successive Approximation Register type  Built-in 3unit  Conversion time: 1.0 μs@ 5 V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)  Base Timer (Max 16 channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer  Multi-function Timer (Max 3units) The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3ch./unit  Input capture × 4ch./unit  Output compare × 6ch./unit  A/D activation compare × 3ch./unit  Waveform generator × 3ch./unit  16-bit PPG timer × 3ch./unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function  Quadrature Position/Revolution Counter (QPRC) (Max 3 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 5 CONFIDENTIAL  Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot  Watch Counter The Watch counter is used for wake up from Low Power Consumption mode. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz  Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, ”Hardware" watchdog is active in any power saving mode except STOP mode.  General Purpose I/O Port This series can use its pins as General Purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up 154 fast General Purpose I/O Ports@176 pin Package  Some pin is 5V tolerant I/O. See "Pin Description" to confirm the corresponding pins.  External Interrupt Controller Unit  Up to 32 external interrupt input pin  Include one non-maskable interrupt (NMI)  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

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 Clock and Reset [Clocks] Five clock sources (2 external oscillator, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main Clock : 4 MHz to 50 MHz  Sub Clock : 32.768 kHz  High-speed internal CR Clock : 4 MHz  Low-speed internal CR Clock : 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low-voltage detector reset  Clock supervisor reset  Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted.  Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-V oltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation  Low Power Mode Three Low Power Consumption modes supported.  SLEEP  TIMER  STOP  Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.  Power Supply Four Power Supplies  Wide range voltage : VCC = 2.7 V to 5.5 V  I/O voltage for USB ch.0 : USBVCC0 = 3.0 V to 3.6 V (when USB ch.0 is used) = 2.7 V to 5.5 V (when GPIO is used)  I/O voltage for USB ch.1 : USBVCC1 = 3.0 V to 3.6 V (when USB ch.1 is used) = 2.7 V to 5.5 V (when GPIO is used)  I/O voltage for Ethernet :ETHVCC = 3.0 V to 5.5 V (when Ethernet is used) = 2.7 V to 5.5 V (when GPIO is used)

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 7 CONFIDENTIAL  Product Lineup  Memory size Product name MB9BFD16S MB9BFD16T MB9BFD17S MB9BFD17T MB9BFD18S MB9BFD18T On-chip Flash memory 512 Kbyte 768 Kbyte 1 Mbyte On-chip RAM 64 Kbyte 96 Kbyte 128 Kbyte  Function Product name MB9BFD16S MB9BFD17S MB9BFD18S MB9BFD16T MB9BFD17T MB9BFD18T Pin count 144 176/192 CPU Cortex-M3 Freq. 144MHz Power supply voltage range VCC: 2.7V to 5.5V (USBVCC0: 3.0V to 3.6V) (USBVCC1: 3.0V to 3.6V) (ETHVCC: 3.0V to 5.5V) USB2.0 (Function/Host) 2ch. (Max) CAN 2ch. (Max) Ethernet-MAC 2ch.(Max) MII: 1ch. / RMII: 2ch.(Max) DMAC 8ch. External Bus Interface Addr: 19-bit (Max) R/Wdata: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR & NAND Flash Addr: 25-bit (Max) R/Wdata :8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR & NAND Flash Multi-function Serial Interface (UART/CSIO/LIN/I2C) 8ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO Base Timer (PWC/ Reload timer/PWM/PPG) 16ch.(Max) MF- Timer A/D activation compare 3ch. 3 units (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. QPRC 3ch. (Max) Dual Timer 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 32pins (Max)+ NMI × 1 I/O ports 122 pins (Max) 154 pins (Max) 12-bit A/D converter 24ch. (3 units) 32ch. (3 units) CSV (Clock Super Visor) Yes LVD (Low-V oltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP/ETM Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the General I/O port according to your function use. See " Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for accuracy of built-in CR.

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 Packages Product name Package MB9BFD16S MB9BFD17S MB9BFD18S MB9BFD16T MB9BFD17T MB9BFD18T LQFP: FPT-144P-M08 (0.5mm pitch)  - LQFP: FPT-176P-M07 (0.5mm pitch) -  BGA: BGA-192P-M06 (0.8mm pitch) -  : Supported Note : See "Package Dimensions" for detailed information on each package

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 9 CONFIDENTIAL  Pin Assignment  FPT-176P-M07 (TOP VIEW) VSS P81/UDP0 P80/UDM0 USBVCC0 PF5/SCK6_2/INT08_0/ZIN2_1 PF4/TIOB06_0/SOT6_2/INT07_0/BIN2_1 PF3/TIOA06_0/SIN6_2/INT06_0/AIN2_1 P60/SIN5_0/TIOA02_2/INT15_1 P61/SOT5_0/TIOB02_2/UHCONX0 P62/E_PPS0_PPS1/SCK5_0/ADTG_3 PD3/E_TXEN0/TIOB03_2 PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2 PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1 PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1 PCF/E_TX03_TX11/CTS4_0/TIOB08_2 PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1 PCD/E_TCK0_MDC1 PCC/E_MDIO1 PCB/E_COUT VSS ETHVCC PCA/E_CRS0 PC9/E_COL0 PC8/E_RXCK0_REFCK PC7/E_MDC0/CROUT_1 PC6/E_MDIO0/TIOA14_0 PC5/E_RXDV0/TIOA10_2 PC4/E_RX00/TIOA08_2 PC3/E_RX01/TIOA06_1 PC2/E_RX02_RX10 PC1/E_RX03_RX11 PC0/E_RXER0_RXDV1 P95/TIOB13_0/RTO25_1/INT27_0/MAD24_0 P94/TIOB12_0/RTO24_1/SCK5_1/INT26_0/MAD23_0 P93/TIOB11_0/RTO23_1/SOT5_1/MAD22_0 P92/TIOB10_0/RTO22_1/SIN5_1/MAD21_0 P91/TIOB09_0/RTO21_1/INT31_0/MAD20_0 P90/TIOB08_0/RTO20_1/INT30_0/MAD19_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC 1 132 VSS PA0/RTO20_0/TIOA08_0/FRCK1_0 2 131 P83/UDP1 PA1/RTO21_0/TIOA09_0/IC10_0 3 130 P82/UDM1 PA2/RTO22_0/TIOA10_0/IC11_0 4 129 USBVCC1 PA3/RTO23_0/TIOA11_0/IC12_0 5 128 PF6/FRCK2_0/NMIX PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0 6 127 P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0 PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2 7 126 P21/SIN0_0/INT06_1/BIN1_1 P05/TRACED0/TIOA05_2/SIN4_2/INT00_1 8 125 P22/AN31/SOT0_0/TIOB07_1/ZIN1_1 P06/TRACED1/TIOB05_2/SOT4_2/INT01_1 9 124 P23/AN30/SCK0_0/TIOA07_1/RTO00_1 P07/TRACED2/ADTG_0/SCK4_2 10 123 P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0 P08/TRACED3/TIOA00_2/CTS4_2 11 122 P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0 P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0 12 121 P26/AN27/SCK2_1/RTO03_1/MAD15_0 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0 13 120 P27/AN26/INT02_2/RTO04_1/MAD14_0 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0 14 119 P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0 15 118 P29/AN24/MAD12_0 P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0 16 117 PB7/AN23/TIOB12_1/INT23_0/ZIN2_2 P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0 17 116 PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2 P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0 18 115 PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2 P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0 19 114 PB4/AN20/TIOA11_1/SIN0_2/INT20_0 P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0 20 113 PB3/AN19/TIOB10_1/INT19_0 P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0 21 112 PB2/AN18/TIOA10_1/SCK7_2/INT18_0 P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0 22 111 PB1/AN17/TIOB09_1/SOT7_2/INT17_0 P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0 23 110 PB0/AN16/TIOA09_1/SIN7_2/INT16_0 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0 24 109 VSS P5C/TIOA06_2/INT28_0/IC20_1 25 108 AVSS P5D/TIOB06_2/INT29_0/DTTI2X_1 26 107 AVRH VSS 27 106 AVCC P30/AIN0_0/TIOB00_1/INT03_2 28 105 P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0 P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2 29 104 P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0 P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2 30 103 P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0 P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6 31 102 P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0 P34/FRCK0_0/TIOB04_1/TX0_1 32 101 P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0 P35/IC03_0/TIOB05_1/RX0_1/INT08_1 33 100 P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0 P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0 34 99 P19/AN09/SCK2_2/INT22_1/MAD05_0 P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0 35 98 P18/AN08/SOT2_2/INT21_1/MAD04_0 P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0 36 97 P17/AN07/SIN2_2/INT04_1/MAD03_0 P39/DTTI0X_0/ADTG_2 37 96 P16/AN06/SCK0_1/INT20_1/MAD02_0 P3A/RTO00_0/TIOA00_1 38 95 P15/AN05/SOT0_1/IC03_2/MAD01_0 P3B/RTO01_0/TIOA01_1 39 94 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0 P3C/RTO02_0/TIOA02_1 40 93 P13/AN03/SCK1_1/IC01_2/MCSX4_0 P3D/RTO03_0/TIOA03_1 41 92 P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0 P3E/RTO04_0/TIOA04_1 42 91 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0 P3F/RTO05_0/TIOA05_1 43 90 P10/AN00/MCSX7_0 VSS 44 89 VCC VCC P40/TIOA00_0/RTO10_1/INT12_1 P41/TIOA01_0/RTO11_1/INT13_1 P42/TIOA02_0/RTO12_1 P43/TIOA03_0/RTO13_1/ADTG_7 P44/TIOA04_0/RTO14_1 P45/TIOA05_0/RTO15_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2 P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2 P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0 P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0 P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0 P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0 P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0 P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0 P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0 P74/SCK2_0/ZIN2_0/MADATA09_0 P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P7B/TIOB07_0/INT10_0 P7C/TIOA07_0/INT11_0 P7D/TIOA14_1/FRCK2_1/INT12_0 P7E/TIOB14_1/IC21_1/INT24_0 P7F/TIOA15_1/IC22_1/INT25_0 PF0/TIOB15_1/SIN1_2/INT13_0/IC23_1 PF1/TIOA08_1/SOT1_2/INT14_0 PF2/TIOB08_1/SCK1_2/INT15_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 176 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.

10 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 FPT-144P-M08 (TOP VIEW) VSS P81/UDP0 P80/UDM0 USBVCC0 PF5/SCK6_2/INT08_0/ZIN2_1 P60/SIN5_0/TIOA02_2/INT15_1 P61/SOT5_0/TIOB02_2/UHCONX0 P62/E_PPS0_PPS1/SCK5_0/ADTG_3 PD3/E_TXEN0/TIOB03_2 PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2 PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1 PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1 PCF/E_TX03_TX11/CTS4_0/TIOB08_2 PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1 PCD/E_TCK0_MDC1 PCC/E_MDIO1 PCB/E_COUT VSS ETHVCC PCA/E_CRS0 PC9/E_COL0 PC8/E_RXCK0_REFCK PC7/E_MDC0/CROUT_1 PC6/E_MDIO0/TIOA14_0 PC5/E_RXDV0/TIOA10_2 PC4/E_RX00/TIOA08_2 PC3/E_RX01/TIOA06_1 PC2/E_RX02_RX10 PC1/E_RX03_RX11 PC0/E_RXER0_RXDV1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VCC 1 108 VSS PA0/RTO20_0/TIOA08_0/FRCK1_0 2 107 P83/UDP1 PA1/RTO21_0/TIOA09_0/IC10_0 3 106 P82/UDM1 PA2/RTO22_0/TIOA10_0/IC11_0 4 105 USBVCC1 PA3/RTO23_0/TIOA11_0/IC12_0 5 104 PF6/FRCK2_0/NMIX PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0 6 103 P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0 PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2 7 102 P21/SIN0_0/INT06_1/BIN1_1 P05/TRACED0/TIOA05_2/SIN4_2/INT00_1 8 101 P22/AN31/SOT0_0/TIOB07_1/ZIN1_1 P06/TRACED1/TIOB05_2/SOT4_2/INT01_1 9 100 P23/AN30/SCK0_0/TIOA07_1/RTO00_1 P07/TRACED2/ADTG_0/SCK4_2 10 99 P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0 P08/TRACED3/TIOA00_2/CTS4_2 11 98 P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0 P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0 12 97 P26/AN27/SCK2_1/RTO03_1/MAD15_0 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0 13 96 P27/AN26/INT02_2/RTO04_1/MAD14_0 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0 14 95 P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0 15 94 P29/AN24/MAD12_0 P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0 16 93 VSS P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0 17 92 AVSS P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0 18 91 AVRH P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0 19 90 AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0 20 89 P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0 P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0 21 88 P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0 P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0 22 87 P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0 P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0 23 86 P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0 24 85 P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0 VSS 25 84 P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0 P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0 26 83 P19/AN09/SCK2_2/INT22_1/MAD05_0 P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0 27 82 P18/AN08/SOT2_2/INT21_1/MAD04_0 P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0 28 81 P17/AN07/SIN2_2/INT04_1/MAD03_0 P39/DTTI0X_0/ADTG_2 29 80 P16/AN06/SCK0_1/INT20_1/MAD02_0 P3A/RTO00_0/TIOA00_1 30 79 P15/AN05/SOT0_1/IC03_2/MAD01_0 P3B/RTO01_0/TIOA01_1 31 78 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0 P3C/RTO02_0/TIOA02_1 32 77 P13/AN03/SCK1_1/IC01_2/MCSX4_0 P3D/RTO03_0/TIOA03_1 33 76 P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0 P3E/RTO04_0/TIOA04_1 34 75 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0 P3F/RTO05_0/TIOA05_1 35 74 P10/AN00/MCSX7_0 VSS 36 73 VCC VCC P40/TIOA00_0/RTO10_1/INT12_1 P41/TIOA01_0/RTO11_1/INT13_1 P42/TIOA02_0/RTO12_1 P43/TIOA03_0/RTO13_1/ADTG_7 P44/TIOA04_0/RTO14_1 P45/TIOA05_0/RTO15_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2 P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2 P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0 P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0 P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0 P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0 P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0 P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0 P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0 P74/SCK2_0/ZIN2_0/MADATA09_0 P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 144 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. TIOA09_0 and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 11 CONFIDENTIAL  BGA-192P-M06 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A UDP0 UDM0 USB VCC0 VSS PCD PCB VSS ETH VCC PC8 VSS TCK VCC B VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6 UDP1 D PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 UDM1 E VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 USB VCC1 F P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS G VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS H P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH J VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC K P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17 L P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS M VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC N VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS P C VSS VCC X0A X1A VSS P75 P77 P7C VSS X0 X1 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.

12 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 List of Pin Functions  List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 1 1 C1 VCC - 2 2 B2 PA0 G I RTO20_0 TIOA08_0 FRCK1_0 3 3 C2 PA1 G I RTO21_0 TIOA09_0 IC10_0 4 4 C3 PA2 G I RTO22_0 TIOA10_0 IC11_0 5 5 D5 PA3 G I RTO23_0 TIOA11_0 IC12_0 6 6 D2 PA4 G H RTO24_0 TIOA12_0 RX0_2 IC13_0 INT03_0 7 7 D1 PA5 G H RTO25_0 TX0_2 TIOA13_0 INT10_2 8 8 D3 P05 E F TRACED0 TIOA05_2 SIN4_2 INT00_1 9 9 D4 P06 E F TRACED1 TIOB05_2 SOT4_2 INT01_1

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 13 CONFIDENTIAL Pin No Pin Name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 10 10 E2 P07 E G TRACED2 ADTG_0 SCK4_2 11 11 E3 P08 E G TRACED3 TIOA00_2 CTS4_2 12 12 E4 P09 E G TRACECLK TIOB00_2 RTS4_2 DTTI2X_0 13 13 E5 P50 E H INT00_0 AIN0_2 SIN3_1 RTO10_0 IC20_0 MOEX_0 14 14 F1 P51 E H INT01_0 BIN0_2 SOT3_1 RTO11_0 IC21_0 MWEX_0 15 15 F2 P52 E H INT02_0 ZIN0_2 SCK3_1 RTO12_0 IC22_0 MDQM0_0

14 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin Name I/O circuit type Pin State type LQFP-176 LQFP-144 BGA-192 16 16 F3 P53 E H SIN6_0 TIOA01_2 INT07_2 RTO13_0 IC23_0 MDQM1_0 17 17 F4 P54 E I SOT6_0 TIOB01_2 RTO14_0 MALE_0 18 18 F5 P55 E I SCK6_0 ADTG_1 RTO15_0 MRDY_0 19 19 F6 P56 E H SIN1_0 INT08_2 TIOA09_2 DTTI1X_0 MNALE_0 20 20 G2 P57 E H SOT1_0 TIOB09_2 INT16_1 MNCLE_0 21 21 G3 P58 E H SCK1_0 TIOA11_2 INT17_1 MNWEX_0 22 22 G4 P59 E H SIN7_0 RX1_1 TIOB11_2 INT09_2 MNREX_0

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 15 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 23 23 G5 P5A E H SOT7_0 TX1_1 TIOA13_1 INT18_1 MCSX0_0 24 24 G6 P5B E H SCK7_0 TIOB13_1 INT19_1 MCSX1_0 25 - H1 P5C E H TIOA06_2 INT28_0 IC20_1 26 - H2 P5D E H TIOB06_2 INT29_0 DTTI2X_1 27 25 J1 VSS - 28 - H3 P30 E H AIN0_0 TIOB00_1 INT03_2 29 - H4 P31 E H BIN0_0 TIOB01_1 SCK6_1 INT04_2 30 - H5 P32 E H ZIN0_0 TIOB02_1 SOT6_1 INT05_2 31 - H6 P33 E H INT04_0 TIOB03_1 SIN6_1 ADTG_6

16 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 32 - J5 P34 E I FRCK0_0 TX0_1 TIOB04_1 33 - J4 P35 E H IC03_0 RX0_1 TIOB05_1 INT08_1 34 26 J3 P36 E H IC02_0 SIN5_2 INT09_1 TIOA12_2 MCSX2_0 35 27 J2 P37 E H IC01_0 SOT5_2 INT10_1 TIOB12_2 MCSX3_0 36 28 K1 P38 E H IC00_0 SCK5_2 INT11_1 MCLKOUT_0 37 29 K2 P39 E I DTTI0X_0 ADTG_2 38 30 K3 P3A G I RTO00_0 TIOA00_1 39 31 K4 P3B G I RTO01_0 TIOA01_1 40 32 L1 P3C G I RTO02_0 TIOA02_1

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 17 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 41 33 L2 P3D G I RTO03_0 TIOA03_1 42 34 L3 P3E G I RTO04_0 TIOA04_1 43 35 M2 P3F G I RTO05_0 TIOA05_1 44 36 M1 VSS - 45 37 N1 VCC - 46 38 N2 P40 G H TIOA00_0 RTO10_1 INT12_1 47 39 N3 P41 G H TIOA01_0 RTO11_1 INT13_1 48 40 M3 P42 G I TIOA02_0 RTO12_1 49 41 L4 P43 G I TIOA03_0 RTO13_1 ADTG_7 50 42 M4 P44 G I TIOA04_0 RTO14_1 51 43 N4 P45 G I TIOA05_0 RTO15_1 52 44 P2 C - 53 45 P3 VSS - 54 46 P4 VCC - 55 47 P5 P46 D M X0A 56 48 P6 P47 D N X1A 57 49 N5 INITX B C 58 50 M5 P48 E H DTTI1X_1 INT14_1 SIN3_2

18 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 59 51 L5 P49 E I TIOB00_0 IC10_1 AIN0_1 SOT3_2 60 52 K5 P4A E I TIOB01_0 IC11_1 BIN0_1 SCK3_2 MADA TA00_0 61 53 N6 P4B E I TIOB02_0 IC12_1 ZIN0_1 MADA TA01_0 62 54 M6 P4C E I TIOB03_0 IC13_1 SCK7_1 AIN1_2 MADA TA02_0 63 55 L6 P4D E I TIOB04_0 FRCK1_1 SOT7_1 BIN1_2 MADA TA03_0 64 56 K6 P4E E H TIOB05_0 INT06_2 SIN7_1 ZIN1_2 MADA TA04_0 65 57 J6 P70 E I TIOA04_2 TX0_0 MADA TA05_0 66 58 N8 P71 E H INT13_2 TIOB04_2 RX0_0 MADA TA06_0

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 19 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 67 59 M8 P72 E H SIN2_0 INT14_2 AIN2_0 MADA TA07_0 68 60 L8 P73 E H SOT2_0 INT15_2 BIN2_0 MADA TA08_0 69 61 K8 P74 E I SCK2_0 ZIN2_0 MADA TA09_0 70 62 P8 P75 E H SIN3_0 ADTG_8 INT07_1 MADA TA10_0 71 63 J8 P76 E H SOT3_0 TIOA07_2 INT11_2 MADA TA11_0 72 64 P9 P77 E H SCK3_0 TIOB07_2 INT12_2 MADA TA12_0 73 65 N9 P78 E I AIN1_0 TIOA15_0 MADA TA13_0 74 66 M9 P79 E H BIN1_0 TIOB15_0 INT23_1 MADA TA14_0 - - E1 VSS - - - G1 VSS -

20 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 75 67 L9 P7A E H ZIN1_0 INT24_1 MADA TA15_0 76 - K9 P7B E H TIOB07_0 INT10_0 77 - P10 P7C E H TIOA07_0 INT11_0 78 - N10 P7D E H TIOA14_1 FRCK2_1 INT12_0 79 - L10 P7E E H TIOB14_1 IC21_1 INT24_0 80 - K10 P7F E H TIOA15_1 IC22_1 INT25_0 81 - M10 PF0 I* H TIOB15_1 SIN1_2 INT13_0 IC23_1 82 - N11 PF1 I* H TIOA08_1 SOT1_2 INT14_0 83 - M11 PF2 I* H TIOB08_1 SCK1_2 INT15_0 84 68 N13 PE0 C P MD1 85 69 N12 MD0 J D 86 70 P12 PE2 A A X0 87 71 P13 PE3 A B X1 88 72 N14 VSS - 89 73 M14 VCC - - - L7 VSS - - - K7 VSS -

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 21 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 90 74 M13 P10 F K AN00 MCSX7_0 91 75 M12 P11 F L AN01 SIN1_1 RX1_2 INT02_1 FRCK0_2 MCSX6_0 92 76 L13 P12 F K AN02 SOT1_1 TX1_2 IC00_2 MCSX5_0 93 77 L12 P13 F K AN03 SCK1_1 IC01_2 MCSX4_0 94 78 L11 P14 F L AN04 SIN0_1 INT03_1 IC02_2 MAD00_0 95 79 K13 P15 F K AN05 SOT0_1 IC03_2 MAD01_0 96 80 K12 P16 F L AN06 SCK0_1 INT20_1 MAD02_0 97 81 K14 P17 F L AN07 SIN2_2 INT04_1 MAD03_0 - - P7 VSS - - - P11 VSS - - - L14 VSS -

22 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 98 82 K11 P18 F L AN08 SOT2_2 INT21_1 MAD04_0 99 83 J13 P19 F L AN09 SCK2_2 INT22_1 MAD05_0 100 84 J12 P1A F L AN10 SIN4_1 INT05_1 TIOA13_2 IC00_1 MAD06_0 101 85 J11 P1B F L AN11 SOT4_1 INT25_1 TIOB13_2 IC01_1 MAD07_0 102 86 J10 P1C F L AN12 SCK4_1 INT26_1 TIOA14_2 IC02_1 MAD08_0 103 87 J9 P1D F L AN13 CTS4_1 INT27_1 TIOB14_2 IC03_1 MAD09_0 104 88 H10 P1E F L AN14 RTS4_1 INT28_1 TIOA15_2 DTTI0X_1 MAD10_0

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 23 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 105 89 H9 P1F F L AN15 ADTG_5 INT29_1 TIOB15_2 FRCK0_1 MAD11_0 106 90 J14 A VCC - 107 91 H14 A VRH - 108 92 G14 AVSS - 109 93 F14 VSS - 110 - H13 PB0 F L AN16 TIOA09_1 SIN7_2 INT16_0 111 - H12 PB1 F L AN17 TIOB09_1 SOT7_2 INT17_0 112 - H11 PB2 F L AN18 TIOA10_1 SCK7_2 INT18_0 113 - G13 PB3 F L AN19 TIOB10_1 INT19_0 114 - G12 PB4 F L AN20 TIOA11_1 SIN0_2 INT20_0 115 - G11 PB5 F L AN21 TIOB11_1 SOT0_2 INT21_0 AIN2_2 - - G7 VSS - - - J7 VSS -

24 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 116 - G10 PB6 F L AN22 TIOA12_1 SCK0_2 INT22_0 BIN2_2 117 - G9 PB7 F L AN23 TIOB12_1 INT23_0 ZIN2_2 118 94 F10 P29 F K AN24 MAD12_0 119 95 F11 P28 F L AN25 ADTG_4 INT09_0 RTO05_1 MAD13_0 120 96 F12 P27 F L AN26 INT02_2 RTO04_1 MAD14_0 121 97 F13 P26 F K AN27 SCK2_1 RTO03_1 MAD15_0 122 98 E10 P25 F K AN28 SOT2_1 TX1_0 RTO02_1 MAD16_0 123 99 E11 P24 F L AN29 SIN2_1 RX1_0 INT01_2 RTO01_1 MAD17_0

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 25 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 124 100 E12 P23 F K AN30 SCK0_0 TIOA07_1 RTO00_1 125 101 E13 P22 F K AN31 SOT0_0 TIOB07_1 ZIN1_1 126 102 D12 P21 E H SIN0_0 INT06_1 BIN1_1 127 103 D13 P20 E H INT05_0 CROUT_0 UHCONX1 AIN1_1 MAD18_0 128 104 C13 PF6 I* J FRCK2_0 NMIX 129 105 E14 USBVCC1 - 130 106 D14 P82 H O UDM1 131 107 C14 P83 H O UDP1 132 108 B14 VSS - 133 109 A13 VCC - 134 110 B13 P00 E E TRSTX 135 111 A12 P01 E E TCK SWCLK 136 112 C12 P02 E E TDI 137 113 B12 P03 E E TMS SWDIO 138 114 B11 P04 E E TDO SWO 139 - C11 P90 E H TIOB08_0 RTO20_1 INT30_0 MAD19_0 - - A8 VSS -

26 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 140 - D11 P91 E H TIOB09_0 RTO21_1 INT31_0 MAD20_0 141 - B10 P92 E I TIOB10_0 RTO22_1 SIN5_1 MAD21_0 142 - C10 P93 E I TIOB11_0 RTO23_1 SOT5_1 MAD22_0 143 - D10 P94 E H TIOB12_0 RTO24_1 SCK5_1 INT26_0 MAD23_0 144 - B9 P95 E H TIOB13_0 RTO25_1 INT27_0 MAD24_0 145 115 C9 PC0 K Q E_RXER0_RXDV1 146 116 B8 PC1 K Q E_RX03_RX11 147 117 D9 PC2 K Q E_RX02_RX10 148 118 E9 PC3 K Q E_RX01 TIOA06_1 149 119 F9 PC4 K Q E_RX00 TIOA08_2 150 120 C8 PC5 K Q E_RXDV0 TIOA10_2 - - A5 VSS -

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 27 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 151 121 D8 PC6 K Q E_MDIO0 TIOA14_0 152 122 E8 PC7 L Q E_MDC0 CROUT_1 153 123 A10 PC8 K Q E_RXCK0_REFCK 154 124 F8 PC9 K Q E_COL0 155 125 B7 PCA K Q E_CRS0 156 126 A9 ETHVCC - 157 127 A11 VSS - 158 128 A7 PCB L Q E_COUT 159 129 C7 PCC K Q E_MDIO1 160 130 A6 PCD K Q E_TCK0_MDC1 161 131 D7 PCE L Q E_TXER0_TXEN1 RTS4_0 TIOB06_1 162 132 E7 PCF L Q E_TX03_TX11 CTS4_0 TIOB08_2 163 133 F7 PD0 L R E_TX02_TX10 SCK4_0 TIOB10_2 INT30_1 164 134 B6 PD1 L R E_TX01 SOT4_0 TIOB14_0 INT31_1 - - N7 VSS - - - G8 VSS - - - H7 VSS - - - H8 VSS -

28 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 165 135 C6 PD2 L R E_TX00 SIN4_0 TIOA03_2 INT00_2 166 136 D6 PD3 L Q E_TXEN0 TIOB03_2 167 137 E6 P62 E Q E_PPS0_PPS1 SCK5_0 ADTG_3 168 138 B5 P61 E I SOT5_0 TIOB02_2 UHCONX0 169 139 C5 P60 E H SIN5_0 TIOA02_2 INT15_1 170 - B4 PF3 I* H TIOA06_0 SIN6_2 INT06_0 AIN2_1 171 - C4 PF4 I* H TIOB06_0 SOT6_2 INT07_0 BIN2_1 172 140 B3 PF5 I* H SCK6_2 INT08_0 ZIN2_1 173 141 A4 USBVCC0 - 174 142 A3 P80 H O UDM0 175 143 A2 P81 H O UDP0 176 144 B1 VSS - - - M7 VSS - *: 5V tolerant I/O

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 29 CONFIDENTIAL  List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 ADC ADTG_0 A/D converter external trigger input pin 10 10 E2 ADTG_1 18 18 F5 ADTG_2 37 29 K2 ADTG_3 167 137 E6 ADTG_4 119 95 F11 ADTG_5 105 89 H9 ADTG_6 31 - H6 ADTG_7 49 41 L4 ADTG_8 70 62 P8 AN00 A/D converter analog input pin (ANxx describes ADC ch.xx) 90 74 M13 AN01 91 75 M12 AN02 92 76 L13 AN03 93 77 L12 AN04 94 78 L11 AN05 95 79 K13 AN06 96 80 K12 AN07 97 81 K14 AN08 98 82 K11 AN09 99 83 J13 AN10 100 84 J12 AN11 101 85 J11 AN12 102 86 J10 AN13 103 87 J9 AN14 104 88 H10 AN15 105 89 H9 AN16 110 - H13 AN17 111 - H12 AN18 112 - H11 AN19 113 - G13 AN20 114 - G12 AN21 115 - G11 AN22 116 - G10 AN23 117 - G9 AN24 118 94 F10 AN25 119 95 F11 AN26 120 96 F12 AN27 121 97 F13 AN28 122 98 E10 AN29 123 99 E11 AN30 124 100 E12 AN31 125 101 E13

30 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA0_0 Base timer ch.0 TIOA pin 46 38 N2 TIOA0_1 38 30 K3 TIOA0_2 11 11 E3 TIOB0_0 Base timer ch.0 TIOB pin 59 51 L5 TIOB0_1 28 - H3 TIOB0_2 12 12 E4 Base Timer TIOA1_0 Base timer ch.1 TIOA pin 47 39 N3 TIOA1_1 39 31 K4 TIOA1_2 16 16 F3 TIOB1_0 Base timer ch.1 TIOB pin 60 52 K5 TIOB1_1 29 - H4 TIOB1_2 17 17 F4 Base Timer TIOA2_0 Base timer ch.2 TIOA pin 48 40 M3 TIOA2_1 40 32 L1 TIOA2_2 169 139 C5 TIOB2_0 Base timer ch.2 TIOB pin 61 53 N6 TIOB2_1 30 - H5 TIOB2_2 168 138 B5 Base Timer TIOA3_0 Base timer ch.3 TIOA pin 49 41 L4 TIOA3_1 41 33 L2 TIOA3_2 165 135 C6 TIOB3_0 Base timer ch.3 TIOB pin 62 54 M6 TIOB3_1 31 - H6 TIOB3_2 166 136 D6 Base Timer TIOA4_0 Base timer ch.4 TIOA pin 50 42 M4 TIOA4_1 42 34 L3 TIOA4_2 65 57 J6 TIOB4_0 Base timer ch.4 TIOB pin 63 55 L6 TIOB4_1 32 - J5 TIOB4_2 66 58 N8 Base Timer TIOA5_0 Base timer ch.5 TIOA pin 51 43 N4 TIOA5_1 43 35 M2 TIOA5_2 8 8 D3 TIOB5_0 Base timer ch.5 TIOB pin 64 56 K6 TIOB5_1 33 - J4 TIOB5_2 9 9 D4 Base Timer TIOA6_0 Base timer ch.6 TIOA pin 170 - B4 TIOA6_1 148 118 E9 TIOA6_2 25 - H1 TIOB6_0 Base timer ch.6 TIOB pin 171 - C4 TIOB6_1 161 131 D7 TIOB6_2 26 - H2

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 31 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA07_0 Base timer ch.7 TIOA pin 77 - P10 TIOA07_1 124 100 E12 TIOA07_2 71 63 J8 TIOB07_0 Base timer ch.7 TIOB pin 76 - K9 TIOB07_1 125 101 E13 TIOB07_2 72 64 P9 Base Timer TIOA08_0 Base timer ch.8 TIOA pin 2 2 B2 TIOA08_1 82 - N11 TIOA08_2 149 119 F9 TIOB08_0 Base timer ch.8 TIOB pin 139 - C11 TIOB08_1 83 - M11 TIOB08_2 162 132 E7 Base Timer TIOA09_0 Base timer ch.9 TIOA pin 3 3 C2 TIOA09_1 110 - H13 TIOA09_2 19 19 F6 TIOB09_0 Base timer ch.9 TIOB pin 140 - D11 TIOB09_1 111 - H12 TIOB09_2 20 20 G2 Base Timer TIOA10_0 Base timer ch.10 TIOA pin 4 4 C3 TIOA10_1 112 - H11 TIOA10_2 150 120 C8 TIOB10_0 Base timer ch.10 TIOB pin 141 - B10 TIOB10_1 113 - G13 TIOB10_2 163 133 F7 Base Timer TIOA11_0 Base timer ch.11 TIOA pin 5 5 D5 TIOA11_1 114 - G12 TIOA11_2 21 21 G3 TIOB11_0 Base timer ch.11 TIOB pin 142 - C10 TIOB11_1 115 - G11 TIOB11_2 22 22 G4 Base Timer TIOA12_0 Base timer ch.12 TIOA pin 6 6 D2 TIOA12_1 116 - G10 TIOA12_2 34 26 J3 TIOB12_0 Base timer ch.12 TIOB pin 143 - D10 TIOB12_1 117 - G9 TIOB12_2 35 27 J2 Base Timer TIOA13_0 Base timer ch.13 TIOA pin 7 7 D1 TIOA13_1 23 23 G5 TIOA13_2 100 84 J12 TIOB13_0 Base timer ch.13 TIOB pin 144 - B9 TIOB13_1 24 24 G6 TIOB13_2 101 85 J11

32 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA14_0 Base timer ch.14 TIOA pin 151 121 D8 TIOA14_1 78 - N10 TIOA14_2 102 86 J10 TIOB14_0 Base timer ch.14 TIOB pin 164 134 B6 TIOB14_1 79 - L10 TIOB14_2 103 87 J9 Base Timer TIOA15_0 Base timer ch.15 TIOA pin 73 65 N9 TIOA15_1 80 - K10 TIOA15_2 104 88 H10 TIOB15_0 Base timer ch.15 TIOB pin 74 66 M9 TIOB15_1 81 - M10 TIOB15_2 105 89 H9 CAN 0 TX0_0 CAN interface ch.0 TX output pin 65 57 J6 TX0_1 32 - J5 TX0_2 7 7 D1 RX0_0 CAN interface ch.0 RX output pin 66 58 N8 RX0_1 33 - J4 RX0_2 6 6 D2 CAN 1 TX1_0 CAN interface ch.1 TX output pin 122 98 E10 TX1_1 23 23 G5 TX1_2 92 76 L13 RX1_0 CAN interface ch.1 RX output pin 123 99 E11 RX1_1 22 22 G4 RX1_2 91 75 M12 Debugger SWCLK Serial wire debug interface clock input pin 135 111 A12 SWDIO Serial wire debug interface data input / output pin 137 113 B12 SWO Serial wire viewer output pin 138 114 B11 TCK J-TAG test clock input pin 135 111 A12 TDI J-TAG test data input pin 136 112 C12 TDO J-TAG debug data output pin 138 114 B11 TMS J-TAG test mode state input/output pin 137 113 B12 TRACECLK Trace CLK output pin of ETM 12 12 E4 TRACED0 Trace data output pin of ETM 8 8 D3 TRACED1 9 9 D4 TRACED2 10 10 E2 TRACED3 11 11 E3 TRSTX J-TAG test reset input pin 134 110 B13

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 33 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 External Bus MAD00_0 External bus interface address bus 94 78 L11 MAD01_0 95 79 K13 MAD02_0 96 80 K12 MAD03_0 97 81 K14 MAD04_0 98 82 K11 MAD05_0 99 83 J13 MAD06_0 100 84 J12 MAD07_0 101 85 J11 MAD08_0 102 86 J10 MAD09_0 103 87 J9 MAD10_0 104 88 H10 MAD11_0 105 89 H9 MAD12_0 118 94 F10 MAD13_0 119 95 F11 MAD14_0 120 96 F12 MAD15_0 121 97 F13 MAD16_0 122 98 E10 MAD17_0 123 99 E11 MAD18_0 127 103 D13 MAD19_0 139 - C11 MAD20_0 140 - D11 MAD21_0 141 - B10 MAD22_0 142 - C10 MAD23_0 143 - D10 MAD24_0 144 - B9 MCSX0_0 External bus interface chip select output pin 23 23 G5 MCSX1_0 24 24 G6 MCSX2_0 34 26 J3 MCSX3_0 35 27 J2 MCSX4_0 93 77 L12 MCSX5_0 92 76 L13 MCSX6_0 91 75 M12 MCSX7_0 90 74 M13 MDQM0_0 External bus interface byte mask signal output pin 15 15 F2 MDQM1_0 16 16 F3 MOEX_0 External bus interface read enable signal for SRAM 13 13 E5 MWEX_0 External bus interface write enable signal for SRAM 14 14 F1

34 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 External Bus MNALE_0 External bus interface ALE signal to control NAND Flash output pin 19 19 F6 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 20 20 G2 MNREX_0 External bus interface read enable signal to control NAND Flash 22 22 G4 MNWEX_0 External bus interface write enable signal to control NAND Flash 21 21 G3 MADA TA00_0 External bus interface data bus (Address / data multiplex bus) 60 52 K5 MADA TA01_0 61 53 N6 MADA TA02_0 62 54 M6 MADA TA03_0 63 55 L6 MADA TA04_0 64 56 K6 MADA TA05_0 65 57 J6 MADA TA06_0 66 58 N8 MADA TA07_0 67 59 M8 MADA TA08_0 68 60 L8 MADA TA09_0 69 61 K8 MADA TA10_0 70 62 P8 MADA TA11_0 71 63 J8 MADA TA12_0 72 64 P9 MADA TA13_0 73 65 N9 MADA TA14_0 74 66 M9 MADA TA15_0 75 67 L9 MALE_0 External bus interface Address Latch enable output signal for multiplex 17 17 F4 MRDY_0 External bus interface external RDY input signal 18 18 F5 MCLKOUT_0 External bus interface external clock output pin 36 28 K1

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 35 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 External Interrupt INT00_0 External interrupt request 00 input pin 13 13 E5 INT00_1 8 8 D3 INT00_2 165 135 C6 INT01_0 External interrupt request 01 input pin 14 14 F1 INT01_1 9 9 D4 INT01_2 123 99 E11 INT02_0 External interrupt request 02 input pin 15 15 F2 INT02_1 91 75 M12 INT02_2 120 96 F12 INT03_0 External interrupt request 03 input pin 6 6 D2 INT03_1 94 78 L11 INT03_2 28 - H3 INT04_0 External interrupt request 04 input pin 31 - H6 INT04_1 97 81 K14 INT04_2 29 - H4 INT05_0 External interrupt request 05 input pin 127 103 D13 INT05_1 100 84 J12 INT05_2 30 - H5 INT06_0 External interrupt request 06 input pin 170 - B4 INT06_1 126 102 D12 INT06_2 64 56 K6 INT07_0 External interrupt request 07 input pin 171 - C4 INT07_1 70 62 P8 INT07_2 16 16 F3 INT08_0 External interrupt request 08 input pin 172 140 B3 INT08_1 33 - J4 INT08_2 19 19 F6 INT09_0 External interrupt request 09 input pin 119 95 F11 INT09_1 34 26 J3 INT09_2 22 22 G4 INT10_0 External interrupt request 10 input pin 76 - K9 INT10_1 35 27 J2 INT10_2 7 7 D1 INT11_0 External interrupt request 11 input pin 77 - P10 INT11_1 36 28 K1 INT11_2 71 63 J8 INT12_0 External interrupt request 12 input pin 78 - N10 INT12_1 46 38 N2 INT12_2 72 64 P9 INT13_0 External interrupt request 13 input pin 81 - M10 INT13_1 47 39 N3 INT13_2 66 58 N8 INT14_0 External interrupt request 14 input pin 82 - N11 INT14_1 58 50 M5 INT14_2 67 59 M8

36 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 External Interrupt INT15_0 External interrupt request 15 input pin 83 - M11 INT15_1 169 139 C5 INT15_2 68 60 L8 INT16_0 External interrupt request 16 input pin 110 - H13 INT16_1 20 20 G2 INT17_0 External interrupt request 17 input pin 111 - H12 INT17_1 21 21 G3 INT18_0 External interrupt request 18 input pin 112 - H11 INT18_1 23 23 G5 INT19_0 External interrupt request 19 input pin 113 - G13 INT19_1 24 24 G6 INT20_0 External interrupt request 20 input pin 114 - G12 INT20_1 96 80 K12 INT21_0 External interrupt request 21 input pin 115 - G11 INT21_1 98 82 K11 INT22_0 External interrupt request 22 input pin 116 - G10 INT22_1 99 83 J13 INT23_0 External interrupt request 23 input pin 117 - G9 INT23_1 74 66 M9 INT24_0 External interrupt request 24 input pin 79 - L10 INT24_1 75 67 L9 INT25_0 External interrupt request 25 input pin 80 - K10 INT25_1 101 85 J11 INT26_0 External interrupt request 26 input pin 143 - D10 INT26_1 102 86 J10 INT27_0 External interrupt request 27 input pin 144 - B9 INT27_1 103 87 J9 INT28_0 External interrupt request 28 input pin 25 - H1 INT28_1 104 88 H10 INT29_0 External interrupt request 29 input pin 26 - H2 INT29_1 105 89 H9 INT30_0 External interrupt request 30 input pin 139 - C11 INT30_1 163 133 F7 INT31_0 External interrupt request 31 input pin 140 - D11 INT31_1 164 134 B6 NMIX Non-Maskable Interrupt input pin 128 104 C13

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 37 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 GPIO P00 General-purpose I/O port 0 134 110 B13 P01 135 111 A12 P02 136 112 C12 P03 137 113 B12 P04 138 114 B11 P05 8 8 D3 P06 9 9 D4 P07 10 10 E2 P08 11 11 E3 P09 12 12 E4 P10 General-purpose I/O port 1 90 74 M13 P11 91 75 M12 P12 92 76 L13 P13 93 77 L12 P14 94 78 L11 P15 95 79 K13 P16 96 80 K12 P17 97 81 K14 P18 98 82 K11 P19 99 83 J13 P1A 100 84 J12 P1B 101 85 J11 P1C 102 86 J10 P1D 103 87 J9 P1E 104 88 H10 P1F 105 89 H9 P20 General-purpose I/O port 2 127 103 D13 P21 126 102 D12 P22 125 101 E13 P23 124 100 E12 P24 123 99 E11 P25 122 98 E10 P26 121 97 F13 P27 120 96 F12 P28 119 95 F11 P29 118 94 F10

38 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 GPIO P30 General-purpose I/O port 3 28 - H3 P31 29 - H4 P32 30 - H5 P33 31 - H6 P34 32 - J5 P35 33 - J4 P36 34 26 J3 P37 35 27 J2 P38 36 28 K1 P39 37 29 K2 P3A 38 30 K3 P3B 39 31 K4 P3C 40 32 L1 P3D 41 33 L2 P3E 42 34 L3 P3F 43 35 M2 P40 General-purpose I/O port 4 46 38 N2 P41 47 39 N3 P42 48 40 M3 P43 49 41 L4 P44 50 42 M4 P45 51 43 N4 P46 55 47 P5 P47 56 48 P6 P48 58 50 M5 P49 59 51 L5 P4A 60 52 K5 P4B 61 53 N6 P4C 62 54 M6 P4D 63 55 L6 P4E 64 56 K6 P50 General-purpose I/O port 5 13 13 E5 P51 14 14 F1 P52 15 15 F2 P53 16 16 F3 P54 17 17 F4 P55 18 18 F5 P56 19 19 F6 P57 20 20 G2 P58 21 21 G3 P59 22 22 G4 P5A 23 23 G5 P5B 24 24 G6 P5C 25 - H1 P5D 26 - H2

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 39 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 GPIO P60 General-purpose I/O port 6 169 139 C5 P61 168 138 B5 P62 167 137 E6 P70 General-purpose I/O port 7 65 57 J6 P71 66 58 N8 P72 67 59 M8 P73 68 60 L8 P74 69 61 K8 P75 70 62 P8 P76 71 63 J8 P77 72 64 P9 P78 73 65 N9 P79 74 66 M9 P7A 75 67 L9 P7B 76 - K9 P7C 77 - P10 P7D 78 - N10 P7E 79 - L10 P7F 80 - K10 P80 General-purpose I/O port 8 174 142 A3 P81 175 143 A2 P82 130 106 D14 P83 131 107 C14 P90 General-purpose I/O port 9 139 - C11 P91 140 - D11 P92 141 - B10 P93 142 - C10 P94 143 - D10 P95 144 - B9 PA0 General-purpose I/O port A 2 2 B2 PA1 3 3 C2 PA2 4 4 C3 PA3 5 5 D5 PA4 6 6 D2 PA5 7 7 D1 PB0 General-purpose I/O port B 110 - H13 PB1 111 - H12 PB2 112 - H11 PB3 113 - G13 PB4 114 - G12 PB5 115 - G11 PB6 116 - G10 PB7 117 - G9

40 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin no LQFP-176 LQFP-144 BGA-192 GPIO PC0 General-purpose I/O port C 145 115 C9 PC1 146 116 B8 PC2 147 117 D9 PC3 148 118 E9 PC4 149 119 F9 PC5 150 120 C8 PC6 151 121 D8 PC7 152 122 E8 PC8 153 123 A10 PC9 154 124 F8 PCA 155 125 B7 PCB 158 128 A7 PCC 159 129 C7 PCD 160 130 A6 PCE 161 131 D7 PCF 162 132 E7 PD0 General-purpose I/O port D 163 133 F7 PD1 164 134 B6 PD2 165 135 C6 PD3 166 136 D6 PE0 General-purpose I/O port E 84 68 N13 PE2 86 70 P12 PE3 87 71 P13 PF0 General-purpose I/O port F* 81 - M10 PF1 82 - N11 PF2 83 - M11 PF3 170 - B4 PF4 171 - C4 PF5 172 140 B3 PF6 128 104 C13

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 41 CONFIDENTIAL Module Pin name Function Pin No. LQFP-176 LQFP-144 BGA-192 Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 126 102 D12 SIN0_1 94 78 L11 SIN0_2 114 - G12 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 125 101 E13 SOT0_1 (SDA0_1) 95 79 K13 SOT0_2 (SDA0_2) 115 - G11 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). 124 100 E12 SCK0_1 (SCL0_1) 96 80 K12 SCK0_2 (SCL0_2) 116 - G10 Multi- function Serial SIN1_0 Multi-function serial interface ch.1 input pin 19 19 F6 SIN1_1 91 75 M12 SIN1_2 81 - M10 SOT1_0 (SDA1_0) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 20 20 G2 SOT1_1 (SDA1_1) 92 76 L13 SOT1_2 (SDA1_2) 82 - N11 SCK1_0 (SCL1_0) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). 21 21 G3 SCK1_1 (SCL1_1) 93 77 L12 SCK1_2 (SCL1_2) 83 - M11

42 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No. LQFP-176 LQFP-144 BGA-192 Multi- function Serial SIN2_0 Multi-function serial interface ch.2 input pin 67 59 M8 SIN2_1 123 99 E11 SIN2_2 97 81 K14 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 68 60 L8 SOT2_1 (SDA2_1) 122 98 E10 SOT2_2 (SDA2_2) 98 82 K11 SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). 69 61 K8 SCK2_1 (SCL2_1) 121 97 F13 SCK2_2 (SCL2_2) 99 83 J13 Multi- function Serial SIN3_0 Multi-function serial interface ch.3 input pin 70 62 P8 SIN3_1 13 13 E5 SIN3_2 58 50 M5 SOT3_0 (SDA3_0) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 71 63 J8 SOT3_1 (SDA3_1) 14 14 F1 SOT3_2 (SDA3_2) 59 51 L5 SCK3_0 (SCL3_0) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). 72 64 P9 SCK3_1 (SCL3_1) 15 15 F2 SCK3_2 (SCL3_2) 60 52 K5

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 43 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 165 135 C6 SIN4_1 100 84 J12 SIN4_2 8 8 D3 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 164 134 B6 SOT4_1 (SDA4_1) 101 85 J11 SOT4_2 (SDA4_2) 9 9 D4 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). 163 133 F7 SCK4_1 (SCL4_1) 102 86 J10 SCK4_2 (SCL4_2) 10 10 E2 RTS4_0 Multi-function serial interface ch.4 RTS output pin 161 131 D7 RTS4_1 104 88 H10 RTS4_2 12 12 E4 CTS4_0 Multi-function serial interface ch.4 CTS input pin 162 132 E7 CTS4_1 103 87 J9 CTS4_2 11 11 E3 Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 169 139 C5 SIN5_1 141 - B10 SIN5_2 34 26 J3 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 168 138 B5 SOT5_1 (SDA5_1) 142 - C10 SOT5_2 (SDA5_2) 35 27 J2 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). 167 137 E6 SCK5_1 (SCL5_1) 143 - D10 SCK5_2 (SCL5_2) 36 28 K1

44 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 16 16 F3 SIN6_1 31 - H6 SIN6_2 170 - B4 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 17 17 F4 SOT6_1 (SDA6_1) 30 - H5 SOT6_2 (SDA6_2) 171 - C4 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). 18 18 F5 SCK6_1 (SCL6_1) 29 - H4 SCK6_2 (SCL6_2) 172 140 B3 Multi- function Serial SIN7_0 Multi-function serial interface ch.7 input pin 22 22 G4 SIN7_1 64 56 K6 SIN7_2 110 - H13 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 23 23 G5 SOT7_1 (SDA7_1) 63 55 L6 SOT7_2 (SDA7_2) 111 - H12 SCK7_0 (SCL7_0) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4). 24 24 G6 SCK7_1 (SCL7_1) 62 54 M6 SCK7_2 (SCL7_2) 112 - H11

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 45 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Multi- function Timer DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of multi-function timer 0. 37 29 K2 DTTI0X_1 104 88 H10 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 32 - J5 FRCK0_1 105 89 H9 FRCK0_2 91 75 M12 IC00_0 16-bit input capture ch.0 input pin of multi-function timer 0. (ICxx describes chanel number) 36 28 K1 IC00_1 100 84 J12 IC00_2 92 76 L13 IC01_0 35 27 J2 IC01_1 101 85 J11 IC01_2 93 77 L12 IC02_0 34 26 J3 IC02_1 102 86 J10 IC02_2 94 78 L11 IC03_0 33 - J4 IC03_1 103 87 J9 IC03_2 95 79 K13 RTO00_0 (PPG00_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 38 30 K3 RTO00_1 (PPG00_1) 124 100 E12 RTO01_0 (PPG00_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 39 31 K4 RTO01_1 (PPG00_1) 123 99 E11 RTO02_0 (PPG02_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 40 32 L1 RTO02_1 (PPG02_1) 122 98 E10 RTO03_0 (PPG02_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 41 33 L2 RTO03_1 (PPG02_1) 121 97 F13 RTO04_0 (PPG04_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 42 34 L3 RTO04_1 (PPG04_1) 120 96 F12 RTO05_0 (PPG04_0) Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 43 35 M2 RTO05_1 (PPG04_1) 119 95 F11

46 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Multi- function Timer DTTI1X_0 Input signal controlling wave form generator outputs RTO10 to RTO15 of multi-function timer 1. 19 19 F6 DTTI1X_1 58 50 M5 FRCK1_0 16-bit free-run timer ch.1 external clock input pin 2 2 B2 FRCK1_1 63 55 L6 IC10_0 16-bit input capture ch.1 input pin of multi-function timer 1. (ICxx describes chanel number) 3 3 C2 IC10_1 59 51 L5 IC11_0 4 4 C3 IC11_1 60 52 K5 IC12_0 5 5 D5 IC12_1 61 53 N6 IC13_0 6 6 D2 IC13_1 62 54 M6 RTO10_0 (PPG10_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 13 13 E5 RTO10_1 (PPG10_1) 46 38 N2 RTO11_0 (PPG10_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 14 14 F1 RTO11_1 (PPG10_1) 47 39 N3 RTO12_0 (PPG12_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 15 15 F2 RTO12_1 (PPG12_1) 48 40 M3 RTO13_0 (PPG12_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 16 16 F3 RTO13_1 (PPG12_1) 49 41 L4 RTO14_0 (PPG14_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 17 17 F4 RTO14_1 (PPG14_1) 50 42 M4 RTO15_0 (PPG14_0) Wave form generator output pin of multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 18 18 F5 RTO15_1 (PPG14_1) 51 43 N4

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 47 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Multi- function Timer DTTI2X_0 Input signal controlling wave form generator outputs RTO20 to RTO25 of multi-function timer 2. 12 12 E4 DTTI2X_1 26 - H2 FRCK2_0 16-bit free-run timer ch.2 external clock input pin 128 104 C13 FRCK2_1 78 - N10 IC20_0 16-bit input capture ch.2 input pin of multi-function timer 2. (ICxx describes chanel number) 13 13 E5 IC20_1 25 - H1 IC21_0 14 14 F1 IC21_1 79 - L10 IC22_0 15 15 F2 IC22_1 80 - K10 IC23_0 16 16 F3 IC23_1 81 - M10 RTO20_0 (PPG20_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. 2 2 B2 RTO20_1 (PPG20_1) 139 - C11 RTO21_0 (PPG20_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. 3 3 C2 RTO21_1 (PPG20_1) 140 - D11 RTO22_0 (PPG22_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 4 4 C3 RTO22_1 (PPG22_1) 141 - B10 RTO23_0 (PPG22_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 5 5 D5 RTO23_1 (PPG22_1) 142 - C10 RTO24_0 (PPG24_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 6 6 D2 RTO24_1 (PPG24_1) 143 - D10 RTO25_0 (PPG24_0) Wave form generator output pin of multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 7 7 D1 RTO25_1 (PPG24_1) 144 - B9

48 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Quadrature Position/ Revolution Counter AIN0_0 QPRC ch.0 AIN input pin 28 - H3 AIN0_1 59 51 L5 AIN0_2 13 13 E5 BIN0_0 QPRC ch.0 BIN input pin 29 - H4 BIN0_1 60 52 K5 BIN0_2 14 14 F1 ZIN0_0 QPRC ch.0 ZIN input pin 30 - H5 ZIN0_1 61 53 N6 ZIN0_2 15 15 F2 Quadrature Position/ Revolution Counter AIN1_0 QPRC ch.1 AIN input pin 73 65 N9 AIN1_1 127 103 D13 AIN1_2 62 54 M6 BIN1_0 QPRC ch.1 BIN input pin 74 66 M9 BIN1_1 126 102 D12 BIN1_2 63 55 L6 ZIN1_0 QPRC ch.1 ZIN input pin 75 67 L9 ZIN1_1 125 101 E13 ZIN1_2 64 56 K6 Quadrature Position/ Revolution Counter AIN2_0 QPRC ch.2 AIN input pin 67 59 M8 AIN2_1 170 - B4 AIN2_2 115 - G11 BIN2_0 QPRC ch.2 BIN input pin 68 60 L8 BIN2_1 171 - C4 BIN2_2 116 - G10 ZIN2_0 QPRC ch.2 ZIN input pin 69 61 K8 ZIN2_1 172 140 B3 ZIN2_2 117 - G9 USB0 UDM0 USB ch.0 function/host D – pin 174 142 A3 UDP0 USB ch.0 function/host D + pin 175 143 A2 UHCONX0 USB ch.0. USB external pull-up control pin 168 138 B5 USB1 UDM1 USB ch.1 function/host D – pin 130 106 D14 UDP1 USB ch.1 function/host D + pin 131 107 C14 UHCONX1 USB ch.1. USB external pull-up control pin 127 103 D13

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 49 CONFIDENTIAL Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 Ethernet E_COL0 Ch.0 collision detection 154 124 F8 E_COUT Clock output pin for EtherPHY 158 128 A7 E_CRS0 Ch.0 carrer detection 155 125 B7 E_MDC0 Ch.0 management clock 152 122 E8 E_MDIO0 Ch.0 management data input/output 151 121 D8 E_MDIO1 Ch.1 management data input/output 159 129 C7 E_PPS0_PPS1 Ch.0 PTP counter monitor/ Ch.1 PTP counter monitor 167 137 E6 E_RX00 Ch.0 received data0 149 119 F9 E_RX01 Ch.0 received data1 148 118 E9 E_RX02_RX10 Ch.0 received data2/ Ch.1 received data0 147 117 D9 E_RX03_RX11 Ch.0 received data3/ Ch.1 received data1 146 116 B8 E_RXCK0_REFCK Ch.0 received clock input/ reference clock 153 123 A10 E_RXDV0 Ch.0 received data enable 150 120 C8 E_RXER0_RXDV1 Ch.0 received data error detection/ Ch.1 received data enable 145 115 C9 E_TCK0_MDC1 Ch.0 transition clock input/ Ch.1 mangement clock 160 130 A6 E_TX00 Ch.0 transition data0 165 135 C6 E_TX01 Ch.0 trasition data1 164 134 B6 E_TX02_TX10 Ch.0 transition data2/ Ch.1 transition data0 163 133 F7 E_TX03_TX11 Ch.0 transition data3/ Ch.1 transition data1 162 132 E7 E_TXEN0 Ch.0 transition data enable 166 136 D6 E_TXER0_TXEN1 Ch.0 transition data error detection/ Ch.1 transition data enable 161 131 D7

50 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Module Pin name Function Pin No LQFP-176 LQFP-144 BGA-192 RESET INITX External Reset Input pin. A reset is valid when INITX="L". 57 49 N5 Mode MD0 Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. 85 69 N12 MD1 Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. 84 68 N13 POWER VCC Power supply Pin 1 1 C1 VCC Power supply Pin 45 37 N1 VCC Power supply Pin 54 46 P4 VCC Power supply Pin 89 73 M14 VCC Power supply Pin 133 109 A13 USBVCC0 3.3V Power supply port for USB I/O 173 141 A4 USBVCC1 129 105 E14 ETHVCC Power supply pin for Ethernet I/O 156 126 A9 GND VSS GND Pin 27 25 J1 VSS GND Pin 44 36 M1 VSS GND Pin 53 45 P3 VSS GND Pin 88 72 N14 VSS GND Pin 109 93 F14 VSS GND Pin 132 108 B14 VSS GND Pin 157 127 A11 VSS GND Pin 176 144 B1 VSS GND Pin - - E1 VSS GND Pin - - G1 VSS GND Pin - - P7 VSS GND Pin - - P11 VSS GND Pin - - L14 VSS GND Pin - - A8 VSS GND Pin - - A5 VSS GND Pin - - N7 VSS GND Pin - - M7 VSS GND Pin - - L7 VSS GND Pin - - K7 VSS GND Pin - - J7 VSS GND Pin - - G7 VSS GND Pin - - H7 VSS GND Pin - - H8 VSS GND Pin - - G8

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 51 CONFIDENTIAL Module Pin name Function Pin No. LQFP-176 LQFP-144 BGA-192 CLOCK X0 Main clock (oscillation) input pin 86 70 P12 X0A Sub clock (oscillation) input pin 55 47 P5 X1 Main clock (oscillation) I/O pin 87 71 P13 X1A Sub clock (oscillation) I/O pin 56 48 P6 CROUT_0 Bulit-in high-speed CR-osc clock output port 127 103 D13 CROUT_1 152 122 E8 Analog POWER A VCC A/D converter analog power supply pin 106 90 J14 A VRH A/D converter analog reference voltage input pin 107 91 H14 Analog GND A VSS A/D converter GND pin 108 92 G14 C pin C Power stabilization capacity pin 52 44 P2

52 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With Standby mode control  When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA B  CMOS level hysteresis input  Pull-up resistor : Approximately 50 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control Pull-up resistor Digital input

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 53 CONFIDENTIAL Type Circuit Remarks C N-ch  Open drain output  CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5 MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -4 mA, IOL = 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Control pin Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

54 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

E P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -4 mA, IOL = 4 mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off  +B input is available F P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With input control  Analog input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -4 mA, IOL = 4 mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off  +B input is available Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 55 CONFIDENTIAL Type Circuit Remarks G P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -12 mA, IOL = 12 mA  +B input is available H EBP EBM Differential It is possible to select the USB I/O / GPIO function. When the USB I/O is selected.  Full-speed, Low-speed control When the GPIO is selected.  CMOS level output  CMOS level hysteresis input  With standby mode control  IOH = -20.5 mA, IOL = 18.5 mA Digital output Digital output Pull-up resistor control Digital input Standby mode control GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP (+) output USB Full-speed/Low-speed control UDP (+) input Differential input USB/GPIO select UDM (-) input UDM (-) output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control

56 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

I P-ch N-ch R  CMOS level output  CMOS level hysteresis input  5 V tolerant  With standby mode control  IOH = -4 mA, IOL = 4 mA  Available to control of PZR registers.  When this pin is used as an I2C pin, the digital output P- ch transistor is always off J CMOS level hysteresis input Digital output Digital output Digital input Standby mode control Mode input

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 57 CONFIDENTIAL Type Circuit Remarks K P-chP-ch N-ch R  CMOS level output  TTL level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -4 mA, IOL = 4 mA L P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50 kΩ  IOH = -8 mA, IOL = 8 mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off  +B input is available Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control

58 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equip ment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exce ed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconducto r devices to power supply and input/output functions. (1) Preventing Over-V oltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance ca n cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 59 CONFIDENTIAL  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for hea t resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through -holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch re sults in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions.

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 Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use o f an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to grou nd through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 61 CONFIDENTIAL 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to c hemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

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 Handling Devices  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be c onnected as a bypass capacitor between each Power supply pins and GND pins, between A VCC pin and A VSS pin near this device.  Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board.  Using an external clock When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1,X1A pin should be kept open.  Handling when using Multi-function serial pin as I2C pin If it is using multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I 2C bus system with power OFF.  Example of Using an External Clock Device X0(X0A) X1(X1A) Open

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 63 CONFIDENTIAL  C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series.  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.  Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect A VCC =VCC and A VSS = VSS. Turning on : VCC → USBVCC0 VCC → USBVCC1 VCC → ETHVCC VCC → A VCC → A VRH Turning off : USBVCC0 → VCC USBVCC1 → VCC ETHVCC → VCC A VRH → A VCC → VCC Device C VSS Cs GND

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 Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.  Base Timer In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input (TGIN). Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to be "0b00" in order to disable trigger input.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 65 CONFIDENTIAL  Block Diagram AHB-APB Bridge : APB2 (Max 72MHz) AHB-APB Bridge : APB1 (Max 72MHz) AHB-APB Bridge: APB0(Max 72MHz) Flash I/F Cortex-M3 Core 144MHz(Max) Clock Reset Generator Dual-Timer Watchdog Timer (Hardware) DMAC 8ch. On-chip Flash 512Kbyte/ 768Kbyte/ 1024Kbyte Multi-function Timer ×3 Multi-Function Serial I/F 8ch. (with FIFO ch.4 to ch.7) HW flow control(ch.4) 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 3ch. 16-bit PPG 3ch. Watch Counter Unit 0 GPIO CSV LVD External Interrupt Controller 32-pin + NMI Power On Reset TPIU ROM Table ETM SRAM0 32/48/64Kbyte SWJ-DP SRAM1 32/48/64Kbyte I D Sys MB9BFD16/D17/D18 Base Timer 16-bit 16ch./ 32-bit 8ch. NVIC Watchdog Timer (Software) Security 12-bit A/D Converter Unit 1 Unit 2 TRSTX,TCK, TDI,TMS TRACED[3:0], TRACECLK AVCC, AVSS,AVRH AN[31:00] TIOA[15:00] TIOB[15:00] IC0[3:0] DTTI[2:0]X RTO0[5:0] FRCK[2:0] C TDO SCK[7:0] SIN[7:0] SOT[7:0] INT[31:00] NMIX INITX MODE-Ctrl IRQ-Monitor PIN-Function-Ctrl MD[1:0] Regulator QPRC 3ch. AIN[2:0] BIN[2:0] ZIN[2:0] LVD Ctrl CRC Accelerator IC1[3:0] ADTG[8:0] RTS4 CTS4 External Bus I/F MAD[24:00] MADATA[15:00] MCSX[7:0], MOEX,MWEX, MNALE, MNCLE, MNWEX, MNREX, MDQM[1:0] MALE MRDY MCLKOUT RTO1[5:0] USB 2.0 (Host/ Func) PHY UDP0,UDM0 USBVCC0 UHCONX0 USB-Ethernet Clk Ctrl PLL MPU Trace Buffer (16Kbyte) Ethernet- MAC1 IC2[3:0] RTO2[5:0] USB 2.0 (Host/ Func) PHY UDP1,UDM1 USBVCC1 UHCONX1 Ethernet- MAC0 SelectorMII/ RMII RMII CAN Prescaler TX1, RX1 TX0, RX0 CAN CAN E_TXx, E_RXx, E_MDx P0x, P1x, PFx X0A PLL CLK CR 100kHz Source Clock CROUT Main Osc Sub Osc CR 4MHzX1A Multi-layer AHB (Max 144MHz) AHB-AHB Bridge (Slave) AHB-AHB Bridge (Master) Note: The following items vary depending on the package. A) Number of external bus interface pin B) Number of 12-bit A/D converter channel

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 Memory Size See "Memory size" of "Product Lineup" to confirm the memory size.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 67 CONFIDENTIAL  Memory Map  Memory Map (1) Peripherals Area 0x41FF_FFFF 0x4006_9000 0x4006_7000 Ethernet-MAC1 0xFFFF_FFFF 0x4006_6000 Ethernet-Control-Reg. 0x4006_4000 Ethernet-MAC0 0xE010_0000 0x4006_3000 CAN ch.1 0x4006_2000 CAN ch.0 0xE000_0000 0x4006_1000 Reserved 0x4006_0000 DMAC 0x4005_0000 0x4004_0000 0x4003_F000 EXT-bus I/F 0x7000_0000 0x4003_B000 0x6000_0000 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS 0x4400_0000 0x4003_7000 CAN Prescaler 0x4003_6000 USB-Ethernet Clk Ctrl 0x4200_0000 0x4003_5000 LVD Ctrl 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_8000 0x2008_0000 0x4002_7000 A/DC 0x2000_0000 SRAM1 0x4002_6000 QPRC 0x1FFF_0000 SRAM0 0x4002_5000 Base Timer 0x4002_4000 PPG 0x0010_2000 0x4002_3000 Reserved 0x0010_0000 Security/CR Trim 0x4002_2000 MFT unit2 0x4002_1000 MFT unit1 0x4002_0000 MFT unit0 0x4001_6000 0x4001_5000 Dual Timer 0x0000_0000 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved 32Mbyte Bit band alias Reserved Reserved Cortex-M3 Private Peripherals Reserved USB ch.1 USB ch.0 Reserved Reserved Reserved External Device Area Reserved Reserved Reserved See the next page “●Memory Map (2)” for the memory size details. 32Mbyte Bit band alias Reserved Reserved On-chip Flash Peripherals

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 Memory Map(2) MB9BFD18S/T MB9BFD17S/T MB9BFD16S/T 0x2008_0000 0x2008_0000 0x2008_0000 0x2001_0000 0x2001_C000 0x2000_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_8000 0x1FFF_4000 0x1FFF_0000 0x0010_2000 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0010_0000 Security 0x000C_0000 0x0008_0000 0x0000_0000 SA4-7(8KBx4) 0x0000_0000 SA4-7(8KBx4) 0x0000_0000 SA4-7(8KBx4) Flash 768Kbyte Flash 512Kbyte SA8-9(48KBx2) SA10-23(64KBx14) SA8-9(48KBx2) SA8-9(48KBx2) SA10-19(64KBx10) SA10-15(64KBx6) Reserved Reserved SRAM1 48Kbyte Reserved SRAM1 32Kbyte Reserved Reserved SRAM0 32KbyteSRAM0 48Kbyte Reserved Reserved SRAM1 64Kbyte SRAM0 64Kbyte Reserved Flash 1Mbyte *: See "MB9BD10T/610T/510T/410T/310T/210T/110T Series Flash programming Manual" for sector structure of Flash.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 69 CONFIDENTIAL  Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4002_3FFF Multi-function timer unit2 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter (QPRC) 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_5FFF Low-V oltage Detector 0x4003_6000 0x4003_6FFF USB-Ethernet clock generator 0x4003_7000 0x4003_7FFF CAN Prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External bus I/F 0x4004_0000 0x4004_FFFF AHB USB ch.0 0x4005_0000 0x4005_FFFF USB ch.1 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF Reserved 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x4006_5FFF Ethernet-MAC ch.0 0x4006_6000 0x4006_6FFF Ethernet-MAC setting Register 0x4006_7000 0x4006_8FFF Ethernet-MAC ch.1 0x4006_9000 0x41FF_FFFF Reserved

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 Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi -Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 71 CONFIDENTIAL  List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or sleep mode state Timer mode or sleep mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Main crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Main crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" C INITX input pin Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E JTAG selected Hi-Z Pull-up/ Input enabled Pull-up/ Input enabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z/ Internal input fixed at "0" F Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output External interrupt enabled selected Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0"

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unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 G Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" H External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" I GPIO selected, resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" J NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0"

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 73 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or sleep mode state Timer mode or sleep mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 K Analog input selected Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled GPIO selected, or resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" L External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Analog input selected Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled GPIO selected, or resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" M GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

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unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 N GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" O GPIO selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" USB I/O pin Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z at transmission/ Input enabled/ Internal input fixed at "0" at reception Hi-Z at transmission/ Input enabled/ Internal input fixed at "0" at reception P Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Input enabled Q Ethernet input or output selected*3 Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" R Ethernet input or output pin selected*3 Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state External interrupt enabled selected GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" *1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode. *2: Oscillation is stopped at STOP mode. *3: When selected by EPFR14.E_SPLC register.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 75 CONFIDENTIAL  Electrical Characteristics 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1,*2 Vcc Vss - 0.5 Vss + 6.5 V Power supply voltage (for USB ch.0)*1,*3 USBVcc0 Vss - 0.5 Vss + 6.5 V Power supply voltage (for USB ch.1)*1,*3 USBVcc1 Vss - 0.5 Vss + 6.5 V Power supply voltage (for Ethernet)*1,*4 ETHVcc Vss - 0.5 Vss + 6.5 V Analog power supply voltage*1,*5 A Vcc Vss - 0.5 Vss + 6.5 V Analog reference voltage*1,*5 A VRH Vss - 0.5 Vss + 6.5 V Input voltage*1 VI Vss - 0.5 Vcc + 0.5 (≤ 6.5V) V Except for USB pin and Ethernet-MAC pin Vss - 0.5 USBVcc0 + 0.5 (≤ 6.5V) V USB ch.0 pin Vss - 0.5 USBVcc1 + 0.5 (≤ 6.5V) V USB ch.1 pin Vss - 0.5 ETHVcc + 0.5 (≤ 6.5V) V Ethernet-MAC pin Vss - 0.5 Vss + 6.5 V 5V tolerant Analog pin input voltage*1 VIA Vss - 0.5 A Vcc + 0.5 (≤ 6.5V) V Output voltage*1 VO Vss - 0.5 Vcc + 0.5 (≤ 6.5V) V Clamp maximum current ICLAMP -2 +2 mA *9 Clamp total maximum current Σ[ICLAMP] +20 mA *9 "L" level maximum output current*6 IOL - 10 mA 4 mA type 20 mA 8 mA type 20 mA 12 mA type 39 mA P80,P81,P82,P83 "L" level average output current*7 IOLA V - 4 mA 4 mA type 8 mA 8 mA type 12 mA 12 mA type 18.5 mA P80,P81,P82,P83 "L" level total maximum output current ∑IOL - 100 mA "L" level total average output current*8 ∑IOLA V - 50 mA "H" level maximum output current*6 IOH - - 10 mA 4 mA type - 20 mA 8 mA type - 20 mA 12 mA type - 39 mA P80,P81,P82,P83 "H" level average output current*7 IOHA V - - 4 mA 4 mA type - 8 mA 8 mA type - 12 mA 12 mA type - 20.5 mA P80,P81,P82,P83 "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current*8 ∑IOHA V - - 50 mA Power consumption PD - 1000 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that Vss = A Vss = 0.0 V. *2: Vcc must not drop below Vss - 0.5 V. *3: USBVcc0 and USBVcc1 must not drop below Vss - 0.5 V. *4: ETHVcc must not drop below Vss - 0.5 V. *5: Ensure that the voltage does not to exceed Vcc + 0.5 V , for example, when the power is turned on.

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*6: The maximum output current is the peak value for a single pin. *7: The average output is the average current for a single pin over a period of 100 ms. *8: The total average output current is the average current for all pins over a period of 100 ms. *9:  See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.  Use within recommended operating conditions.  Use at DC voltage (current) the +B input.  The +B signal should always be applied a limiting resistance placed between the +B signal and the device.  The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods.  Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.  Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result.  The following is a recommended circuit example (I/O equivalent circuit). <WARNING> Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. R Protection Diode P-ch VCC VCC Limiting resistor N-ch AVCC Analog input Digital input Digital output +B input (0V to 16V)

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 77 CONFIDENTIAL 2. Recommended Operating Conditions (Vss = A Vss = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage Vcc - 2.7*8 5.5 V Power supply voltage (3V power supply) for USB ch.0 USBVcc0 - 3.0 3.6 (≤ Vcc) V 2.7 5.5 (≤ Vcc) *2 Power supply voltage (3V power supply) for USB ch.1 USBVcc1 - 3.0 3.6 (≤ Vcc) V 2.7 5.5 (≤ Vcc) *4 Power supply voltage for Ethernet ETHVcc - 3.0 3.6 (≤ Vcc) V 4.5 5.5 (≤ Vcc) *5 2.7 5.5 (≤ Vcc) *6 Analog power supply voltage A Vcc - 2.7 5.5 V A Vcc = Vcc Analog reference voltage A VRH - 2.7 A Vcc V Smoothing capacitor CS - 1 10 μF for built-in regulator *7 Operating temperature FPT-144P-M08, FPT-176P-M07, BGA-192P-M06 Ta When mounted on four-layer PCB - 40 + 85 °C *1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80). *3: When P83/UDP1 and P82/UDM1 pin are used as USB (UDP1, UDM1). *4: When P83/UDP1 and P82/UDM1 pin are used as GPIO (P83, P82). *5: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as Ethernet-MAC pin. *6: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as function pins other than Ethernet-MAC pin. *7: See "●C pin" in "Handling Devices" for the connection of the smoothing capacitor. *8 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

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 Ethernet-MAC pins Pin Name Ethernet-MAC function Except for Ethernet-MAC function Power Supply type P62/E_PPS0_PPS1/SCK5_0/ADTG_3 E_PPS0_PPS1* P62 /SCK5_0/ADTG_3 Vcc PC0/E_RXER0_RXDV1 E_RXER0_RXDV1 PC0 ETHVcc PC1/E_RX03_RX11 E_RX03_RX11 PC1 PC2/E_RX02_RX10 E_RX02_RX10 PC2 PC3/E_RX01/TIOA06_1 E_RX01 PC3/TIOA06_1 PC4/E_RX00/TIOA08_2 E_RX00 PC4/TIOA08_2 PC5/E_RXDV0/TIOA10_2 E_RXDV0 PC5/TIOA10_2 PC6/E_MDIO0/TIOA14_0 E_MDIO0 PC6/TIOA14_0 PC7/E_MDC0/CROUT_1 E_MDC0 PC7/CROUT_1 PC8/E_RXCK0_REFCK E_RXCK0_REFCK PC8 PC9/E_COL0 E_COL0 PC9 PCA/E_CRS0 E_CRS0 PCA PCB/E_COUT E_COUT PCB PCC/E_MDIO1 E_MDIO1 PCC PCD/E_TCK0_MDC1 E_TCK0_MDC1 PCD PCE/E_TXER0_TXEN1/RTS4_0/ TIOB06_1 E_TXER0_TXEN PCE/RTS4_0/TIOB06_1 PCF/E_TX03_TX11/CTS4_0/TIOB08_2 E_TX03_TX11 PCF/CTS4_0/TIOB08_2 PD0/E_TX02_TX10/SCK4_0/TIOB10_2/ INT30_1 E_TX02_TX10 PD0/SCK4_0/TIOB10_2/ INT30_1 PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1 E_TX01 PD1/SOT4_0/TIOB14_0/ INT31_1 PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2 E_TX00 PD2/TIOA03_2/INT00_2 PD3/E_TXEN0/TIOB03_2 E_TXEN0 PD3/TIOB03_2 *: It is used to confirm the PTP counter cycle in Ethernet-MAC by wave forms.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 79 CONFIDENTIAL 3. DC Characteristics (1) Current Rating (Vcc = A Vcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7V to 5.5V , Vss = A Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 RUN mode current Icc VCC PLL RUN mode CPU : 144 MHz, Peripheral : 72 MHz, Flash 2 Wait, TraceBuffer : ON, FRWTR.RWT = 10, FSYNDN.SD = 000, FBFCR.BE = 1 100 180 mA *1, *5 CPU : 72 MHz, Peripheral : 72 MHz, Flash 0 Wait, TraceBuffer : OFF, FRWTR.RWT = 00, FSYNDN.SD = 000, FBFCR.BE = 0 65 135 mA *1, *5 High-speed CR RUN mode CPU/ Peripheral : 4 MHz*2, Flash 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 6 57.8 mA *1 Sub RUN mode CPU/ Peripheral : 32 kHz, Flash 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 1.3 51.7 mA *1, *6 Low-speed CR RUN mode CPU/ Peripheral : 100 kHz, Flash 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 1.3 51.7 mA *1 SLEEP mode current Iccs PLL SLEEP mode Peripheral : 72 MHz 30 89 mA *1, *5 High-speed CR SLEEP mode Peripheral : 4 MHz*2 4.5 55.9 mA *1 Sub SLEEP mode Peripheral : 32 kHz 1.2 51.6 mA *1, *6 Low-speed CR SLEEP mode Peripheral : 100 kHz 1.2 51.6 mA *1 *1: When all ports are fixed, Ethernet is stopped. *2: When setting it to 4MHz by trimming. *3: Ta=+25°C, VCC=5.5 V *4: Ta=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

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(Vcc = A Vcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7V to 5.5V , Vss = A Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*2 TIMER mode current ICCT VCC Main TIMER mode Ta = + 25°C, When LVD is off 4 10 mA *1, *3 Ta = + 85°C, When LVD is off - 55 mA *1, *3 Sub TIMER mode Ta = + 25°C, When LVD is off 1.1 5 mA *1, *4 Ta = + 85°C, When LVD is off - 50 mA *1, *4 STOP mode current ICCH STOP mode Ta = + 25°C, When LVD is off 1 5 mA *1 Ta = + 85°C, When LVD is off - 50 mA *1 *1: When all ports are fixed. *2: VCC=5.5 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

• Low-Voltage Detection Current (VCC = 2.7V to 5.5V , VSS = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for interrupt 4 7 μA At not detect
• Flash Memory Current (VCC = 2.7V to 5.5V , VSS = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 12 14 mA
• A/D Converter Current (VCC = AVCC = 2.7V to 5.5V , VSS = AVSS = A VRL = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD A VCC At 1unit operation 0.57 0.72 mA At stop 0.06 35 μA Reference power supply current ICCA VRH A VRH At 1unit operation A VRH=5.5V 1.1 1.96 mA At stop 0.06 4 μA

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 81 CONFIDENTIAL (2) Pin Characteristics (Vcc = USBVcc0 = USBVcc1 = ETHVcc = A Vcc = 2.7V to 5.5V , Vss = A Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max "H" level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 Vcc (ETHVcc) × 0.8 Vcc (ETHVcc) + 0.3 V *1 5V tolerant input pin - Vcc × 0.8 - Vss + 5.5 V TTL Schmitt input pin - 2.0 - ETHVcc + 0.3 V "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - Vss - 0.3 - Vcc (ETHVcc) × 0.2 V *1 5V tolerant input pin - Vss - 0.3 - Vcc × 0.2 V TTL Schmitt input pin "H" level output voltage VOH 4mA type Vcc (ETHVcc) ≥ 4.5 V, IOH = - 4 mA Vcc (ETHVcc) - 0.5 - Vcc (ETHVcc) V *1 Vcc (ETHVcc) < 4.5 V, IOH = - 2 mA 8mA type ETHVcc ≥ 4.5 V, IOH = - 8 mA ETHVcc - 0.5 - ETHVcc V *1 ETHVcc < 4.5 V, IOH = - 4 mA 12mA type Vcc ≥ 4.5 V, IOH = - 12 mA Vcc - 0.5 - Vcc V Vcc < 4.5 V, IOH = - 8 mA P80, P81, P82, P83 USBVcc ≥ 4.5 V, IOH = - 20.5 mA USBVcc - 0.4 - USBVcc V *2 USBVcc < 4.5 V, IOH = - 13.0 mA

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"L" level output voltage VOL 4mA type Vcc (ETHVcc) ≥ 4.5 V, IOL = 4 mA Vss - 0.4 V *1 Vcc (ETHVcc) < 4.5 V, IOL = 2 mA 8mA type ETHVcc ≥ 4.5 V, IOL = 8 mA Vss - 0.4 V *1 ETHVcc < 4.5 V, IOL = 4 mA 12mA type Vcc ≥ 4.5 V, IOL = 12 mA Vss - 0.4 V Vcc < 4.5 V, IOL = 8 mA P80, P81, P82, P83 USBVcc ≥ 4.5 V, IOL = 18.5 mA Vss - 0.4 V *2 USBVcc < 4.5 V, IOL = 10.5 mA Input leak current IIL - - - 5 - + 5 μA Pull-up resistance value RPU Pull-up pin Vcc ≥ 4.5 V 25 50 100 kΩ Vcc < 4.5 V 30 80 200 Input capacitance CIN Other than VCC, USBVCC0, USBVCC1, ETHVCC, VSS, A VCC, A VSS, A VRH - - 5 15 pF *1: The power supply type varies depending on the pin position. For example, power supply A (power supply B) shows that either of power supply A or power supply B becomes a power supply voltage. *2: USBVcc0 and USBVcc1 are described as USBVcc.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 83 CONFIDENTIAL 4. AC Characteristics (1) Main Clock Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency FCH X0, Vcc ≥ 4.5V 4 50 MHz When crystal oscillator is connected Vcc < 4.5V 4 20 Vcc ≥ 4.5V 4 50 MHz When using external clock Vcc < 4.5V 4 20 Input clock cycle tCYLH Vcc ≥ 4.5V 20 250 ns When using external clock Vcc < 4.5V 50 250 Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rise time and fall time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency FCM - - - 144 MHz Master clock FCC - - - 144 MHz Base clock (HCLK/FCLK) FCP0 - - - 72 MHz APB0 bus clock*2 FCP1 - - - 72 MHz APB1 bus clock*2 FCP2 - - - 72 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 6.94 - ns Base clock (HCLK/FCLK) tCYCP0 - - 13.8 - ns APB0 bus clock*2 tCYCP1 - - 13.8 - ns APB1 bus clock*2 tCYCP2 - - 13.8 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.

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(2) Sub Clock Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency 1/tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock (3) Internal CR Oscillation Characteristics  High-speed Internal CR (Vcc = 2.7V to 5.5V , Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRH Ta = + 25°C 3.96 4 4.04 MHz When trimming* Ta = 0°C to + 70°C 3.84 4 4.16 Ta = - 40°C to + 85°C 3.8 4 4.2 Ta = - 40°C to + 85°C 3 4 5 When not trimming Frequency stability time tCRWT - - - 90 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR. clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.  Low-speed Internal CR (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRL - 50 100 150 kHz X0A

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 85 CONFIDENTIAL (4-1) Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input of PLL) (Vcc = 2.7V to 5.5V , Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency FPLLI 4 - 16 MHz PLL multiple rate - 13 - 75 multiple PLL macro oscillation clock frequency FPLLO 200 - 300 MHz Main PLL clock frequency*2 FCLKPLL - - 144 MHz USB/Ethernet clock frequency*3 FCLKSPLL - - 50 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". *3: For more information about USB/Ethernet clock, see "CHAPTER 2-3: USB/Ethernet Clock Generation" in "FM3 Family PERIPHERAL MANUAL Communication Macro Part". (4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR) (Vcc = 2.7V to 5.5V , Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiple rate - 50 - 71 multiple PLL macro oscillation clock frequency FPLLO 190 - 300 MHz Main PLL clock frequency*2 FCLKPLL - - 144 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed. Main clock (CLKMO) K divider PLL input clock USB/Ethernet PLL M divider USB/Ethernet clock N divider USB/Ethernet PLL connection PLL macro oscillation clock K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection High-speed CR clock (CLKHC) Main clock (CLKMO)

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(5) Reset Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns (6) Power-on Reset Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Max Power supply rising time Tr VCC 0 - ms Power supply shut down time Toff 1 - ms Time until releasing Power-on reset Tprt 0.46 0.76 ms 0.2V VDH_minimum VCC_minimum Tprt Internal RST VCC CPU Operation start RST Active Release Tr 0.2V 0.2V Toff Glossary  VCC_minimum : Minimum VCC of recommended operating conditions  VDH_minimum : Minimum release voltage of Low-Voltage detection reset. See "7. Low-Voltage Detection Characteristics"

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 87 CONFIDENTIAL (7) External Bus Timing  External bus clock output characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT*1 Vcc ≥ 4.5 V - 50*2 MHz Vcc < 4.5 V - 32*3 MHz *1: External bus clock (MCLKOUT) is divided clock of HCLK. For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL". When external bus clock is not output, this characteristic does not give any effect on external bus operati on. *2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more than 4. *3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more than 4.  External bus signal input/output characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH Input signal Output signal MCLKOUT

88 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 Separate Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX Vcc ≥ 4.5 V MCLK×n-3 - ns Vcc < 4.5 V MCSX ↓ → Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] Vcc ≥ 4.5 V -9 +9 ns Vcc < 4.5 V -12 +12 MOEX ↑ → Address hold time tOEH - AX MOEX, MAD[24:0] Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 MCSX ↓ → MOEX ↓ delay time tCSL - OEL MOEX, MCSX[7:0] Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5 V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX, MDQM[1:0] Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5 V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX, MADA TA[15:0] Vcc ≥ 4.5 V 20 - ns Vcc < 4.5 V 38 - MOEX ↑ → Data hold time tDH - OE MOEX, MADA TA[15:0] Vcc ≥ 4.5 V 0 - ns Vcc < 4.5 V MWEX Min pulse width tWEW MWEX Vcc ≥ 4.5 V MCLK×n-3 - ns Vcc < 4.5 V MWEX ↑ → Address output delay time tWEH - AX MWEX, MAD[24:0] Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX, MCSX[7:0] Vcc ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5 V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL-WDQML MCSX, MDQM[1:0] Vcc ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5 V MCLK×n-12 MCLK×n+12 MCSX ↓ → Data output time tCSL - DV MCSX, MADA TA[15:0] Vcc ≥ 4.5 V MCLK-9 MCLK+9 ns Vcc < 4.5 V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX, MADA TA[15:0] Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 89 CONFIDENTIAL Invalid Address tCSL-OEL tCSL-AV RD Address WD tDH-OEtDS-OE tWEH-DX tOEW tOEH-AX tOEH-CSH tWEW tCYCLE tCSL-WEL tCSL-AV tWEH-CSH tWEH-AX tCSL-WDQMLtCSL-RDQML tCSL-DV MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

90 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 Separate Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 MCSX delay time tCSL MCLK, MCSX[7:0] Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 tCSH Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 MOEX delay time tREL MCLK, MOEX Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 tREH Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 Data set up → MCLK ↑ time tDS MCLK, MADA TA[15:0] Vcc ≥ 4.5 V 19 - ns Vcc < 4.5 V 37 MCLK ↑ → Data hold time tDH MCLK, MADA TA[15:0] Vcc ≥ 4.5 V 0 - ns Vcc < 4.5 V MWEX delay time tWEL MCLK, MWEX Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 tWEH Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 tDQMH Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 MCLK ↑ → Data output time tOD MCLK, MADA TA[15:0] Vcc ≥ 4.5 V MCLK+1 MCLK+18 ns Vcc < 4.5 V MCLK+24 MCLK ↑ → Data hold time tOD MCLK, MADA TA[15:0] Vcc ≥ 4.5 V 1 18 ns Vcc < 4.5 V 24 Note: When the external load capacitance = 30 pF. Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 91 CONFIDENTIAL  Multiplexed Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADA TA[15:0] Vcc ≥ 4.5 V 0 10 ns Vcc < 4.5 V 20 Multiplexed address hold time tCHMADH Vcc ≥ 4.5 V MCLK×n+0 MCLK×n+10 ns Vcc < 4.5 V MCLK×n+0 MCLK×n+20 Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16) MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

92 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 Multiplexed Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 ns tCHAH Vcc ≥ 4.5 V 1 9 ns Vcc < 4.5 V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK, MADA TA[15:0] Vcc ≥ 4.5 V 1 tOD ns Vcc < 4.5 V MCLK ↑ → Multiplexed Data output time tCHMADX Vcc ≥ 4.5 V 1 tOD ns Vcc < 4.5 V Note: When the external load capacitance = 30 pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 93 CONFIDENTIAL  NAND Flash Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MNREX Min pulse width tNREW MNREX Vcc ≥ 4.5 V MCLK×n-3 - ns Vcc < 4.5 V Data setup → MNREX↑time tDS – NRE MNREX, MADA TA[15:0] Vcc ≥ 4.5 V 20 - ns Vcc < 4.5 V 38 - MNREX↑→ Data hold time tDH – NRE MNREX, MADA TA[15:0] Vcc ≥ 4.5 V 0 - ns Vcc < 4.5 V MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5 V MCLK×m-12 MCLK×m+12 MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5 V MCLK×m-12 MCLK×m+12 MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5 V MCLK×m-12 MCLK×m+12 MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 MNWEX Min pulse width tNWEW MNWEX Vcc ≥ 4.5 V MCLK×n-3 - ns Vcc < 4.5 V MNWEX↓→ Data output time tNWEL – DV MNWEX, MADA TA[15:0] Vcc ≥ 4.5 V -9 +9 ns Vcc < 4.5 V -12 +12 MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADA TA[15:0] Vcc ≥ 4.5 V 0 MCLK×m+9 ns Vcc < 4.5 V MCLK×m+12 Note: When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16) NAND Flash Read MCLK MNREX MADATA[15:0] Read

94 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

MADATA[15:0] MNWEX Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 95 CONFIDENTIAL  External Ready Input Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MCLK ↑ MRDY input setup time tRDYI MCLK, MRDY Vcc ≥ 4.5 V 19 - ns Vcc < 4.5 V 37 When RDY is input

• · · Over 2cycles tRDYI When RDY is released 2 cycles tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

96 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

(8) Base Timer Input Timing  Timer input timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns tTIWH VIHS VIHS VILS VILS tTIWL  Trigger input timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns tTRGH VIHS VIHS VILS VILS tTRGL Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which Base Timer is connected to, see "Block Diagram" in this data sheet. ECK TIN TGIN

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 97 CONFIDENTIAL (9) CSIO/UART Timing  CSIO (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30 pF.

98 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 99 CONFIDENTIAL  CSIO (SPI = 0, SCINV = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30 pF.

100 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 101 CONFIDENTIAL  CSIO (SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Vcc < 4.5 V Vcc ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30 pF.

102 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

*: Changes when writing to TDR register SCK SOT SIN SCK SOT SIN

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 103 CONFIDENTIAL  CSIO (SPI = 1, SCINV = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Vcc < 4.5 V Vcc ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30 pF.

104 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 UART external clock input (EXT = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock "L" pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock "H" pulse width tSHSL tCYCP + 10 - ns SCK fall time tF - 5 ns SCK rise time tR - 5 ns tSHSL VIL VIL VIL VIH VIH VIH tR tFtSLSH SCK SOT SIN SCK SOT SIN SCK

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 105 CONFIDENTIAL (10) External Input Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP* - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP* - ns Wave form generator INTxx, NMIX Except Timer mode, Stop mode 2tCYCP + 100* - ns External interrupt NMI Timer mode, Stop mode 500 - ns *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "Block Diagram" in this data sheet.

106 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

(11) Quadrature Position/Revolution Counter timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Min Max AIN pin "H" width tAHL - 2tCYCP* - ns AIN pin "L" width tALL - BIN pin "H" width tBHL - BIN pin "L" width tBLL - BIN rise time from AIN pin "H" level tAUBU PC_Mode2 or PC_Mode3 AIN fall time from BIN pin "H" level tBUAD PC_Mode2 or PC_Mode3 BIN fall time from AIN pin "L" level tADBD PC_Mode2 or PC_Mode3 AIN rise time from BIN pin "L" level tBDAU PC_Mode2 or PC_Mode3 AIN rise time from BIN pin "H" level tBUAU PC_Mode2 or PC_Mode3 BIN fall time from AIN pin "H" level tAUBD PC_Mode2 or PC_Mode3 AIN fall time from BIN pin "L" level tBDAD PC_Mode2 or PC_Mode3 BIN rise time from AIN pin "L" level tADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC="0" ZIN pin "L" width tZLL QCR:CGSC="0" AIN/BIN rise and fall time from determined ZIN level tZABE QCR:CGSC="1" Determined ZIN level from AIN/BIN rise and fall time tABEZ QCR:CGSC="1" *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "Block Diagram" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 107 CONFIDENTIAL BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN

108 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

(12) I2C Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCLclock "L" width tLOW 4.7 - 1.3 - μs SCLclock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDA T 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDA T 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP

8 MHz ≤

tCYCP ≤ 40 MHz 2 tCYCP*4 - 2 tCYCP*4 - ns *5

40 MHz <

tCYCP ≤ 60 MHz 3 tCYCP*4 - 3 tCYCP*4 - ns *5

60 MHz <

tCYCP ≤ 72 MHz 4 tCYCP*4 - 4 tCYCP*4 - ns *5 *1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDA T must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDA T ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see "Block Diagram" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. *5: The number of steps of the noise filter can be changed with register settings. Change the number of the noise filter steps according to APB2 bus clock frequency. SDA SCL

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 109 CONFIDENTIAL (13) ETM Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] Vcc ≥ 4.5 V 2 9 ns Vcc < 4.5 V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK Vcc ≥ 4.5 V - 50 MHz Vcc < 4.5 V - 32 MHz TRACECLK cycle time tTRACE Vcc ≥ 4.5 V 20 - ns Vcc < 4.5 V 31.25 - ns Note: When the external load capacitance = 30 pF. HCLK TRACECLK TRACED[3:0]

110 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

(14) JTAG Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI Vcc ≥ 4.5 V 15 - ns Vcc < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI Vcc ≥ 4.5 V 15 - ns Vcc < 4.5 V TDO delay time tJTAGD TCK, TDO Vcc ≥ 4.5 V - 25 ns Vcc < 4.5 V - 45 Note: When the external load capacitance = 30 pF. TCK TMS/TDI TDO

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 111 CONFIDENTIAL (15) Ethernet-MAC Timing  RMII transmission (100Mbps/10Mbps) (ETHVcc = 3.0V to 3.6V , 4.5V to 5.5V*1) (Vss = 0V , Ta = - 40°C to + 85°C, CL=25pF) Parameter Symbol Pin name Conditions Value Unit Min Max Reference Clock Cycle time*2 tREFCYC E_RXCK0_REFCK 20 ns (typical) - - ns Reference Clock High pulse width duty tREFCYCH E_RXCK0_REFCK tREFCYCH / tREFCYC 35 65 % Reference Clock Low pulse width duty tREFCYCL E_RXCK0_REFCK tREFCYCL / tREFCYC 35 65 % REFCK ↑ → Transmitted data Delay time (ch.0) tRMIITX E_TX01, E_TX00, E_TXEN0 - - 12 ns REFCK ↑ → Transmitted data Delay time (ch.1) E_TX03_TX11, E_TX02_TX10, E_TXER0_TXEN1 *1: When ETHV=4.5 V to 5.5 V , it is recommended to add a series resistor at the output pin to suppress the output current. *2: The reference clock is fixed to 50MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications. E_RXCK0_REFCK E_TX03_TX11 E_TX02_TX10 E_TX01 E_TX00 E_TXEN0 E_TXER0_TXEN1 tREFCYC tREFCYCH tREFCYCL tRMIITX VOH VOL VIHSVIHS VILS

112 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

 RMII receiving (100Mbps/10Mbps) (ETHVcc = 3.0V to 3.6V , 4.5V to 5.5V) (Vss = 0V , Ta = - 40°C to + 85°C, CL=25pF) Parameter Symbol Pin name Conditions Value Unit Min Max Reference Clock Cycle time* tREFCYC E_RXCK0_REFCK 20 ns (typical) - - ns Reference Clock High pulse width duty tREFCYCH E_RXCK0_REFCK tREFCYCH / tREFCYC 35 65 % Reference Clock Low pulse width duty tREFCYCL E_RXCK0_REFCK tREFCYCL / tREFCYC 35 65 % Received data → REFCK↑ Setup time(ch.0) tRMIIRXS E_RX01, E_RX00, E_RXDV0 - 4 - ns Received data → REFCK↑ Setup time(ch.1) E_RX03_RX11, E_RX02_RX10, E_RXER0_RXDV1 REFCK ↑ → Received data Hold time(ch.0) tRMIIRXH E_RX01, E_RX00, E_RXDV0 - 2 - ns REFCK ↑ → Received data Hold time (ch.1) E_RX03_RX11, E_RX02_RX10, E_RXER0_RXDV1 *: The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications. E_RXCK0_REFCK E_RX03_RX11 E_RX02_RX10 E_RX01 E_RX00 E_RXDV0 E_RXER0_RXDV1 tREFCYC tREFCYCH tREFCYCL tRMIIRXS tRMIIRXH VIHS VIHS VIHS VIHS VILS VILS VILS

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 113 CONFIDENTIAL  Management Interface (ETHVcc = 3.0V to 3.6V , 4.5V to 5.5V) (Vss = 0V , Ta = - 40°C to + 85°C, CL=25pF) Parameter Symbol Pin name Conditions Value Unit Min Max Management Clock Cycle time* (ch.0) tMDCYC E_MDC0 - 400 - ns Management Clock Cycle time* (ch.1) E_TCK0_MDC1 Management Clock High pulse width duty (ch.0) tMDCYCH E_MDC0 tMDCYCH / tMDCYC 45 55 % Management Clock High pulse width duty (ch.1) E_TCK0_MDC1 Management Clock Low pulse width duty (ch.0) tMDCYCL E_MDC0 tMDCYCL / tMDCYC 45 55 % Management Clock Low pulse width duty (ch.1) E_TCK0_MDC1 MDC ↓ → MDIO Delay time (ch.0) tMDO E_MDIO0 - - 60 ns MDC ↓ → MDIO Delay time (ch.1) E_MDIO1 MDIO → MDC ↑ Setup time (ch.0) tMDIS E_MDIO0 - 20 - ns MDIO → MDC ↑ Setup time (ch.1) E_MDIO1 MDC ↑ → MDIO Hold time (ch.0) tMDIH E_MDIO0 - 0 - ns MDC ↑ → MDIO Hold time (ch.1) E_MDIO1 *: The clock time should be set to a value greater than the minimum value by setting the Ether-MAC setting register. E_MDC0 (output) E_TCK0_MDC1 (output) tMDCYC tMDCYCH tMDCYCL tMDIS tMDIH E_MDIO0 (input) E_MDIO1 (input) tMDO E_MDIO0 (output) E_MDIO1 (output) tMDIS tMDIH tMDO VOL VOL VOHVOH VIHS VILS VIHS VILS VIHS VILS VIHS VILS VOH VOL VOH VOL

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 MII transmission (100Mbps/10Mbps) (ETHVcc = 3.0V to 3.6V , 4.5V to 5.5V*1) (Vss = 0V , Ta = - 40°C to + 85°C, CL=25pF) Parameter Symbol Pin name Conditions Value Unit Min Max Transmission Clock Cycle time*2 tTXCYC E_TCK0_MDC1

100 Mbps,

40 ns (typical) - - ns

10 Mbps,

400 ns (typical) - - ns Transmission Clock High pulse width duty tTXCYCH E_TCK0_MDC1 tTXCYCH / tTXCYC 35 65 % Transmission Clock Low pulse width duty tTXCYCL E_TCK0_MDC1 tTXCYCL / tTXCYC 35 65 % TXCK ↑ → Transmitted data Delay time tMIITX E_TX03_TX11, E_TX02_TX10, E_TX01, E_TX00, E_TXEN0, E_TXER0_TXEN1 - - 24 ns *1: When ETHV=4.5 V to 5.5 V , it is recommended to add a series resistor at the output pin to suppress the output current. *2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the PHY-device specifications. E_TCK0_MDC1 E_TX03_TX11 E_TX02_TX10 E_TX01 E_TX00 E_TXEN0 E_TXER0_TXEN1 tTXCYC tTXCYCH tTXCYCL tMIITX VOH VOL VIHS VIHS VILS

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 115 CONFIDENTIAL  MII receiving (100Mbps/10Mbps) (ETHVcc = 3.0V to 3.6V , 4.5V to 5.5V) (Vss = 0V , Ta = - 40°C to + 85°C, CL=25pF) Parameter Symbol Pin name Conditions Value Unit Min Max Receiving Clock Cycle time* tRXCYC E_RXCK0_REFCK 40 ns (typical) - - ns 400 ns (typical) - - ns Receiving Clock High pulse width duty tRXCYCH E_RXCK0_REFCK tRXCYCH / tRXCYC 35 65 % Receiving Clock Low pulse width duty tRXCYCL E_RXCK0_REFCK tRXCYCL / tRXCYC 35 65 % Received data → REFCK ↑ Setup time tMIIRXS E_RX03_RX11, E_RX02_RX10, E_RX01, E_RX00, E_RXDV0, E_RXER0_RXDV1 - 5 - ns REFCK ↑ → Received data Hold time tMIIRXH E_RX03_RX11, E_RX02_RX10, E_RX01, E_RX00, E_RXDV0, E_RXER0_RXDV1 - 2 - ns *: The receiving clock 100 Mbps is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the PHY-device specifications. E_RX03_RX11 E_RX02_RX10 E_RX01 E_RX00 E_RXDV0 E_RXER0_RXDV1 tRXCYC tRXCYCH tRXCYCL tMIIRXS tMIIRXH E_RXCK0_REFCK VIHSVIHS VIHS VILS VILS VIHS VILS

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1. 12-bit A/D Converter  Electrical characteristics for the A/D converter (Vcc = A Vcc = 2.7V to 5.5V , Vss = A Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 4.5 LSB A VRH = 2.7 V to 5.5 V Differential Nonlinearity - - - ± 2.5 LSB Zero transition voltage VZT ANxx - ± 15 mV Full-scale transition voltage VFST ANxx - A VRH ± 15 mV Conversion time - - 1.0*1 - - μs A Vcc ≥ 4.5 V Sampling time Ts - *2 - - ns A Vcc ≥ 4.5 V *2 - - A Vcc < 4.5 V Compare clock cycle*3 Tcck - 50 - 2000 ns State transition time to operation permission Tstt - - - 1.0 μs Analog input capacity CAIN - - - 12.9 pF Analog input resistance RAIN - - - 2 kΩ A Vcc ≥ 4.5 V 3.8 A Vcc < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - A VRH V Reference voltage - A VRH 2.7 - AVCC V *1: The Conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is the following. A Vcc ≥ 4.5 V , HCLK=120 MHz sampling time: 300 ns compare time: 700 ns A Vcc < 4.5 V, HCLK=120 MHz sampling time: 500 ns compare time: 700 ns Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: Compare time (Tc) is the value of (Equation 2).

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 117 CONFIDENTIAL (Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9 Ts : Sampling time RAIN : input resistance of A/D = 2 kΩ at 4.5 ≤ AVCC ≤ 5.5 input resistance of A/D = 3.8 kΩ at 2.7 ≤ AVCC < 4.5 CAIN : input capacity of A/D = 12.9 pF at 2.7 ≤ AVCC ≤ 5.5 Rext : Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc : Compare time Tcck : Compare clock cycle Rext RAIN CAIN Analog signal source ANxx Analog input pin Comparator

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 Definition of 12-bit A/D Converter Terms  Resolution : Analog variation that is recognized by an A/D converter.  Integral Nonlinearity : Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N : A/D converter digital output value. VZT : Voltage at which the digital output changes from 0x000 to 0x001. VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVss AVRH AVss AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 119 CONFIDENTIAL 6. USB characteristics The USB characteristics of ch.0 and those of ch.1 are the same. USBVcc0 and USBVcc1 are described as USBVcc below. (Vcc = 2.7V to 5.5V , USBVcc = 3.0V to 3.6V , Vss = 0V , Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input charact- eristics Input "H" level voltage VIH UDP0, UDM0 - 2.0 USBVcc + 0.3 V *1 Input "L" level voltage VIL - Vss - 0.3 0.8 V *1 Differential input sensitivity VDI - 0.2 - V *2 Different common mode range VCM - 0.8 2.5 V *2 Output charact- eristics Output "H" level voltage VOH External pull-down resistance= 15kΩ 2.8 3.6 V *3 Output "L" level voltage VOL External pull-up resistance= 1.5kΩ 0.0 0.3 V *3 Crossover voltage VCRS - 1.3 2.0 V *4 Rise time tFR Full-Speed 4 20 ns *5 Fall time tFF Full-Speed 4 20 ns *5 Rise/ fall time matching tFRFM Full-Speed 90 111.11 % *5 Output impedance ZDRV Full-Speed 28 44 Ω *6 Rise time tLR Low-Speed 75 300 ns *7 Fall time tLF Low-Speed 75 300 ns *7 Rise/ fall time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Minimum differential input sensitivity [V]

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*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to ground and 1.5 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V . *5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. VCRS specified range Rising time Falling time

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 121 CONFIDENTIAL *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30Ω (recommendation value 27 Ω)series resistor Rs. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. See Figure " Low-Speed Load (Compliance Load)" for conditions of external load. Mount it as external resistance. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Rising time Falling time

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 Low-Speed Load (Upstream Port Load) - Reference 1  Low-Speed Load (Downstream Port Load) - Reference 2  Low-Speed Load (Compliance Load) CL = 50pF to 150pF CL = 50pF to 150pF CL =200pF to 600pF CL =200pF to 600pF CL = 200pF to 450pF CL = 200pF to 450pF

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 123 CONFIDENTIAL 7. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.25 2.45 2.65 V When voltage drops Released voltage VDH - 2.30 2.50 2.70 V When voltage rises (2) Interrupt of Low-Voltage Detection (Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 0000 2.58 2.8 3.02 V When voltage drops Released voltage VDH 2.67 2.9 3.13 V When voltage rises Detected voltage VDL SVHI = 0001 2.76 3.0 3.24 V When voltage drops Released voltage VDH 2.85 3.1 3.34 V When voltage rises Detected voltage VDL SVHI = 0010 2.94 3.2 3.45 V When voltage drops Released voltage VDH 3.04 3.3 3.56 V When voltage rises Detected voltage VDL SVHI = 0011 3.31 3.6 3.88 V When voltage drops Released voltage VDH 3.40 3.7 3.99 V When voltage rises Detected voltage VDL SVHI = 0100 3.40 3.7 3.99 V When voltage drops Released voltage VDH 3.50 3.8 4.10 V When voltage rises Detected voltage VDL SVHI = 0111 3.68 4.0 4.32 V When voltage drops Released voltage VDH 3.77 4.1 4.42 V When voltage rises Detected voltage VDL SVHI = 1000 3.77 4.1 4.42 V When voltage drops Released voltage VDH 3.86 4.2 4.53 V When voltage rises Detected voltage VDL SVHI = 1001 3.86 4.2 4.53 V When voltage drops Released voltage VDH 3.96 4.3 4.64 V When voltage rises LVD stabilization wait time TLVDW - - - 4032 × tCYCP* μs *: tCYCP indicates the APB2 bus clock cycle time.

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1. Flash Memory Write/Erase Characteristics (1) Write / Erase time (Vcc = 2.7V to 5.5V, Ta = - 40°C to + 85°C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 0.7 3.7 s Includes write time prior to internal erase Small Sector 0.3 1.1 Half word (16-bit) write time 12 384 μs Not including system-level overhead time. Chip erase time 13.6 68 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. (2) Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* 100,000 5* *: At average + 85°C

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 125 CONFIDENTIAL 9. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation.  Return Count Time (VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Ticnt tCYCC ns High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 40 80 μs Low-speed CR TIMER mode 453 737 μs Sub TIMER mode 453 737 μs STOP mode 453 737 μs *: The maximum value depends on the accuracy of built-in CR.  Operation example of return from Low-Power consumption mode (by external interrupt*) Ext.INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

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 Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal Resource INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes:  The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.  When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 127 CONFIDENTIAL (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation.  Return Count Time (VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Trcnt 321 461 μs High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 321 461 μs Low-speed CR TIMER mode 441 701 μs Sub TIMER mode 441 701 μs STOP mode 441 701 μs *: The maximum value depends on the accuracy of built-in CR.  Operation example of return from Low-Power consumption mode (by INITX) INITX Trcnt Internal RST CPU Operation Start RST Active Release

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 Operation example of return from low power consumption mode (by internal resource reset*) Internal Resource RST Trcnt Internal RST CPU Operation Start RST Active Release *: Internal resource reset is not included in return factor by the kind of Low -Power consumption mode. Notes:  The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL.  When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".  The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing in 4. AC Characteristics in ■Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset.  When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.  The internal resource reset means the watchdog reset and the CSV reset.

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 129 CONFIDENTIAL  Ordering Information Part number On-chip Flash memory On-chip MB9BFD16SPMC-GE1 512 Kbyte 64 Kbyte Plastic · LQFP 144-pin (0.5mm pitch), (FPT-144P-M08) Tray MB9BFD17SPMC-GE1 768 Kbyte 96 Kbyte MB9BFD18SPMC-GE1 1 Mbyte 128 Kbyte MB9BFD16TPMC-GE1 512 Kbyte 64 Kbyte Plastic · LQFP 176-pin (0.5mm pitch), (FPT-176P-M07) MB9BFD17TPMC-GE1 768 Kbyte 96 Kbyte MB9BFD18TPMC-GE1 1 Mbyte 128 Kbyte MB9BFD16TBGL-GE1 512 Kbyte 64 Kbyte Plastic · PFBGA 192-pin (0.8mm pitch), (BGA-192P-M06) MB9BFD17TBGL-GE1 768 Kbyte 96 Kbyte MB9BFD18TBGL-GE1 1 Mbyte 128 Kbyte

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 PACKAGE DIMENSIONS 176-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 24.0 × 24.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LQFP-0176-2424-0.50 176-pin plastic LQFP (FPT-176P-M07) (FPT-176P-M07) C Details of "A" part 0°~8° 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) (Stand off) (.004±.004) 0.10±0.10 1.50 +0.20 –0.10 +.008 –.004 .059 (Mounting height) 0.08(.003) (.006±.002) 0.145±0.055 "A" INDEX 1LEAD No. 44 89132 133 176 (.009±.002) M0.08(.003) Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder. 2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 131 CONFIDENTIAL 144-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20 g Code (Reference) P-LFQFP144-20×20-0.50 144-pin plastic LQFP (FPT-144P-M08) (FPT-144P-M08) Details of "A" part 0.25(.010) (Stand off) (.004±.004) 0.10±0.10 (.024±.006) 0.60±0.15 (.020±.008) 0.50±0.20 1.50 +0.20 –0.10 +.008 –.004 .059 0°~8° 0.50(.020) "A" 0.08(.003) 0.145±0.055 (.006±.002) LEAD No. 1 36 INDEX 73108 109 144 0.22±0.05 (.009±.002) M0.08(.003) (Mounting height) Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8

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192-ball plastic FBGA Ball pitch 0.80 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Ball Sealing method Plastic mold Mounting height 1.45 mm Max. Weight 0.34 g 192-ball plastic FBGA (BGA-192P-M06) (BGA-192P-M06) C 12.00±0.10 (.472±.004) ABCDEFGHJKLM M S AB B REF 0.80(.031) N A 0.80(.031) REF 192-ø0.45±0.10 0.20(.008) S A S S0.10(.004) (Stand off) (.014±.004) 0.35±0.10 (Seated height) 1.25±0.20 (.049±.008) INDEX(INDEX AREA) 10.40(.409)REF 10.40(.409) REF P Dimensions in mm (inches). Note: The values in parentheses are reference values.2008-2010 FUJITSU SEMICONDUCTOR LIMITED B192006S-c-1-3

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 133 CONFIDENTIAL  Major Changes Page Section Change Results Revision 1.0 - - Preliminary → Data Sheet 1 DESCRIPTION Corrected the description. FEATURES

• Multi-function Serial Interface (Max 8channels) Revised the following description. "4 channels with 16-byte FIFO" →"4 channels with 16steps×9-bit FIFO" PRODUCT LINEUP Multi-function Serial Interface (UART/CSIO/LIN/I2C) Added the following description. "ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO" 9 to 11 PIN ASSIGNMENT Added the description of "Note". 55 I/O CIRCUIT TYPE Added the following description to "Type H". IOH = -20.5mA, IOL = 18.5mA 62 to 64 HANDLING DEVICES • Revised the description of "•Power supply pins".
• Revised the description of "•C pin".
• Added the description of "•Base Timer". BLOCK DIAGRAM Corrected the figure.
• TIOA: input → input/output
• TIOB: output → input ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions
• Corrected the value of "Analog reference voltage (A VRH)". Min: AVSS → 2.7V
• Added the "Smoothing capacitor (CS)".
• Added the footnote. 3. DC Characteristics (1) Current Rating
• Revised the value of "TBD".
• Revised the unit.
• Deleted "and estimated values." 83 4. AC Characteristics (1) Main Clock Input Characteristics Added "Internal operating clock frequency (FCM): Master clock". (4-1) Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input of PLL)
• Added "Main PLL clock frequency (FCLKPLL)".
• Added "USB/Ethernet clock frequency (FCLKSPLL)". (4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR) 113 • Management Interface Revised the value of "MDC ↑ → MDIO Hold time". Min: 20 → 0 116 5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
• Deleted "(Preliminary value)".
• Added the Symbol.
• Revised the value of "TBD".
• Revised the maximum value of "Power supply current (analog + digital)": A/D 1unit operation: Typ: 0.47 → 0.57 When A/D stops: Typ: 0.01 → 0.06
• Revised the value of "Reference power supply current (between A VRH to A VSS)" When A/D stops: Typ: 0.01 → 0.06
• Deleted the following Pin name. - "Sampling time" - "Compare clock cycle" - "State transition time to operation permission" - "Analog input capacity" - "Analog input resistance"
• Corrected the value of "Compare clock cycle (Tcck)". Max: 10000 → 2000 119 6. USB Characteristics Corrected the condition of " Output L level voltage". External pull-down → External pull-up 123 7. Low-voltage Detection Characteristics (2) Interrupt of Low-V oltage Detection Corrected the value of "LVD stabilization wait time (TLVDW)". Max: 2240 × tcyc → 4032 × tCYCP 124 8. Flash Memory Write/Erase Characteristics Erase/write cycles and data hold time Deleted "(targeted value)". Revision 1.1 - - Company name and layout design change Revision 2.0 Features USB Interface Ethernet-MAC Added the description of PLL for USB and Ethernet 2 Features USB Interface Added the size of each EndPoint 3 Features External Bus Interface Added the description of Maximum area size

134 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

Page Section Change Results 9, 10 Pin Assignment Added SWCLK and SWDIO and SWO 52 to 57 I/O Circuit Type · Added the description of I2C to the type of E, F, I, L

• Added about +B input 62 Handling Devices Added "Stabilizing power supply voltage" 62 Handling Devices Crystal oscillator circuit Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." 63 Handling Devices C Pin Changed the description 65 Block Diagram Modified the block diagram 67 Memory Map
• Memory map(1) Modified the area of "Extarnal Device Area" 68 Memory Map
• Memory map(2) Added the summary of Flash memory sector and the note 75, 76 Electrical Characteristics 1. Absolute Maximum Ratings
• Added the Clamp maximum current
• Added the output current of P80, P81, P82, P83
• Added about +B input 77 Electrical Characteristics 2. Recommended Operation Conditions
• Modified the minimum value of Analog reference voltage
• Added Smoothing capacitor
• Added the note about less than the minimum power supply voltage 79, 80 Electrical Characteristics 3. DC Characteristics (1) Current rating
• Changed the table format
• Added Main TIMER mode current
• Added Flash Memory Current
• Moved A/D Converter Current Electrical Characteristics 4. AC Characteristics (3) Built-in CR Oscillation Characteristics Added Frequency stability time at Built-in high-speed CR Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing
• Added Time until releasing Power-on reset
• Changed the figure of timing 88 to 90 Electrical Characteristics 4. AC Characteristics (7) External Bus Timing Modified Data output time 97 to 104 Electrical Characteristics 4. AC Characteristics (9) CSIO/UART Timing
• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode 116 Electrical Characteristics 5. 12bit A/D Converter
• Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
• Added Conversion time at A Vcc < 4.5 V
• Modified Stage transition time to operation permission
• Modified the minimum value of Reference voltage 125 to 128 Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode 129 Ordering Information Change to full part number

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 135 CONFIDENTIAL

136 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

February 10, 2015, MB9BD10T-DS706-00031-2v0-E 137 CONFIDENTIAL

138 MB9BD10T-DS706-00031-2v0-E, February 10, 2015

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