MB9B560R

SPANSION

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2 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.

32-bit ARM® Cortex®-M4F based Microcontroller MB9BF566M/N/R, MB9BF567M/N/R, MB9BF568M/N/R, MB9BF568F Data Sheet (Full Production) Publication Number MB9B560R_DS709-00001 Revision 2.0 Issue Date February 2, 2015 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. d eems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. 1. Description Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN). Note: − ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

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February 2, 2015, MB9B560R_DS709-00001-2v0-E 5 CONFIDENTIAL 2. Features 32-bit ARM Cortex-M4F Core  Processor version: r0p1  Up to 160 MHz Frequency Operation  FPU built-in  Support DSP instruction  Memory Protection Unit (MPU): improves the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories  Flash memory These series are based on two independent on-chip Flash memories. − MainFlash memory − Up to 1024 Kbytes − Built-in Flash Accelerator System with 16 Kbytes trace buffer memory − The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. − Security function for code protection − WorkFlash memory − 32 Kbytes − Read cycle: − 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz − 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz − 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz − 0wait-cycle: the operation frequency up to 40 MHz − Security function is shared with code protection  SRAM This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. − SRAM0: Up to 64 Kbytes − SRAM1: Up to 32 Kbytes − SRAM2: Up to 32 Kbytes

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 Supports SRAM, NOR, NAND Flash, and SDRAM device  Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  8-/16-bit Data width  Up to 25-bit Address bit  Supports Address/Data multiplex  Supports external RDY function  Supports scramble function − Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. − Possible to set two kinds of the scramble key Note: − It is necessary to prepare the dedicated software library to use the scramble function. USB Interface USB interface is composed of Function and Host. [USB function]  USB2.0 Full-Speed supported  Max 6 EndPoint supported − EndPoint 0 is control transfer − EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer − EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer − EndPoint 1 to 5 comprise Double Buffer − The size of each endpoint is according to the follows. − Endpoint 0, 2 to 5: 64 bytes − Endpoint 1: 256 bytes [USB host]  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer support  USB Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported CAN Interface (Max two channels)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32 message buffer

February 2, 2015, MB9B560R_DS709-00001-2v0-E 7 CONFIDENTIAL Multi-function Serial Interface (Max eight channels)  64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)  Operation mode is selectable from the followings for each channel. − UART − CSIO − LIN − I2C  UART − Full-duplex double buffer − Selection with or without parity supported − Built-in dedicated baud rate generator − External clock available as a serial clock − Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) − Various error detect functions available (parity errors, framing errors, and overrun errors)  CSIO − Full-duplex double buffer − Built-in dedicated baud rate generator − Overrun error detect function available − Serial chip select function (ch.6 and ch.7 only) − Supports high-speed SPI (ch.4 and ch.6 only) − Data length 5 to 16-bit  LIN − LIN protocol Rev.2.1 supported − Full-duplex double buffer − Master/Slave mode supported − LIN break field generation (can change to 13 to 16-bit length) − LIN break delimiter generation (can change to 1 to 4-bit length) − Various error detect functions available (parity errors, framing errors, and overrun errors)  I2C − Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported − Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported DMA Controller (Eight channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536

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DSTC (Descriptor System data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 24 channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 3 units  Conversion time: 0.5 μs @ 5 V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) DA Converter (Max two channels)  R-2R type  12-bit resolution Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 100 high-speed general-purpose I/O ports @ 120 pin Package  Some pin is 5 V tolerant I/O. See 6. Pin Description and 7. I/O Circuit Type for the corresponding pins.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 9 CONFIDENTIAL Multi-function Timer (Max two units) The Multi-function timer is composed of the following blocks. Minimum resolution : 6.25 ns  16-bit free-run timer × 3 ch./unit  Input capture × 4 ch./unit  Output compare × 6 ch./unit  A/D activation compare × 6 ch./unit  Waveform generator × 3 ch./unit  16-bit PPG timer × 3 ch./unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (Max two channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN, and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz

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External Interrupt Controller Unit  External interrupt input pin: Max 16 pins  Include one non-maskable interrupt (NMI) Watchdog Timer (two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power saving mode except STOP . CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 SD Card Interface It is possible to use the SD card that conforms to the following standards.  Part 1 Physical Layer Specification version 3.01  Part E1 SDIO Specification version 3.00  Part A2 SD Host Controller Standard Specification version 3.00  1-bit or 4-bit data bus Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub Clock : 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset

February 2, 2015, MB9B560R_DS709-00001-2v0-E 11 CONFIDENTIAL Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-power Consumption Mode Six low-power consumption modes are supported.  SLEEP  TIMER  RTC  STOP  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used.  RTC  32 kHz oscillation circuit  Power-on circuit  Back up register: 32 bytes  Port circuit Voice Function These features are enabled for the voice function. A dedicated library is necessary for using the voice function.  Automatic Speech Recognition (ASR) − 100 custom commands in multiple languages − User commands defined with a text file (no audio input or training required)  Natural Language Understanding (NLU) Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique ID Unique value of the device (41-bit) is set.

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 Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for USB I/O: USBVCC = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for VBAT: VBAT = 2.7 V to 5.5 V

February 2, 2015, MB9B560R_DS709-00001-2v0-E 13 CONFIDENTIAL 3. Product Lineup Memory Size Product name MB9BF566M/N/R MB9BF567M/N/R MB9BF568M/N/R/F MainFlash memory 512 Kbytes 768 Kbytes 1024 Kbytes WorkFlash memory 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM 64 Kbytes 96 Kbytes 128 Kbytes SRAM0 32 Kbytes 48 Kbytes 64 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes

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Pin count 80 100/112 120/144 CPU Cortex-M4F, MPU, NVIC 128ch. Freq. 160 MHz Power supply voltage range 2.7 V to 5.5 V USB2.0 (Function/Host) 1ch. CAN 2ch. (Max) DMAC 8ch. DSTC 128ch. External Bus Interface Addr:19-bit (Max), R/W data: 8-bit (Max), CS:5 (Max), SRAM, NOR Flash Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, SDRAM Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, NAND Flash, SDRAM Multi-function Serial Interface (UART/CSIO/LIN/I2C) 8ch. (Max) Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF Timer A/D activation compare 6ch. 2 units (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. SD Card Interface 1 unit QPRC 2ch. (Max) Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog Timer 1ch. (SW) + 1ch. (HW) External Interrupts 16 pins (Max) + NMI × 1 I/O Ports 63 pins (Max) 80 pins (Max) 100 pins (Max) 12-bit A/D Converter 16ch. (3 units) 24ch. (3 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz (±2%) Low-speed 100 kHz (Typ) Debug Function SWJ-DP/ETM Unique ID Yes Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 15 CONFIDENTIAL 4. Packages Product Name Package MB9BF566M MB9BF567M MB9BF568M MB9BF566N MB9BF567N MB9BF568N MB9BF566R MB9BF567R MB9BF568R MB9BF568F LQFP: FPT-80P-M37 (0.5 mm pitch)  - - LQFP: FPT-80P-M40 (0.65 mm pitch)  - - QFP: FPT-100P-M36 (0.65 mm pitch) -  - LQFP: FPT-100P-M23 (0.5 mm pitch) -  - LQFP: FPT-120P-M37 (0.5 mm pitch) - -  BGA: BGA-112P-M05 (0.5 mm pitch) -  - BGA: BGA-144P-M09 (0.5 mm pitch) - -  : Supported Note: − See 16. Package Dimensions for detailed information on each package.

16 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Assignment FPT-80P-M37/M40 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0 P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VCC 1 60 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 59 P21/AN17/SIN0_0/INT06_1 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 58 P22/CROUT_0/AN16/TIOB7_1/SOT0_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 57 P23/AN15/TIOA7_1/SCK0_0/RTO00_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 56 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 55 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 53 P18/AN08/SCK2_2/MAD15_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 52 AVRH P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 51 AVRL P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 50 AVSS P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 49 AVCC P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13 48 P17/AN07/SOT2_2/WKUP3/MAD14_0 P3A/TIOA0_1/AIN0_0/RTO00_0 14 47 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3B/TIOA1_1/BIN0_0/RTO01_0 15 46 P15/AN05/SCK0_1/MAD12_0 P3C/TIOA2_1/ZIN0_0/RTO02_0 16 45 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3D/TIOA3_1/RTO03_0/MAD00_0 17 44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3E/TIOA4_1/RTO04_0/MAD01_0 18 43 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3F/TIOA5_1/RTO05_0/MAD02_0 19 42 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0 VSS 20 41 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80

February 2, 2015, MB9B560R_DS709-00001-2v0-E 17 CONFIDENTIAL FPT-100P-M23 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC 100 VCC 1 75 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 74 P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 73 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 72 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 71 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 68 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 67 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 66 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 64 P18/AN08/SCK2_2/MAD15_0 P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0 13 63 AVRH P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0 14 62 AVRL P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15 61 AVSS P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16 60 AVCC P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 17 59 P17/AN07/SOT2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 18 58 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 19 57 P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 20 56 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 21 55 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/TIOA3_1/RTO03_0/MAD00_0 22 54 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_0 23 53 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_0 24 52 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0 VSS 25 51 VCC VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100

18 MB9B560R_DS709-00001-2v0-E, February 2, 2015

(TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/RX0_2/SIN5_1/INT03_0/S_CD_0/MWEX_0 P64/TIOA7_0/SOT5_1/INT10_2 P65/TIOB7_0/SCK5_1 P66/ADTG_8/SIN3_0/INT11_2 P67/TIOA7_2/SOT3_0 P68/TIOB7_2/SCK3_0/INT00_2 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 VCC 1 90 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 89 P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 85 P24/RX1_0/SIN2_1/RTO01_1/INT01_2 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 84 P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 83 P26/TIOB5_0/SCK2_1/RTO03_1 P57/SCK6_0/MADATA07_0 9 82 P27/TIOA6_2/RTO04_1/INT02_2 P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10 81 P1F/ADTG_4/TIOB6_2/RTO05_1 P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11 80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0 12 79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P5B/CTS4_2/MADATA11_0 13 78 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14 77 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15 76 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16 75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17 74 P18/AN08/SCK2_2/MAD15_0 P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0 18 73 AVRH P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0 19 72 AVRL P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20 71 AVSS P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21 70 AVCC P38/SCK5_2/IC00_0/INT06_2 22 69 P17/AN07/SOT2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 23 68 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 24 67 P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 25 66 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 26 65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/TIOA3_1/RTO03_0/MAD00_0 27 64 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_0 28 63 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_0 29 62 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0 VSS 30 61 VCC VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 P70/TX0_0/TIOA4_2/AIN0_1/IC13_1 P71/RX0_0/TIOB4_2/BIN0_1/IC12_1/INT15_1 P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2 P73/TIOB6_0/SOT2_0/IC10_1/INT03_2 P74/SCK2_0/DTTI1X_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 120

February 2, 2015, MB9B560R_DS709-00001-2v0-E 19 CONFIDENTIAL FPT-100P-M36 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 VCC VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VSS P20/AN18/AIN1_1/INT05_0/MAD24_0 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 81 50 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 82 49 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 83 48 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 84 47 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 85 46 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 86 45 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 87 44 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 88 43 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 89 42 P18/AN08/SCK2_2/MAD15_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 90 41 AVRH P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0 91 40 AVRL P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0 92 39 AVSS P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 93 38 AVCC P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 94 37 P17/AN07/SOT2_2/WKUP3/MAD14_0 P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 95 36 P16/AN06/SIN2_2/INT14_1/MAD13_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 96 35 P15/AN05/SCK0_1/MAD12_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 97 34 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 98 33 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 99 32 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3D/TIOA3_1/RTO03_0/MAD00_0 100 31 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0 P3E/TIOA4_1/RTO04_0/MAD01_0 P3F/TIOA5_1/RTO05_0/MAD02_0 VSS VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0 QFP - 100

20 MB9B560R_DS709-00001-2v0-E, February 2, 2015

February 2, 2015, MB9B560R_DS709-00001-2v0-E 21 CONFIDENTIAL BGA-144P-M09 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS UDP0 UDM0 USBVCC VSS P66 VSS VSS AN21 VSS P0C VCC VSS B VCC VSS P60 P61 P63 P67 TCK/ SWCLK TDO/ SWO AN20 P0B VSS VSS P0E C P50 P51 VSS P62 P64 P68 TDI AN23 AN19 P0D VSS AN18 VSS D P52 P53 P54 VSS P65 TRSTX TMS/ SWDIO AN22 P0A VSS AN17 AN16 AN15 E P55 P56 P57 P58 P24 P25 P26 P27 F P59 P5A P5B P30 P1F AN14 AN13 AN12 G P31 P32 P33 P34 AN11 AN10 AN09 AVRH H P35 P36 P37 P38 AN08 AN07 AN06 AVRL J P39 P3A P3B P3C AN05 AN04 AN03 AVSS K VSS P3D P3E VSS P45 P49 P4C P70 P72 VSS AN02 AN01 AVCC L P3F P41 VSS P44 VSS P48 P4B P4E P71 P74 VSS AN00 VSS M VCC VSS P43 VSS X1A VSS VSS VBAT C VSS P4D VCC VSSN VSS P40 P42 INITX X0A MD1 X0 X1 VSS VCCP73 MD0 VSS index

22 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Description

6.1 List of Pin Numbers

February 2, 2015, MB9B560R_DS709-00001-2v0-E 23 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 7 7 7 85 E1 E1 P55 E K ADTG_1 SIN6_0 RTO15_0 (PPG14_0) INT07_2 MADATA05_0 8 8 8 86 E2 E2 P56 E K SOT6_0 (SDA6_0) DTTI1X_0 INT08_2 MADATA06_0 9 - - - - E3 P57 E I SCK6_0 (SCL6_0) MADATA07_0 10 - - - - E4 P58 E K SIN4_2 AIN1_0 INT04_2 MADATA08_0 11 - - - - F1 P59 E K RX1_1 SOT4_2 (SDA4_2) BIN1_0 INT07_1 MADATA09_0 12 - - - - F2 P5A E I TX1_1 SCK4_2 (SCL4_2) ZIN1_0 MADATA10_0 13 - - - - F3 P5B E I CTS4_2 MADATA11_0 9 9 87 E3 P30 E Q TIOB0_1 RTS4_2 INT15_2 WKUP1 - - MADATA07_0 14 - - - - F4 MADATA12_0

24 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 10 10 88 F1 P31 I K TIOB1_1 SIN3_1 INT09_2 - - MADATA08_0 15 - - - - G1 MADATA13_0 11 11 89 F2 P32 N K TIOB2_1 SOT3_1 (SDA3_1) INT10_1 - - MADATA09_0 16 - - - - G2 MADATA14_0 12 12 90 F3 P33 N K ADTG_6 TIOB3_1 SCK3_1 (SCL3_1) INT04_0 - - MADATA10_0 17 - - - - G3 MADATA15_0 13 - 91 G1 P34 E I TX0_1 TIOB4_1 FRCK0_0 - - MADATA11_0 18 - - - - G4 MNALE_0 14 - 92 G2 P35 E K RX0_1 TIOB5_1 IC03_0 INT08_1 - - MADATA12_0 19 - - - - H1 MNCLE_0 15 - 93 G3 P36 E K SIN5_2 IC02_0 INT09_1 - - MADATA13_0 20 - - - - H2 MNWEX_0 16 - 94 H2 P37 E K SOT5_2 (SDA5_2) IC01_0 INT05_2 - - MADATA14_0 21 - - - - H3 MNREX_0

February 2, 2015, MB9B560R_DS709-00001-2v0-E 25 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 17 - 95 H3 P38 E K SCK5_2 (SCL5_2) IC00_0 INT06_2 - - MADATA15_0 23 18

96 J1 J1

ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 - MSDCLK_0 24 19

97 J2 J2

TIOA0_1 AIN0_0 RTO00_0 (PPG00_0) - MSDCKE_0 25 20

98 J3 J3

TIOA1_1 BIN0_0 RTO01_0 (PPG00_0) - MRASX_0 26 21

99 K1 J4

TIOA2_1 ZIN0_0 RTO02_0 (PPG02_0) - MCASX_0 27 22 17 100 K2 K2 P3D G I TIOA3_1 RTO03_0 (PPG02_0) MAD00_0 28 23 18 1 L1 K3 P3E G I TIOA4_1 RTO04_0 (PPG04_0) MAD01_0 29 24 19 2 L2 L1 P3F G I TIOA5_1 RTO05_0 (PPG04_0) MAD02_0 30 25 20 3 N1 N1 VSS - - 31 26 - 4 M1 M1 VCC - -

26 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 32 27 - 5 N2 N2 P40 G K TIOA0_0 RTO10_1 (PPG10_1) INT12_1 33 28 - 6 N3 L2 P41 G K TIOA1_0 RTO11_1 (PPG10_1) INT13_1 34 29 - 7 M3 N3 P42 G I TIOA2_0 RTO12_1 (PPG12_1) MSDWEX_0 35 30 - 8 L3 M3 P43 G I ADTG_7 TIOA3_0 RTO13_1 (PPG12_1) MCSX8_0 36 31 21 9 M4 L4 P44 R J TIOA4_0 RTO14_1 (PPG14_1) DA0 37 32 22 10 L5 K5 P45 R J TIOB0_0 RTO15_1 (PPG14_1) DA1 38 33 23 11 M6 N4 INITX B C 39 34 24 12 N5 N5 P46 P S X0A 40 35 25 13 N6 M5 P47 Q T X1A 41 36 26 14 L6 L6 P48 O U VREGCTL 42 37 27 15 M7 K6 P49 O U VWAKEUP 43 38 28 16 N8 N7 VBAT - - 44 39 29 17 N9 N8 C - - 45 40 30 18 N10 N9 VSS - - 46 41 31 19 M8 M9 VCC - - 47 42 32 20 L7 L7 P4B E I TIOB1_0 SCS7_1 MAD03_0

February 2, 2015, MB9B560R_DS709-00001-2v0-E 27 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 48 43 33 21 L8 K7 P4C N I TIOB2_0 SCK7_1 (SCL7_1) AIN1_2 MAD04_0 49 44 34 22 M9 M8 P4D N K TIOB3_0 SOT7_1 (SDA7_1) BIN1_2 INT13_2 MAD05_0 50 45 35 23 L9 L8 P4E I Q TIOB4_0 SIN7_1 ZIN1_2 FRCK1_1 INT11_1 WKUP2 MAD06_0 51 - - - - K8 P70 E I TX0_0 TIOA4_2 AIN0_1 IC13_1 52 - - - - L9 P71 E K RX0_0 TIOB4_2 BIN0_1 IC12_1 INT15_1 53 - - - - K9 P72 E K TIOA6_0 SIN2_0 ZIN0_1 IC11_1 INT14_2 54 - - - - M10 P73 E K TIOB6_0 SOT2_0 (SDA2_0) IC10_1 INT03_2 55 - - - - L10 P74 E I SCK2_0 (SCL2_0) DTTI1X_1

28 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 56 46 36 24 M10 N10 PE0 C E MD1 57 47 37 25 M11 M11 MD0 J D 58 48 38 26 N11 N11 PE2 A A 59 49 39 27 N12 N12 PE3 A B 60 50 40 28 N13 N13 VSS - - 61 51 - 29 M13 M13 VCC - - 62 52 41 30 L13 L12 P10 F M AN00 RX1_2 SIN1_1 FRCK0_2 INT02_1 MAD07_0 63 53 42 31 L12 K12 P11 F L AN01 TX1_2 SOT1_1 (SDA1_1) IC00_2 MAD08_0 64 54 43 32 K13 K11 P12 F L AN02 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 MAD09_0 65 55 44 33 K12 J12 P13 F M AN03 SIN0_1 IC02_2 INT03_1 MAD10_0 66 56 45 34 J13 J11 P14 F L AN04 SOT0_1 (SDA0_1) IC03_2 MAD11_0 67 57 46 35 J12 J10 P15 F L AN05 SCK0_1 (SCL0_1) MAD12_0

February 2, 2015, MB9B560R_DS709-00001-2v0-E 29 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 68 58 47 36 J11 H12 P16 F M AN06 SIN2_2 INT14_1 MAD13_0 69 59 48 37 H12 H11 P17 F P AN07 SOT2_2 (SDA2_2) WKUP3 MAD14_0 70 60 49 38 H13 K13 AVCC - - 71 61 50 39 G13 J13 AVSS - - 72 62 51 40 F13 H13 AVRL - - 73 63 52 41 E13 G13 AVRH - - 74 64 53 42 H11 H10 P18 F L AN08 SCK2_2 (SCL2_2) MAD15_0 75 65 54 43 G12 G12 P19 F M AN09 SIN4_1 IC00_1 INT05_1 MAD16_0 76 66 55 44 G11 G11 P1A M L AN10 SOT4_1 (SDA4_1) IC01_1 MAD17_0 77 67 56 45 F12 G10 P1B M L AN11 SCK4_1 (SCL4_1) IC02_1 MAD18_0 78 68 - 46 F11 F13 P1C F L AN12 CTS4_1 IC03_1 MAD19_0 79 69 - 47 E12 F12 P1D F L AN13 RTS4_1 DTTI0X_1 MAD20_0

30 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 80 70 - 48 E11 F11 P1E F L AN14 ADTG_5 FRCK0_1 MAD21_0 81 - - - - F10 P1F E I ADTG_4 TIOB6_2 RTO05_1 (PPG04_1) 82 - - - - E13 P27 E K TIOA6_2 RTO04_1 (PPG04_1) INT02_2 83 - - - - E12 P26 E I TIOB5_0 SCK2_1 (SCL2_1) RTO03_1 (PPG02_1) 84 - - - - E11 P25 E I TX1_0 TIOA5_0 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) 85 - - - - E10 P24 E K RX1_0 SIN2_1 RTO01_1 (PPG00_1) INT01_2 86 71

49 D13 D13

TIOA7_1 SCK0_0 (SCL0_0) RTO00_1 (PPG00_1) - MAD22_0 87 72

50 D12 D12

CROUT_0 AN16 TIOB7_1 SOT0_0 (SDA0_0) - ZIN1_1

February 2, 2015, MB9B560R_DS709-00001-2v0-E 31 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 88 73

51 C13 D11

SIN0_0 - BIN1_1

59 INT06_1

MAD23_0 89 74 - 52 C12 C12 P20 F M AN18 AIN1_1 INT05_0 MAD24_0 90 75 60 53 A13 A13 VSS - - 91 76 61 54 B13 A12 VCC - - 92 77 62 55 A12 B13 P0E L I TIOB5_2 SCS6_1 IC13_0 S_CLK_0 MDQM1_0 93 78 63 56 B11 C10 P0D L I TIOA5_2 SCK6_1 (SCL6_1) IC12_0 S_CMD_0 MDQM0_0 94 79 64 57 B10 A11 P0C L I TIOA6_1 SOT6_1 (SDA6_1) IC11_0 S_DATA1_0 MALE_0 95 80 65 58 A10 B10 P0B L K TIOB6_1 SIN6_1 IC10_0 INT00_1 S_DATA0_0 MCSX0_0 96 81 66 59 A9 D9 P0A L K SIN1_0 FRCK1_0 INT12_2 S_DATA3_0 MCSX1_0

32 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 97 82

60 B9 C9

TRACED0 TIOA3_2 SOT1_0 (SDA1_0) S_DATA2_0 MCSX5_0 98 83 - 61 C9 B9 P08 F N AN20 TRACED1 TIOB3_2 SCK1_0 (SCL1_0) MCSX4_0 99 84 - 62 A8 A9 P07 F N AN21 TRACED2 TIOA0_2 SCK7_0 (SCL7_0) MCLKOUT_0 100 85 - 63 B8 D8 P06 F N AN22 TRACED3 TIOB0_2 SOT7_0 (SDA7_0) MCSX3_0 101 86 - 64 C8 C8 P05 F O AN23 ADTG_0 TRACECLK SIN7_0 INT01_1 MCSX2_0 102 87 68 65 C7 B8 P04 E G TDO SWO 103 88 69 66 B7 D7 P03 E G TMS SWDIO 104 89 70 67 C6 C7 P02 E H TDI MCSX6_0 105 90 71 68 A6 B7 P01 E G TCK SWCLK

February 2, 2015, MB9B560R_DS709-00001-2v0-E 33 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 106 91 72 69 B6 D6 P00 E H TRSTX MCSX7_0 107 92 - 70 A5 A7 VSS - - 108 - - - - C6 P68 E K TIOB7_2 SCK3_0 (SCL3_0) INT00_2 109 - - - - B6 P67 E I TIOA7_2 SOT3_0 (SDA3_0) 110 - - - - A6 P66 E K ADTG_8 SIN3_0 INT11_2 111 - - - - D5 P65 E I TIOB7_0 SCK5_1 (SCL5_1) 112 - - - - C5 P64 E K TIOA7_0 SOT5_1 (SDA5_1) INT10_2 113 93 73 71 C5 P63 E K CROUT_1 RX0_2 - - - - SIN5_1 93 73 71 C5 INT03_0 S_CD_0 MWEX_0 114 94 74 72 B5 C4 P62 I K ADTG_3 TX0_2 SIN5_0 INT04_1 S_WP_0 MOEX_0 115 95 75 73 B4 B4 P61 E I UHCONX0 TIOB2_2 SOT5_0 (SDA5_0) RTCCO_0 SUBOUT_0

34 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Type LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 116 96 76 74 B3 B3 P60 I F TIOA2_2 SCK5_0 (SCL5_0) NMIX WKUP0 MRDY_0 117 97 77 75 A4 A4 USBVCC - - 118 98 78 76 A3 A3 P80 H R UDM0 119 99 79 77 A2 A2 P81 H R UDP0 120 100 80 78 A1 A1 VSS - - - - - - A7 A5 - - - - - - B2 A8 - - - - - - C11 B2 - - - - - - H1 B11 - - - - - - N4 B12 - - - - - - M5 C3 - - - - - - N7 C11 - - - - - - A11 D4 - - - - - - M2 K1 - - - - - - - K4 VSS - - - - - - - K10 - - - - - - - L3 - - - - - - - L5 - - - - - - - L11 - - - - - - - L13 - - - - - - - M2 - - - - - - - M4 - - - - - - - M6 - - - - - - - M7 - - - - - - - M12 - - - - - - - N6 - -

February 2, 2015, MB9B560R_DS709-00001-2v0-E 35 CONFIDENTIAL

6.2 List of Pin Functions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 ADC ADTG_0 A/D converter external trigger input pin 101 86 - 64 C8 C8 ADTG_1 7 7 7 85 E1 E1 ADTG_2 23 18 13 96 J1 J1 ADTG_3 114 94 74 72 B5 C4 ADTG_4 81 - - - - F10 ADTG_5 80 70 - 48 E11 F11 ADTG_6 17 12 12 90 F3 G3 ADTG_7 35 30 - 8 L3 M3 ADTG_8 110 - - - - A6 AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 62 52 41 30 L13 L12 AN01 63 53 42 31 L12 K12 AN02 64 54 43 32 K13 K11 AN03 65 55 44 33 K12 J12 AN04 66 56 45 34 J13 J11 AN05 67 57 46 35 J12 J10 AN06 68 58 47 36 J11 H12 AN07 69 59 48 37 H12 H11 AN08 74 64 53 42 H11 H10 AN09 75 65 54 43 G12 G12 AN10 76 66 55 44 G11 G11 AN11 77 67 56 45 F12 G10 AN12 78 68 - 46 F11 F13 AN13 79 69 - 47 E12 F12 AN14 80 70 - 48 E11 F11 AN15 86 71 57 49 D13 D13 AN16 87 72 58 50 D12 D12 AN17 88 73 59 51 C13 D11 AN18 89 74 - 52 C12 C12 AN19 97 82 67 60 B9 C9 AN20 98 83 - 61 C9 B9 AN21 99 84 - 62 A8 A9 AN22 100 85 - 63 B8 D8 AN23 101 86 - 64 C8 C8 Base Timer 0 TIOA0_0 Base timer ch.0 TIOA pin 32 27 - 5 N2 N2 TIOA0_1 24 19 14 97 J2 J2 TIOA0_2 99 84 - 62 A8 A9 TIOB0_0 Base timer ch.0 TIOB pin 37 32 22 10 L5 K5 TIOB0_1 14 9 9 87 E3 F4 TIOB0_2 100 85 - 63 B8 D8

36 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Base Timer 1 TIOA1_0 Base timer ch.1 TIOA pin 33 28 - 6 N3 L2 TIOA1_1 25 20 15 98 J3 J3 TIOA1_2 5 5 5 83 D1 D2 TIOB1_0 Base timer ch.1 TIOB pin 47 42 32 20 L7 L7 TIOB1_1 15 10 10 88 F1 G1 TIOB1_2 6 6 6 84 D2 D3 Base Timer 2 TIOA2_0 Base timer ch.2 TIOA pin 34 29 - 7 M3 N3 TIOA2_1 26 21 16 99 K1 J4 TIOA2_2 116 96 76 74 B3 B3 TIOB2_0 Base timer ch.2 TIOB pin 48 43 33 21 L8 K7 TIOB2_1 16 11 11 89 F2 G2 TIOB2_2 115 95 75 73 B4 B4 Base Timer 3 TIOA3_0 Base timer ch.3 TIOA pin 35 30 - 8 L3 M3 TIOA3_1 27 22 17 100 K2 K2 TIOA3_2 97 82 67 60 B9 C9 TIOB3_0 Base timer ch.3 TIOB pin 49 44 34 22 M9 M8 TIOB3_1 17 12 12 90 F3 G3 TIOB3_2 98 83 - 61 C9 B9 Base Timer 4 TIOA4_0 Base timer ch.4 TIOA pin 36 31 21 9 M4 L4 TIOA4_1 28 23 18 1 L1 K3 TIOA4_2 51 - - - - K8 TIOB4_0 Base timer ch.4 TIOB pin 50 45 35 23 L9 L8 TIOB4_1 18 13 - 91 G1 G4 TIOB4_2 52 - - - - L9 Base Timer 5 TIOA5_0 Base timer ch.5 TIOA pin 84 - - - - E11 TIOA5_1 29 24 19 2 L2 L1 TIOA5_2 93 78 63 56 B11 C10 TIOB5_0 Base timer ch.5 TIOB pin 83 - - - - E12 TIOB5_1 19 14 - 92 G2 H1 TIOB5_2 92 77 62 55 A12 B13 Base Timer 6 TIOA6_0 Base timer ch.6 TIOA pin 53 - - - - K9 TIOA6_1 94 79 64 57 B10 A11 TIOA6_2 82 - - - - E13 TIOB6_0 Base timer ch.6 TIOB pin 54 - - - - M10 TIOB6_1 95 80 65 58 A10 B10 TIOB6_2 81 - - - - F10 Base Timer 7 TIOA7_0 Base timer ch.7 TIOA pin 112 - - - - C5 TIOA7_1 86 71 57 49 D13 D13 TIOA7_2 109 - - - - B6 TIOB7_0 Base timer ch.7 TIOB pin 111 - - - - D5 TIOB7_1 87 72 58 50 D12 D12 TIOB7_2 108 - - - - C6 CAN 0 TX0_0 CAN interface ch.0 TX output pin 51 - - - - K8 TX0_1 18 13 - 91 G1 G4 TX0_2 114 94 74 72 B5 C4 RX0_0 CAN interface ch.0 RX output pin 52 - - - - L9 RX0_1 19 14 - 92 G2 H1 RX0_2 113 93 73 71 C5 B5

February 2, 2015, MB9B560R_DS709-00001-2v0-E 37 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 CAN 1 TX1_0 CAN interface ch.1 TX output pin 84 - - - - E11 TX1_2 63 53 42 31 L12 K12 RX1_0 CAN interface ch.1 RX output pin 85 - - - - E10 RX1_2 62 52 41 30 L13 L12 Debugger SWCLK Serial wire debug interface clock input pin 105 90 71 68 A6 B7 SWDIO Serial wire debug interface data input / output pin 103 88 69 66 B7 D7 SWO Serial wire viewer output pin 102 87 68 65 C7 B8 TCK J-TAG test clock input pin 105 90 71 68 A6 B7 TDI J-TAG test data input pin 104 89 70 67 C6 C7 TDO J-TAG debug data output pin 102 87 68 65 C7 B8 TMS J-TAG test mode state input/output pin 103 88 69 66 B7 D7 TRACECLK Trace CLK output pin of ETM 101 86 - 64 C8 C8 TRACED0 Trace data output pin of ETM 97 82 - 60 B9 C9 TRACED1 98 83 - 61 C9 B9 TRACED2 99 84 - 62 A8 A9 TRACED3 100 85 - 63 B8 D8 TRSTX J-TAG test reset input pin 106 91 72 69 B6 D6 External Bus MAD00_0 External bus interface address bus 27 22 17 100 K2 K2 MAD01_0 28 23 18 1 L1 K3 MAD02_0 29 24 19 2 L2 L1 MAD03_0 47 42 32 20 L7 L7 MAD04_0 48 43 33 21 L8 K7 MAD05_0 49 44 34 22 M9 M8 MAD06_0 50 45 35 23 L9 L8 MAD07_0 62 52 41 30 L13 L12 MAD08_0 63 53 42 31 L12 K12 MAD09_0 64 54 43 32 K13 K11 MAD10_0 65 55 44 33 K12 J12 MAD11_0 66 56 45 34 J13 J11 MAD12_0 67 57 46 35 J12 J10 MAD13_0 68 58 47 36 J11 H12 MAD14_0 69 59 48 37 H12 H11 MAD15_0 74 64 53 42 H11 H10 MAD16_0 75 65 54 43 G12 G12 MAD17_0 76 66 55 44 G11 G11 MAD18_0 77 67 56 45 F12 G10 MAD19_0 78 68 - 46 F11 F13 MAD20_0 79 69 - 47 E12 F12 MAD21_0 80 70 - 48 E11 F11 MAD22_0 86 71 - 49 D13 D13 MAD23_0 88 73 - 51 C13 D11 MAD24_0 89 74 - 52 C12 C12

38 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 External Bus MCSX0_0 External bus interface chip select output pin 95 80 65 58 A10 B10 MCSX1_0 96 81 66 59 A9 D9 MCSX2_0 101 86 - 64 C8 C8 MCSX3_0 100 85 - 63 B8 D8 MCSX4_0 98 83 - 61 C9 B9 MCSX5_0 97 82 67 60 B9 C9 MCSX6_0 104 89 70 67 C6 C7 MCSX7_0 106 91 72 69 B6 D6 MCSX8_0 35 30 - 8 L3 M3 MADATA00_0 External bus interface data bus (Address / data multiplex bus) 2 2 2 80 C1 C1 MADATA01_0 3 3 3 81 C2 C2 MADATA02_0 4 4 4 82 C3 D1 MADATA03_0 5 5 5 83 D1 D2 MADATA04_0 6 6 6 84 D2 D3 MADATA05_0 7 7 7 85 E1 E1 MADATA06_0 8 8 8 86 E2 E2 MADATA07_0 9 9 9 87 E3 E3 MADATA08_0 10 10 10 88 F1 E4 MADATA09_0 11 11 11 89 F2 F1 MADATA10_0 12 12 12 90 F3 F2 MADATA11_0 13 13 - 91 G1 F3 MADATA12_0 14 14 - 92 G2 F4 MADATA13_0 15 15 - 93 G3 G1 MADATA14_0 16 16 - 94 H2 G2 MADATA15_0 17 17 - 95 H3 G3 MDQM0_0 External bus interface byte mask signal output pin 93 78 63 56 B11 C10 MDQM1_0 92 77 62 55 A12 B13 MALE_0 External bus interface Address Latch enable output signal for multiplex 94 79 64 57 B10 A11 MRDY_0 External bus interface external RDY input signal 116 96 76 74 B3 B3 MCLKOUT_0 External bus interface external clock output pin 99 84 - 62 A8 A9 MNALE_0 External bus interface ALE signal to control NAND Flash output pin 18 - - - - G4 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 19 - - - - H1 MNREX_0 External bus interface read enable signal to control NAND Flash 21 - - - - H3 MNWEX_0 External bus interface write enable signal to control NAND Flash 20 - - - - H2 MOEX_0 External bus interface read enable signal for SRAM 114 94 74 72 B5 C4 MWEX_0 External bus interface write enable signal for SRAM 113 93 73 71 C5 B5

February 2, 2015, MB9B560R_DS709-00001-2v0-E 39 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 External Bus MSDCLK_0 SDRAM interface SDRAM clock output pin 23 18 - 96 J1 J1 MSDCKE_0 SDRAM interface SDRAM clock enable pin 24 19 - 97 J2 J2 MRASX_0 SDRAM interface SDRAM row address strobe pin 25 20 - 98 J3 J3 MCASX_0 SDRAM interface SDRAM column address strobe pin 26 21 - 99 K1 J4 MSDWEX_0 SDRAM interface SDRAM write enable pin 34 29 - 7 M3 N3 External Interrupt INT00_0 External interrupt request 00 input pin 2 2 2 80 C1 C1 INT00_1 95 80 65 58 A10 B10 INT00_2 108 - - - - C6 INT01_0 External interrupt request 01 input pin 3 3 3 81 C2 C2 INT01_1 101 86 - 64 C8 C8 INT01_2 85 - - - - E10 INT02_0 External interrupt request 02 input pin 6 6 6 84 D2 D3 INT02_1 62 52 41 30 L13 L12 INT02_2 82 - - - - E13 INT03_0 External interrupt request 03 input pin 113 93 73 71 C5 B5 INT03_1 65 55 44 33 K12 J12 INT03_2 54 - - - - M10 INT04_0 External interrupt request 04 input pin 17 12 12 90 F3 G3 INT04_1 114 94 74 72 B5 C4 INT04_2 10 - - - - E4 INT05_0 External interrupt request 05 input pin 89 74 - 52 C12 C12 INT05_1 75 65 54 43 G12 G12 INT05_2 21 16 - 94 H2 H3 INT06_1 External interrupt request 06 input pin 88 73 59 51 C13 D11 INT06_2 22 17 - 95 H3 H4 INT07_1 External interrupt request 07 input pin 11 - - - - F1 INT07_2 7 7 7 85 E1 E1 INT08_1 External interrupt request 08 input pin 19 14 - 92 G2 H1 INT08_2 8 8 8 86 E2 E2 INT09_1 External interrupt request 09 input pin 20 15 - 93 G3 H2 INT09_2 15 10 10 88 F1 G1 INT10_1 External interrupt request 10 input pin 16 11 11 89 F2 G2 INT10_2 112 - - - - C5 INT11_1 External interrupt request 11 input pin 50 45 35 23 L9 L8 INT11_2 110 - - - - A6 INT12_1 External interrupt request 12 input pin 32 27 - 5 N2 N2 INT12_2 96 81 66 59 A9 D9 INT13_1 External interrupt request 13 input pin 33 28 - 6 N3 L2 INT13_2 49 44 34 22 M9 M8 INT14_1 External interrupt request 14 input pin 68 58 47 36 J11 H12 INT14_2 53 - - - - K9 INT15_1 External interrupt request 15 input pin 52 - - - - L9 INT15_2 14 9 9 87 E3 F4

40 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 External Interrupt NMIX Non-Maskable Interrupt input pin 116 96 76 74 B3 B3 GPIO P00 General-purpose I/O port 0 106 91 72 69 B6 D6 P01 105 90 71 68 A6 B7 P02 104 89 70 67 C6 C7 P03 103 88 69 66 B7 D7 P04 102 87 68 65 C7 B8 P05 101 86 - 64 C8 C8 P06 100 85 - 63 B8 D8 P07 99 84 - 62 A8 A9 P08 98 83 - 61 C9 B9 P09 97 82 67 60 B9 C9 P0A 96 81 66 59 A9 D9 P0B 95 80 65 58 A10 B10 P0C 94 79 64 57 B10 A11 P0D 93 78 63 56 B11 C10 P0E 92 77 62 55 A12 B13 P10 General-purpose I/O port 1 62 52 41 30 L13 L12 P11 63 53 42 31 L12 K12 P12 64 54 43 32 K13 K11 P13 65 55 44 33 K12 J12 P14 66 56 45 34 J13 J11 P15 67 57 46 35 J12 J10 P16 68 58 47 36 J11 H12 P17 69 59 48 37 H12 H11 P18 74 64 53 42 H11 H10 P19 75 65 54 43 G12 G12 P1A 76 66 55 44 G11 G11 P1B 77 67 56 45 F12 G10 P1C 78 68 - 46 F11 F13 P1D 79 69 - 47 E12 F12 P1E 80 70 - 48 E11 F11 P1F 81 - - - - F10 P20 General-purpose I/O port 2 89 74 - 52 C12 C12 P21 88 73 59 51 C13 D11 P22 87 72 58 50 D12 D12 P23 86 71 57 49 D13 D13 P24 85 - - - - E10 P25 84 - - - - E11 P26 83 - - - - E12 P27 82 - - - - E13

February 2, 2015, MB9B560R_DS709-00001-2v0-E 41 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 GPIO P30 General-purpose I/O port 3 14 9 9 87 E3 F4 P31 15 10 10 88 F1 G1 P32 16 11 11 89 F2 G2 P33 17 12 12 90 F3 G3 P34 18 13 - 91 G1 G4 P35 19 14 - 92 G2 H1 P36 20 15 - 93 G3 H2 P37 21 16 - 94 H2 H3 P38 22 17 - 95 H3 H4 P39 23 18 13 96 J1 J1 P3A 24 19 14 97 J2 J2 P3B 25 20 15 98 J3 J3 P3C 26 21 16 99 K1 J4 P3D 27 22 17 100 K2 K2 P3E 28 23 18 1 L1 K3 P3F 29 24 19 2 L2 L1 P40 General-purpose I/O port 4 32 27 - 5 N2 N2 P41 33 28 - 6 N3 L2 P42 34 29 - 7 M3 N3 P43 35 30 - 8 L3 M3 P44 36 31 21 9 M4 L4 P45 37 32 22 10 L5 K5 P46 39 34 24 12 N5 N5 P47 40 35 25 13 N6 M5 P48 41 36 26 14 L6 L6 P49 42 37 27 15 M7 K6 P4B 47 42 32 20 L7 L7 P4C 48 43 33 21 L8 K7 P4D 49 44 34 22 M9 M8 P4E 50 45 35 23 L9 L8 P50 General-purpose I/O port 5 2 2 2 80 C1 C1 P51 3 3 3 81 C2 C2 P52 4 4 4 82 C3 D1 P53 5 5 5 83 D1 D2 P54 6 6 6 84 D2 D3 P55 7 7 7 85 E1 E1 P56 8 8 8 86 E2 E2 P57 9 - - - - E3 P58 10 - - - - E4 P59 11 - - - - F1 P5A 12 - - - - F2 P5B 13 - - - - F3

42 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 GPIO P60 General-purpose I/O port 6 116 96 76 74 B3 B3 P61 115 95 75 73 B4 B4 P62 114 94 74 72 B5 C4 P63 113 93 73 71 C5 B5 P64 112 - - - - C5 P65 111 - - - - D5 P66 110 - - - - A6 P67 109 - - - - B6 P68 108 - - - - C6 P70 General-purpose I/O port 7 51 - - - - K8 P71 52 - - - - L9 P72 53 - - - - K9 P73 54 - - - - M10 P74 55 - - - - L10 P80 General-purpose I/O port 8 118 98 78 76 A3 A3 P81 119 99 79 77 A2 A2 PE0 General-purpose I/O port E 56 46 36 24 M10 N10 PE2 58 48 38 26 N11 N11 PE3 59 49 39 27 N12 N12 Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 88 73 59 51 C13 D11 SIN0_1 65 55 44 33 K12 J12 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 87 72 58 50 D12 D12 SOT0_1 (SDA0_1) 66 56 45 34 J13 J11 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). 86 71 57 49 D13 D13 SCK0_1 (SCL0_1) 67 57 46 35 J12 J10 Multi- function Serial SIN1_0 Multi-function serial interface ch.1 input pin 96 81 66 59 A9 D9 SIN1_1 62 52 41 30 L13 L12 SOT1_0 (SDA1_0) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 97 82 67 60 B9 C9 SOT1_1 (SDA1_1) 63 53 42 31 L12 K12 SCK1_0 (SCL1_0) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 4) and as SCL1 when it is used in an I2C (operation mode 4). 98 83 - 61 C9 B9 SCK1_1 (SCL1_1) 64 54 43 32 K13 K11

February 2, 2015, MB9B560R_DS709-00001-2v0-E 43 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Multi- function Serial SIN2_0 Multi-function serial interface ch.2 input pin 53 - - - - K9 SIN2_1 85 - - - - E10 SIN2_2 68 58 47 36 J11 H12 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 54 - - - - M10 SOT2_1 (SDA2_1) 84 - - - - E11 SOT2_2 (SDA2_2) 69 59 48 37 H12 H11 SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). 55 - - - - L10 SCK2_1 (SCL2_1) 83 - - - - E12 SCK2_2 (SCL2_2) 74 64 53 42 H11 H10 Multi- function Serial SIN3_0 Multi-function serial interface ch.3 input pin 110 - - - - A6 SIN3_1 15 10 10 88 F1 G1 SOT3_0 (SDA3_0) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 109 - - - - B6 SOT3_1 (SDA3_1) 16 11 11 89 F2 G2 SCK3_0 (SCL3_0) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). 108 - - - - C6 SCK3_1 (SCL3_1) 17 12 12 90 F3 G3

44 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 6 6 6 84 D2 D3 SIN4_1 75 65 54 43 G12 G12 SIN4_2 10 - - - - E4 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 5 5 5 83 D1 D2 SOT4_1 (SDA4_1) 76 66 55 44 G11 G11 SOT4_2 (SDA4_2) 11 - - - - F1 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). 4 4 4 82 C3 D1 SCK4_1 (SCL4_1) 77 67 56 45 F12 G10 SCK4_2 (SCL4_2) 12 - - - - F2 CTS4_0 Multi-function serial interface ch.4 CTS input pin 2 2 2 80 C1 C1 CTS4_1 78 68 - 46 F11 F13 CTS4_2 13 - - - - F3 RTS4_0 Multi-function serial interface ch.4 RTS output pin 3 3 3 81 C2 C2 RTS4_1 79 69 - 47 E12 F12 RTS4_2 14 9 9 87 E3 F4 Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 114 94 74 72 B5 C4 SIN5_1 113 - - - - B5 SIN5_2 20 15 - 93 G3 H2 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 115 95 75 73 B4 B4 SOT5_1 (SDA5_1) 112 - - - - C5 SOT5_2 (SDA5_2) 21 16 - 94 H2 H3 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). 116 96 76 74 B3 B3 SCK5_1 (SCL5_1) 111 - - - - D5 SCK5_2 (SCL5_2) 22 17 - 95 H3 H4

February 2, 2015, MB9B560R_DS709-00001-2v0-E 45 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 7 7 7 85 E1 E1 SIN6_1 95 80 65 58 A10 B10 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 8 8 8 86 E2 E2 SOT6_1 (SDA6_1) 94 79 64 57 B10 A11 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). 9 - - - - E3 SCK6_1 (SCL6_1) 93 78 63 56 B11 C10 SCS6_1 Multi-function serial interface ch.6 serial chip select pin 92 77 62 55 A12 B13 Multi- function Serial SIN7_0 Multi-function serial interface ch.7 input pin 101 86 - 64 C8 C8 SIN7_1 50 45 35 23 L9 L8 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 100 85 - 63 B8 D8 SOT7_1 (SDA7_1) 49 44 34 22 M9 M8 SCK7_0 (SCL7_0) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). 99 84 - 62 A8 A9 SCK7_1 (SCL7_1) 48 43 33 21 L8 K7 SCS7_1 Multi-function serial interface ch.7 serial chip select pin 47 42 32 20 L7 L7

46 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Multi- function Timer DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 23 18 13 96 J1 J1 DTTI0X_1 79 69 - 47 E12 F12 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 18 13 - 91 G1 G4 FRCK0_1 80 70 - 48 E11 F11 FRCK0_2 62 52 41 30 L13 L12 IC00_0 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. 22 17 - 95 H3 H4 IC00_1 75 65 54 43 G12 G12 IC00_2 63 53 42 31 L12 K12 IC01_0 21 16 - 94 H2 H3 IC01_1 76 66 55 44 G11 G11 IC01_2 64 54 43 32 K13 K11 IC02_0 20 15 - 93 G3 H2 IC02_1 77 67 56 45 F12 G10 IC02_2 65 55 44 33 K12 J12 IC03_0 19 14 - 92 G2 H1 IC03_1 78 68 - 46 F11 F13 IC03_2 66 56 45 34 J13 J11 RTO00_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 24 19 14 97 J2 J2 RTO00_1 (PPG00_1) 86 71 57 49 D13 D13 RTO01_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 25 20 15 98 J3 J3 RTO01_1 (PPG00_1) 85 - - - - E10 RTO02_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 26 21 16 99 K1 J4 RTO02_1 (PPG02_1) 84 - - - - E11 RTO03_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 27 22 17 100 K2 K2 RTO03_1 (PPG02_1) 83 - - - - E12 RTO04_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 28 23 18 1 L1 K3 RTO04_1 (PPG04_1) 82 - - - - E13 RTO05_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 29 24 19 2 L2 L1 RTO05_1 (PPG04_1) 81 - - - - F10

February 2, 2015, MB9B560R_DS709-00001-2v0-E 47 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Multi- function Timer DTTI1X_0 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 8 8 8 86 E2 E2 DTTI1X_1 55 - - - - L10 FRCK1_0 16-bit free-run timer ch.1 external clock input pin 96 81 66 59 A9 D9 FRCK1_1 50 45 35 23 L9 L8 IC10_0 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. 95 80 65 58 A10 B10 IC10_1 54 - - - - M10 IC11_0 94 79 64 57 B10 A11 IC11_1 53 - - - - K9 IC12_0 93 78 63 56 B11 C10 IC12_1 52 - - - - L9 IC13_0 92 77 62 55 A12 B13 IC13_1 51 - - - - K8 RTO10_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 2 2 2 80 C1 C1 RTO10_1 (PPG10_1) 32 27 - 5 N2 N2 RTO11_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 3 3 3 81 C2 C2 RTO11_1 (PPG10_1) 33 28 - 6 N3 L2 RTO12_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 4 4 4 82 C3 D1 RTO12_1 (PPG12_1) 34 29 - 7 M3 N3 RTO13_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 5 5 5 83 D1 D2 RTO13_1 (PPG12_1) 35 30 - 8 L3 M3 RTO14_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 6 6 6 84 D2 D3 RTO14_1 (PPG14_1) 36 31 21 9 M4 L4 RTO15_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 7 7 7 85 E1 E1 RTO15_1 (PPG14_1) 37 32 22 10 L5 K5

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Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 Quadrature Position/ Revolution Counter AIN0_0 QPRC ch.0 AIN input pin 24 19 14 97 J2 J2 AIN0_1 51 - - - - K8 AIN0_2 2 2 2 80 C1 C1 BIN0_0 QPRC ch.0 BIN input pin 25 20 15 98 J3 J3 BIN0_1 52 - - - - L9 BIN0_2 3 3 3 81 C2 C2 ZIN0_0 QPRC ch.0 ZIN input pin 26 21 16 99 K1 J4 ZIN0_1 53 - - - - K9 ZIN0_2 4 4 4 82 C3 D1 Quadrature Position/ Revolution Counter AIN1_0 QPRC ch.1 AIN input pin 10 - - - - E4 AIN1_1 89 74 - 52 C12 C12 AIN1_2 48 43 33 21 L8 K7 BIN1_0 QPRC ch.1 BIN input pin 11 - - - - F1 BIN1_1 88 73 - 51 C13 D11 BIN1_2 49 44 34 22 M9 M8 ZIN1_0 QPRC ch.1 ZIN input pin 12 - - - - F2 ZIN1_1 87 72 - 50 D12 D12 ZIN1_2 50 45 35 23 L9 L8 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 115 95 75 73 B4 B4 RTCCO_1 64 54 43 32 K13 K11 RTCCO_2 23 18 13 96 J1 J1 SUBOUT_0 Sub clock output pin 115 95 75 73 B4 B4 SUBOUT_1 64 54 43 32 K13 K11 SUBOUT_2 23 18 13 96 J1 J1 USB UDM0 USB function/host D – pin 118 98 78 76 A3 A3 UDP0 USB function/host D + pin 119 99 79 77 A2 A2 UHCONX0 USB external pull-up control pin 115 95 75 73 B4 B4 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 116 96 76 74 B3 B3 WKUP1 Deep standby mode return signal input pin 1 14 9 9 87 E3 F4 WKUP2 Deep standby mode return signal input pin 2 50 45 35 23 L9 L8 WKUP3 Deep standby mode return signal input pin 3 69 59 48 37 H12 H11 DAC DA0 D/A converter ch.0 analog output pin 36 31 21 9 M4 L4 DA1 D/A converter ch.1 analog output pin 37 32 22 10 L5 K5 VBAT VREGCTL On-board regulator control pin 41 36 26 14 L6 L6 VWAKEUP The return signal input pin from a hibernation state 42 37 27 15 M7 K6 SD I/F S_CLK_0 SD memory card interface SD memory card clock output pin 92 77 62 55 A12 B13 S_CMD_0 SD memory card interface SD memory card command output 93 78 63 56 B11 C10 S_DATA1_0 SD memory card interface SD memory card data bus 94 79 64 57 B10 A11 S_DATA0_0 95 80 65 58 A10 B10 S_DATA3_0 96 81 66 59 A9 D9 S_DATA2_0 97 82 67 60 B9 C9 S_CD_0 SD memory card interface SD memory card detection pin 113 93 73 71 C5 B5 S_WP_0 SD memory card interface SD memory card write protection 114 94 74 72 B5 C4

February 2, 2015, MB9B560R_DS709-00001-2v0-E 49 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 RESET INITX External Reset Input pin. A reset is valid when INITX="L". 38 33 23 11 M6 N4 MODE MD1 Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. 56 46 36 24 M10 N10 MD0 Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. 57 47 37 25 M11 M11 POWER VCC Power supply Pin 1 1 1 79 B1 B1 31 26 - 4 M1 M1 46 41 31 19 M8 M9 61 51 - 29 M13 M13 91 76 61 54 B13 A12 USBVCC 3.3 V Power supply port for USB I/O 117 97 77 75 A4 A4 GND VSS GND Pin 107 92 - 70 A5 A7 30 25 20 3 N1 N1 45 40 30 18 N10 N9 60 50 40 28 N13 N13 90 75 60 53 A13 A13 120 100 80 78 A1 A1 - - - - A7 A5 - - - - B2 A8 - - - - B12 A10 - - - - C11 B2 - - - - H1 B11 - - - - N4 B12 - - - - M5 C3 - - - - N7 C11 - - - - L11 C13 - - - - A11 D4 - - - - M12 D10 - - - - M2 K1 - - - - - K4 - - - - - K10 - - - - - L3 - - - - - L5 - - - - - L11 - - - - - L13 - - - - - M2 - - - - - M4 - - - - - M6 - - - - - M7 - - - - - M12 - - - - - N6

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Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP QFP 100 BGA 112 BGA 144 CLOCK X0 Main clock (oscillation) input pin 58 48 38 26 N11 N11 X1 Main clock (oscillation) I/O pin 59 49 39 27 N12 N12 X0A Sub clock (oscillation) input pin 39 34 24 12 N5 N5 X1A Sub clock (oscillation) I/O pin 40 35 25 13 N6 M5 CROUT_0 Built-in high-speed CR-osc clock output port 87 72 58 50 D12 D12 CROUT_1 113 93 73 71 C5 B5 ADC POWER AVCC A/D converter and D/A converter analog power supply pin 70 60 49 38 H13 K13 AVRL A/D converter analog reference voltage input pin 72 62 51 40 F13 H13 AVRH A/D converter analog reference voltage input pin 73 63 52 41 E13 G13 VBAT POWER VBAT VBAT power supply pin. Backup power supply (battery etc.) and system power supply. 43 38 28 16 N8 N7 ADC GND AVSS A/D converter and D/A converter GND pin 71 61 50 39 G13 J13 C pin C Power supply stabilization capacity pin 44 39 29 17 N9 N8

February 2, 2015, MB9B560R_DS709-00001-2v0-E 51 CONFIDENTIAL 7. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. − Oscillation feedback resistor : Approximately 1 MΩ − With Standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA B − CMOS level hysteresis input − Pull-up resistor : Approximately 50 kΩ P-chP-ch N-ch R R P-chP-ch N-ch Standby mode control Digital input Standby mode control Digital output Digital output Clock input Digital input Standby mode control Pull-up resistor control Pull-up resistor control Digital output Digital output Pull-up resistor Digital input

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C − Open drain output − CMOS level hysteresis input E − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA F − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA N-ch P-chP-ch N-ch R P-chP-ch N-ch R Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

February 2, 2015, MB9B560R_DS709-00001-2v0-E 53 CONFIDENTIAL Type Circuit Remarks G − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA H It is possible to select the USB I/O / GPIO function. When the USB I/O is selected. − Full-speed, Low-speed control When the GPIO is selected. − CMOS level output − CMOS level hysteresis input − With standby mode control − IOH = -20.5 mA, IOL = 18.5 mA P-chP-ch N-ch R UDP/Pxx UDM/Pxx Differential Standby mode control Pull-up resistor control Digital input Digital output Digital output GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output USB Full-speed/Low-speed control UDP input Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control

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I − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. J CMOS level hysteresis input L − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA P-chP-ch N-ch R P-chP-ch N-ch R Standby mode control Pull-up resistor control Digital input Digital output Digital output Mode input Digital output Digital output Pull-up resistor control Digital input Standby mode control

February 2, 2015, MB9B560R_DS709-00001-2v0-E 55 CONFIDENTIAL Type Circuit Remarks M − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA N − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA (GPIO) − IOL = 20 mA (Fast Mode Plus) P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Digital output Digital output Pull-up resistor control Digital input Standby mode control

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O − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P-ch P-ch N-ch R P-ch P-ch N-ch R Digital output Digital output Digital input Pull-up resistor control Standby mode control Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC X0A

February 2, 2015, MB9B560R_DS709-00001-2v0-E 57 CONFIDENTIAL Type Circuit Remarks Q It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 10 MΩ − With Standby mode control − When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual R − CMOS level output − CMOS level hysteresis input − Analog output − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA (4.5 V to 5.5 V) − IOH = -8 mA, IOL = 8 mA (2.7 V to 4.5 V) P-ch P-ch N-ch R RX P-ch N-ch R P-ch X1A Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC Standby mode control Clock input Pull-up resistor control Digital input Standby mode control Analog output Digital output Digital output

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Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices.

8.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Code: DS00-00004-3E

February 2, 2015, MB9B560R_DS709-00001-2v0-E 59 CONFIDENTIAL Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

8.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.

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Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and have established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 61 CONFIDENTIAL

8.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

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Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power Supply Pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. − Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF − Lead type Load capacitance : Approximately 6 pF to 7 pF

February 2, 2015, MB9B560R_DS709-00001-2v0-E 63 CONFIDENTIAL Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Handling when Using Multi-function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input Device C VSS CS GND

64 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: VBAT → VCC → USBVCC VCC → AVCC → AVRH Turning off: USBVCC → VCC → VBAT AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O. Adjoining Wiring on Circuit Board If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Handling when Using Debug Pins When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. P47/ X1A P48/ VREGCTL Ground P46/ X0A P49/ VWAKEUP Not allowed to run both wirings in parallel Insert the ground pattern Device

February 2, 2015, MB9B560R_DS709-00001-2v0-E 65 CONFIDENTIAL 10. Block Diagram Cortex-M4 Core @160 MHz(Max) MainFlash I/F Clock Reset Generator Dual-Timer Watchdog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 16pin + NMI Power-On Reset SRAM0 32/48/64 Kbytes AHB-APB Bridge : APB1 (Max 160 MHz) SRAM1 16/24/32 Kbytes AHB-APB Bridge: APB0(Max 80 MHz) I D Sys CLK MB9BF566M/N/R, F567M/N/R, F568M/N/R AHB-APB Bridge : APB2 (Max 80 MHz) NVIC Watchdog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, PEx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator AHB-AHB Bridge ADTGx RTS4 CTS4 MADx MADATAx MainFlash

1 Mbytes/

768 Kbytes/

512 Kbytes

8ch. HW flow control(ch.4) External Bus I/F GPIO PIN-Function-Ctrl LVD Multi-layer AHB (Max 160 MHz) TPIU* ROM Table ETM*SWJ-DP Main Osc PLL CR 100 kHz LVD Ctrl Base Timer 16-bit 16ch./ 32-bit 8ch. Peripheral Clock Gating Low-speed CR Prescaler RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 6ch. 16-bit PPG 3ch. DTTI0X FRCK0 QPRC 2ch.BINx ZINx IC0x RTO0x AINx 12-bit A/D Converter Multi-function Timer × 2 MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX Waveform Generator 3ch. MPUFPU 12-bit D/A Converter 2units SRAM2 16/24/32 Kbytes WorkFlash

32 KbytesWorkFlash I/F

(16 Kbytes) DSTC CAN USB2.0 (Host/ Func) PHY USBVCC UDP0,UDM0 UHCONX0 CAN TX0, RX0 TX1, RX1 SD-CARD I/F S_CLK,S_CMD S_DATAx S_CD,S_WP CAN Prescaler USB Clock Ctrl PLL VREGCTL VWAKEUP Unit 2 DAx Real-Time Clock Port Ctrl. Sub Osc VBAT Domain VBAT Domain CR

4 MHz

*: For the MB9BF566M, MB9BF567M and MB9BF568M, ETM is not available.

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Memory Size See Memory size in 3. Product Lineup to confirm the memory size. 12. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0x4007_0000 0x4006_F000 GPIO 0x4006_E000 SD-Card I/F 0x4006_4000 0xFFFF_FFFF 0x4006_3000 CAN ch.1 0x4006_2000 CAN ch.0 0xE010_0000 0x4006_1000 DSTC 0x4006_0000 DMAC 0xE000_0000 0x4005_0000 0x4004_0000 USB ch.0 0x4003_F000 EXT-bus I/F 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x6000_0000 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4400_0000 0x4003_8000 MFS 0x4003_7000 CAN prescaler 0x4200_0000 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 D/AC 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_8000 0x2010_0000 0x4002_7000 A/DC 0x200E_0000 WorkFlash I/F 0x4002_6000 QPRC 0x200C_0000 WorkFlash 0x4002_5000 Base Timer 0x4002_4000 PPG 0x2004_8000 0x2004_0000 SRAM2 0x4002_2000 0x2003_8000 SRAM1 0x4002_1000 MFT Unit1 0x2000_0000 Reserved 0x4002_0000 MFT Unit0 0x1FFF_0000 SRAM0 0x0050_0000 Reserved 0x4001_6000 0x0040_0000 Security/CR Trim 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x0000_0000 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 MainFlash I/F Reserved Reserved Reserved Reserved Cortex-M4 Private Peripherals Reserved Reserved External Device Area Reserved See "lMemory Map (2)" for the memory size details. MainFlash Reserved Reserved Peripherals

32 Mbytes

February 2, 2015, MB9B560R_DS709-00001-2v0-E 67 CONFIDENTIAL Memory Map (2) MB9BF568M/N/R MB9BF567M/N/R MB9BF566M/N/R 0x2008_0000 0x2008_0000 0x2008_0000 0x200C_8000 0x200C_8000 0x200C_8000 0x200C_0000 0x200C_0000 0x200C_0000 0x2004_8000 0x2004_6000 0x2004_4000 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_C000 0x2003_A000 0x2003_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_8000 0x1FFF_4000 0x1FFF_0000 0x0050_0000 0x0050_0000 0x0050_0000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security 0x0010_0000 0x000C_0000 0x0008_0000 0x0000_0000 0x0000_0000 0x0000_0000 SRAM2

24 Kbytes

1 Mbytes

64 Kbytes

32 Kbytes

768 Kbytes

48 Kbytes

16 Kbytes

68 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB MainFlash I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4003_FFFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_4FFF Reserved 0x4003_3000 0x4003_3FFF D/A Converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF RTC/Port Ctrl 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF AHB USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF SD-Card I/F 0x4006_F000 0x4006_FFFF GPIO 0x4006_7000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF WorkFlash I/F register

February 2, 2015, MB9B560R_DS709-00001-2v0-E 69 CONFIDENTIAL 13. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation.

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Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

February 2, 2015, MB9B560R_DS709-00001-2v0-E 71 CONFIDENTIAL Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or SLEEP Mode State TIMER Mode, RTC Mode, or STOP Mode State Deep Standby RTC Mode or Deep Standby STOP Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected F NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state G JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected H JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected I Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

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Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - J Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *2 *3 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

February 2, 2015, MB9B560R_DS709-00001-2v0-E 73 CONFIDENTIAL Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected N Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected

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Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - O Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External interrupt enabled selected Maintain previous state Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected

February 2, 2015, MB9B560R_DS709-00001-2v0-E 75 CONFIDENTIAL Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - Q WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected R GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected USB I/O pin Setting disabled Setting disabled Setting disabled Hi-Z at trans- mission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z at trans- mission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.

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List of VBAT Domain Pin Status VBAT Pin Status Type Function Group VBAT Power-on Reset INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - - - S GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibiti on Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state T GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibiti on External sub clock input selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Maintain previous state Maintain previous state Maintain previous state Maintain previous state/W hen oscillati on stops, Hi-Z* Maintain previous state/Wh en oscillatio n stops, Hi-Z* Maintain previous state/Whe n oscillation stops, Hi-Z* Maintain previous state/Wh en oscillatio n stops, Hi-Z* Maintain previous state Maintain previous state Maintain previous state U Resource selected Hi-Z Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected *: When the SOSCNTL bit in the WTOSCCNT Register is 0, Sub crystal oscillator output pin is maintain previous state. When the SOSCNTL bit in the WTOSCCNT Register is 1,oscillation is stopped at Stop mode and Deep Standby Stop mode.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 77 CONFIDENTIAL 14. Electrical Characteristics

14.1 Absolute Maximum Ratings

Power supply voltage *1, *2 VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB)*1, * 3 USBVCC VSS - 0.5 VSS + 6.5 V Power supply voltage (VBAT) *1 ,*4 VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage *1 ,*5 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage *1 ,*5 AVRH VSS - 0.5 VSS + 6.5 V Input voltage *1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5V) V Except for USB pin VSS - 0.5 USBVCC + 0.5 (≤ 6.5V) V USB pin VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage *1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5V) V Output voltage *1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5V) V "L" level maximum output current *6 IOL - 10 mA 4 mA type 20 mA 8 mA type 20 mA 12 mA type 22.4 mA I2C Fm+ "L" level average output current *7 IOLAV - 4 mA 4 mA type 8 mA 8 mA type 12 mA 12 mA type 20 mA I2C Fm+ "L" level total maximum output current ∑IOL - 100 mA "L" level total maximum output current *8 ∑IOLAV - 50 mA "H" level maximum output current *6 IOH - - 10 mA 4 mA type 20 mA 8 mA type - 20 mA 12 mA type "H" level average output current *7 IOHAV - - 4 mA 4 mA type 8 mA 8 mA type - 12 mA 12 mA type "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current *8 ∑IOHAV - - 50 mA Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: USBVCC must not drop below VSS - 0.5 V. *4: VBAT must not drop below VSS - 0.5 V. *5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period.

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*8: The total average output current is defined as the average current value flowing through all of corresponding pins for a period of 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 79 CONFIDENTIAL

14.2 Recommended Operating Conditions

Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7*5 5.5 V Power supply voltage (for USB) USBVCC - 3.0 3.6 (≤ VCC) V 2.7 5.5 (≤ VCC) Power supply voltage (VBAT) VBAT - 2.7 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC=VCC Analog reference voltage AVRH - *4 AVCC V Operating temperature Junction temperature Tj - - 40 + 125 °C Ambient temperature Ta - - 40 *3 °C *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3: The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (Ta) is shown below. Ta(Max) = Tj(Max) - Pd(Max) × θja Pd: Power dissipation (W) θja: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. *4: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See "5. 12-bit A/D Converter" for the details. *5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only.

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Table for Package Thermal Resistance and Maximum Permissible Power Package Printed Circuit Board Thermal Resistance θja (°C/W) Maximum Permissible Power (mW) Ta=+85 °C Ta=+105 °C FPT-80P-M37 (0.5 mm pitch) Single-layered both sides 60 667 333 4 layers 39 1026 513 FPT-80P-M40 (0.65 mm pitch) Single-layered both sides 58 690 335 4 layers 38 1053 526 FPT-100P-M23 (0.5 mm pitch) Single-layered both sides 57 702 351 4 layers 38 1053 526 FPT-100P-M36 (0.65 mm pitch) Single-layered both sides 48 833 417 4 layers 34 1177 588 FPT-120P-M37 (0.5 mm pitch) Single-layered both sides 62 645 323 4 layers 43 930 465 BGA-112P-M05 (0.5 mm pitch) Single-layered both sides 60 667 333 4 layers 40 1000 500 BGA-144P-M09 (0.5 mm pitch) Single-layered both sides 55 727 364 4 layers 40 1000 500 WARNING: 1. The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 81 CONFIDENTIAL Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: "L" level output current IOH: "H" level output current VOL: "L" level output voltage VOH: "H" level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CINT 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Symbol Conditions Current Value Maximum leak current at operating ICC(leak_max) Tj = +125 °C 45.5 mA Tj = +105 °C 26.8 mA Tj = +85 °C 16.2 mA

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Current Explanation Diagram A V ・・・・・・・・・ V A A Regulator Logic Flash RAM ICC ICC(INT) ΣICC(IO) IOL VOL VOH IOH ICC(IO) Chip VCC CEXT Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC = ICC(INT)＋ΣICC(IO)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 83 CONFIDENTIAL

14.3 DC Characteristics

14.3.1 Current Rating

Table 14-1 Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory (Flash accelerator mode and trace buffer function enabled) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL) *5, *6

160 MHz 54 103

144 MHz 49 98

120 MHz 41 90

100 MHz 35 84

80 MHz 28 77

60 MHz 22 71

40 MHz 16 64

20 MHz 8.9 58 8 MHz 5.1 54 4 MHz 3.8 53

160 MHz 34 83

144 MHz 31 80

120 MHz 26 75

100 MHz 22 71

80 MHz 18 67

60 MHz 14 63

40 MHz 10 59

20 MHz 6.2 55 8 MHz 3.8 53 4 MHz 3.1 52 Table 14-2 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (Flash accelerator mode and trace buffer function disabled) Parameter Symbol Pin Name Conditions Frequency*7 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL)

160 MHz 74 126

144 MHz 68 120

120 MHz 59 112

100 MHz 52 104

80 MHz 44 97

60 MHz 36 89

40 MHz 27 79

20 MHz 17 67

8 MHz 8.3 58 4 MHz 5.4 55

160 MHz 51 103

144 MHz 47 100

120 MHz 42 94

100 MHz 37 90

80 MHz 33 85

60 MHz 28 80

40 MHz 21 73

20 MHz 13 64

8 MHz 6.9 56 4MHz 4.6 54

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*1: Ta=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) Table 14-3 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait) Parameter Symbol Pin Name Conditions Frequency*4 (MHz) Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL)

72 MHz 46 98

60 MHz 40 92

48 MHz 33 85

36 MHz 27 78

24 MHz 19 70

12 MHz 11 61

8 MHz 8.5 58 4 MHz 5.5 55

72 MHz 33 85

60 MHz 29 81

48 MHz 25 76

36 MHz 20 71

24 MHz 15 65

12 MHz 9.2 59 8 MHz 6.9 56 4 MHz 4.6 54 *1: Ta=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 85 CONFIDENTIAL Table 14-4 Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait) *1: Ta=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (built-in high-speed CR) *5 4 MHz 3.3 51 mA When all peripheral clocks are ON 2.8 51 mA When all peripheral clocks are OFF Normal operation (sub oscillation) *5 32 kHz 0.64 48 mA When all peripheral clocks are ON 0.56 48 mA When all peripheral clocks are OFF Normal operation (built-in low-speed CR) *5 100 kHz 0.64 48 mA When all peripheral clocks are ON 0.58 48 mA When all peripheral clocks are OFF

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Table 14-5 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC SLEEP operation (PLL)

160 MHz 35 84

144 MHz 32 81

120 MHz 27 76

100 MHz 23 72

80 MHz 19 68

60 MHz 15 64

40 MHz 11 60

20 MHz 6.5 55 8 MHz 4.1 53 4 MHz 3.3 52

160 MHz 16 65

144 MHz 14 63

120 MHz 12 61

100 MHz 11 60

80 MHz 9.0 58 60 MHz 7.4 56 40 MHz 5.6 54 20 MHz 3.9 53 8 MHz 2.9 52 4 MHz 2.6 51

February 2, 2015, MB9B560R_DS709-00001-2v0-E 87 CONFIDENTIAL Table 14-6 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Symbol Pin Name Conditions Frequency*5 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC SLEEP operation (PLL)

72 MHz 22 71

60 MHz 19 68

48 MHz 16 64

36 MHz 12 61

24 MHz 9.0 58 12 MHz 5.8 55 8 MHz 4.6 54 4 MHz 3.6 52 72 MHz 9.5 58 mA When all peripheral clocks are OFF 60 MHz 8.3 57 48 MHz 7.1 56 36 MHz 5.8 55 24 MHz 4.6 53 12 MHz 3.5 52 8 MHz 3.0 52 4 MHz 2.7 51 *1: Ta=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3 : When all ports are fixed. *4 : Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5 : Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK

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Table 14-7 Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *1: Ta=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC SLEEP operation (built-in high-speed CR) 1.5 49 mA When all peripheral clocks are ON 1.0 49 mA When all peripheral clocks are OFF SLEEP operation (sub oscillation) 32 kHz 0.59 48 mA When all peripheral clocks are ON 0.51 48 mA When all peripheral clocks are OFF SLEEP operation (built-in low-speed CR) 100 kHz 0.61 48 mA When all peripheral clocks are ON 0.53 48 mA When all peripheral clocks are OFF

February 2, 2015, MB9B560R_DS709-00001-2v0-E 89 CONFIDENTIAL Table 14-8 Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCH VCC STOP mode - 0.33 1.8 mA *3, *4 Ta=+25°C - 15 mA *3, *4 Ta=+85°C - 22 mA *3, *4 Ta=+105°C ICCT TIMER mode (built-in high-speed CR) 0.70 2.2 mA *3, *4 Ta=+25°C - 16 mA *3, *4 Ta=+85°C - 22 mA *3, *4 Ta=+105°C TIMER mode (sub oscillation) 32 kHz 0.33 1.8 mA *3, *4 Ta=+25°C - 15 mA *3, *4 Ta=+85°C - 22 mA *3, *4 Ta=+105°C TIMER mode (built-in low-speed CR) 100 kHz 0.34 1.8 mA *3, *4 Ta=+25°C - 15 mA *3, *4 Ta=+85°C - 22 mA *3, *4 Ta=+105°C ICCR RTC mode (sub oscillation) 32 kHz 0.33 1.8 mA *3, *4 Ta=+25°C - 15 mA *3, *4 Ta=+85°C - 22 mA *3, *4 Ta=+105°C

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Table 14-9 Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCHD VCC Deep standby STOP mode (When RAM is OFF) 29 140 µA *3, *4 Ta=+25°C - 644 µA *3, *4 Ta=+85°C - 1011 µA *3, *4 Ta=+105°C Deep standby STOP mode (When RAM is ON) 48 273 µA *3, *4 Ta=+25°C - 2676 µA *3, *4 Ta=+85°C - 4162 µA *3, *4 Ta=+105°C ICCRD Deep standby RTC mode (When RAM is OFF) 32 kHz 29 140 µA *3, *4 Ta=+25°C - 644 µA *3, *4 Ta=+85°C - 1011 µA *3, *4 Ta=+105°C Deep standby RTC mode (When RAM is ON) 48 273 µA *3, *4 Ta=+25°C - 2676 µA *3, *4 Ta=+85°C - 4162 µA *3, *4 Ta=+105°C ICCVBAT VBAT RTC stop 0.015 0.29 µA *3, *4, *5 Ta=+25°C - 5.77 µA *3, *4, *5 Ta=+85°C - 10.6 µA *3, *4, *5 Ta=+105°C RTC operation 1.53 22.6 µA *3, *4 Ta=+25°C - 35.2 µA *3, *4 Ta=+85°C - 41.8 µA *3, *4 Ta=+105°C

February 2, 2015, MB9B560R_DS709-00001-2v0-E 91 CONFIDENTIAL Table 14-10 Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase Peripheral current dissipation Clock System Peripheral Unit Frequency (MHz) Unit Remarks 40 80 160 HCLK GPIO All ports 0.22 0.43 0.85 mA DMAC - 0.74 1.48 2.88 DSTC - 0.32 0.61 1.17 External bus I/F - 0.14 0.27 0.55 SD card I/F - 0.93 1.81 3.63 CAN 1ch. 0.02 0.06 0.11 USB 1ch. 0.34 0.67 1.33 PCLK1 Base timer 4ch. 0.16 0.34 0.66 mA Multi-functional timer/PPG 1 unit/4ch. 0.55 1.09 2.17 Quadrature position/Revolution counter 1 unit 0.04 0.09 0.17 A/DC 1 unit 0.20 0.39 0.78 PCLK2 Multi-function serial 1ch. 0.31 0.62 - mA Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation - 4 7 μA For occurrence of interrupt Main flash memory write/erase current ICCFLASH At Write/Erase - 13.4 15.9 mA Work flash memory write/erase current ICCWFLASH At Write/Erase - 11.5 13.6 mA

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14.3.2 Pin Characteristics

(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "H" level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC×0.8 - VCC + 0.3 V 5V tolerant input pin - VCC×0.8 - VSS + 5.5 V Input pin doubled as I2C Fm+ - VCC×0.7 - VSS + 5.5 V "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC×0.2 V 5V tolerant input pin - VSS - 0.3 - VCC×0.2 V Input pin doubled as I2C Fm+ - VSS - VCC×0.3 V "H" level output voltage VOH 4mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 8mA type VCC ≥ 4.5 V, IOH = - 8 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 4 mA 12mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA The pin doubled as USB I/O USBVCC ≥ 4.5 V, IOH = - 20.5 mA USBVCC - 0.4 - USBVCC V USBVCC < 4.5 V, IOH = - 13.0 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V At GPIO VCC < 4.5 V, IOH = - 3 mA

February 2, 2015, MB9B560R_DS709-00001-2v0-E 93 CONFIDENTIAL Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "L" level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 8 mA type VCC ≥ 4.5 V, IOH = 8 mA VSS - 0.4 V VCC < 4.5 V, IOH = 4 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA The pin doubled as USB I/O USBVCC ≥ 4.5 V, IOL = 18.5 mA VSS - 0.4 V USBVCC < 4.5 V, IOL = 10.5 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOH = 4 mA VSS - 0.4 V At GPIO VCC < 4.5 V, IOH = 3 mA VCC ≤ 5.5 V, IOH = 20 mA At I2C Fm+ Input leak current IIL - - - 5 - + 5 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC < 4.5 V 30 80 200 Input capacitance CIN Other than VCC, USBVCC, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF

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14.4 AC Characteristics

14.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 VCC ≥ 4.5 V 4 48 MHz When using external clock VCC < 4.5 V 4 20 Input clock cycle tCYLH VCC ≥ 4.5 V 20.83 250 ns When using external clock VCC < 4.5 V 50 250 Input clock pulse width PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCC - - - 160 MHz Base clock (HCLK/FCLK) fCP0 - - - 80 MHz APB0 bus clock*2 fCP1 - - - 160 MHz APB1 bus clock*2 fCP2 - - - 80 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 6.25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 12.5 - ns APB0 bus clock*2 tCYCP1 - - 6.25 - ns APB1 bus clock*2 tCYCP2 - - 12.5 - ns APB2 bus clock*2 *1 : For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (MN709-00001). *2 : For about each APB bus which each peripheral is connected to, see 10. Block Diagram in this data sheet.

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14.4.2 Sub Clock Input Characteristics

(VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Input frequency 1/ tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock

14.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TJ = -20°C to +105°C 3.92 4 4.08 MHz When trimming*1 TJ = - 40°C to +125°C 3.88 4 4.12 Clock frequency fCRH TJ = - 40°C to +125°C 3 4 5 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz X0A VBAT VBAT VBAT VBAT 0.8 × VBAT

96 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock

for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz Main PLL clock frequency*2 fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Family Peripheral Manual Main part (MN709-00001).

14.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock

for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz USB clock frequency*2 fCLKSPLL - - 48 MHz After the M frequency division *1 : Time from when the PLL starts operating until the oscillation stabilizes. *2 : For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4 Family Peripheral Manual Communication Macro part (MN709-00004).

14.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in

High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 75 multiplier PLL macro oscillation clock frequency fPLLO 190 - 320 MHz Main PLL clock frequency*2 fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (MN709-00001). Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 97 CONFIDENTIAL

14.4.7 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Condition Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

14.4.8 Power-on Reset Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Max Power supply rising time Tr VCC 0 - ms Power supply shut down time Toff 1 - ms Time until releasing Power-on reset Tprt 0.33 0.60 ms 0.2V VDL_minimum VCC_minimum Tprt Internal RST VCC CPU Operation start RST Active Release Tr 0.2V 0.2V Toff Glossary − VCC_minimum: Minimum VCC of recommended operating conditions. − VDL_minimum: Minimum detection voltage of Low-Voltage detection reset. See 8. Low-Voltage Detection Characteristics.

98 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.9 GPIO Output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Output frequency tPCYCLE Pxx* VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE

February 2, 2015, MB9B560R_DS709-00001-2v0-E 99 CONFIDENTIAL

14.4.10 External Bus Timing

External Bus Clock Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT*1 VCC ≥ 4.5 V - 50*2 MHz VCC < 4.5 V - 32*3 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see CHAPTER 14: External Bus Interface in FM4 Family Peripheral Manual Main part (MN709-00001). *2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz. *3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz. External Bus Signal Input/output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V 0.8 × Vcc0.8 × Vcc tCYCLE VIH VIL VIL VIH VOH VOL VOL VOH MCLK Signal input Signal output

100 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max MOEX Mininum pulse width tOEW MOEX VCC ≥ 4.5V MCLK×n-3 - ns VCC < 4.5V MCSX↓→Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] VCC ≥ 4.5V -9 +9 ns VCC < 4.5V -12 +12 MOEX↑→Address hold time tOEH - AX MOEX, MAD[24:0] VCC ≥ 4.5V MCLK×m+9 ns VCC < 4.5V MCLK×m+12 MCSX↓→ MOEX↓ delay time tCSL - OEL MOEX, MCSX[7:0] VCC ≥ 4.5V MCLK×m-9 MCLK×m+9 ns VCC < 4.5V MCLK×m-12 MCLK×m+12 MOEX↑→ MCSX↑ time tOEH - CSH VCC ≥ 4.5V MCLK×m+9 ns VCC < 4.5V MCLK×m+12 MCSX↓→MDQM↓ delay time tCSL - RDQML MCSX, MDQM[1:0] VCC ≥ 4.5V MCLK×m-9 MCLK×m+9 ns VCC < 4.5V MCLK×m-12 MCLK×m+12 Data set up→MOEX↑ time tDS - OE MOEX, MADATA[15:0] VCC ≥ 4.5V 20 - ns VCC < 4.5V 38 - MOEX↑→ Data hold time tDH - OE MOEX, MADATA[15:0] VCC ≥ 4.5V 0 - ns VCC < 4.5V MWEX Mininum pulse width tWEW MWEX VCC ≥ 4.5V MCLK×n-3 - ns VCC < 4.5V MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24:0] VCC ≥ 4.5V MCLK×m+9 ns VCC < 4.5V MCLK×m+12 MCSX↓→MWEX↓ delay time tCSL - WEL MWEX, MCSX[7:0] VCC ≥ 4.5V MCLK×n-9 MCLK×n+9 ns VCC < 4.5V MCLK×n-12 MCLK×n+12 MWEX↑→MCSX↑ delay time tWEH - CSH VCC ≥ 4.5V MCLK×m+9 ns VCC < 4.5V MCLK×m+12 MCSX↓→MDQM↓ delay time tCSL-WDQML MCSX, MDQM[1:0] VCC ≥ 4.5V MCLK×n-9 MCLK×n+9 ns VCC < 4.5V MCLK×n-12 MCLK×n+12 MWEX↓→ Data output time tCSL-DX MCSX, MADATA[15:0] VCC ≥ 4.5V MCLK-9 MCLK+9 ns VCC < 4.5V MCLK-12 MCLK+12 MWEX↑→ Data hold time tWEH - DX MWEX, MADATA[15:0] VCC ≥ 4.5V MCLK×m+9 ns VCC < 4.5V MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 101 CONFIDENTIAL Invalid Address tCSL-OEL tCSL-AV RD Address WD tDH-OEtDS-OE tWEH-DX tOEW tOEH-AX tOEH-CSH tWEW tCYCLE tCSL-WEL tCSL-AV tWEH-CSH tWEH-AX tCSL-WDQMLtCSL-RDQML tCSL-DX MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

102 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] VCC ≥ 4.5 V ns VCC < 4.5 V 12 MCSX delay time tCSL MCLK, MCSX[7:0] VCC ≥ 4.5 V ns VCC < 4.5 V 12 tCSH VCC ≥ 4.5 V ns VCC < 4.5 V 12 MOEX delay time tREL MCLK, MOEX VCC ≥ 4.5 V ns VCC < 4.5 V 12 tREH VCC ≥ 4.5 V ns VCC < 4.5 V 12 Data set up →MCLK↑ time tDS MCLK, MADATA[15:0] VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37 MCLK↑→ Data hold time tDH MCLK, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX delay time tWEL MCLK, MWEX VCC ≥ 4.5 V ns VCC < 4.5 V 12 tWEH VCC ≥ 4.5 V ns VCC < 4.5 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] VCC ≥ 4.5 V ns VCC < 4.5 V 12 tDQMH VCC ≥ 4.5 V ns VCC < 4.5 V 12 MCLK↑→ Data output time tODS MCLK, MADATA[15:0] VCC ≥ 4.5 V MCLK+1 MCLK+18 ns VCC < 4.5 V MCLK+24 MCLK↑→ Data hold time tOD MCLK, MADATA[15:0] VCC ≥ 4.5 V ns VCC < 4.5 V 24 Note: − When the external load capacitance CL = 30 pF

February 2, 2015, MB9B560R_DS709-00001-2v0-E 103 CONFIDENTIAL Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

104 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADATA[15:0] VCC ≥ 4.5 V ns VCC < 4.5 V 20 Multiplexed address hold time tCHMADH VCC ≥ 4.5 V MCLK×n+0 MCLK×n+10 ns VCC < 4.5 V MCLK×n+0 MCLK×n+20 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

February 2, 2015, MB9B560R_DS709-00001-2v0-E 105 CONFIDENTIAL Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 4.5 V 9 ns VCC < 4.5 V 12 ns tCHAH VCC ≥ 4.5 V 9 ns VCC < 4.5 V 12 ns MCLK↑→ Multiplexed address delay time tCHMADV MCLK, MADATA[15:0] VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V MCLK↑→ Multiplexed data output time tCHMADX VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

106 MB9B560R_DS709-00001-2v0-E, February 2, 2015

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max MNREX Min pulse width tNREW MNREX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V Data set up →MNREX↑ time tDS – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MNREX↑→ Data hold time tDH – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX VCC ≥ 4.5 V MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MNWEX Min pulse width tNWEW MNWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MNWEX↓→ Data output time tNWEL – DV MNWEX, MADATA[15:0] VCC ≥ 4.5 V - 9 + 9 ns VCC < 4.5 V -12 +12 MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADATA[15:0] VCC ≥ 4.5 V MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) NAND Flash Read MCLK MNREX MADATA[15:0] Read

February 2, 2015, MB9B560R_DS709-00001-2v0-E 107 CONFIDENTIAL NAND Flash Address Write NAND Flash Command Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write

108 MB9B560R_DS709-00001-2v0-E, February 2, 2015

External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MCLK↑ MRDY input setup time tRDYI MCLK, MRDY VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37  When RDY is input  When RDY is released

· · Over 2cycle tRDYI 2 cycle tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

February 2, 2015, MB9B560R_DS709-00001-2v0-E 109 CONFIDENTIAL SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Unit Min Max Output frequency tCYCSD MSDCLK - 32 MHz Address delay time tAOSD MSDCLK, MAD[15:0] 2 12 ns MSDCLK↑→Data output delay time tDOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK↑→Data output Hi-Z time tDOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time tWROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time tDHSD MSDCLK, MADATA[31:0] 0 - ns Note: − When the external load capacitance CL = 30 pF

110 MB9B560R_DS709-00001-2v0-E, February 2, 2015

MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE MADATA[15:0] Address MADATA[15:0] MAD[24:0] tCYCSD tAOSD tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDOSD tDOZSD tDSSD tDHSD SDRAM Access

February 2, 2015, MB9B560R_DS709-00001-2v0-E 111 CONFIDENTIAL

14.4.11 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 10. Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

112 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.12 UART Timing

Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 113 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

114 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 115 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

116 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 117 CONFIDENTIAL MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

118 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 119 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

120 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↓setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SUT delay time tDSE - 40 - 40 ns SCS↑→SUT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 121 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=1) SOT (SPI=0) SOT (SPI=1)

122 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↑setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 123 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

124 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↓setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 125 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

126 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 127 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

128 MB9B560R_DS709-00001-2v0-E, February 2, 2015

High-speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, 5 - 5 - ns SINx SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 129 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

130 MB9B560R_DS709-00001-2v0-E, February 2, 2015

High-speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 131 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

132 MB9B560R_DS709-00001-2v0-E, February 2, 2015

High-speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select:SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 133 CONFIDENTIAL MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

134 MB9B560R_DS709-00001-2v0-E, February 2, 2015

High-speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Internal shift clock operation tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select:SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 135 CONFIDENTIAL MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

136 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 137 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=1) SOT (SPI=0) SOT (SPI=1)

138 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 139 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

140 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 141 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

142 MB9B560R_DS709-00001-2v0-E, February 2, 2015

When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (MN709-00001). − When the external load capacitance CL = 30 pF.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 143 CONFIDENTIAL tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1)

144 MB9B560R_DS709-00001-2v0-E, February 2, 2015

External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Max Serial clock "L" pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock "H" pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSHSL VIL VIL VIL VIH VIH VIH tR tFtSLSH SCK

February 2, 2015, MB9B560R_DS709-00001-2v0-E 145 CONFIDENTIAL

14.4.13 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator INT00 to INT31, NMIX 2tCYCP + 100*1 - ns External interrupt, NMI 500*2 - ns WKUPx - 500*3 - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the A/D converter, multi-function timer, external interrupt are connected to, see 10. Block Diagram in this data sheet. *2: When in Stop mode, in timer mode. *3: When in deep standby RTC mode, in Deep Standby Stop mode.

146 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.14 Quadrature Position/Revolution Counter Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC = 0 ZIN pin L width tZLL QCR:CGSC = 0 AIN/BIN rising and falling time from determined ZIN level tZABE QCR:CGSC = 1 Determined ZIN level from AIN/BIN rising and falling time tABEZ QCR:CGSC = 1 *: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 10. Block Diagram in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

February 2, 2015, MB9B560R_DS709-00001-2v0-E 147 CONFIDENTIAL BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN

148 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.15 I2C Timing

Typical Mode, High-speed Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Typical Mode High-speed Mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock "L" width tLOW 4.7 - 1.3 - μs SCL clock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP

2 MHz ≤

tCYCP<40 MHz 2tCYCP*4 - 2tCYCP*4 - ns

40 MHz ≤

tCYCP<60 MHz 4tCYCP*4 - 4tCYCP*4 - ns

60 MHz ≤

tCYCP<80 MHz 6tCYCP*4 - 6tCYCP*4 - ns

80 MHz ≤

tCYCP<100 MHz 8tCYCP*4 - 8tCYCP*4 - ns

100 MHz ≤

tCYCP<120 MHz 10tCYCP*4 - 10tCYCP*4 - ns

120 MHz ≤

tCYCP<140 MHz 12tCYCP*4 - 12tCYCP*4 - ns

140 MHz ≤

tCYCP<160 MHz 14tCYCP*4 - 14tCYCP*4 - ns

160 MHz ≤

tCYCP<180 MHz 16tCYCP*4 - 16tCYCP*4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: A high-speed mode I2C bus device can be used on a typical mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "10. Block Diagram" in this data sheet. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 149 CONFIDENTIAL Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Fast Mode Plus (Fm+)*6 Unit Remarks Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 1000 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 0.26 - μs SCL clock "L" width tLOW 0.5 - μs SCL clock "H" width tHIGH 0.26 - μs SCL clock frequency tSUSTA 0.26 - μs (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDDAT 0 0.45*2, *3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 50 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 0.26 - μs Bus free time between "STOP condition" and "START condition" tBUF 0.5 - μs Noise filter tSP tCYCP<80 MHz 6 tCYCP*4 - ns tCYCP<100 MHz 8 tCYCP*4 - ns tCYCP<120 MHz 10 tCYCP*4 - ns tCYCP<140 MHz 12 tCYCP*4 - ns tCYCP<160 MHz 14 tCYCP*4 - ns tCYCP<180 MHz 16 tCYCP*4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A high-speed mode I2C bus device can be used on a typical mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 10. Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See CHAPTER 12: I/O Port in FM4 Family Peripheral Manual Main part (MN709-00001) for the details.

150 MB9B560R_DS709-00001-2v0-E, February 2, 2015

February 2, 2015, MB9B560R_DS709-00001-2v0-E 151 CONFIDENTIAL

14.4.16 SD Card Interface Timing

 Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Remarks Min Max Clock frequency Data Transfer Mode fPP S_CLK CCARD ≤ 10 pF (1 card) 0 16 MHz Clock frequency Identification Mode fOD S_CLK 0*/100 400 kHz Clock low time tWL S_CLK 10 - ns Clock high time tWH S_CLK 10 - ns Clock rising time tTLH S_CLK - 10 ns Clock falling time tTHL S_CLK - 10 ns *: 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required.  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Input set-up time tISU S_CMD, S_DATA3:0 CCARD ≤ 10 pF (1 card) 5 - ns Input hold time tIH S_CMD, S_DATA3:0 5 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Output Delay time during Data Transfer Mode tODLY S_CMD, S_DATA3:0 CCARD ≤ 40 pF (1 card) 0 22 ns Output Delay time durinn Identification Mode tODLY S_CMD, S_DATA3:0 0 50 ns

152 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Note: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. VIL VIL tWL tWH VIH VIH VIH tTHL tTLH tISU VIH VIL VIH VIL tIH VOH VOL VOH VOL tODLY(Max) tODLY(Min) S_CMD, S_DATA3:0 (Card Output) S_CMD, S_DATA3:0 (Card Input) S_CLK (SD Clock)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 153 CONFIDENTIAL High-Speed Mode  Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Remarks Min Max Clock frequency Data Transfer Mode fPP S_CLK CCARD ≤ 10 pF (1 card) 0 32 MHz Clock low time tWL S_CLK 7 - ns Clock high time tWH S_CLK 7 - ns Clock rising time tTLH S_CLK - 3 ns Clock falling time tTHL S_CLK - 3 ns  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Input set-up time tISU S_CMD, S_DATA3:0 CCARD ≤ 10 pF (1 card) 8 - ns Input hold time tIH S_CMD, S_DATA3:0 2 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Output Delay time during Data Transfer Mode tODLY S_CMD, S_DATA3:0 CL ≤ 40 pF (1 card) - 22 ns Output Hold time tOH S_CMD, S_DATA3:0 CL ≥ 15 pF (1 card) 2.5 - ns Total System capacitance for each line* CL - 1 card - 40 pF *: In order to satisfy severe timing, host shall drive only one card. High-Speed Mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same values. VIL VIL tWL tWH VIH VIH VIH tTHL tTLH tISU VIH VIL VIH VIL tIH VOH VOL VOH VOL tODLY(Max) tOH(Min) 50%VCC 50%VCC S_CMD, S_DATA3:0 (Card Output) S_CMD, S_DATA3:0 (Card Input) S_CLK (SD Clock)

154 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.4.17 ETM Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] VCC ≥ 4.5 V 2 9 ns VCC < 4.5 V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz TRACECLK clock cycle tTRACE VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 31.25 - ns Note: − When the external load capacitance CL= 30 pF. HCLK TRACECLK TRACED[3:0]

February 2, 2015, MB9B560R_DS709-00001-2v0-E 155 CONFIDENTIAL

14.4.18 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC < 4.5 V - 45 Note: − When the external load capacitance CL= 30 pF. TCK TMS/TDI TDO

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14.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - -4.5 - +4.5 LSB AVRH = 2.7 V to 5.5 V Differential Nonlinearity - - -2.5 - +2.5 LSB Zero transition voltage VZT AN00 to AN23 -15 - +15 mV Full-scale transition voltage VFST AN00 to AN23 AVRH - 15 - AVRH + 15 mV Conversion time - - 0.5*1 - - μs AVCC ≥ 4.5V Sampling time Ts - *2 - 10 μs AVCC ≥ 4.5V *2 - AVCC < 4.5V Compare clock cycle*3 Tcck - 25 - 1000 ns AVCC ≥ 4.5V 50 - 1000 AVCC < 4.5V State transition time to operation permission Tstt - 1.0 - - μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1 unit operation - 1.0 18 μA When A/D stop Reference power supply current (between AVRH and AVSS) - AVRH - 1.1 1.97 mA A/D 1unit operation AVRH=5.5 V 0.3 6.3 μA When A/D stop Analog input capacity CAIN - - - 12.05 pF Analog input resistance RAIN - - - 1.2 kΩ AVCC ≥ 4.5 V 1.8 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input current - AN00 to AN23 - - 5 μA Analog input voltage - AN00 to AN23 AVSS - AVRH V Reference voltage - AVRH 4.5 - AVCC V Tcck < 50 ns 2.7 - AVCC Tcck ≥ 50 ns *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of compare time: 350 ns (AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling time and compare clock cycle, see CHAPTER 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part (MN709-00001). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 10. Block Diagram in this data sheet.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 157 CONFIDENTIAL (Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9 Ts : Sampling time RAIN : Input resistance of A/D = 1.2kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 1.8kΩ at 2.7 V < AVCC < 4.5 V CAIN : Input capacity of A/D = 12.05pF at 2.7 V < AVCC < 5.5 V Rext : Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc : Compare time Tcck : Compare clock cycle Rext RAIN CAIN Analog signal source AN00 to AN23 Analog input pin Comparator

158 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Definition of 12-bit A/D Converter Terms − Resolution: Analog variation that is recognized by an A/D converter. − Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. − Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVss AVRH AVss AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

February 2, 2015, MB9B560R_DS709-00001-2v0-E 159 CONFIDENTIAL 14.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - DAx - - 12 bit Conversion time tc20 0.56 0.69 0.81 μs Load 20 pF tc100 2.79 3.42 4.06 μs Load 100 pF Integral Nonlinearity* INL -16 - +16 LSB Differential Nonlinearity* DNL -0.98 - +1.5 LSB Output voltage offset VOFF - - 10.0 mV When setting 0x000 -20.0 - +1.4 mV When setting 0xFFF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ When D/A stop Power supply current* IDDA AVCC 260 330 410 μA D/A 1unit operation AVCC=3.3 V 400 510 620 μA D/A 1unit operation AVCC=5.0 V IDSA - - 14 μA When D/A stop *: During no load

160 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.7 USB Characteristics

(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input characte r-istics Input H level voltage VIH UDP0, UDM0 - 2.0 USBVCC + 0.3 V *1 Input L level voltage VIL - VSS - 0.3 0.8 V *1 Differential input sensitivity VDI - 0.2 - V *2 Different common mode range VCM - 0.8 2.5 V *2 Output characte r-istics Output "H" level voltage VOH External pull-down resistance = 15 kΩ 2.8 3.6 V *3 Output "L" level voltage VOL External pull-up resistance = 1.5 kΩ 0.0 0.3 V *3 Crossover voltage VCRS - 1.3 2.0 V *4 Rising time tFR Full-Speed 4 20 ns *5 Falling time tFF Full-Speed 4 20 ns *5 Rising/falling time matching tFRFM Full-Speed 90 111.11 % *5 Output impedance ZDRV Full-Speed 28 44 Ω *6 Rising time tLR Low-Speed 75 300 ns *7 Falling time tLF Low-Speed 75 300 ns *7 Rising/falling time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Minimum differential input sensitivity [V]

February 2, 2015, MB9B560R_DS709-00001-2v0-E 161 CONFIDENTIAL *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V. *5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. VCRS specified range Rising time Falling time

162 MB9B560R_DS709-00001-2v0-E, February 2, 2015

*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. Rs series resistor 25 Ω to 30 Ω Series resistor of 27 Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7 : They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. See Low-Speed Load (Compliance Load) for conditions of external load. Mount it as external resistance. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Rising time Falling time

February 2, 2015, MB9B560R_DS709-00001-2v0-E 163 CONFIDENTIAL Low-Speed Load (Upstream Port Load) - Reference 1 Low-Speed Load (Downstream Port Load) - Reference 2 Low-Speed Load (Compliance Load) CL = 50pF to 150pF CL = 50pF to 150pF CL =200pF to 600pF CL =200pF to 600pF CL = 200pF to 450pF CL = 200pF to 450pF

164 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.8 Low-Voltage Detection Characteristics

14.8.1 Low-Voltage Detection Reset

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.25 2.45 2.65 V When voltage drops Released voltage VDH - 2.30 2.50 2.70 V When voltage rises

14.8.2 Interrupt of Low-Voltage Detection

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00111 2.58 2.8 3.02 V When voltage drops Released voltage VDH 2.67 2.9 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.0 3.24 V When voltage drops Released voltage VDH 2.85 3.1 3.34 V When voltage rises Detected voltage VDL SVHI = 01100 2.94 3.2 3.45 V When voltage drops Released voltage VDH 3.04 3.3 3.56 V When voltage rises Detected voltage VDL SVHI = 01111 3.31 3.6 3.88 V When voltage drops Released voltage VDH 3.40 3.7 3.99 V When voltage rises Detected voltage VDL SVHI = 01110 3.40 3.7 3.99 V When voltage drops Released voltage VDH 3.50 3.8 4.10 V When voltage rises Detected voltage VDL SVHI = 01001 3.68 4.0 4.32 V When voltage drops Released voltage VDH 3.77 4.1 4.42 V When voltage rises Detected voltage VDL SVHI = 01000 3.77 4.1 4.42 V When voltage drops Released voltage VDH 3.86 4.2 4.53 V When voltage rises Detected voltage VDL SVHI = 11000 3.86 4.2 4.53 V When voltage drops Released voltage VDH 3.96 4.3 4.64 V When voltage rises LVD stabilization wait time TLVDW - - - 4480× tCYCP* μs *: tCYCP indicates the APB2 bus clock cycle time.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 165 CONFIDENTIAL

14.9 MainFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time Large Sector 0.7 3.7 s Includes write time prior to internal erase Small Sector 0.3 1.1 Half word (16-bit) write time Write cycles < 100 times - 12 100 μs Not including system-level overhead time Write cycles > 100 times 200 Chip erase time - 13.6 68 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C) .

14.10 WorkFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time - 0.3 1.5 s Includes write time prior to internal erase Half word (16-bit) write time - 20 200 μs Not including system-level overhead time Chip erase time - 1.2 6 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C) .

166 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.11 Standby Recovery Time

14.11.1 Recovery cause: Interrupt/WKUP

The time from recovery cause reception of the internal circuit to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode Ticnt HCLK×1 μs High-speed CR Timer mode Main Timer mode PLL Timer mode 40 80 μs Low-speed CR timer mode 450 900 μs Sub timer mode 896 1136 μs RTC mode stop mode (High-speed CR /Main/PLL run mode return) 316 540 μs RTC mode stop mode (Low-speed CR/sub run mode return) 270 480 Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention 365 667 μs without RAM retention 365 667 μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 167 CONFIDENTIAL Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (MN709-00001). − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See CHAPTER 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main part (MN709-00001).

168 MB9B560R_DS709-00001-2v0-E, February 2, 2015

14.11.2 Recovery Cause: Reset

The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode Trcnt 155 266 μs High-speed CR timer mode Main timer mode PLL timer mode 155 266 μs Low-speed CR timer mode 315 567 μs Sub timer mode 315 567 μs RTC mode Stop mode 315 567 μs Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention 336 667 μs without RAM retention μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX Trcnt Internal RST CPU Operation Start RST Active Release

February 2, 2015, MB9B560R_DS709-00001-2v0-E 169 CONFIDENTIAL Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST Trcnt Internal RST CPU Operation Start RST Active Release *: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (MN709-00001). − The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See (6) Power-on Reset Timing in 14.4 AC Characteristics in 14. Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

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Ordering Information Part Number Flash RAM Package MB9BF568MPMC-G-JNE2 1 MB 128 KB Plastic・LQFP (0.5 mm pitch), 80 pin (FPT-80P-M37) MB9BF567MPMC-G-JNE2 768 KB 96 KB MB9BF566MPMC-G-JNE2 512 KB 64 KB MB9BF568MPMC1-G-JNE2 1 MB 128 KB Plastic・LQFP (0.65 mm pitch), 80 pin (FPT-80P-M40) MB9BF567MPMC1-G-JNE2 768 KB 96 KB MB9BF566MPMC1-G-JNE2 512 KB 64 KB MB9BF568NPMC-G-JNE2 1 MB 128 KB Plastic・LQFP (0.5 mm pitch), 100 pin (FPT-100P-M23) MB9BF567NPMC-G-JNE2 768 KB 96 KB MB9BF566NPMC-G-JNE2 512 KB 64 KB MB9BF568RPMC-G-JNE2 1 MB 128 KB Plastic・LQFP (0.5 mm pitch), 120 pin (FPT-120P-M37) MB9BF567RPMC-G-JNE2 768 KB 96 KB MB9BF566RPMC-G-JNE2 512 KB 64 KB MB9BF568NBGL-GE1 1 MB 128 KB Plastic・PFBGA (0.5 mm pitch), 112 pin (BGA-112P-M05) MB9BF567NBGL-GE1 768 KB 96 KB MB9BF566NBGL-GE1 512 KB 64 KB MB9BF568RBGL-GE1 1 MB 128 KB Plastic・PFBGA (0.5 mm pitch), 144 pin (BGA-144P-M09) MB9BF567RBGL-GE1 768 KB 96 KB MB9BF566RBGL-GE1 512 KB 64 KB MB9BF568FBGL-000GE1 1 MB 128 KB MB9BF568NPQC-G-JNE2 1 MB 128 KB Plastic・QFP (0.65 mm pitch), 100 pin (FPT-100P-M36) MB9BF567NPQC-G-JNE2 768 KB 96 KB MB9BF566NPQC-G-JNE2 512 KB 64 KB

February 2, 2015, MB9B560R_DS709-00001-2v0-E 171 CONFIDENTIAL 16. Package Dimensions 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 mm × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.88 g Code (Reference) P-LFQFP120-16 × 16-0.50 120-pin plastic LQFP (FPT-120P-M37) (FPT-120P-M37) C 2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1 13 0 91 60 120 (.009± .002) M0.08(.003) ( ) 0.08(.003) "A" INDEX .059–.004 +.008 –0.10 +0.20 1.50 (Mounting height) 0˚~8˚ (.024± .006) 0.60± 0.15 0.25(.010) 0.10± 0.05 (.004± .002) Details of "A" part (Stand off) LEAD No. –0.03 +0.05 0.145 –.001 +.002 .006 Dimensions in mm (inches). Note: The values in parentheses are reference values Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

172 MB9B560R_DS709-00001-2v0-E, February 2, 2015

100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g 100-pin plastic LQFP (FPT-100P-M23) (FPT-100P-M23) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 12 5 100 0.145±0.055 (.006±.002) 0.08(.003) "A" INDEX 0°~8° 0.50±0.20 0.10±0.10 (Stand off) +.008 +0.20 (Mounting height) -0.101.50 .059 -.004( ) Dimensions in mm (inches). Note:The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part (.004±.004) (.009±.002) (.020±.008) (.024±.006)

February 2, 2015, MB9B560R_DS709-00001-2v0-E 173 CONFIDENTIAL 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14 × 20-0.65 100-pin plastic QFP (FPT-100P-M36) (FPT-100P-M36)

2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1C

(.551±.008) 17.90± 0.40 (.705±.016) INDEX (.013±.002) M0.13(.005) "A" 0.17 ± 0.06 (.007 ±. 002) 0.10(.004) Details of "A" part (.035 ±. 006) 0.88 ± 0.15 (.031 ±. 008) 0.80 ± 0.20 0.25(.010)3.00 +0.35 –0.20 +.014 –.008 .118 (Mounting height) 0.25 ± 0.20 (.010 ±. 008) (Stand off) 0~8° *14.00±0.20 Dimensions in mm (inches). Note: The valuesin parentheses are referencevalues. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

174 MB9B560R_DS709-00001-2v0-E, February 2, 2015

80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 80-pin plastic LQFP (FPT-80P-M37) (FPT-80P-M37) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 12 0 60 41 INDEX (.009± .002) M0.08(.003) 0.145± 0.055 (.006± .002) 0.08(.003) "A" (Stand off) Details of "A" part (.004± .002) 0.10± 0.05 (.024± .006) 0.60± 0.15 (.020± .008) 0.25(.010) 0.50± 0.20 (Mounting height).059–.004 +.008 –0.10 +0.20 1.50 0~8° C Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 175 CONFIDENTIAL 80-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm Max. Code (Reference) P-LQFP80-14 × 14-0.65 80-pin plastic LQFP (FPT-80P-M40) (FPT-80P-M40) 0.32±0.06 (.013±.002) M0.13(.005) 0.145±0.055 (.006±.002) 0.10(.004) 0.60±0.15 (.024±.006) 1.50±0.10 (.059±.004) 0˚~7˚ 0.25(.010) 0.10±0.05 (.004±.002) INDEX Details of "A" part 0.65(.026) 0.50±0.20 (.020±.008) 1 20 60 41 C 2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1 Dimensions in mm (inches). Note: The values in parentheses are referencevalues. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

176 MB9B560R_DS709-00001-2v0-E, February 2, 2015

112-ball plastic FBGA Ball pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Ball Sealing method Plastic mold Mounting height 1.35 mm Max. Weight 0.10 g 112-ball plastic FBGA (BGA-112P-M05) (BGA-112P-M05) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED B112005S-c-2-3 6.00(.236) 0.50(.020) TYP ABCDEFGHJKLM (INDEX AREA) S0.10(.004) 1.15±0.20 S (Seated height) (Stand off) 0.25±0.10 S B0.20(.008) S A0.20(.008) 7.00±0.10 (.276±.004) (112-ø.012±.004) REF A 0.50(.020) TYP 6.00(.236)REF B INDEX N (NO BALL) Dimensions in mm (inches). Note: The values in parentheses are reference values.

February 2, 2015, MB9B560R_DS709-00001-2v0-E 177 CONFIDENTIAL 144-pin plastic FBGA Lead pitch 0.5 mm Package width × package length 7.0 mm × 7.0 mm Sealing method Plastic mold Mounting height 1.3 mm MAX Weight 0.11 g 144-pin plastic FBGA (BGA-144P-M09) (BGA-144P-M09) C 2010 FUJITSU SEMICONDUCTOR LIMITED HMbB144-09Sc-1-1 6.00(.236) INDEX AREA S (SEATED HEIGHT) (STAND OFF) 0.25±0.10 S A0.20(.008) S B0.20(.008) 7.00±0.10 (.276±.004) (144-ø.012±.004) B 0.50(.020) A 6.00(.236) 0.50(.020) ABCDEFGHJKLMN INDEX (No Ball) B Dimensions in mm (inches). Note: The values in parenthesesare reference values.

178 MB9B560R_DS709-00001-2v0-E, February 2, 2015

Major Changes Page Section Change Results Revision 1.0 - - Preliminary → Data Sheet 1 ■DESCRIPTION Deleted the following description : The products which are described in this data sheet are placed into TYPE4 product categories in "FM4 Family PERIPHERAL MANUAL". ■FEATURES [USB function] Added the following description : ・The size of each endpoint is according to the follows. - Endpoint 0, 2 to 5 : 64bytes - Endpoint 1 : 256bytes ■FEATURES lMulti-function Serial Interface [I2C] Revised the following description : Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and ch.7) supported →Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported ■FEATURES lUnique ID Added new section ■PRODUCT LINEUP lFunction Added “Unique ID” 51,52 ■I/O CIRCUIT TYPE Revised the remarks of “Type O, P , Q” ■HANDLING DEVICES lHandling when using debug pins Added new section 60 ■BLOCK DIAGRAM Revised the block diagram ■ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions Revised “Table for package thermal resistance and maximum permissible power” 77 to 82 ■ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating

Revised the value of TBD
Revised the unit of “ICCHD”, “ICCRD”, “ICCVBAT” mA → µA
Added the note to “ICCVBAT” ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (2) Sub Clock Input Characteristics Revised the waveform chart ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (3) Built-in CR OscillationCharacteristics
Revised the value of TBD
Revised the table and the note of “Built-in High-speed CR” 146 ■ELECTRICAL CHARACTERISTICS 5. 12-bit A/D Converter ・Electrical Characteristics for the A/D Converter
Revised the value of TBD
Revised the condition of the electrical characteristics table 149 ■ELECTRICAL CHARACTERISTICS 6. 12-bit D/A Converter ・Electrical Characteristics for the D/A Converter
Revised the value of TBD
Revised the condition and Remarks of the electrical characteristics table 156 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (1) Recovery cause: Interrupt/WKUP
Revised the value of TBD
Revised the table of Recovery count time 158 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (2) Recovery cause:Reset
Revised the value of TBD
Revised the table of Recovery count time Revision 1.1 - - Company name and layout design change

February 2, 2015, MB9B560R_DS709-00001-2v0-E 179 CONFIDENTIAL Page Section Change Results Revision 2.0 1,3 Title Added the following product. MB9BF568F 5 2. Features Added the Voice Function 13,14 3. Product Lineup Added the following product. MB9BF568F 15 4. Packages Added the following product. MB9BF568F 169 15. Ordering Information Added the following product. MB9BF568FBGL-000GE1

180 MB9B560R_DS709-00001-2v0-E, February 2, 2015

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2014-2015 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

Product Information

MB9B560R specifications and overview.

Summary

This document states the current technical specifications regarding

Description

This document states the current technical specifications regarding

Source title MB9B560R Datasheet(PDF) - SPANSION

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