MB9A340NB

SPANSION

The MB9A340NB Series are highly integrated

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The following document contains information on Cypress products. Although the document is marked with the name “Spansion”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing custom ers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, wher e supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress (NASDAQ: CY) delivers high -performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes NOR flash memories, F -RAM™ and SRAM, Trav eo™ microcontrollers, the industry’s only PSoC ® programmable system -on-chip solutions, analog and PMIC Power Management ICs, CapSense ® capacitive touch-sensing controllers, and Wireless BLE Bluetooth ® Low-Energy and USB connectivity solutions, Cypress is committed to providing its customers worldwide with consistent innovation, best - in-class support and exceptional system value.

MB9A340NB_DS706-00039-4v0-E, June 10, 2015 CONFIDENTIAL Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.

32-bit ARM® Cortex®-M3 based Microcontroller MB9AF341LB/MB/NB, MB9AF342LB/MB/NB, MB9AF344LB/MB/NB Data Sheet (Full Production) Publication Number MB9A340NB_DS706-00039 Revision 4.0 Issue Date June 10, 2015 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to cha nge. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.  Description The MB9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual. Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.

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 Features  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 40 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory]  Dual operation Flash memory ・Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.  Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)  Work area: 32 Kbytes (lower bank)  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 16 Kbytes  SRAM1: Up to 16 Kbytes  External Bus Interface*  Supports SRAM, NOR Flash memory device  Up to 8 chip selects  8-/16-bit Data width  Up to 25-bit Address bit  Maximum area size : Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY function * : MB9AF341LB, F342LB and F344LB do not support External Bus Interface.  USB Interface The USB interface is composed of Function and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB function]  USB2.0 Full-Speed supported  Max 6 EndPoint supported  EndPoint 0 is control transfer  EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer  EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer  EndPoint 1 to 5 is comprised of Double Buffers.  The size of each endpoint is according to the follows. - Endpoint 0, 2 to 5: 64 bytes - Endpoint 1: 256 bytes [USB host]  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer support  Automatic detection of connected/disconnected USB Device  Automatic processing of the IN/OUT token handshake packet  Max 256-byte packet-length supported  Wake-up function supported

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 3 CONFIDENTIAL  Multi-function Serial Interface (Max 8 channels)  4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)  Operation mode is selectable from the followings for each channel.  UART  CSIO  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detection functions available (parity errors, framing errors, and overrun errors) * : MB9AF341LB, F342LB and F344LB do not support Hardware Flow control. [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported  DMA Controller (8 channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536  A/D Converter (Max 24 channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2 units  Conversion time: 2.0 μs @ 2.7 V to 3.6 V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)  Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer

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 General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 83 fast general-purpose I/O Ports@100 pin Package  Some ports are 5V tolerant I/O. See Pin Description to confirm the corresponding pins.  Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot  HDMI-CEC/Remote Control Receiver (Up to 2 channels)  HDMI-CEC transmitter  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  HDMI-CEC receiver  Automatic ACK reply function available  Line error detection function available  Remote control receiver  4 bytes reception buffer  Repeat code detection function available  Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available.  Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz  External Interrupt Controller Unit  Up to 16 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 5 CONFIDENTIAL  Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC, Deep Standby Stop modes.  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  Built-in high-speed CR Clock: 4 MHz  Built-in low-speed CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset  Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  External clock failure (clock stop) is detected, reset is asserted.  External frequency anomaly is detected, interrupt or reset is asserted.  Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-V oltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation

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 Low-Power Consumption Mode Six low-power consumption modes supported.  Sleep  Timer  RTC  Stop  Deep Standby RTC (selectable between keeping the value of RAM and not)  Deep Standby Stop (selectable between keeping the value of RAM and not)  Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM).* *: MB9AF341LB/MB, F342LB/MB and F344LB/MB support only SWJ-DP.  Unique ID Unique value of the device (41-bit) is set.  Power Supply Wide range voltage: VCC = 1.65 V to 3.6 V VCC = 3.0 V to 3.6 V (when USB is used)

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 7 CONFIDENTIAL  Product Lineup  Memory size Product name MB9AF341LB/MB/NB MB9AF342LB/MB/NB MB9AF344LB/MB/NB On-chip Flash memory Main area 64 Kbytes 128 Kbytes 256 Kbytes Work area 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM SRAM0 8 Kbytes 8 Kbytes 16 Kbytes SRAM1 8 Kbytes 8 Kbytes 16 Kbytes Total 16 Kbytes 16 Kbytes 32 Kbytes  Function Product name MB9AF341LB MB9AF342LB MB9AF344LB MB9AF341MB MB9AF342MB MB9AF344MB MB9AF341NB MB9AF342NB MB9AF344NB Pin count 64 80/96 100/112 CPU Cortex-M3 Freq. 40 MHz Power supply voltage range 1.65 V to 3.6 V USB2.0 (Function/Host) 1ch. DMAC 8ch. External Bus Interface - Addr: 21-bit (Max) R/W Data: 8-bit (Max) CS: 4 (Max) Support: SRAM, NOR Flash memory Addr: 25-bit (Max) R/W Data: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash memory Multi-function Serial Interface (UART/CSIO/I2C) 8ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Receiver 2ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 8 pins (Max) + NMI × 1 11 pins (Max) + NMI × 1 16 pins (Max) + NMI × 1 I/O ports 51 pins (Max) 66 pins (Max) 83 pins (Max) 12-bit A/D converter 12ch. (2 units) 17ch. (2 units) 24ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-V oltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP SWJ-DP/ETM Unique ID Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See  Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for accuracy of built-in CR.

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 Packages Product name Package MB9AF341LB MB9AF342LB MB9AF344LB MB9AF341MB MB9AF342MB MB9AF344MB MB9AF341NB MB9AF342NB MB9AF344NB LQFP: FPT-64P-M38 (0.5mm pitch)  - - LQFP: FPT-64P-M39 (0.65mm pitch)  - - QFN: LCC-64P-M24 (0.5mm pitch)  - - LQFP: FPT-80P-M37 (0.5mm pitch) -  - LQFP: FPT-80P-M40 (0.65mm pitch) -  - BGA: BGA-96P-M07 (0.5mm pitch) -  - LQFP: FPT-100P-M23 (0.5mm pitch) - -  QFP: FPT-100P-M36 (0.65mm pitch) - -  BGA: BGA-112P-M04 (0.8mm pitch) - -  : Supported Note: See Package Dimensions for detailed information on each package.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 9 CONFIDENTIAL  Pin Assignment  FPT-100P-M23 (TOP VIEW) VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/MDQM1_1 P0D/RTS4_0/TIOA3_2/MDQM0_1 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 P0A/SIN4_0/INT00_2/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/AN23/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/AN22/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 100 VCC 1 75 VSS P50/INT00_0/SIN3_1/MADATA00_1 2 74 P20/AN19/INT05_0/CROUT_0/MAD24_1 P51/INT01_0/SOT3_1/MADATA01_1 3 73 P21/AN18/SIN0_0/INT06_1/WKUP2 P52/INT02_0/SCK3_1/MADATA02_1 4 72 P22/AN17/SOT0_0/TIOB7_1 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 5 71 P23/AN16/SCK0_0/TIOA7_1 P54/SOT6_0/TIOB1_2/MADATA04_1 6 70 P1F/AN15/ADTG_5/MAD23_1 P55/SCK6_0/ADTG_1/MADATA05_1 7 69 P1E/AN14/RTS4_1/MAD22_1 P56/INT08_2/MADATA06_1 8 68 P1D/AN13/CTS4_1/MAD21_1 P30/TIOB0_1/INT03_2/MADATA07_1 9 67 P1C/AN12/SCK4_1/MAD20_1 P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 66 P1B/AN11/SOT4_1/MAD19_1 P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 65 P1A/AN10/SIN4_1/INT05_1/MAD18_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 64 P19/AN09/SCK2_2/MAD17_1 P34/TIOB4_1/MADATA11_1 13 63 P18/AN08/SOT2_2/MAD16_1 P35/TIOB5_1/INT08_1/MADATA12_1 14 62 AVSS P36/SIN5_2/INT09_1/MADATA13_1 15 61 AVRH P37/SOT5_2/INT10_1/MADATA14_1 16 60 AVCC P38/SCK5_2/INT11_1/MADATA15_1 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/ADTG_2 18 58 P16/AN06/SCK0_1/MAD14_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 19 57 P15/AN05/SOT0_1/MAD13_1 P3B/TIOA1_1 20 56 P14/AN04/SIN0_1/INT03_1/MAD12_1 P3C/TIOA2_1 21 55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 P3D/TIOA3_1 22 54 P12/AN02/SOT1_1/MAD10_1 P3E/TIOA4_1 23 53 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 P3F/TIOA5_1 24 52 P10/AN00 VSS 25 51 VCC VCC P40/TIOA0_0/INT12_1 P41/TIOA1_0/INT13_1 P42/TIOA2_0 P43/TIOA3_0/ADTG_7 P44/TIOA4_0/MAD00_1 P45/TIOA5_0/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/SOT3_2/MAD03_1 P4A/TIOB1_0/SCK3_2/MAD04_1 P4B/TIOB2_0/MAD05_1 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 P4D/TIOB4_0/SOT7_1/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

10 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 FPT-100P-M36 (TOP VIEW) P50/INT00_0/SIN3_1/MADATA00_1 VCC VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/MDQM1_1 P0D/RTS4_0/TIOA3_2/MDQM0_1 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 P0A/SIN4_0/INT00_2/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/AN23/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/AN22/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC VSS P20/AN19/INT05_0/CROUT_0/MAD24_1 P21/AN18/SIN0_0/INT06_1/WKUP2 P51/INT01_0/SOT3_1/MADATA01_1 81 50 P22/AN17/SOT0_0/TIOB7_1 P52/INT02_0/SCK3_1/MADATA02_1 82 49 P23/AN16/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 83 48 P1F/AN15/ADTG_5/MAD23_1 P54/SOT6_0/TIOB1_2/MADATA04_1 84 47 P1E/AN14/RTS4_1/MAD22_1 P55/SCK6_0/ADTG_1/MADATA05_1 85 46 P1D/AN13/CTS4_1/MAD21_1 P56/INT08_2/MADATA06_1 86 45 P1C/AN12/SCK4_1/MAD20_1 P30/TIOB0_1/INT03_2/MADATA07_1 87 44 P1B/AN11/SOT4_1/MAD19_1 P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88 43 P1A/AN10/SIN4_1/INT05_1/MAD18_1 P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89 42 P19/AN09/SCK2_2/MAD17_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90 41 P18/AN08/SOT2_2/MAD16_1 P34/TIOB4_1/MADATA11_1 91 40 AVSS P35/TIOB5_1/INT08_1/MADATA12_1 92 39 AVRH P36/SIN5_2/INT09_1/MADATA13_1 93 38 AVCC P37/SOT5_2/INT10_1/MADATA14_1 94 37 P17/AN07/SIN2_2/INT04_1/MAD15_1 P38/SCK5_2/INT11_1/MADATA15_1 95 36 P16/AN06/SCK0_1/MAD14_1 P39/ADTG_2 96 35 P15/AN05/SOT0_1/MAD13_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 97 34 P14/AN04/SIN0_1/INT03_1/MAD12_1 P3B/TIOA1_1 98 33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 P3C/TIOA2_1 99 32 P12/AN02/SOT1_1/MAD10_1 P3D/TIOA3_1 100 31 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 P3E/TIOA4_1 P3F/TIOA5_1 VSS VCC P40/TIOA0_0/INT12_1 P41/TIOA1_0/INT13_1 P42/TIOA2_0 P43/TIOA3_0/ADTG_7 P44/TIOA4_0/MAD00_1 P45/TIOA5_0/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/SOT3_2/MAD03_1 P4A/TIOB1_0/SCK3_2/MAD04_1 P4B/TIOB2_0/MAD05_1 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 P4D/TIOB4_0/SOT7_1/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P10/AN00 QFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 11 CONFIDENTIAL  FPT-80P-M37/M40 (TOP VIEW) VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/MDQM1_1 P0D/RTS4_0/TIOA3_2/MDQM0_1 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 P0A/SIN4_0/INT00_2/MCSX1_1 P07/AN22/ADTG_0/MCLKOUT_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 1 60 P20/AN19/INT05_0/CROUT_0/MAD24_1 P50/INT00_0/SIN3_1/MADATA00_1 2 59 P21/AN18/SIN0_0/INT06_1/WKUP2 P51/INT01_0/SOT3_1/MADATA01_1 3 58 P22/AN17/SOT0_0/TIOB7_1 P52/INT02_0/SCK3_1/MADATA02_1 4 57 P23/AN16/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 5 56 P1B/AN11/SOT4_1/MAD19_1 P54/SOT6_0/TIOB1_2/MADATA04_1 6 55 P1A/AN10/SIN4_1/INT05_1/MAD18_1 P55/SCK6_0/ADTG_1/MADATA05_1 7 54 P19/AN09/SCK2_2/MAD17_1 P56/INT08_2/MADATA06_1 8 53 P18/AN08/SOT2_2/MAD16_1 P30/TIOB0_1/INT03_2/MADATA07_1 9 52 AVSS P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 51 AVRH P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 50 AVCC P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 49 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/ADTG_2 13 48 P16/AN06/SCK0_1/MAD14_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 14 47 P15/AN05/SOT0_1/MAD13_1 P3B/TIOA1_1 15 46 P14/AN04/SIN0_1/INT03_1/MAD12_1 P3C/TIOA2_1 16 45 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 P3D/TIOA3_1 17 44 P12/AN02/SOT1_1/MAD10_1 P3E/TIOA4_1 18 43 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 P3F/TIOA5_1 19 42 P10/AN00 VSS 20 41 VCC P44/TIOA4_0/MAD00_1 P45/TIOA5_0/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/SOT3_2/MAD03_1 P4A/TIOB1_0/SCK3_2/MAD04_1 P4B/TIOB2_0/MAD05_1 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 P4D/TIOB4_0/SOT7_1/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

12 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 FPT-64P-M38/M39 (TOP VIEW) VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/AN18/SIN0_0/INT06_1/WKUP2 P50/INT00_0/SIN3_1 2 47 P22/AN17/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN16/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19/AN09/SCK2_2 P30/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS P32/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10 39 P15/AN05 P3B/TIOA1_1 11 38 P14/AN04/INT03_1 P3C/TIOA2_1 12 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1 P3D/TIOA3_1 13 36 P12/AN02/SOT1_1 P3E/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/WKUP1 P3F/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 P4B/TIOB2_0 P4C/TIOB3_0/SCK7_1/CEC0 P4D/TIOB4_0/SOT7_1 P4E/TIOB5_0/INT06_2/SIN7_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 13 CONFIDENTIAL  LCC-64P-M24 (TOP VIEW) VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/AN18/SIN0_0/INT06_1/WKUP2 P50/INT00_0/SIN3_1 2 47 P22/AN17/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN16/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19/AN09/SCK2_2 P30/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS P32/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10 39 P15/AN05 P3B/TIOA1_1 11 38 P14/AN04/INT03_1 P3C/TIOA2_1 12 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1 P3D/TIOA3_1 13 36 P12/AN02/SOT1_1 P3E/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/WKUP1 P3F/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 P4B/TIOB2_0 P4C/TIOB3_0/SCK7_1/CEC0 P4D/TIOB4_0/SOT7_1 P4E/TIOB5_0/INT06_2/SIN7_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

14 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 BGA-112P-M04 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 VCC P0E B VCC VSS P52 P61 P0F P0C AN23 TDO/ SWO P0B AN22 TMS/ SWDIO TRSTX VCC VSS TCK/ SWCLK VSS TDI VSS AN19 AN18 D P53 P54 P55 VSS AN15P56 P63 P0A VSS AN21 AN16 C P50 P51 VSS P60 P62 P0D P09 AN20 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH E P30 P31 P32 P33 Index AN17 AN14 AN12 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C G P37 P38 P3A P3D AN08 AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E P43 P49 P4D AN02 VSS AN01 P4A MD0 X0 X1 VSS MD1 VSS VCC L VSS C X0A VSS P41 P45 PFBGA - 112 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 15 CONFIDENTIAL  BGA-96P-M07 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 VCC VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ SWO P0F VSS AN22 TMS/ SWDIO TRSTX VSS TCK/ SWCLK VSS TDI VSS AN19 AN18 D P53 P54 P55 Index VSSAN17 AN16 C P50 P51 VSS P60 P62 P0E P0B P0A E P56 P30 P31 AN11 AN10 AN09 AN01 AN00 AN04 AN08 AN07 AVRH G P32 P33 P39 AN06 F VSS VSS VSS AN05 AVSS H P3A P3B P3C AN03 AVCC P49 P4C P4E MD1 VSS VCCK VCC VSS X1A INITX P45 J P3D P3E VSS P3F P48 P4A P4D AN02 VSS VSS P4B MD0 X0 X1 VSSL VSS C X0A VSS P44 PFBGA - 96 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

16 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 List of Pin Functions  List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 1 79 B1 1 B1 1 VCC - 2 80 C1 2 C1 2 P50 E L INT00_0 SIN3_1 - MADA TA00_1 3 81 C2 3 C2 3 P51 E L INT01_0 SOT3_1 (SDA3_1) - MADA TA01_1 4 82 B3 4 B3 4 P52 E L INT02_0 SCK3_1 (SCL3_1) - MADA TA02_1 5 83 D1 5 D1 - P53 E L SIN6_0 TIOA1_2 INT07_2 MADA TA03_1 6 84 D2 6 D2 - P54 E K SOT6_0 (SDA6_0) TIOB1_2 MADA TA04_1

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 17 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 7 85 D3 7 D3 - P55 E K SCK6_0 (SCL6_0) ADTG_1 MADA TA05_1 8 86 D5 8 E1 - P56 E L INT08_2 MADA TA06_1 9 87 E1 9 E2 5 P30 E L TIOB0_1 INT03_2 - MADA TA07_1 10 88 E2 10 E3 6 P31 E L TIOB1_1 SCK6_1 (SCL6_1) INT04_2 - MADA TA08_1 11 89 E3 11 G1 7 P32 E L TIOB2_1 SOT6_1 (SDA6_1) INT05_2 - MADA TA09_1 12 90 E4 12 G2 8 P33 E L INT04_0 TIOB3_1 SIN6_1 ADTG_6 - MADA TA10_1 13 91 F1 - - - P34 E K TIOB4_1 MADA TA11_1 14 92 F2 - - - P35 E L TIOB5_1 INT08_1 MADA TA12_1

18 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 15 93 F3 - - - P36 E L SIN5_2 INT09_1 MADA TA13_1 - - - - F1 - VSS - - - - - F2 - VSS - - - - - F3 - VSS - 16 94 G1 - - - P37 E L SOT5_2 (SDA5_2) INT10_1 MADA TA14_1 17 95 G2 - - - P38 E L SCK5_2 (SCL5_2) INT11_1 MADA TA15_1 18 96 F4 13 G3 9 P39 E K ADTG_2 19 97 G3 14 H1 10 P3A E K TIOA0_1 RTCCO_2 SUBOUT_2 20 98 H1 15 H2 11 P3B E K TIOA1_1 21 99 H2 16 H3 12 P3C E K TIOA2_1 22 100 G4 17 J1 13 P3D E K TIOA3_1 - - B2 - B2 - VSS - 23 1 H3 18 J2 14 P3E E K TIOA4_1 24 2 J2 19 J4 15 P3F E K TIOA5_1 25 3 L1 20 L1 16 VSS - 26 4 J1 - - - VCC -

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 19 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 27 5 J4 - - - P40 E L TIOA0_0 INT12_1 28 6 L5 - - - P41 E L TIOA1_0 INT13_1 29 7 K5 - - - P42 E K TIOA2_0 30 8 J5 - - - P43 E K TIOA3_0 ADTG_7 31 9 H5 21 L5 - P44 E K TIOA4_0 MAD00_1 32 10 L6 22 K5 - P45 E K TIOA5_0 MAD01_1 - - K2 - K2 - VSS - - - J3 - J3 - VSS - - - H4 - - - VSS - - - - - L6 - VSS - 33 11 L2 23 L2 17 C - 34 12 L4 24 L4 - VSS - 35 13 K1 25 K1 18 VCC - 36 14 L3 26 L3 19 P46 D F X0A 37 15 K3 27 K3 20 P47 D G X1A 38 16 K4 28 K4 21 INITX B C 39 17 K6 29 J5 - P48 E L INT14_1 SIN3_2 MAD02_1 40 18 J6 30 K6

22 P49

TIOB0_0 SOT3_2 (SDA3_2) MAD03_1

20 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 41 19 L7 31 J6

23 P4A

TIOB1_0 SCK3_2 (SCL3_2) MAD04_1 42 20 K7 32 L7 24 P4B E K TIOB2_0 - MAD05_1 43 21 H6 33 K7 25 P4C I S TIOB3_0 SCK7_1 (SCL7_1) CEC0 - MAD06_1 44 22 J7 34 J7 26 P4D I K TIOB4_0 SOT7_1 (SDA7_1) - MAD07_1 45 23 K8 35 K8 27 P4E I L TIOB5_0 INT06_2 SIN7_1 - MAD08_1 46 24 K9 36 K9 28 MD1 C E PE0 47 25 L8 37 L8 29 MD0 G D 48 26 L9 38 L9 30 X0 A A PE2 49 27 L10 39 L10 31 X1 A B PE3 50 28 L11 40 L11 32 VSS - 51 29 K11 41 K11 33 VCC - 52 30 J11 42 J11 34 P10 F M AN00 53 31 J10 43 J10 35 P11 F R AN01 SIN1_1 INT02_1 WKUP1 - MAD09_1

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 21 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 54 32 J8 44 J8 36 P12 F M AN02 SOT1_1 (SDA1_1) - MAD10_1 - - K10 - K10 - VSS - - - J9 - J9 - VSS - 55 33 H10 45 H10 37 P13 F M AN03 SCK1_1 (SCL1_1) RTCCO_1 SUBOUT_1 - MAD11_1 56 34 H9 46 H9 P14 F N AN04 INT03_1 - SIN0_1 MAD12_1 57 35 H7 47 G10

39 P15

SOT0_1 (SDA0_1) MAD13_1 58 36 G10 48 G9 - P16 F M AN06 SCK0_1 (SCL0_1) MAD14_1 59 37 G9 49 F10 40 P17 F N AN07 SIN2_2 INT04_1 - MAD15_1 60 38 H11 50 H11 41 A VCC - 61 39 F11 51 F11 42 A VRH - 62 40 G11 52 G11 43 A VSS -

22 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 63 41 G8 53 F9 44 P18 F M AN08 SOT2_2 (SDA2_2) - MAD16_1 64 42 F10 54 E11 45 P19 F M AN09 SCK2_2 (SCL2_2) - MAD17_1 - - H8 - - - VSS - 65 43 F9 55 E10 - P1A F N AN10 SIN4_1 INT05_1 MAD18_1 66 44 E11 56 E9 - P1B F M AN11 SOT4_1 (SDA4_1) MAD19_1 67 45 E10 - - - P1C F M AN12 SCK4_1 (SCL4_1) MAD20_1 68 46 F8 - - - P1D F M AN13 CTS4_1 MAD21_1 69 47 E9 - - - P1E F M AN14 RTS4_1 MAD22_1 70 48 D11 - - - P1F F M AN15 ADTG_5 MAD23_1

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 23 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 - - B10 - B10 - VSS - - - C9 - C9 - VSS - 71 49 D10 57 D10 46 P23 F M AN16 SCK0_0 (SCL0_0) TIOA7_1 72 50 E8 58 D9 47 P22 F M AN17 SOT0_0 (SDA0_0) TIOB7_1 73 51 C11 59 C11 48 P21 F R AN18 SIN0_0 INT06_1 WKUP2 74 52 C10 60 C10 - P20 F N AN19 INT05_0 CROUT_0 MAD24_1 75 53 A11 - A11 - VSS - 76 54 A10 - - - VCC - 77 55 A9 61 A10 49 P00 E J TRSTX - MCSX7_1 78 56 B9 62 B9 50 P01 E J TCK SWCLK 79 57 B11 63 B11 51 P02 E J TDI - MCSX6_1 80 58 A8 64 A9 52 P03 E J TMS SWDIO 81 59 B8 65 B8 53 P04 E J TDO SWO

24 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 82 60 C8 - - - P05 F Q AN20 TRACED0 TIOA5_2 SIN4_2 INT00_1 MCSX5_1 - - D8 - - - VSS - 83 61 D9 - - - P06 F Q AN21 TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 MCSX4_1 84 62 A7 66 A8 P07 F P AN22 ADTG_0 MCLKOUT_1 - - TRACED2 SCK4_2 (SCL4_2) - - - - A7 - VSS - 85 63 B7 - - - P08 F P AN23 TRACED3 TIOA0_2 CTS4_2 MCSX3_1 86 64 C7 - - - P09 E O TRACECLK TIOB0_2 RTS4_2 MCSX2_1 87 65 D7 67 C8 54 P0A I L SIN4_0 INT00_2 - MCSX1_1

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 25 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 88 66 A6 68 C7 55 P0B I K SOT4_0 (SDA4_0) TIOB6_1 - MCSX0_1 89 67 B6 69 B7 56 P0C I K SCK4_0 (SCL4_0) TIOA6_1 - MALE_1 - - D4 - - - VSS - - - C3 - C3 - VSS - 90 68 C6 70 B6 - P0D E K RTS4_0 TIOA3_2 MDQM0_1 91 69 A5 71 C6 - P0E E K CTS4_0 TIOB3_2 MDQM1_1 - - - - A5 - VSS - 92 70 B5 72 A6 57 P0F E I NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 93 71 D6 73 B5 - P63 E L INT03_0 MWEX_1 94 72 C5 74 C5 58 P62 E K SCK5_0 (SCL5_0) ADTG_3 - MOEX_1 95 73 B4 75 B4 59 P61 E K SOT5_0 (SDA5_0) TIOB2_2 UHCONX

26 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Type LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 96 74 C4 76 C4 60 P60 I T SIN5_0 TIOA2_2 INT15_1 WKUP3 CEC1 - MRDY_1 97 75 A4 77 A4 61 VCC - 98 76 A3 78 A3 62 P80 H H UDM0 99 77 A2 79 A2 63 P81 H H UDP0 100 78 A1 80 A1 64 VSS -

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 27 CONFIDENTIAL  List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- ADC ADTG_0 A/D converter external trigger input pin 84 62 A7 66 A8 - ADTG_1 7 85 D3 7 D3 - ADTG_2 18 96 F4 13 G3 9 ADTG_3 94 72 C5 74 C5 58 ADTG_4 - - - - - - ADTG_5 70 48 D11 - - - ADTG_6 12 90 E4 12 G2 8 ADTG_7 30 8 J5 - - - ADTG_8 - - - - - - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 52 30 J11 42 J11 34 AN01 53 31 J10 43 J10 35 AN02 54 32 J8 44 J8 36 AN03 55 33 H10 45 H10 37 AN04 56 34 H9 46 H9 38 AN05 57 35 H7 47 G10 39 AN06 58 36 G10 48 G9 - AN07 59 37 G9 49 F10 40 AN08 63 41 G8 53 F9 44 AN09 64 42 F10 54 E11 45 AN10 65 43 F9 55 E10 - AN11 66 44 E11 56 E9 - AN12 67 45 E10 - - - AN13 68 46 F8 - - - AN14 69 47 E9 - - - AN15 70 48 D11 - - - AN16 71 49 D10 57 D10 46 AN17 72 50 E8 58 D9 47 AN18 73 51 C11 59 C11 48 AN19 74 52 C10 60 C10 - AN20 82 60 C8 - - - AN21 83 61 D9 - - - AN22 84 62 A7 66 A8 - AN23 85 63 B7 - - -

28 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Base Timer TIOA0_0 Base timer ch.0 TIOA pin 27 5 J4 - - - TIOA0_1 19 97 G3 14 H1 10 TIOA0_2 85 63 B7 - - - TIOB0_0 Base timer ch.0 TIOB pin 40 18 J6 30 K6 22 TIOB0_1 9 87 E1 9 E2 5 TIOB0_2 86 64 C7 - - - Base Timer TIOA1_0 Base timer ch.1 TIOA pin 28 6 L5 - - - TIOA1_1 20 98 H1 15 H2 11 TIOA1_2 5 83 D1 5 D1 - TIOB1_0 Base timer ch.1 TIOB pin 41 19 L7 31 J6 23 TIOB1_1 10 88 E2 10 E3 6 TIOB1_2 6 84 D2 6 D2 - Base Timer TIOA2_0 Base timer ch.2 TIOA pin 29 7 K5 - - - TIOA2_1 21 99 H2 16 H3 12 TIOA2_2 96 74 C4 76 C4 60 TIOB2_0 Base timer ch.2 TIOB pin 42 20 K7 32 L7 24 TIOB2_1 11 89 E3 11 G1 7 TIOB2_2 95 73 B4 75 B4 59 Base Timer TIOA3_0 Base timer ch.3 TIOA pin 30 8 J5 - - - TIOA3_1 22 100 G4 17 J1 13 TIOA3_2 90 68 C6 70 B6 - TIOB3_0 Base timer ch.3 TIOB pin 43 21 H6 33 K7 25 TIOB3_1 12 90 E4 12 G2 8 TIOB3_2 91 69 A5 71 C6 - Base Timer TIOA4_0 Base timer ch.4 TIOA pin 31 9 H5 21 L5 - TIOA4_1 23 1 H3 18 J2 14 TIOB4_0 Base timer ch.4 TIOB pin 44 22 J7 34 J7 26 TIOB4_1 13 91 F1 - - - Base Timer TIOA5_0 Base timer ch.5 TIOA pin 32 10 L6 22 K5 - TIOA5_1 24 2 J2 19 J4 15 TIOA5_2 82 60 C8 - - - TIOB5_0 Base timer ch.5 TIOB pin 45 23 K8 35 K8 27 TIOB5_1 14 92 F2 - - - TIOB5_2 83 61 D9 - - - Base Timer TIOA6_1 Base timer ch.6 TIOA pin 89 67 B6 69 B7 56 TIOB6_1 Base timer ch.6 TIOB pin 88 66 A6 68 C7 55 Base Timer TIOA7_0 Base timer ch.7 TIOA pin - - - - - - TIOA7_1 71 49 D10 57 D10 46 TIOB7_0 Base timer ch.7 TIOB pin - - - - - - TIOB7_1 72 50 E8 58 D9 47

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 29 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Debugger SWCLK Serial wire debug interface clock input pin 78 56 B9 62 B9 50 SWDIO Serial wire debug interface data input / output pin 80 58 A8 64 A9 52 SWO Serial wire viewer output pin 81 59 B8 65 B8 53 TCK J-TAG test clock input pin 78 56 B9 62 B9 50 TDI J-TAG test data input pin 79 57 B11 63 B11 51 TDO J-TAG debug data output pin 81 59 B8 65 B8 53 TMS J-TAG test mode state input/output pin 80 58 A8 64 A9 52 TRACECLK Trace CLK output pin of ETM 86 64 C7 - - - TRACED0 Trace data output pins of ETM 82 60 C8 - - - TRACED1 83 61 D9 - - - TRACED2 84 62 A7 - - - TRACED3 85 63 B7 - - - TRSTX J-TAG test reset input pin 77 55 A9 61 A10 49 External Bus MAD00_1 External bus interface address bus 31 9 H5 21 L5 - MAD01_1 32 10 L6 22 K5 - MAD02_1 39 17 K6 29 J5 - MAD03_1 40 18 J6 30 K6 - MAD04_1 41 19 L7 31 J6 - MAD05_1 42 20 K7 32 L7 - MAD06_1 43 21 H6 33 K7 - MAD07_1 44 22 J7 34 J7 - MAD08_1 45 23 K8 35 K8 - MAD09_1 53 31 J10 43 J10 - MAD10_1 54 32 J8 44 J8 - MAD11_1 55 33 H10 45 H10 - MAD12_1 56 34 H9 46 H9 - MAD13_1 57 35 H7 47 G10 - MAD14_1 58 36 G10 48 G9 - MAD15_1 59 37 G9 49 F10 - MAD16_1 63 41 G8 53 F9 - MAD17_1 64 42 F10 54 E11 - MAD18_1 65 43 F9 55 E10 - MAD19_1 66 44 E11 56 E9 - MAD20_1 67 45 E10 - - - MAD21_1 68 46 F8 - - - MAD22_1 69 47 E9 - - - MAD23_1 70 48 D11 - - - MAD24_1 74 52 C10 60 C10 -

30 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- External Bus MCSX0_1 External bus interface chip select output pin 88 66 A6 68 C7 - MCSX1_1 87 65 D7 67 C8 - MCSX2_1 86 64 C7 - - - MCSX3_1 85 63 B7 - - - MCSX4_1 83 61 D9 - - - MCSX5_1 82 60 C8 - - - MCSX6_1 79 57 B11 63 B11 - MCSX7_1 77 55 A9 61 A10 - MDQM0_1 External bus interface byte mask signal output pin 90 68 C6 70 B6 - MDQM1_1 91 69 A5 71 C6 - MOEX_1 External bus interface read enable signal for SRAM 94 72 C5 74 C5 - MWEX_1 External bus interface write enable signal for SRAM 93 71 D6 73 B5 - MADA TA00_1 External bus interface data bus 2 80 C1 2 C1 - MADA TA01_1 3 81 C2 3 C2 - MADA TA02_1 4 82 B3 4 B3 - MADA TA03_1 5 83 D1 5 D1 - MADA TA04_1 6 84 D2 6 D2 - MADA TA05_1 7 85 D3 7 D3 - MADA TA06_1 8 86 D5 8 E1 - MADA TA07_1 9 87 E1 9 E2 - MADA TA08_1 10 88 E2 10 E3 - MADA TA09_1 11 89 E3 11 G1 - MADA TA10_1 12 90 E4 12 G2 - MADA TA11_1 13 91 F1 - - - MADA TA12_1 14 92 F2 - - - MADA TA13_1 15 93 F3 - - - MADA TA14_1 16 94 G1 - - - MADA TA15_1 17 95 G2 - - - MALE_1 Address Latch enable signal for multiplex 89 67 B6 69 B7 - MRDY_1 External RDY input signal 96 74 C4 76 C4 - MCLKOUT_1 External bus clock output pin 84 62 A7 66 A8 -

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 31 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- External Interrupt INT00_0 External interrupt request 00 input pin 2 80 C1 2 C1 2 INT00_1 82 60 C8 - - - INT00_2 87 65 D7 67 C8 54 INT01_0 External interrupt request 01 input pin 3 81 C2 3 C2 3 INT01_1 83 61 D9 - - - INT02_0 External interrupt request 02 input pin 4 82 B3 4 B3 4 INT02_1 53 31 J10 43 J10 35 INT03_0 External interrupt request 03 input pin 93 71 D6 73 B5 - INT03_1 56 34 H9 46 H9 38 INT03_2 9 87 E1 9 E2 5 INT04_0 External interrupt request 04 input pin 12 90 E4 12 G2 8 INT04_1 59 37 G9 49 F10 40 INT04_2 10 88 E2 10 E3 6 INT05_0 External interrupt request 05 input pin 74 52 C10 60 C10 - INT05_1 65 43 F9 55 E10 - INT05_2 11 89 E3 11 G1 7 INT06_1 External interrupt request 06 input pin 73 51 C11 59 C11 48 INT06_2 45 23 K8 35 K8 27 INT07_2 External interrupt request 07 input pin 5 83 D1 5 D1 - INT08_1 External interrupt request 08 input pin 14 92 F2 - - - INT08_2 8 86 D5 8 E1 - INT09_1 External interrupt request 09 input pin 15 93 F3 - - - INT10_1 External interrupt request 10 input pin 16 94 G1 - - - INT11_1 External interrupt request 11 input pin 17 95 G2 - - - INT12_1 External interrupt request 12 input pin 27 5 J4 - - - INT13_1 External interrupt request 13 input pin 28 6 L5 - - - INT14_1 External interrupt request 14 input pin 39 17 K6 29 J5 - INT15_1 External interrupt request 15 input pin 96 74 C4 76 C4 60 NMIX Non-Maskable Interrupt input pin 92 70 B5 72 A6 57

32 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- GPIO P00 General-purpose I/O port 0 77 55 A9 61 A10 49 P01 78 56 B9 62 B9 50 P02 79 57 B11 63 B11 51 P03 80 58 A8 64 A9 52 P04 81 59 B8 65 B8 53 P05 82 60 C8 - - - P06 83 61 D9 - - - P07 84 62 A7 66 A8 - P08 85 63 B7 - - - P09 86 64 C7 - - - P0A 87 65 D7 67 C8 54 P0B 88 66 A6 68 C7 55 P0C 89 67 B6 69 B7 56 P0D 90 68 C6 70 B6 - P0E 91 69 A5 71 C6 - P0F 92 70 B5 72 A6 57 P10 General-purpose I/O port 1 52 30 J11 42 J11 34 P11 53 31 J10 43 J10 35 P12 54 32 J8 44 J8 36 P13 55 33 H10 45 H10 37 P14 56 34 H9 46 H9 38 P15 57 35 H7 47 G10 39 P16 58 36 G10 48 G9 - P17 59 37 G9 49 F10 40 P18 63 41 G8 53 F9 44 P19 64 42 F10 54 E11 45 P1A 65 43 F9 55 E10 - P1B 66 44 E11 56 E9 - P1C 67 45 E10 - - - P1D 68 46 F8 - - - P1E 69 47 E9 - - - P1F 70 48 D11 - - - P20 General-purpose I/O port 2 74 52 C10 60 C10 - P21 73 51 C11 59 C11 48 P22 72 50 E8 58 D9 47 P23 71 49 D10 57 D10 46

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 33 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- GPIO P30 General-purpose I/O port 3 9 87 E1 9 E2 5 P31 10 88 E2 10 E3 6 P32 11 89 E3 11 G1 7 P33 12 90 E4 12 G2 8 P34 13 91 F1 - - - P35 14 92 F2 - - - P36 15 93 F3 - - - P37 16 94 G1 - - - P38 17 95 G2 - - - P39 18 96 F4 13 G3 9 P3A 19 97 G3 14 H1 10 P3B 20 98 H1 15 H2 11 P3C 21 99 H2 16 H3 12 P3D 22 100 G4 17 J1 13 P3E 23 1 H3 18 J2 14 P3F 24 2 J2 19 J4 15 P40 General-purpose I/O port 4 27 5 J4 - - - P41 28 6 L5 - - - P42 29 7 K5 - - - P43 30 8 J5 - - - P44 31 9 H5 21 L5 - P45 32 10 L6 22 K5 - P46 36 14 L3 26 L3 19 P47 37 15 K3 27 K3 20 P48 39 17 K6 29 J5 - P49 40 18 J6 30 K6 22 P4A 41 19 L7 31 J6 23 P4B 42 20 K7 32 L7 24 P4C 43 21 H6 33 K7 25 P4D 44 22 J7 34 J7 26 P4E 45 23 K8 35 K8 27 P50 General-purpose I/O port 5 2 80 C1 2 C1 2 P51 3 81 C2 3 C2 3 P52 4 82 B3 4 B3 4 P53 5 83 D1 5 D1 - P54 6 84 D2 6 D2 - P55 7 85 D3 7 D3 - P56 8 86 D5 8 E1 - P60 General-purpose I/O port 6 96 74 C4 76 C4 60 P61 95 73 B4 75 B4 59 P62 94 72 C5 74 C5 58 P63 93 71 D6 73 B5 - P80 General-purpose I/O port 8 98 76 A3 78 A3 62 P81 99 77 A2 79 A2 63 PE0 General-purpose I/O port E 46 24 K9 36 K9 28 PE2 48 26 L9 38 L9 30 PE3 49 27 L10 39 L10 31

34 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 73 51 C11 59 C11 48 SIN0_1 56 34 H9 46 H9 - SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 72 50 E8 58 D9 47 SOT0_1 (SDA0_1) 57 35 H7 47 G10 - SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 71 49 D10 57 D10 46 SCK0_1 (SCL0_1) 58 36 G10 48 G9 - Multi- function Serial SIN1_1 Multi-function serial interface ch.1 input pin 53 31 J10 43 J10 35 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 54 32 J8 44 J8 36 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 55 33 H10 45 H10 37

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 35 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Multi- function Serial SIN2_2 Multi-function serial interface ch.2 input pin 59 37 G9 49 F10 40 SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 63 41 G8 53 F9 44 SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 64 42 F10 54 E11 45 Multi- function Serial SIN3_1 Multi-function serial interface ch.3 input pin 2 80 C1 2 C1 2 SIN3_2 39 17 K6 29 J5 - SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 3 81 C2 3 C2 3 SOT3_2 (SDA3_2) 40 18 J6 30 K6 - SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 82 B3 4 B3 4 SCK3_2 (SCL3_2) 41 19 L7 31 J6 -

36 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 87 65 D7 67 C8 54 SIN4_1 65 43 F9 55 E10 - SIN4_2 82 60 C8 - - - SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 88 66 A6 68 C7 55 SOT4_1 (SDA4_1) 66 44 E11 56 E9 - SOT4_2 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 89 67 B6 69 B7 56 SCK4_1 (SCL4_1) 67 45 E10 - - - SCK4_2 RTS4_0 Multi-function serial interface ch.4 RTS output pin 90 68 C6 70 B6 - RTS4_1 69 47 E9 - - - RTS4_2 86 64 C7 - - - CTS4_0 Multi-function serial interface ch.4 CTS input pin 91 69 A5 71 C6 - CTS4_1 68 46 F8 - - - CTS4_2 85 63 B7 - - - Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 96 74 C4 76 C4 60 SIN5_2 15 93 F3 - - - SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 95 73 B4 75 B4 59 SOT5_2 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 94 72 C5 74 C5 58 SCK5_2

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 37 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 5 83 D1 5 D1 - SIN6_1 12 90 E4 12 G2 8 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). 6 84 D2 6 D2 - SOT6_1 (SDA6_1) 11 89 E3 11 G1 7 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 7 85 D3 7 D3 - SCK6_1 (SCL6_1) 10 88 E2 10 E3 6 Multi- function Serial SIN7_1 Multi-function serial interface ch.7 input pin 45 23 K8 35 K8 27 SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 44 22 J7 34 J7 26 SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 43 21 H6 33 K7 25

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Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- USB UDM0 USB function/host D – pin 98 76 A3 78 A3 62 UDP0 USB function/host D + pin 99 77 A2 79 A2 63 UHCONX USB external pull-up control pin 95 73 B4 75 B4 59 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 92 70 B5 72 A6 57 RTCCO_1 55 33 H10 45 H10 37 RTCCO_2 19 97 G3 14 H1 10 SUBOUT_0 Sub clock output pin 92 70 B5 72 A6 57 SUBOUT_1 55 33 H10 45 H10 37 SUBOUT_2 19 97 G3 14 H1 10 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 92 70 B5 72 A6 57 WKUP1 Deep standby mode return signal input pin 1 53 31 J10 43 J10 35 WKUP2 Deep standby mode return signal input pin 2 73 51 C11 59 C11 48 WKUP3 Deep standby mode return signal input pin 3 96 74 C4 76 C4 60 HDMI- CEC/ Remote Control Reception CEC0 HDMI-CEC/Remote Control Reception ch.0 input/output pin 43 21 H6 33 K7 25 CEC1 HDMI-CEC/Remote Control Reception ch.1 input/output pin 96 74 C4 76 C4 60 Reset INITX External Reset Input pin. A reset is valid when INITX=L. 38 16 K4 28 K4 21 Mode MD0 Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. 47 25 L8 37 L8 29 MD1 Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. 46 24 K9 36 K9 28 Power VCC Power supply Pin 1 79 B1 1 B1 1 26 4 J1 - - - 35 13 K1 25 K1 18 51 29 K11 41 K11 33 76 54 A10 - - - 97 75 A4 77 A4 61

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 39 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- BGA- LQFP/ QFN- GND VSS GND Pin - - - - F1 - - - - - F2 - - - - - F3 - - - B2 - B2 - 25 3 L1 20 L1 16 - - K2 - K2 - - - J3 - J3 - - - H4 - - - - - - - L6 - 34 12 L4 24 L4 - 50 28 L11 40 L11 32 - - K10 - K10 - - - J9 - J9 - - - H8 - - - - - B10 - B10 - - - C9 - C9 - - - - - D11 - 75 53 A11 - A11 - - - D8 - - - - - - - A7 - - - D4 - - - - - C3 - C3 - - - - - A5 - 100 78 A1 80 A1 64 Clock X0 Main clock (oscillation) input pin 48 26 L9 38 L9 30 X0A Sub clock (oscillation) input pin 36 14 L3 26 L3 19 X1 Main clock (oscillation) I/O pin 49 27 L10 39 L10 31 X1A Sub clock (oscillation) I/O pin 37 15 K3 27 K3 20 CROUT_0 Built-in high-speed CR-osc clock output port 74 52 C10 60 C10 - CROUT_1 92 70 B5 72 A6 57 ADC power A VCC A/D converter analog power supply pin 60 38 H11 50 H11 41 A VRH A/D converter analog reference voltage input pin 61 39 F11 51 F11 42 ADC GND A VSS A/D converter GND pin 62 40 G11 52 G11 43 C pin C Power supply stabilization capacity pin 33 11 L2 23 L2 17

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 I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 33 kΩ  IOH= -4 mA, IOL= 4 mA B  CMOS level hysteresis input  Pull-up resistor : Approximately 33 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control Pull-up resistor Digital input

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 41 CONFIDENTIAL Type Circuit Remarks C N-ch  Open drain output  CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5 MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With Standby mode control  Pull-up resistor : Approximately 33 kΩ  IOH= -4 mA, IOL= 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

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E P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With Standby mode control  Pull-up resistor : Approximately 33 kΩ  IOH= -4 mA, IOL= 4 mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off F P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  With input control  Analog input  With pull-up resistor control  With Standby mode control  Pull-up resistor : Approximately 33 kΩ  IOH= -4 mA, IOL= 4 mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off G CMOS level hysteresis input Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Mode input

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 43 CONFIDENTIAL Type Circuit Remarks H UDP0/P81 UDM0/P80 Differential It is possible to select the USB I/O / GPIO function. When the USB I/O is selected.  Full-speed, Low-speed control When the GPIO is selected.  CMOS level output  CMOS level hysteresis input  With Standby mode control I P-chP-ch N-ch R  CMOS level output  CMOS level hysteresis input  5 V tolerant  With pull-up resistor control  With Standby mode control  Pull-up resistor : Approximately 33 kΩ  IOH= -4 mA, IOL= 4 mA  Available to control PZR registers.  When this pin is used as an I2C pin, the digital output P-ch transistor is always off GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output USB Full-speed/Low-speed control UDP input Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Digital output Digital output Pull-up resistor control Digital input Standby mode control

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 Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semicondu ctor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-V oltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of op eration. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 45 CONFIDENTIAL  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or w here extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through -holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions.

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 Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 47 CONFIDENTIAL 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to c hemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

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 Handling Devices  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypa ss capacitor between each Power supply pin and GND pin, between A VCC pin and A VSS pin near this device.  Stabilizing supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circ uit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0 /X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board.  Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ・Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF ・Lead type Load capacitance: Approximately 6 pF to 7 pF

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 49 CONFIDENTIAL  Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.  Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.  C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equiva lent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series.  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.

Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Device C VSS CS GND Set as External clock input

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 Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect A VCC = VCC and A VSS = VSS. Turning on : VCC →AVCC → AVRH Turning off : AVRH → AVCC → VCC  Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applyi ng a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to e valuate the electric characteristics.  Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 51 CONFIDENTIAL  Block Diagram AHB-APB Bridge: APB0(Max 40 MHz) Multi-layer AHB (Max 40 MHz) AHB-AHB Bridge AHB-APB Bridge : APB1 (Max 40 MHz) AHB-APB Bridge : APB2 (Max 40 MHz) Cortex-M3 Core @40 MHz(Max) Flash I/F Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 16-pin + NMI Power-On Reset SRAM0 8/16 Kbyte SRAM1 8/16 Kbyte I D Sys NVIC WatchDog Timer (Software) Security 12-bit A/D Converter Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO SCKx SINx SOTx INTx NMIX P0x, P1x, PEx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator ADTGx RTS4 CTS4 MADx MADATAx MCSXx, MOEX, MWEX, MALE, MRDY, MCLKOUT, MDQMx On-Chip Flash 64+32 Kbyte/ 128+32 Kbyte/ 256+32 Kbyte UDP0/UDM0 UHCONX Multi-Function Serial I/F 8ch. (with FIFO ch.4 to ch.7) HW flow control(ch.4)*2 External Bus I/F*2 GPIO PIN-Function-Ctrl LVD USB2.0 (Host/ Func) PHY TPIU*1 ROM Table ETM*1SWJ-DP CEC0,CEC1 LVD Ctrl Base Timer 16-bit 8ch./ 32-bit 4ch. HDMI-CEC/ Remote Reciver Control Real-Time ClockRTCCO, SUBOUT USB Clock Ctrl PLL Deep Standby CtrlWKUPx CLK X0A X1A Main Osc PLL Sub Osc CR

4 MHz

*1: For the MB9AF341LB/MB, MB9AF342LB/MB, and MB9AF344LB/MB, ETM is not available. *2: For the MB9AF341LB, MB9AF342LB and MB9AF344LB, the External Bus Interface is not available. And the Multi-function Serial Interface does not support hardware flow control in these products.  Memory Size See  Memory size in Product Lineup to confirm the memory size.

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 Memory Map  Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0x4006_1000 0xE000_0000 0x4006_0000 DMAC 0x4005_0000 Reserved 0x4004_0000 USB ch.0 0x4003_F000 EXT-bus I/F 0x4003_C000 Reserved 0x4003_B000 RTC 0x4003_A000 Watch Counter 0x7000_0000 0x4003_9000 CRC 0x4003_8000 MFS 0x6000_0000 0x4003_7000 Reserved 0x4003_6000 USB Clock Ctrl 0x4003_5000 LVD/DS mode 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4000_0000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2400_0000 0x4002_E000 CR Trim 0x2200_0000 0x4002_8000 0x4002_7000 A/DC 0x4002_6000 Reserved 0x2008_0000 0x4002_5000 Base Timer 0x2000_0000 SRAM1 0x1FFF_0000 SRAM0 0x0020_8000 Reserved 0x0020_0000 Flash(Work area) 0x0010_4000 Reserved 0x0010_0000 Security/CR Trim 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x0000_0000 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F See the next page "lMemory Map (2)" for the memory size details. HDMI-CEC/ Remote Control Receiver Reserved Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved 32Mbytes Bit band alias Flash(Main area) Reserved Reserved Reserved Reserved Cortex-M3 Private Peripherals Reserved Reserved External Device Area

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 53 CONFIDENTIAL  Memory Map (2) MB9AF344LB/MB/NB MB9AF342LB/MB/NB MB9AF341LB/MB/NB 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_E000 0x1FFF_E000 0x1FFF_C000 0x0020_8000 0x0020_8000 0x0020_8000 0x0020_0000 0x0020_0000 0x0020_0000 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0010_0000 Security 0x0004_0000 0x0002_0000 0x0001_0000 0x0000_0000 SA2-3 (8 KBx2) 0x0000_0000 SA2-3 (8 KBx2) 0x0000_0000 SA2-3 (8 KBx2) Flash(Main area)

64 Kbytes

SA9 (64 KB) SA8 (48 KB) SA8 (48 KB) SA8 (48 KB) Reserved SA9-11 (64 KBx3) Flash(Main area)

256 Kbytes

Flash(Main area)

128 Kbytes

Flash(Work area)

32 Kbytes

SA4-7 (8 KBx4) SA4-7 (8 KBx4) Reserved Reserved Reserved SRAM1 8Kbytes SRAM1 8Kbytes SRAM0 8Kbytes SRAM0 8Kbytes Reserved Reserved Flash(Work area) SA4-7 (8 KBx4) Reserved Flash(Work area) Refer to the programming manual for the detail of Flash main area. ・MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Progra mming Manual

54 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_4FFF APB1 Reserved 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Reserved 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Receiver 0x4003_5000 0x4003_57FF Low-V oltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Bus interface 0x4004_0000 0x4004_FFFF AHB USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x41FF_FFFF Reserved

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 55 CONFIDENTIAL  Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.

56 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at or Input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 57 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z/ Internal input fixed at 0 Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 H GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected USB I/O pin Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z at trans- mission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z at trans- mission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled

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Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - I NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected J JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected K Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected L External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 59 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - N Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected O Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected

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Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Q Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External interrupt enabled selected Maintain previous state Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected R Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected S CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 61 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - T CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.

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 Electrical Characteristics 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1, *2 VCC VSS - 0.5 VSS + 4.6 V Analog power supply voltage*1, *3 AVCC VSS - 0.5 VSS + 4.6 V Analog reference voltage*1, *3 AVRH VSS - 0.5 VSS + 4.6 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 4.6 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V L level maximum output current*4 IOL - 10 mA 39 mA P81/UDP0 , P80/UDM0 pins L level average output current*5 IOLA V - 4 mA 10.5 mA *7 27 mA *8 L level total maximum output current ∑IOL - 100 mA L level total average output current*6 ∑IOLA V - 50 mA H level maximum output current*4 IOH - - 10 mA 39 mA P81/UDP0 , P80/UDM0 pins H level average output current*5 IOHA V - - 4 mA 12 mA *7 27 mA *8 H level total maximum output current ∑IOH - - 100 mA H level total average output current*6 ∑IOHA V - - 50 mA Power consumption PD - 300 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. *7: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *8: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 63 CONFIDENTIAL 2. Recommended Operating Conditions (VSS = A VSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 1.65*4 3.6 V *1 3.0*4 3.6 *2 Analog power supply voltage AVCC - 1.65 3.6 V AVCC = VCC Analog reference voltage A VRH - 2.7 AVCC V AVCC ≥ 2.7 V AVCC AVCC V AVCC<2.7 V Smoothing capacitor CS -- 1 10 µF For Regulator*3 Operating temperature TA - - 40 + 85 °C *1: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *2: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *3: See  C Pin in  Handling Devices for the connection of the smoothing capacitor. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

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DC Characteristics (1) Current rating (VCC = A VCC = 1.65V to 3.6V, VSS = A VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 Power supply current ICC VCC PLL Rrun mode CPU: 40 MHz, Peripheral: 40 MHz 15.5 21 mA *1, *5 CPU: 40 MHz, Peripheral: the clock stops NOP operation 8.7 12 mA *1, *5 High-speed CR Rrun mode CPU/ Peripheral: 4 MHz*2 1.8 2.9 mA *1 Sub Rrun mode CPU/ Peripheral: 32 kHz 110 680 μA *1, *6 Low-speed CR Run mode CPU/ Peripheral: 100 kHz 125 700 μA *1 ICCS PLL Sleep mode Peripheral: 40 MHz 9 12.5 mA *1, *5 High-speed CR Sleep mode Peripheral: 4 MHz*2 0.8 1.6 mA *1 Sub Sleep mode Peripheral: 32 kHz 96 670 μA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 110 680 μA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.6 V *4: TA=+85°C, VCC=3.6 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 65 CONFIDENTIAL Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*2 Power supply current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 2.1 2.5 mA *1, *3 TA = + 85°C, When LVD is off - 3.4 mA *1, *3 Sub Timer mode TA = + 25°C, When LVD is off 12 35 μA *1, *4 TA = + 85°C, When LVD is off - 330 μA *1, *4 ICCR RTC mode TA = + 25°C, When LVD is off 9.8 29 μA *1, *4 TA = + 85°C, When LVD is off - 280 μA *1, *4 ICCH Stop mode TA = + 25°C, When LVD is off 9 28 μA *1 TA = + 85°C, When LVD is off - 270 μA *1 ICCHD Deep Standby Stop mode TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off - 70 μA *1, *4, *5 TA = + 85°C, When LVD is off, When RAM is on 100 μA *1, *4, *5 ICCRD Deep Standby RTC mode TA = + 25°C, When LVD is off, When RAM is off 1.9 9 μA *1, *5 TA = + 25°C, When LVD is off, When RAM is on 5.9 20 μA *1, *5 TA = + 85°C, When LVD is off, When RAM is off - 75 μA *1, *5 TA = + 85°C, When LVD is off, When RAM is on 105 μA *1, *5 *1: When all ports are fixed. *2: VCC=3.6 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) *5: RAM on/off setting is on-chip SRAM only.

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Low-Voltage Detection Current (VCC = 1.65V to 3.6V , VDDI = 1.1V to 1.3V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for reset VCC = 3.6 V 0.13 0.3 μA At not detect At operation for interrupt VCC = 3.6 V 0.13 0.3 μA At not detect
Flash Memory Current (VCC = 1.65V to 3.6V , VDDI = 1.1V to 1.3V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 9.5 11.2 mA * *: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
A/D Converter Current (VCC = VCC28 = A VCC = 1.65V to 3.6V , VDDI = 1.1V to 1.3V , VSS = A VSS = 0V , TA = - 40°C to +85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD A VCC At 1unit operation 0.27 0.42 mA At stop 0.03 10 μA Reference power supply current ICCA VRH A VRH At 1unit operation A VRH=3.6 V 0.72 1.29 mA At stop 0.02 2.6 μA

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 67 CONFIDENTIAL (2) Pin Characteristics (VCC = AVCC = 1.65V to 3.6V, VSS = A VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 VCC ≥ 2.7 V VCC × 0.8 - VCC + 0.3 V VCC < 2.7 V VCC × 0.7 5V tolerant input pin VCC ≥ 2.7 V VCC × 0.8 - VSS + 5.5 V VCC < 2.7 V VCC × 0.7 L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 VCC ≥ 2.7 V VSS - 0.3 - VCC × 0.2 V VCC < 2.7 V VCC × 0.3

5 V tolerant

VCC ≥ 2.7 V VSS - 0.3 - VCC × 0.2 V VCC < 2.7 V VCC × 0.3 H level output voltage VOH 4 mA type VCC ≥ 2.7 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 2.7 V, IOH = - 2 mA VCC - 0.45 The pin doubled as USB I/O VCC ≥ 2.7 V, IOH = - 12 mA VCC - 0.4 - VCC V VCC < 2.7 V, IOH = - 6.5 mA L level output voltage VOL 4 mA type VCC ≥ 2.7 V, IOL = 4 mA VSS - 0.4 V VCC < 2.7 V, IOL = 2 mA The pin doubled as USB I/O VCC ≥ 2.7 V, IOL = 10.5 mA VSS - 0.4 V VCC < 2.7 V, IOL = 5 mA Input leak current IIL - - - 5 - + 5 μA CEC0, CEC1 VCC = AVCC = AVRH = VSS = AVSS = 0.0 V - - +1.8 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 2.7 V 21 33 66 kΩ VCC < 2.7 V - - 134 Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, A VRH - - 5 15 pF

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AC Characteristics (1) Main Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 2.7 V 4 48 MHz When crystal oscillator is connected VCC < 2.7 V 4 20 - 4 48 MHz When using external clock Input clock cycle tCYLH - 20.83 250 ns When using external clock Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCM - - - 40 MHz Master clock fCC - - - 40 MHz Base clock (HCLK/FCLK) fCP0 - - - 40 MHz APB0 bus clock*2 fCP1 - - - 40 MHz APB1 bus clock*2 fCP2 - - - 40 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 25 - ns APB0 bus clock*2 tCYCP1 - - 25 - ns APB1 bus clock*2 tCYCP2 - - 25 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see  Block Diagram in this data sheet.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 69 CONFIDENTIAL (2) Sub Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency fCL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock (3) Built-in CR Oscillation Characteristics  Built-in High-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TA = + 25°C VCC ≥ 2.7 V 3.96 4 4.04 MHz When trimming*1 TA = + 25°C VCC < 2.7 V 3.9 4 4.1 TA = - 40°C to + 85°C 3.84 4 4.16 TA = - 40°C to + 85°C 2.8 - 5.2 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock.  Built-in Low-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz X0A

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(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiple rate - 5 - 37 multiple PLL macro oscillation clock frequency fPLLO 75 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 40 MHz USB clock frequency*3 fCLKSPLL - - 48 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *3: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM3 Family Peripheral Manual Communication Macro Part. (4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiple rate - 19 - 35 multiple PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 40 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. High-speed CR clock (CLKHC) PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection Main clock (CLKMO) K divider Main clock (CLKMO) K divider PLL input clock USB PLL M divider USB clock N divider USB PLL connection PLL macro oscillation clock

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 71 CONFIDENTIAL (5) Reset Input Characteristics (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns (6) Power-on Reset Timing (VCC= 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Max Power supply rising time tVCCR VCC 0 - ms Power supply shut down time tOFF 1 - ms Time until releasing Power-on reset tPRT 1.34 16.09 ms 0.2V VDH_minimum VCC_minimum tPRT Internal reset VCC CPU Operation start Reset active Release tVCCR 0.2V 0.2V tOFF Glossary ・ VCC_minimum: Minimum VCC of recommended operating conditions ・ VDH_minimum: Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset See 7. Low-Voltage Detection Characteristics

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(7) External Bus Timing  External bus clock output characteristics (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT* VCC ≥ 2.7 V - 40 MHz VCC < 2.7 V - 20 MHz *: The external bus clock output (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual. When external bus clock is not output, this characteristic does not give any effect on external bus operation.  External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH Input signal Output signal MCLKOUT

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 73 CONFIDENTIAL  Separate Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V MCSX ↓ → Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] VCC ≥ 2.7 V -9 +9 ns VCC < 2.7 V -12 +12 MOEX ↑ → Address hold time tOEH - AX MOEX, MAD[24:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MOEX ↓ delay time tCSL - OEL MOEX, MCSX[7:0] VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX, MDQM[1:0] VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX, MADA TA[15:0] VCC ≥ 2.7 V 30 - ns VCC < 2.7 V 38 - MOEX ↑ → Data hold time tDH - OE MOEX, MADA TA[15:0] VCC ≥ 2.7 V 0 - ns VCC < 2.7 V MWEX Min pulse width tWEW MWEX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V MWEX ↑ → Address output delay time tWEH - AX MWEX, MAD[24:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX, MCSX[7:0] VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 ns VCC < 2.7 V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓→ MDQM ↓ delay time tCSL-WDQML MCSX, MDQM[1:0] VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 ns VCC < 2.7 V MCLK×n-12 MCLK×n+12 MWEX ↓→ Data output time tCSL - DV MCSX, MADA TA[15:0] VCC ≥ 2.7 V MCLK-9 MCLK+9 ns VCC < 2.7 V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX, MADA TA[15:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).

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MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 75 CONFIDENTIAL  Separate Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] VCC ≥ 2.7 V 1 12 ns VCC < 2.7 V 13 MCSX delay time tCSL MCLK, MCSX[7:0] VCC ≥ 2.7 V 1 12 ns VCC < 2.7 V tCSH VCC ≥ 2.7 V 1 12 ns VCC < 2.7 V MOEX delay time tREL MCLK, MOEX VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tREH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 Data set up → MCLK ↑ time tDS MCLK, MADA TA[15:0] VCC ≥ 2.7 V 24 - ns VCC < 2.7 V 37 MCLK ↑ → Data hold time tDH MCLK, MADA TA[15:0] VCC ≥ 2.7 V 0 - ns VCC < 2.7 V MWEX delay time tWEL MCLK, MWEX VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tWEH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tDQMH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MCLK ↑ → Data output time tODS MCLK, MADA TA[15:0] VCC ≥ 2.7 V MCLK + 1 MCLK + 18 ns VCC <2.7 V MCLK + 24 MCLK ↑ → Data hold time tOD MCLK, MADA TA[15:0] VCC ≥ 2.7 V 1 18 ns VCC <2.7 V 24 Note: When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

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 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADA TA[15:0] VCC ≥ 2.7 V -2 +10 ns VCC < 2.7 V +20 Multiplexed address hold time tCHMADH VCC ≥ 2.7 V MCLK×n+0 MCLK×n+10 ns VCC < 2.7 V MCLK×n+0 MCLK×n+20 Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 77 CONFIDENTIAL  Multiplexed Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 ns tCHAH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK, MADA TA[15:0] VCC ≥ 2.7 V 1 tOD ns VCC < 2.7 V MCLK ↑ → Multiplexed Data output time tCHMADX VCC ≥ 2.7 V 1 tOD ns VCC < 2.7 V Note: When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

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 External Ready Input Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MCLK ↑ MRDY input setup time tRDYI MCLK, MRDY VCC ≥ 2.7 V 23 - ns VCC < 2.7 V 37 When RDY is input

· · Over 2cycles tRDYI When RDY is released 2 cycles tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 79 CONFIDENTIAL (8) Base Timer Input Timing  Timer input timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns tTIWH VIHS VIHS VILS VILS tTIWL  Trigger input timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns tTRGH VIHS VIHS VILS VILS tTRGL Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see  Block Diagram in this data sheet. ECK TIN TGIN

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(9) CSIO/UART Timing  CSIO (SPI = 0, SCINV = 0) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 36 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to clock synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see  Block Diagram in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30 pF.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 81 CONFIDENTIAL Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

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 CSIO (SPI = 0, SCINV = 1) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 36 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to clock synchronous mode.  tCYCP indicates the APB bus clock cycle time.  About the APB bus number which Multi-function serial is connected to, see  Block Diagram in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30 pF.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 83 CONFIDENTIAL Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

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 CSIO (SPI = 1, SCINV = 0) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 36 - ns SCK ↓→ SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 34 - 2tCYCP - 34 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to clock synchronous mode.  tCYCP indicates the APB bus clock cycle time.  About the APB bus number which Multi-function serial is connected to, see  Block Diagram in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30 pF.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 85 CONFIDENTIAL Master mode Slave mode *: Changes when writing to TDR register tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN

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 CSIO (SPI = 1, SCINV = 1) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 36 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 34 - 2tCYCP - 34 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to clock synchronous mode.  tCYCP indicates the APB bus clock cycle time.  About the APB bus number which Multi-function serial is connected to, see  Block Diagram in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30 pF.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 87 CONFIDENTIAL Master mode Slave mode  UART external clock input (EXT = 1) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN SCK

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(10) External Input Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt NMI *3 500 - ns WKUPx *4 600 - ns Deep standby wake up *1 : tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Multi-function Timer is connected to, see  Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Stop mode, in Timer mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 89 CONFIDENTIAL (11) I2C Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDA T 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDA T 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDA T must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDA T ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see  Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

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(12) ETM Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] VCC ≥ 2.7 V 2 11 ns VCC < 2.7 V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK VCC ≥ 2.7 V - 40 MHz VCC < 2.7 V - 20 MHz TRACECLK clock cycle tTRACE VCC ≥ 2.7 V 25 - ns VCC < 2.7 V 50 - ns Note: When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[3:0]

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 91 CONFIDENTIAL (13) JTAG Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 2.7 V 15 - ns VCC < 2.7 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 2.7 V 15 - ns VCC < 2.7 V TDO delay time tJTAGD TCK, TDO VCC ≥ 2.7 V - 25 ns VCC < 2.7 V - 45 Note: When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO

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12-bit A/D Converter  Electrical Characteristics for the A/D Converter (VCC = A VCC = 1.65V to 3.6V , VSS = AVSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 2 ± 4.5 LSB Differential Nonlinearity - - - ± 2.2 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 6 ± 15 mV Full-scale transition voltage VFST ANxx - A VRH ± 6 A VRH ± 15 mV Conversion time - - 2.0*1 - - μs AVCC ≥ 2.7 V 10*1 - - 1.65 V< AVCC < 1.8 V Sampling time*2 tS - 0.6 - 10 us AVCC ≥ 2.7 V 1.2 - 1.8 V< AVCC < 2.7 V 3.0 - 1.65 V< AVCC < 1.8 V Compare clock cycle*3 tCCK - 100 - 1000 ns AVCC ≥ 2.7 V 200 1.8 V< AVCC < 2.7 V 500 1.65 V< AVCC < 1.8 V State transition time to operation permission tSTT - - - 1.0 μs Power supply current (analog + digital) - A VCC - 0.27 0.42 mA A/D 1unit operation - 0.03 10 μA When A/D stops Reference power supply current (between A VRH to A VSS) - A VRH - 0.72 1.29 mA A/D 1unit operation A VRH=3.6 V - 0.02 2.6 μA When A/D stops Analog input capacity CAIN - - - 9.4 pF Analog input resistor RAIN - - - 2.2 kΩ AVCC ≥ 2.7 V 5.5 1.8 V< AVCC < 2.7 V 10.5 1.65 V< AVCC < 1.8 V Interchannel disparity - - - - 4 LSB Analog port input current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - A VRH V Reference voltage - A VRH 2.7 - AVCC V AVCC ≥ 2.7 V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V , HCLK=40 MHz sampling time: 0.6 μs, compare time: 1.4 μs 1.8 V < AVCC < 2.7 V, HCLK=40 MHz sampling time: 1.2 μs, compare time: 2.8 μs 1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Port. The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see  Block Diagram in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 93 CONFIDENTIAL (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time[ns] RAIN: input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V CAIN: input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V REXT: Output impedance of external circuit[kΩ] (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Analog signal source ANxx Analog input pin Comparator REXT RAIN CAIN

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 Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Linearity error of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential linearity error of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVSS AVRH AVSS AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 95 CONFIDENTIAL 6. USB Characteristics (VCC = 3.0V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input charac- teristics Input H level voltage VIH UDP0, UDM0 - 2.0 VCC + 0.3 V *1 Input L level voltage VIL - VSS - 0.3 0.8 V *1 Differential input sensitivity VDI - 0.2 - V *2 Different common mode range VCM - 0.8 2.5 V *2 Output charac- teristics Output H level voltage VOH External pull-down resistor = 15 kΩ 2.8 3.6 V *3 Output L level voltage VOL External pull-up resistor = 1.5 kΩ 0 0.3 V *3 Crossover voltage VCRS - 1.3 2.0 V *4 Rising time tFR Full-Speed 4 20 ns *5 Falling time tFF Full-Speed 4 20 ns *5 Rising/falling time matching tFRFM Full-Speed 90 111.11 % *5 Output impedance ZDRV Full-Speed 28 44 Ω *6 Rising time tLR Low-Speed 75 300 ns *7 Falling time tLF Low-Speed 75 300 ns *7 Rising/falling time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use the differential-Receiver to receive the USB differential data signal. The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Minimum differential input sensitivity [V]

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*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to ground and 15 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V . *5: They indicate the rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. VCRS specified range Rising time Falling time

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 97 CONFIDENTIAL *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 2 8 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use resistance with an uncertainty of 5% by E24 sequence. *7: They indicate the rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. See Figure  Low-Speed Load (Compliance Load) for conditions of the external load. Mount it as external resistor. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Rising time Falling time

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 Low-Speed Load (Upstream Port Load) - Reference 1  Low-Speed Load (Downstream Port Load) - Reference 2  Low-Speed Load (Compliance Load) CL = 50pF to 150pF CL = 50pF to 150pF CL = 200pF to 600pF CL = 200pF to 600pF CL = 200pF to 450pF CL = 200pF to 450pF

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 99 CONFIDENTIAL 7. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHR*1 = 00000 1.38 1.50 1.60 V When voltage drops Released voltage VDH 1.43 1.55 1.65 V When voltage rises Detected voltage VDL SVHR*1 = 00001 1.43 1.55 1.65 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00010 1.47 1.60 1.73 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00011 1.52 1.65 1.78 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00100 1.56 1.70 1.84 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00101 1.61 1.75 1.89 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00110 1.66 1.80 1.94 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00111 1.70 1.85 2.00 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01000 1.75 1.90 2.05 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01001 1.79 1.95 2.11 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01010 1.84 2.00 2.16 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01011 1.89 2.05 2.21 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01100 2.30 2.50 2.70 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01101 2.39 2.60 2.81 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01110 2.48 2.70 2.92 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01111 2.58 2.80 3.02 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10000 2.67 2.90 3.13 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10001 2.76 3.00 3.24 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10010 2.85 3.10 3.35 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10011 2.94 3.20 3.46 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises LVD stabilization wait time tLVDW - - - 5200 × tCYCP*2 μs LVD detection delay time tLVDDL - - - 200 μs *1: The SVHR bit of Low-Voltage Detection V oltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection Reset. *2: tCYCP indicates the APB2 bus clock cycle time.

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(2) Interrupt of Low-Voltage Detection (TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00100 1.56 1.70 1.84 V When voltage drops Released voltage VDH 1.61 1.75 1.89 V When voltage rises Detected voltage VDL SVHI = 00101 1.61 1.75 1.89 V When voltage drops Released voltage VDH 1.66 1.80 1.94 V When voltage rises Detected voltage VDL SVHI = 00110 1.66 1.80 1.94 V When voltage drops Released voltage VDH 1.70 1.85 2.00 V When voltage rises Detected voltage VDL SVHI = 00111 1.70 1.85 2.00 V When voltage drops Released voltage VDH 1.75 1.90 2.05 V When voltage rises Detected voltage VDL SVHI = 01000 1.75 1.90 2.05 V When voltage drops Released voltage VDH 1.79 1.95 2.11 V When voltage rises Detected voltage VDL SVHI = 01001 1.79 1.95 2.11 V When voltage drops Released voltage VDH 1.84 2.00 2.16 V When voltage rises Detected voltage VDL SVHI = 01010 1.84 2.00 2.16 V When voltage drops Released voltage VDH 1.89 2.05 2.21 V When voltage rises Detected voltage VDL SVHI = 01011 1.89 2.05 2.21 V When voltage drops Released voltage VDH 1.93 2.10 2.27 V When voltage rises Detected voltage VDL SVHI = 01100 2.30 2.50 2.70 V When voltage drops Released voltage VDH 2.39 2.60 2.81 V When voltage rises Detected voltage VDL SVHI = 01101 2.39 2.60 2.81 V When voltage drops Released voltage VDH 2.48 2.70 2.92 V When voltage rises Detected voltage VDL SVHI = 01110 2.48 2.70 2.92 V When voltage drops Released voltage VDH 2.58 2.80 3.02 V When voltage rises Detected voltage VDL SVHI = 01111 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHI = 10000 2.67 2.90 3.13 V When voltage drops Released voltage VDH 2.76 3.00 3.24 V When voltage rises Detected voltage VDL SVHI = 10001 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHI = 10010 2.85 3.10 3.35 V When voltage drops Released voltage VDH 2.94 3.20 3.46 V When voltage rises Detected voltage VDL SVHI = 10011 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises LVD stabilization wait time tLVDW - - - 5200 × tCYCP* μs LVD detection delay time tLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 101 CONFIDENTIAL 8. Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 1.1 2.7 s Includes write time prior to internal erase Small Sector 0.3 0.9 Half word (16-bit) write time 30 528 μs Not including system-level overhead time Chip erase time 6.8 18 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. (2) Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* *: At average + 85C

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Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. ・ Return Count Time (VCC = 1.65V to 3.6V , VDDI = 1.1V to 1.3V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs Low-speed CR Timer mode 350 700 μs Sub Timer mode 690 880 μs RTC mode, Stop mode 278 523 μs Deep Standby RTC mode Deep Standby Stop mode 318 603 μs When RAM is off 278 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 103 CONFIDENTIAL ・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.

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(2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. ・ Return Count Time (VCC = 1.65V to 3.6V , VDDI = 1.1V to 1.3V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 148 263 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 148 263 μs Low-speed CR Timer mode 258 483 μs Sub Timer mode 322 516 μs RTC/Stop mode 278 523 μs Deep Standby RTC mode Deep Standby Stop mode 318 603 μs When RAM is off 278 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 105 CONFIDENTIAL ・ Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. ・ The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. ・ When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. ・ The internal resource reset means the watchdog reset and the CSV reset.

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 Ordering Information Part number On-chip Flash memory On-chip MB9AF341LBPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  LQFP 64-pin (0.5mm pitch), (FPT-64P-M38) Tray MB9AF342LBPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344LBPMC1-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341LBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  LQFP 64-pin (0.65mm pitch), (FPT-64P-M39) MB9AF342LBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344LBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341LBQN-G-A VE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  QFN 64-pin (0.5mm pitch), (LCC-64P-M24) MB9AF342LBQN-G-A VE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344LBQN-G-A VE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341MBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  LQFP 80-pin (0.5mm pitch), (FPT-80P-M37) MB9AF342MBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344MBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341MBPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  LQFP 80-pin (0.65mm pitch), (FPT-80P-M40) MB9AF342MBPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344MBPMC1-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341MBBGL-GE1 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  PFBGA 96-pin (0.5mm pitch), (BGA-96P-M07) MB9AF342MBBGL-GE1 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344MBBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341NBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  LQFP 100-pin (0.5mm pitch), (FPT-100P-M23) MB9AF342NBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344NBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 107 CONFIDENTIAL Part number On-chip Flash memory On-chip MB9AF341NBPQC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  QFP 100-pin (0.65mm pitch), (FPT-100P-M36) Tray MB9AF342NBPQC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344NBPQC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9AF341NBBGL-GE1 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic  PFBGA 112-pin (0.8mm pitch), (BGA-112P-M04) MB9AF342NBBGL-GE1 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9AF344NBBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte

108 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

 Package Dimensions 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g 100-pin plastic LQFP (FPT-100P-M23) (FPT-100P-M23) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 12 5 100 0.145±0.055 (.006±.002) 0.08(.003) "A" INDEX 0°~8° 0.50±0.20 0.10±0.10 (Stand off) +.008 +0.20 (Mounting height) -0.101.50 .059 -.004( ) Dimensions in mm (inches). Note:The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part (.004±.004) (.009±.002) (.020±.008) (.024±.006)

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 109 CONFIDENTIAL 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14 × 20-0.65 100-pin plastic QFP (FPT-100P-M36) (FPT-100P-M36)

2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1C

(.551±.008) 17.90± 0.40 (.705±.016) INDEX (.013±.002) M0.13(.005) "A" 0.17 ± 0.06 (.007 ±. 002) 0.10(.004) Details of "A" part (.035 ±. 006) 0.88 ± 0.15 (.031 ±. 008) 0.80 ± 0.20 0.25(.010)3.00 +0.35 –0.20 +.014 –.008.118 (Mounting height) 0.25 ± 0.20 (.010 ±. 008) (Stand off) 0~8° *14.00±0.20 Dimensions in mm (inches). Note: The valuesin parentheses are referencevalues. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

110 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 80-pin plastic LQFP (FPT-80P-M37) (FPT-80P-M37) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 12 0 60 41 INDEX (.009± .002) M0.08(.003) 0.145± 0.055 (.006± .002) 0.08(.003) "A" (Stand off) Details of "A" part (.004± .002) 0.10± 0.05 (.024± .006) 0.60± 0.15 (.020± .008) 0.25(.010) 0.50± 0.20 (Mounting height).059–.004 +.008 –0.10 +0.20 1.50 0~8° C Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 111 CONFIDENTIAL 80-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm Max. Code (Reference) P-LQFP80-14 × 14-0.65 80-pin plastic LQFP (FPT-80P-M40) (FPT-80P-M40) 0.32±0.06 (.013±.002) M0.13(.005) 0.145±0.055 (.006±.002) 0.10(.004) 0.60±0.15 (.024±.006) 1.50±0.10 (.059±.004) 0˚~7˚ 0.25(.010) 0.10±0.05 (.004±.002) INDEX Details of "A" part 0.65(.026) 0.50±0.20 (.020±.008) 1 20 60 41 C 2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1 Dimensions in mm (inches). Note: The values in parentheses are referencevalues. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include

112 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g 64-pin plastic LQFP (FPT-64P-M38) (FPT-64P-M38) "A" 0.08(.003) 0.145 ± 0.055 (.006 ± .002) INDEX 3348 161

2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2

(Stand off) Details of "A" part 0.10 ± 0.10 (.004±.004) 0.60 ± 0.15 0.25(.010) C 0.50±0.20 (.020±.008) (Mounting height) .059–.004 +.008 –0.10 +0.20 1.50 0~8° Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. (.009±.002) (.024±.006)

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 113 CONFIDENTIAL 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 64-pin plastic LQFP (FPT -64P-M39) (FPT-64P-M39) "A" 0.10(.004) 0.145±0.055 (.006±.002) INDEX 3348 161 2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2 Details of "A" part 0.10±0.10 0.60±0.15 (.024±.006) 0.25(.010)BSC C .059–.004 +.008 –0.10 +0.20 1.50 0~8˚ 0.50±0.20 Dimensions in mm (inches). Note: The values in parentheses are referencevalues. Note 1) Pins width and pins thickness include plating thickness. (.013±.002) (.020±.008) (.004±.004)

114 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight - 64-pin plastic QFN (LCC-64P-M24) (LCC-64P-M24) C 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1 (.354±.004) 9.00±0.10 (.236±.004) 6.00±0.10 (.236±.004) 6.00±0.10 (.354±.004) 9.00±0.10 0.40±0.05 (.016±.002) 0.50 (.020) (TYP) 0.25±0.05 (.010±.002) 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) INDEX AREA Dimensions in mm (inches). Note: The values in parentheses are reference values.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 115 CONFIDENTIAL 112-ball plastic PFBGA Ball pitch 0.80 mm Package width × package length 10.00 × 10.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size Ф 0.45 mm Mounting height 1.45 mm Max. Weight 0.22 g 112-ball plastic PFBGA (BGA-112P-M04) (BGA-112P-M04) C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3 (.049±.008) 1.25±0.20 (Seated height) F INDEX (INDEX AREA) 10.00±0.10 (.394±.004) (112-Ф0.18±.004) 112-Ф0.45±010 0.35±0.10 (.014±.004) (Stand off) 0.10(.004) S B A GHJKLE D C B A 0.80(.031) REF REF 0.80(.031) Ф0.08(.003) B ASM 0.20(.008) S B S AS0.20(.008) Dimensions in mm (inches). Note: The values in parentheses are reference values.

116 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

96-pin plastic FBGA Lead pitch 0.5 mm Package width × package length 6.00 mm × 6.00 mm Lead shape Ball Sealing method Plastic mold 1.30 mm MAXMounting height Weight 0.08 g 96-pin plastic FBGA (BGA-96P-M07) (BGA-96P-M07) HA BCDEFGJKL C 2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1 TYP 0.20(.008) BS 0.20(.008) AS 6.00±0.10 (.236±.004) (INDEX AREA) S 1.15±0.15 INDEX M S Aø0.05(.002) 0.50(.020) TYP A B 5.00(.197) REF 5.00(.197) REF (Seated height) (.010±.004) 0.25±0.10 (Stand off) (.020) (96-ø.012±.004) 96-ø0.30±0.10 B Dimensions in mm (inches). Note: The values in parentheses are reference values.

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 117 CONFIDENTIAL  Major Changes Page Section Change Results Revision 2.0 FEATURE

On-chip Memories Revised the descriptions of [Flash memory].
USB Interface Revised the descriptions of [USB function]. 6 • Unique ID Added the descriptions of "Unique ID". 7 PRODUCT LINEUP
Function 48 HANDLING DEVICES Added the descriptions. 53 MEMORY MAP
Memory Map (2) 58 PIN STA TUS IN EACH CPU STATE
List of Pin Status Revised the Pin status type of "I". ELECTRICAL CHARACTERISTICS 3.DC Characteristics (1) Current rating  Revised the descriptions of Power supply current.  Added the "Flash memory write/erase current".  Added the footnote. 4.AC Characteristics (3) Built-in CR Oscillation Characteristics
Built-in high-speed CR Revised the table and the footnote. 72, 73 (7) External Bus Timing
Separate Bus Access Asynchronous SRAM Mode Revised the table and the figure. 74 • Separate Bus Access Synchronous SRAM Mode 79, 81, 83, 85 (9) CSIO Timing  Revised the title to "CSIO Timing".  Revised the note. 88 (11) I2C Timing Revised the footnote. 5. 12-bit A/D Converter
Electrical characteristics for the A/D converter (Preliminary value)
Revised the parameter.
Revised the symbol.
Corrected the value. 93 • Definition of 12-bit A/D Converter Terms • Revised the parameter.
Revised the symbol. 98 7. Low-V oltage Detection Characteristics (1) Low-V oltage Detection Reset
Corrected "Conditions" and "Value" in the table.
Added the Item.
Added the footnote. 99 (2) Interrupt of Low-V oltage Detection Added the Item. Revision 2.1 - - Company name and layout design change Revision 3.0 - - Corrected the Series name. MB9A340NA Series → MB9A340NB Series - - Corrected the Product name as follows. MB9AF344LB, MB9AF342LB, MB9AF341LB MB9AF344MB, MB9AF342MB, MB9AF341MB MB9AF344NB, MB9AF342NB, MB9AF341NB 2  FEATURES
External Bus Interface Added the Item.
Maximum area size : Up to 256 Mbytes 3 •Multi-function Serial Interface Corrected the description of "I2C" 7 PRODUCT LINEUP
Function Added the footnote 51 BLOCK DIAGRAM Corrected the figure 52 MEMORY MAP
Memory Map (1) Corrected the address "External Device Area" 63  ELECTRICAL CHARACTERISTICS 2.Recommended Operating Conditions Add the footnote 64,65 3.DC Characteristics (1)Current rating
Corrected the Condition
Delete the minmun value
Corrected the remarks
Add the footnote (9)CSIO Timing
Synchronous serial (SPI=1, SCINV=1) Corrected the figure of "MS bit=1" (9) CSIO Timing
External clock(EXT=1):asyntironous only Corrected the figure (12)I2C Timing Corrected the description as follows.
Typical mode → Standard-mode
High-speed mode→ Fast-mode

118 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

Page Section Change Results 5.12-bit A/D Converter

Electrical Characteristics for the A/D Converter
Corrected the terminal name AN00 ~ AN23 → ANxx
Corrected the minmum value of "Sampling time"
Corrected the max and min value of "State transition time to oprerationpermission"
Corrected the footnote 101 ORDERING INFORMA TON Corrected the "Part number" Revision 4.0 2 Features USB Interface Added the description of PLL for USB 53 Memory Map
Memory map(2) Added the summary of Flash memory sector and the note 64 - 66 Electrical Characteristics 3. DC Characteristics (1) Current rating
Changed the table format
Added Main Timer mode current
Moved A/D Converter Current Electrical Characteristics 3. DC Characteristics (2) Pin Characteristics Added input leak current of CEC pin at power off. Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main and USB PLL (4-2) Operating Conditions of Main PLL Added the figure of Main PLL connection and USB PLL connection Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing
Added Time until releasing Power-on reset
Changed the figure of timing 80 - 87 Electrical Characteristics 4. AC Characteristics (9) CSIO/UART Timing
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode 92 Electrical Characteristics 5. 12bit A/D Converter
Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
Added Conversion time at A Vcc < 2.7V 102 - 105 Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode 106, 107 Ordering Information Changed notation of part number

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 119 CONFIDENTIAL

120 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

June 10, 2015, MB9A340NB_DS706-00039-4v0-E 121 CONFIDENTIAL

122 MB9A340NB_DS706-00039-4v0-E, June 10, 2015

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

Product Information

MB9A340NB specifications and overview.

Summary

The MB9A340NB Series are highly integrated

Description

The MB9A340NB Series are highly integrated

Source title MB9A340NB Datasheet(PDF) - SPANSION

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