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32-bit ARM® Cortex®-M3 based Microcontroller MB9AF154MB/NB/RB, MB9AF155MB/NB/RB, MB9AF156MB/NB/RB Data Sheet (Full Production) Publication Number MB9A150RB_DS706-00047 Revision 3.0 Issue Date April 28, 2015 CONFIDENTIAL Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
MB9A150RB_DS706-00047-3v0-E, April 28, 2015 CONFIDENTIAL Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.
32-bit ARM® Cortex®-M3 based Microcontroller MB9AF154MB/NB/RB, MB9AF155MB/NB/RB, MB9AF156MB/NB/RB Data Sheet (Full Production) Publication Number MB9A150RB_DS706-00047 Revision 3.0 Issue Date April 28, 2015 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. Description The MB9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE8 product categories in FM3 Family Peripheral Manual. Note: ARM and Cortex are theregistered trademarks of ARM Limited in the EU and other countries.
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Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Main area: Up to 512 Kbytes (Upto 496 Kbytes upper bank + 16 Kbytes lower bank) Work area: 32 Kbytes (lower bank) Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 32 Kbytes SRAM1: Up to 32 Kbytes External Bus Interface Supports SRAM, NOR NAND Flash memory device Up to 8 chip selects 8-/16-bit Data width Up to 25-bit Address bit Maximum area size : Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function Multi-function Serial Interface (Max 16 channels) 16 channels with 16 steps×9-bit FIFO Operation mode is selectable from the followings for each channel. UART CSIO I2C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4) Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 3 CONFIDENTIAL DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536 A/D Converter (Max 24 channels) [12-bit A/D Converter] Successive Approximation type Built-in 2 units Conversion time: 2.0 μs @ 2.7 V to 3.6 V Priority conversion available (priority at 2 levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) Base Timer (Max 16channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 103 high-speed general-purpose I/O Ports@120 pin Package Some ports are 5 V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot
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Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer × 3ch. Input capture × 4ch. Output compare × 6ch. A/D activation compare × 2ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Quadrature Position/Revolution Counter (QPRC) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter. The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers HDMI-CEC/Remote Control Reception (Up to 2channels) HDMI-CEC transmission Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) HDMI-CEC reception Automatic ACK reply function available Line error detection function available Remote control reception 4 bytes reception buffer Repeat code detection function available Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 5 CONFIDENTIAL External Interrupt Controller Unit Up to 24 external interrupt input pins Include one non-maskable interrupt (NMI) input pin Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The Hardware watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC and Deep Standby Stop modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: 4 MHz to 48 MHz Sub Clock: 32.768 kHz Built-in High-speed CR Clock: 4 MHz Built-in Low-speed CR Clock: 100 kHz Main PLL Clock [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-V oltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation
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Low-Power Consumption Mode Six low-power consumption modes supported. Sleep Timer RTC Stop Deep Standby RTC (selectable between keeping the value of RAM and not) Deep Standby Stop (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM).* *: MB9AF154MB, F155MB and F156MB support only SWJ-DP. Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 1.65 V to 3.6 V
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 7 CONFIDENTIAL Product Lineup Memory size Product name MB9AF154MB/NB/RB MB9AF155MB/NB/RB MB9AF156MB/NB/RB On-chip Flash memory Main area 256 Kbytes 384 Kbytes 512 Kbytes Work area 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM SRAM0 16 Kbytes 24 Kbytes 32 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes Total 32 Kbytes 48 Kbytes 64 Kbytes
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Function Product name MB9AF154MB MB9AF155MB MB9AF156MB MB9AF154NB MB9AF155NB MB9AF156NB MB9AF154RB MB9AF155RB MB9AF156RB Pin count 80/96 100/112 120 CPU Cortex-M3 Freq. 40 MHz Power supply voltage range 1.65V to 3.6V DMAC 8ch. External Bus Interface Addr: 21-bit (Max) R/W Data: 8-bit (Max) CS: 4 (Max) Support: SRAM, NOR Flash memory Addr: 25-bit (Max) R/W Data: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash memory Addr: 25-bit (Max) R/W Data: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash memory, NAND Flash memory Multi-function Serial Interface (UART/CSIO/I2C) 10ch. (Max) Enabled channels : ch.0 to ch.7, ch.10, ch.11 14ch. (Max) Enabled channels : ch.0 to ch.13 16ch. (Max) Enabled channels : ch.0 to ch.15 Base Timer (PWC/Reload timer/PWM/PPG) 16ch. (Max) MF- Timer A/D activation compare 2ch. 1 unit (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. QPRC 2ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Reception 2ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 23 pins (Max) + NMI × 1 24 pins (Max) + NMI × 1 I/O ports 66 pins (Max) 83 pins (Max) 103 pins (Max) 12-bit A/D converter 17ch. (2 units) 24ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-V oltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP SWJ-DP/ETM Unique ID Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for accuracy of built-in CR.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 9 CONFIDENTIAL Packages Product name Package MB9AF154MB MB9AF155MB MB9AF156MB MB9AF154NB MB9AF155NB MB9AF156NB MB9AF154RB MB9AF155RB MB9AF156RB LQFP: FPT-80P-M37 (0.5 mm pitch) - - BGA: BGA-96P-M07 (0.5 mm pitch) - - LQFP: FPT-100P-M23 (0.5 mm pitch) - - BGA: BGA-112P-M04 (0.8 mm pitch) - - LQFP: FPT-120P-M37 (0.5 mm pitch) - - : Supported Note: See Package Dimensions for detailed information on each package.
10 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Assignment FPT-120P-M37 (TOP VIEW) VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 P61/SOT5_0/TIOB2_2 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 P63/SIN5_1/TIOB15_1/INT03_0/MWEX_0 P64/SOT5_1/TIOA7_0/INT10_2 P65/SCK5_1/TIOB7_0/TIOB12_2/INT23_0 P66/SIN3_0/TIOA12_2/INT11_2 P67/SOT3_0/TIOA7_2/INT22_0 P68/SCK3_0/TIOB7_2/INT12_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 VCC 1 90 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 89 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 88 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 87 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 86 P23/AN16/SCK0_0/RTO00_1/TIOA7_1 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 85 P24/SIN2_1/RTO01_1/TIOB14_1/INT01_2 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 84 P25/SOT2_1/RTO02_1/TIOA14_1/TIOB11_2 P56/SIN1_0/TIOA8_0/INT08_2/CEC1_1/MADATA06_0 8 83 P26/SCK2_1/RTO03_1/TIOA11_2 P57/SOT1_0/TIOA9_0/MADATA07_0 9 82 P27/SIN15_0/RTO04_1/TIOA6_2/INT02_2 P58/SCK1_0/TIOA10_0/MADATA08_0 10 81 P28/ADTG_4/SOT15_0/RTO05_1/TIOB6_2 P59/SIN7_0/TIOA11_0/INT09_2/MADATA09_0 11 80 P1F/AN15/ADTG_5/SCK15_0/FRCK0_1/TIOB9_2/MAD23_0 P5A/SOT7_0/TIOA12_0/INT16_2/MADATA10_0 12 79 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0 P5B/SCK7_0/TIOA13_0/INT17_2/MADATA11_0 13 78 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA12_0 14 77 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA13_0 15 76 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA14_0 16 75 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA15_0 17 74 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MNALE_0 18 73 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MNCLE_0 19 72 AVSS P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MNWEX_0 20 71 AVRH P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MNREX_0 21 70 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT11_1 22 69 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 23 68 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 24 67 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RTO01_0/TIOA1_1 25 66 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 26 65 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT11_0/RTO03_0/TIOA3_1 27 64 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 28 63 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 29 62 P10/AN00 VSS 30 61 VCC VCC P40/SIN12_0/TIOA0_0/INT12_1 P41/SOT12_0/TIOA1_0/INT13_1 P42/SCK12_0/TIOA2_0/INT08_0 P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1/MAD02_0 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 P4E/SIN14_0/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 P70/SOT14_0/TIOA4_2 P71/SCK14_0/TIOB4_2/INT13_2 P72/SIN2_0/TIOA6_0/INT14_2 P73/SOT2_0/TIOB6_0/INT15_2 P74/SCK2_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 120 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 11 CONFIDENTIAL FPT-100P-M23 (TOP VIEW) VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 P61/SOT5_0/TIOB2_2 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 P63/TIOB15_1/INT03_0/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 VCC 100 VCC 1 75 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 74 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 73 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 72 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 71 P23/AN16/SCK0_0/TIOA7_1 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 70 P1F/AN15/ADTG_5/FRCK0_1/TIOB9_2/MAD23_0 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 69 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0 P56/INT08_2/CEC1_1/MADATA06_0 8 68 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0 9 67 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10 66 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11 65 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12 64 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MADATA11_0 13 63 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MADATA12_0 14 62 AVSS P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MADATA13_0 15 61 AVRH P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MADATA14_0 16 60 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT11_1/MADATA15_0 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 18 58 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 19 57 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RTO01_0/TIOA1_1 20 56 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 21 55 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT11_0/RTO03_0/TIOA3_1 22 54 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 23 53 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 24 52 P10/AN00 VSS 25 51 VCC VCC P40/SIN12_0/TIOA0_0/INT12_1 P41/SOT12_0/TIOA1_0/INT13_1 P42/SCK12_0/TIOA2_0/INT08_0 P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1/MAD02_0 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.
12 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
FPT-80P-M37 (TOP VIEW) VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 P61/SOT5_0/TIOB2_2 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 P63/TIOB15_1/INT03_0/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P07/AN22/ADTG_0/INT23_1/MCLKOUT_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/TIOA14_2/MCSX7_0 VCC 1 60 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 59 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 58 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 57 P23/AN16/SCK0_0/TIOA7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 56 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 55 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 54 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P56/INT08_2/CEC1_1/MADATA06_0 8 53 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0 9 52 AVSS P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10 51 AVRH P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11 50 AVCC P33/ADTG_6/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12 49 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/INT06_0 13 48 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 14 47 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RTO01_0/TIOA1_1 15 46 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 16 45 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT11_0/RTO03_0/TIOA3_1 17 44 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 18 43 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 19 42 P10/AN00 VSS 20 41 VCC P44/TIOA4_0/INT10_0/MAD00_0 P45/TIOA5_0/INT11_0/MAD01_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1/MAD02_0 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 13 CONFIDENTIAL BGA-112P-M04 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC P0E B VCC VSS P52 P61 P0F P0C P08 TDO/ SWO P0B P07 TMS/ SWDIO TRSTX VCC VSS TCK/ SWCLK VSS TDI VSS P20 P21 D P53 P54 P55 VSS AN15P56 P63 P0A VSS P06 P23 C P50 P51 VSS P60 P62 P0D P09 P05 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH E P30 P31 P32 P33 Index P22 AN14 AN12 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C G P37 P38 P3A P3D AN08 AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E P43 P49 P4D AN02 VSS AN01 P4A MD0 X0 X1 VSS MD1 VSS VCC L VSS C X0A VSS P41 P45 PFBGA - 112 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.
14 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
BGA-96P-M07 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ SWO P0F VSS P07 TMS/ SWDIO TRSTX VSS TCK/ SWCLK VSS TDI VSS P20 P21 D P53 P54 P55 Index VSSP22 P23 C P50 P51 VSS P60 P62 P0E P0B P0A E P56 P30 P31 AN11 AN10 AN09 AN01 AN00 AN04 AN08 AN07 AVRH G P32 P33 P39 AN06 F VSS VSS VSS AN05 AVSS H P3A P3B P3C AN03 AVCC P49 P4C P4E MD1 VSS VCCK VCC VSS X1A INITX P45 J P3D P3E VSS P3F P48 P4A P4D AN02 VSS VSS P4B MD0 X0 X1 VSSL VSS C X0A VSS P44 PFBGA - 96 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 15 CONFIDENTIAL List of Pin Function List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 1 1 B1 1 B1 VCC - 2 2 C1 2 C1 P50 E K SIN3_1 AIN0_2 TIOB8_0 INT00_0 MADA TA00_0 3 3 C2 3 C2 P51 E K SOT3_1 (SDA3_1) BIN0_2 TIOB9_0 INT01_0 MADA TA01_0 4 4 B3 4 B3 P52 E K SCK3_1 (SCL3_1) ZIN0_2 TIOB10_0 INT02_0 MADA TA02_0 5 5 D1 5 D1 P53 E K SIN6_0 TIOB11_0 TIOA1_2 INT07_2 MADA TA03_0 6 6 D2 6 D2 P54 E K SOT6_0 (SDA6_0) TIOB12_0 TIOB1_2 INT18_1 MADA TA04_0 7 7 D3 7 D3 P55 E K ADTG_1 SCK6_0 (SCL6_0) TIOB13_0 INT19_1 MADA TA05_0
16 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
8 D5 8 E1
H* R INT08_2 CEC1_1 MADA TA06_0 - - - - SIN1_0 TIOA8_0 9 - - - - P57 H* J SOT1_0 (SDA1_0) TIOA9_0 MADA TA07_0 10 - - - - P58 H* J SCK1_0 (SCL1_0) TIOA10_0 MADA TA08_0 11 - - - - P59 E K SIN7_0 TIOA11_0 INT09_2 MADA TA09_0 12 - - - - P5A E K SOT7_0 (SDA7_0) TIOA12_0 INT16_2 MADA TA10_0 13 - - - - P5B E K SCK7_0 (SCL7_0) TIOA13_0 INT17_2 MADA TA11_0 14 - - - - P30 E S AIN0_0 TIOB0_1 TIOA13_2 INT03_2 WKUP4 MADA TA12_0 - 9 E1 9 E2 P30 E S AIN0_0 TIOB0_1 TIOA13_2 INT03_2 WKUP4 MADA TA07_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 17 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 15 - - - - P31 E K SCK6_1 (SCL6_1) BIN0_0 TIOB1_1 TIOB13_2 INT04_2 MADA TA13_0 - 10 E2 10 E3 P31 E K SCK6_1 (SCL6_1) BIN0_0 TIOB1_1 TIOB13_2 INT04_2 MADA TA08_0 16 - - - - P32 E K SOT6_1 (SDA6_1) ZIN0_0 TIOB2_1 INT05_2 MADA TA14_0 - 11 E3 11 G1 P32 E K SOT6_1 (SDA6_1) ZIN0_0 TIOB2_1 INT05_2 MADA TA09_0 17 - - - - P33 E K ADTG_6 SIN9_0 SIN6_1 TIOB3_1 INT04_0 MADA TA15_0 - 12 E4 12 G2 P33 E K ADTG_6 SIN6_1 TIOB3_1 INT04_0 MADA TA10_0 - - SIN9_0
18 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 18 - - - - P34 E J SOT9_0 (SDA9_0) FRCK0_0 TIOB4_1 TIOA15_2 MNALE_0 - 13 F1 - - P34 E J SOT9_0 (SDA9_0) FRCK0_0 TIOB4_1 TIOA15_2 MADA TA11_0 19 - - - - P35 E K SCK9_0 (SCL9_0) IC03_0 TIOB5_1 TIOB15_2 INT08_1 MNCLE_0 - 14 F2 - - P35 E K SCK9_0 (SCL9_0) IC03_0 TIOB5_1 TIOB15_2 INT08_1 MADA TA12_0 20 - - - - P36 E K SIN5_2 IC02_0 TIOB14_0 INT09_1 MNWEX_0 - 15 F3 - - P36 E K SIN5_2 IC02_0 TIOB14_0 INT09_1 MADA TA13_0 - - - - F1 VSS - - - - - F2 VSS - - - - - F3 VSS -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 19 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 21 - - - - P37 E K SOT5_2 (SDA5_2) IC01_0 TIOA14_0 INT10_1 MNREX_0 - 16 G1 - - P37 E K SOT5_2 (SDA5_2) IC01_0 TIOA14_0 INT10_1 MADA TA14_0 22 17 G2 - - P38 E K SCK5_2 (SCL5_2) IC00_0 TIOA08_2 INT11_1 - MADA TA15_0 23 18 F4 13 G3 P39 E K ADTG_2 SIN10_0 DTTI0X_0 INT06_0 - - TIOB8_2 24 19 G3 14 H1 P3A E K SOT10_0 (SDA10_0) RTO00_0 TIOA0_1 INT07_0 RTCCO_2 SUBOUT_2 25 20 H1 15 H2 P3B E J SCK10_0 (SCL10_0) RTO01_0 TIOA1_1 26 21 H2 16 H3 P3C E K SIN11_0 RTO02_0 TIOA2_1 INT18_2
20 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 27 22 G4 17 J1 P3D E J SOT11_0 (SDA11_0) RTO03_0 TIOA3_1 - - B2 - B2 VSS - 28 23 H3 18 J2 P3E E K SCK11_0 (SCL11_0) RTO04_0 TIOA4_1 INT19_2 29 24 J2 19 J4 P3F E J RTO05_0 TIOA5_1 30 25 L1 20 L1 VSS - 31 26 J1 - - VCC - 32 27 J4 - - P40 E K SIN12_0 TIOA0_0 INT12_1 33 28 L5 - - P41 E K SOT12_0 (SDA12_0) TIOA1_0 INT13_1 34 29 K5 - - P42 E K SCK12_0 (SCL12_0) TIOA2_0 INT08_0 35 30 J5 - - P43 E K ADTG_7 SIN13_0 TIOA3_0 INT09_0 36 31 H5
21 L5 P44
- - SOT13_0 (SDA13_0) 21 L5 TIOA4_0 INT10_0 MAD00_0 37 32 L6
22 K5 P45
- - SCK13_0 22 K5 TIOA5_0 INT11_0 MAD01_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 21 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 - - K2 - K2 VSS - - - J3 - J3 VSS - - - H4 - - VSS - - - - - L6 VSS - 38 33 L2 23 L2 C - 39 34 L4 24 L4 VSS - 40 35 K1 25 K1 VCC - 41 36 L3 26 L3 P46 D F X0A 42 37 K3 27 K3 P47 D G X1A 43 38 K4 28 K4 INITX B C 44 39 K6 29 J5 P48 E K SIN3_2 INT14_1 MAD02_0 45 40 J6 30 K6 P49 E K SOT3_2 (SDA3_2) AIN0_1 TIOB0_0 INT20_1 MAD03_0 46 41 L7 31 J6 P4A E K SCK3_2 (SCL3_2) BIN0_1 TIOB1_0 INT21_1 MAD04_0 47 42 K7 32 L7 P4B E K IGTRG_0 ZIN0_1 TIOB2_0 INT22_1 MAD05_0 48 43 H6 33 K7 P4C H* R SCK7_1 (SCL7_1) AIN1_2 TIOB3_0 INT12_0 CEC0_0 MAD06_0
22 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 49 44 J7 34 J7 P4D H* K SOT7_1 (SDA7_1) BIN1_2 TIOB4_0 INT13_0 MAD07_0 50 45 K8 35 K8 P4E H* K SIN7_1 ZIN1_2 TIOB5_0 INT06_2 MAD08_0 - - - - SIN14_0 51 - - - - P70 E J SOT14_0 (SDA14_0) TIOA4_2 52 - - - - P71 E K SCK14_0 (SCL14_0) TIOB4_2 INT13_2 53 - - - - P72 E K SIN2_0 TIOA6_0 INT14_2 54 - - - - P73 E K SOT2_0 (SDA2_0) TIOB6_0 INT15_2 55 - - - - P74 E J SCK2_0 (SCL2_0) 56 46 K9 36 K9 MD1 C E PE0 57 47 L8 37 L8 MD0 G D 58 48 L9 38 L9 X0 A A PE2 59 49 L10 39 L10 X1 A B PE3 60 50 L11 40 L11 VSS - 61 51 K11 41 K11 VCC - 62 52 J11 42 J11 P10 F L AN00
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 23 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 63 53 J10 43 J10 P11 F P AN01 SIN1_1 FRCK0_2 TIOB8_1 INT02_1 WKUP1 MAD09_0 64 54 J8 44 J8 P12 F L AN02 SOT1_1 (SDA1_1) IC00_2 TIOB9_1 MAD10_0 - - K10 - K10 VSS - - - J9 - J9 VSS - 65 55 H10 45 H10 P13 F L AN03 SCK1_1 (SCL1_1) IC01_2 TIOB10_1 RTCCO_1 SUBOUT_1 MAD11_0 66 56 H9 46 H9 P14 F M AN04 SIN0_1 IC02_2 TIOB11_1 INT03_1 MAD12_0 67 57 H7 47 G10 P15 F M AN05 SOT0_1 (SDA0_1) IC03_2 TIOB12_1 INT14_0 MAD13_0
24 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 68 58 G10 48 G9 P16 F M AN06 SCK0_1 (SCL0_1) TIOB13_1 INT15_0 MAD14_0 69 59 G9 49 F10 P17 F M AN07 SIN2_2 INT04_1 MAD15_0 70 60 H11 50 H11 AVCC - 71 61 F11 51 F11 A VRH - 72 62 G11 52 G11 A VSS - 73 63 G8 53 F9 P18 F L AN08 SOT2_2 (SDA2_2) TIOA8_1 MAD16_0 74 64 F10 54 E11 P19 F L AN09 SCK2_2 (SCL2_2) TIOA9_1 MAD17_0 - - H8 - - VSS - 75 65 F9 55 E10 P1A F M AN10 SIN4_1 IC00_1 TIOA10_1 INT05_1 MAD18_0 76 66 E11 56 E9 P1B F M AN11 SOT4_1 (SDA4_1) IC01_1 TIOA11_1 INT20_2 MAD19_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 25 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 77 67 E10 - - P1C F M AN12 SCK4_1 (SCL4_1) IC02_1 TIOA12_1 INT21_2 MAD20_0 78 68 F8 - - P1D F M AN13 CTS4_1 IC03_1 TIOA13_1 INT22_2 MAD21_0 79 69 E9 - - P1E F M AN14 RTS4_1 DTTI0X_1 TIOA9_2 INT23_2 MAD22_0
70 D11 - -
ADTG_5 FRCK0_1 TIOB9_2 MAD23_0 - - - - SCK15_0 (SCL15_0) - - B10 - B10 VSS - - - C9 - C9 VSS - - - - - D11 VSS - 81 - - - - P28 E J ADTG_4 SOT15_0 (SDA15_0) RTO05_1 TIOB6_2 82 - - - - P27 E K SIN15_0 RTO04_1 TIOA6_2 INT02_2
26 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 83 - - - - P26 E J SCK2_1 (SCL2_1) RTO03_1 TIOA11_2 84 - - - - P25 E J SOT2_1 (SDA2_1) RTO02_1 TIOA14_1 TIOB11_2 85 - - - - P24 E K SIN2_1 RTO01_1 TIOB14_1 INT01_2 86 71 D10 57 D10 P23 F L AN16 SCK0_0 (SCL0_0) TIOA7_1 - - - - RTO00_1 87 72 E8 58 D9 P22 F L AN17 SOT0_0 (SDA0_0) ZIN1_1 TIOB7_1 88 73 C11 59 C11 P21 F P AN18 SIN0_0 BIN1_1 TIOB10_2 INT06_1 WKUP2 89 74 C10 60 C10 P20 F M AN19 CROUT_0 AIN1_1 TIOA10_2 INT05_0 MAD24_0 90 75 A11 - A11 VSS - 91 76 A10 - - VCC -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 27 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 92 77 A9
61 A10
TIOA14_2 MCSX7_0 - - SCK8_0 (SCL8_0) 93 78 B9 62 B9 P01 E I TCK SWCLK 94 79 B11 63 B11 P02 E I TDI TIOB14_2 MCSX6_0 - - SOT8_0 95 80 A8 64 A9 P03 E I TMS SWDIO 96 81 B8 65 B8 P04 E I TDO SWO 97 82 C8 - - P05 F O AN20 TRACED0 SIN8_0 SIN4_2 TIOA5_2 INT00_1 MCSX5_0 - - D8 - - VSS - 98 83 D9 - - P06 F O AN21 TRACED1 SOT4_2 (SDA4_2) TIOB5_2 INT01_1 MCSX4_0 99 84 A7 66 A8 P07 F O AN22 ADTG_0 MCLKOUT_0 INT23_1 - - TRACED2 SCK4_2 (SCL4_2) - - - - A7 VSS -
28 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 100 85 B7 - - P08 F O AN23 TRACED3 CTS4_2 TIOA0_2 INT16_0 MCSX3_0 101 86 C7 - - P09 E N TRACECLK RTS4_2 TIOB0_2 INT17_0 MCSX2_0 102 87 D7 67 C8 P0A H* S SIN4_0 INT00_2 WKUP5 MCSX1_0 103 88 A6 68 C7 P0B H* R SOT4_0 (SDA4_0) TIOB6_1 INT18_0 CEC0_1 MCSX0_0 104 89 B6 69 B7 P0C H* K SCK4_0 (SCL4_0) TIOA6_1 INT19_0 MALE_0 - - D4 - - VSS - - - C3 - C3 VSS - 105 90 C6 70 B6 P0D E K RTS4_0 TIOA3_2 INT20_0 MDQM0_0 106 91 A5 71 C6 P0E E K CTS4_0 TIOB3_2 INT21_0 MDQM1_0 - - - - A5 VSS -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 29 CONFIDENTIAL Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 107 92 B5 72 A6 P0F E H NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 108 - - - - P68 E K SCK3_0 (SCL3_0) TIOB7_2 INT12_2 109 - - - - P67 E K SOT3_0 (SDA3_0) TIOA7_2 INT22_0 110 - - - - P66 E K SIN3_0 TIOA12_2 INT11_2 111 - - - - P65 E K SCK5_1 (SCL5_1) TIOB7_0 TIOB12_2 INT23_0 112 - - - - P64 E K SOT5_1 (SDA5_1) TIOA7_0 INT10_2 113 93 D6 73 B5 P63 E K TIOB15_1 INT03_0 MWEX_0 - - - - SIN5_1 114 94 C5 74 C5 P62 E K ADTG_3 SCK5_0 (SCL5_0) TIOA15_1 INT07_1 MOEX_0
30 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin No Pin Name I/O Circuit Type Pin State Type LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 115 95 B4 75 B4 P61 E J SOT5_0 (SDA5_0) TIOB2_2 116 96 C4 76 C4 P60 H* Q SIN5_0 IGTRG_1 TIOA2_2 INT15_1 WKUP3 CEC1_0 MRDY_0 117 97 A4 77 A4 VCC - 118 98 A3 78 A3 P80 E K TIOB15_0 INT16_1 119 99 A2 79 A2 P81 E K TIOA15_0 INT17_1 120 100 A1 80 A1 VSS - *: 5V tolerant I/O
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 31 CONFIDENTIAL List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- ADC ADTG_0 A/D converter external trigger input pin 99 84 A7 66 A8 ADTG_1 7 7 D3 7 D3 ADTG_2 23 18 F4 13 G3 ADTG_3 114 94 C5 74 C5 ADTG_4 81 - - - - ADTG_5 80 70 D11 - - ADTG_6 17 12 E4 12 G2 ADTG_7 35 30 J5 - - ADTG_8 - - - - - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 62 52 J11 42 J11 AN01 63 53 J10 43 J10 AN02 64 54 J8 44 J8 AN03 65 55 H10 45 H10 AN04 66 56 H9 46 H9 AN05 67 57 H7 47 G10 AN06 68 58 G10 48 G9 AN07 69 59 G9 49 F10 AN08 73 63 G8 53 F9 AN09 74 64 F10 54 E11 AN10 75 65 F9 55 E10 AN11 76 66 E11 56 E9 AN12 77 67 E10 - - AN13 78 68 F8 - - AN14 79 69 E9 - - AN15 80 70 D11 - - AN16 86 71 D10 57 D10 AN17 87 72 E8 58 D9 AN18 88 73 C11 59 C11 AN19 89 74 C10 60 C10 AN20 97 82 C8 - - AN21 98 83 D9 - - AN22 99 84 A7 66 A8 AN23 100 85 B7 - -
32 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Base Timer TIOA0_0 Base timer ch.0 TIOA pin 32 27 J4 - - TIOA0_1 24 19 G3 14 H1 TIOA0_2 100 85 B7 - - TIOB0_0 Base timer ch.0 TIOB pin 45 40 J6 30 K6 TIOB0_1 14 9 E1 9 E2 TIOB0_2 101 86 C7 - - Base Timer TIOA1_0 Base timer ch.1 TIOA pin 33 28 L5 - - TIOA1_1 25 20 H1 15 H2 TIOA1_2 5 5 D1 5 D1 TIOB1_0 Base timer ch.1 TIOB pin 46 41 L7 31 J6 TIOB1_1 15 10 E2 10 E3 TIOB1_2 6 6 D2 6 D2 Base Timer TIOA2_0 Base timer ch.2 TIOA pin 34 29 K5 - - TIOA2_1 26 21 H2 16 H3 TIOA2_2 116 96 C4 76 C4 TIOB2_0 Base timer ch.2 TIOB pin 47 42 K7 32 L7 TIOB2_1 16 11 E3 11 G1 TIOB2_2 115 95 B4 75 B4 Base Timer TIOA3_0 Base timer ch.3 TIOA pin 35 30 J5 - - TIOA3_1 27 22 G4 17 J1 TIOA3_2 105 90 C6 70 B6 TIOB3_0 Base timer ch.3 TIOB pin 48 43 H6 33 K7 TIOB3_1 17 12 E4 12 G2 TIOB3_2 106 91 A5 71 C6 Base Timer TIOA4_0 Base timer ch.4 TIOA pin 36 31 H5 21 L5 TIOA4_1 28 23 H3 18 J2 TIOA4_2 51 - - - - TIOB4_0 Base timer ch.4 TIOB pin 49 44 J7 34 J7 TIOB4_1 18 13 F1 - - TIOB4_2 52 - - - - Base Timer TIOA5_0 Base timer ch.5 TIOA pin 37 32 L6 22 K5 TIOA5_1 29 24 J2 19 J4 TIOA5_2 97 82 C8 - - TIOB5_0 Base timer ch.5 TIOB pin 50 45 K8 35 K8 TIOB5_1 19 14 F2 - - TIOB5_2 98 83 D9 - - Base Timer TIOA6_0 Base timer ch.6 TIOA pin 53 - - - - TIOA6_1 104 89 B6 69 B7 TIOA6_2 82 - - - - TIOB6_0 Base timer ch.6 TIOB pin 54 - - - - TIOB6_1 103 88 A6 68 C7 TIOB6_2 81 - - - - Base Timer TIOA7_0 Base timer ch.7 TIOA pin 112 - - - - TIOA7_1 86 71 D10 57 D10 TIOB7_0 Base timer ch.7 TIOB pin 111 - - - - TIOB7_1 87 72 E8 58 D9
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 33 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Base Timer TIOA8_0 Base timer ch.8 TIOA pin 8 8 D5 8 E1 TIOA8_1 73 63 G8 53 F9 TIOA8_2 22 17 G2 - - TIOB8_0 Base timer ch.8 TIOB pin 2 2 C1 2 C1 TIOB8_1 63 53 J10 43 J10 TIOB8_2 23 18 F4 - - Base Timer TIOA9_0 Base timer ch.9 TIOA pin 9 - - - - TIOA9_1 74 64 F10 54 E11 TIOA9_2 79 69 E9 - - TIOB9_0 Base timer ch.9 TIOB pin 3 3 C2 3 C2 TIOB9_1 64 54 J8 44 J8 TIOB9_2 80 70 D11 - - Base Timer TIOA10_0 Base timer ch.10 TIOA pin 10 - - - - TIOA10_1 75 65 F9 55 E10 TIOA10_2 89 74 C10 60 C10 TIOB10_0 Base timer ch.10 TIOB pin 4 4 B3 4 B3 TIOB10_1 65 55 H10 45 H10 TIOB10_2 88 73 C11 59 C11 Base Timer TIOA11_0 Base timer ch.11 TIOA pin 11 - - - - TIOA11_1 76 66 E11 56 E9 TIOB11_0 Base timer ch.11 TIOB pin 5 5 D1 5 D1 TIOB11_1 66 56 H9 46 H9 Base Timer TIOA12_0 Base timer ch.12 TIOA pin 12 - - - - TIOA12_1 77 67 E10 - - TIOA12_2 110 - - - - TIOB12_0 Base timer ch.12 TIOB pin 6 6 D2 6 D2 TIOB12_1 67 57 H7 47 G10 TIOB12_2 111 - - - - Base Timer TIOA13_0 Base timer ch.13 TIOA pin 13 - - - - TIOA13_1 78 68 F8 - - TIOA13_2 14 9 E1 9 E2 TIOB13_0 Base timer ch.13 TIOB pin 7 7 D3 7 D3 TIOB13_1 68 58 G10 48 G9 TIOB13_2 15 10 E2 10 E3 Base Timer TIOA14_0 Base timer ch.14 TIOA pin 21 16 G1 - - TIOA14_2 92 77 A9 61 A10 TIOB14_0 Base timer ch.14 TIOB pin 20 15 F3 - - TIOB14_2 94 79 B11 63 B11 Base Timer TIOA15_0 Base timer ch.15 TIOA pin 119 99 A2 79 A2 TIOA15_1 114 94 C5 74 C5 TIOA15_2 18 13 F1 - - TIOB15_0 Base timer ch.15 TIOB pin 118 98 A3 78 A3 TIOB15_1 113 93 D6 73 B5 TIOB15_2 19 14 F2 - -
34 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Debugger SWCLK Serial wire debug interface clock input pin 93 78 B9 62 B9 SWDIO Serial wire debug interface data input / output pin 95 80 A8 64 A9 SWO Serial wire viewer output pin 96 81 B8 65 B8 TCK J-TAG test clock input pin 93 78 B9 62 B9 TDI J-TAG test data input pin 94 79 B11 63 B11 TDO J-TAG debug data output pin 96 81 B8 65 B8 TMS J-TAG test mode state input/output pin 95 80 A8 64 A9 TRACECLK Trace CLK output pin of ETM 101 86 C7 - - TRACED0 Trace data output pin of ETM 97 82 C8 - - TRACED1 98 83 D9 - - TRACED2 99 84 A7 - - TRACED3 100 85 B7 - - TRSTX J-TAG test reset input pin 92 77 A9 61 A10 External Bus MAD00_0 External bus interface address bus 36 31 H5 21 L5 MAD01_0 37 32 L6 22 K5 MAD02_0 44 39 K6 29 J5 MAD03_0 45 40 J6 30 K6 MAD04_0 46 41 L7 31 J6 MAD05_0 47 42 K7 32 L7 MAD06_0 48 43 H6 33 K7 MAD07_0 49 44 J7 34 J7 MAD08_0 50 45 K8 35 K8 MAD09_0 63 53 J10 43 J10 MAD10_0 64 54 J8 44 J8 MAD11_0 65 55 H10 45 H10 MAD12_0 66 56 H9 46 H9 MAD13_0 67 57 H7 47 G10 MAD14_0 68 58 G10 48 G9 MAD15_0 69 59 G9 49 F10 MAD16_0 73 63 G8 53 F9 MAD17_0 74 64 F10 54 E11 MAD18_0 75 65 F9 55 E10 MAD19_0 76 66 E11 56 E9 MAD20_0 77 67 E10 - - MAD21_0 78 68 F8 - - MAD22_0 79 69 E9 - - MAD23_0 80 70 D11 - - MAD24_0 89 74 C10 60 C10
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 35 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- External Bus MCSX0_0 External bus interface chip select output pin 103 88 A6 68 C7 MCSX1_0 102 87 D7 67 C8 MCSX2_0 101 86 C7 - - MCSX3_0 100 85 B7 - - MCSX4_0 98 83 D9 - - MCSX5_0 97 82 C8 - - MCSX6_0 94 79 B11 63 B11 MCSX7_0 92 77 A9 61 A10 MDQM0_0 External bus interface byte mask signal output pin 105 90 C6 70 B6 MDQM1_0 106 91 A5 71 C6 MOEX_0 External bus interface read enable signal for SRAM 114 94 C5 74 C5 MWEX_0 External bus interface write enable signal for SRAM 113 93 D6 73 B5 MNALE_0 External bus interface ALE signal to control NAND Flash memory output pin 18 - - - - MNCLE_0 External bus interface CLE signal to control NAND Flash memory output pin 19 - - - - MNREX_0 External bus interface read enable signal to control NAND Flash memory 21 - - - - MNWEX_0 External bus interface write enable signal to control NAND Flash memory 20 - - - - MADA TA00_0 External bus interface data bus 2 2 C1 2 C1 MADA TA01_0 3 3 C2 3 C2 MADA TA02_0 4 4 B3 4 B3 MADA TA03_0 5 5 D1 5 D1 MADA TA04_0 6 6 D2 6 D2 MADA TA05_0 7 7 D3 7 D3 MADA TA06_0 8 8 D5 8 E1 MADA TA07_0 9 9 E1 9 E2 MADA TA08_0 10 10 E2 10 E3 MADA TA09_0 11 11 E3 11 G1 MADA TA10_0 12 12 E4 12 G2 MADA TA11_0 13 13 F1 - - MADA TA12_0 14 14 F2 - - MADA TA13_0 15 15 F3 - - MADA TA14_0 16 16 G1 - - MADA TA15_0 17 17 G2 - - MALE_0 Latch enable signal for multiplex 104 89 B6 69 B7 MRDY_0 External RDY input signal 116 96 C4 76 C4 MCLKOUT_0 External bus clock output pin 99 84 A7 66 A8
36 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- External Interrupt INT00_0 External interrupt request 00 input pin 2 2 C1 2 C1 INT00_1 97 82 C8 - - INT00_2 102 87 D7 67 C8 INT01_0 External interrupt request 01 input pin 3 3 C2 3 C2 INT01_1 98 83 D9 - - INT01_2 85 - - - - INT02_0 External interrupt request 02 input pin 4 4 B3 4 B3 INT02_1 63 53 J10 43 J10 INT02_2 82 - - - - INT03_0 External interrupt request 03 input pin 113 93 D6 73 B5 INT03_1 66 56 H9 46 H9 INT03_2 14 9 E1 9 E2 INT04_0 External interrupt request 04 input pin 17 12 E4 12 G2 INT04_1 69 59 G9 49 F10 INT04_2 15 10 E2 10 E3 INT05_0 External interrupt request 05 input pin 89 74 C10 60 C10 INT05_1 75 65 F9 55 E10 INT05_2 16 11 E3 11 G1 INT06_0 External interrupt request 06 input pin 23 18 F4 13 G3 INT06_1 88 73 C11 59 C11 INT06_2 50 45 K8 35 K8 INT07_0 External interrupt request 07 input pin 24 19 G3 14 H1 INT07_1 114 94 C5 74 C5 INT07_2 5 5 D1 5 D1 INT08_0 External interrupt request 08 input pin 34 29 K5 - - INT08_1 19 14 F2 - - INT08_2 8 8 D5 8 E1 INT09_0 External interrupt request 09 input pin 35 30 J5 - - INT09_1 20 15 F3 - - INT09_2 11 - - - - INT10_0 External interrupt request 10 input pin 36 31 H5 21 L5 INT10_1 21 16 G1 - - INT11_0 External interrupt request 11 input pin 37 32 L6 22 K5 INT11_1 22 17 G2 - - INT12_0 External interrupt request 12 input pin 48 43 H6 33 K7 INT12_1 32 27 J4 - - INT13_0 External interrupt request 13 input pin 49 44 J7 34 J7 INT13_1 33 28 L5 - - INT13_2 52 - - - - INT14_0 External interrupt request 14 input pin 67 57 H7 47 G10 INT14_1 44 39 K6 29 J5 INT14_2 53 - - - -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 37 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- External Interrupt INT15_0 External interrupt request 15 input pin 68 58 G10 48 G9 INT15_1 116 96 C4 76 C4 INT15_2 54 - - - - INT16_0 External interrupt request 16 input pin 100 85 B7 - - INT16_1 118 98 A3 78 A3 INT16_2 12 - - - - INT17_0 External interrupt request 17 input pin 101 86 C7 - - INT17_1 119 99 A2 79 A2 INT17_2 13 - - - - INT18_0 External interrupt request 18 input pin 103 88 A6 68 C7 INT18_1 6 6 D2 6 D2 INT18_2 26 21 H2 16 H3 INT19_0 External interrupt request 19 input pin 104 89 B6 69 B7 INT19_1 7 7 D3 7 D3 INT19_2 28 23 H3 18 J2 INT20_0 External interrupt request 20 input pin 105 90 C6 70 B6 INT20_1 45 40 J6 30 K6 INT20_2 76 66 E11 56 E9 INT21_0 External interrupt request 21 input pin 106 91 A5 71 C6 INT21_1 46 41 L7 31 J6 INT21_2 77 67 E10 - - INT22_0 External interrupt request 22 input pin 109 - - - - INT22_1 47 42 K7 32 L7 INT22_2 78 68 F8 - - INT23_0 External interrupt request 23 input pin 111 - - - - INT23_1 99 84 A7 66 A8 INT23_2 79 69 E9 - - NMIX Non-Maskable Interrupt input pin 107 92 B5 72 A6
38 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- GPIO P00 General-purpose I/O port 0 92 77 A9 61 A10 P01 93 78 B9 62 B9 P02 94 79 B11 63 B11 P03 95 80 A8 64 A9 P04 96 81 B8 65 B8 P05 97 82 C8 - - P06 98 83 D9 - - P07 99 84 A7 66 A8 P08 100 85 B7 - - P09 101 86 C7 - - P0A 102 87 D7 67 C8 P0B 103 88 A6 68 C7 P0C 104 89 B6 69 B7 P0D 105 90 C6 70 B6 P0E 106 91 A5 71 C6 P0F 107 92 B5 72 A6 P10 General-purpose I/O port 1 62 52 J11 42 J11 P11 63 53 J10 43 J10 P12 64 54 J8 44 J8 P13 65 55 H10 45 H10 P14 66 56 H9 46 H9 P15 67 57 H7 47 G10 P16 68 58 G10 48 G9 P17 69 59 G9 49 F10 P18 73 63 G8 53 F9 P19 74 64 F10 54 E11 P1A 75 65 F9 55 E10 P1B 76 66 E11 56 E9 P1C 77 67 E10 - - P1D 78 68 F8 - - P1E 79 69 E9 - - P1F 80 70 D11 - - P20 General-purpose I/O port 2 89 74 C10 60 C10 P21 88 73 C11 59 C11 P22 87 72 E8 58 D9 P23 86 71 D10 57 D10 P24 85 - - - - P25 84 - - - - P26 83 - - - - P27 82 - - - - P28 81 - - - -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 39 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- GPIO P30 General-purpose I/O port 3 14 9 E1 9 E2 P31 15 10 E2 10 E3 P32 16 11 E3 11 G1 P33 17 12 E4 12 G2 P34 18 13 F1 - - P35 19 14 F2 - - P36 20 15 F3 - - P37 21 16 G1 - - P38 22 17 G2 - - P39 23 18 F4 13 G3 P3A 24 19 G3 14 H1 P3B 25 20 H1 15 H2 P3C 26 21 H2 16 H3 P3D 27 22 G4 17 J1 P3E 28 23 H3 18 J2 P3F 29 24 J2 19 J4 P40 General-purpose I/O port 4 32 27 J4 - - P41 33 28 L5 - - P42 34 29 K5 - - P43 35 30 J5 - - P44 36 31 H5 21 L5 P45 37 32 L6 22 K5 P46 41 36 L3 26 L3 P47 42 37 K3 27 K3 P48 44 39 K6 29 J5 P49 45 40 J6 30 K6 P4A 46 41 L7 31 J6 P4B 47 42 K7 32 L7 P4C 48 43 H6 33 K7 P4D 49 44 J7 34 J7 P4E 50 45 K8 35 K8 P50 General-purpose I/O port 5 2 2 C1 2 C1 P51 3 3 C2 3 C2 P52 4 4 B3 4 B3 P53 5 5 D1 5 D1 P54 6 6 D2 6 D2 P55 7 7 D3 7 D3 P56 8 8 D5 8 E1 P57 9 - - - - P58 10 - - - - P59 11 - - - - P5A 12 - - - - P5B 13 - - - - P60 General-purpose I/O port 6 116 96 C4 76 C4 P61 115 95 B4 75 B4 P62 114 94 C5 74 C5 P63 113 93 D6 73 B5 P64 112 - - - - P65 111 - - - - P66 110 - - - - P67 109 - - - - P68 108 - - - -
40 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- GPIO P70 General-purpose I/O port 7 51 - - - - P71 52 - - - - P72 53 - - - - P73 54 - - - - P74 55 - - - - P80 General-purpose I/O port 8 118 98 A3 78 A3 P81 119 99 A2 79 A2 PE0 General-purpose I/O port E 56 46 K9 36 K9 PE2 58 48 L9 38 L9 PE3 59 49 L10 39 L10
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 41 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 88 73 C11 59 C11 SIN0_1 66 56 H9 46 H9 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 87 72 E8 58 D9 SOT0_1 (SDA0_1) 67 57 H7 47 G10 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 86 71 D10 57 D10 SCK0_1 (SCL0_1) 68 58 G10 48 G9 Multi- function Serial SIN1_0 Multi-function serial interface ch.1 input pin 8 - - - - SIN1_1 63 53 J10 43 J10 SOT1_0 (SDA1_0) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 9 - - - - SOT1_1 (SDA1_1) 64 54 J8 44 J8 SCK1_0 (SCL1_0) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 10 - - - - SCK1_1 (SCL1_1) 65 55 H10 45 H10
42 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN2_0 Multi-function serial interface ch.2 input pin 53 - - - - SIN2_1 85 - - - - SIN2_2 69 59 G9 49 F10 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 54 - - - - SOT2_1 SOT2_2 (SDA2_2) 73 63 G8 53 F9 SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 55 - - - - SCK2_1 SCK2_2 (SCL2_2) 74 64 F10 54 E11 Multi- function Serial SIN3_0 Multi-function serial interface ch.3 input pin 110 - - - - SIN3_1 2 2 C1 2 C1 SIN3_2 44 39 K6 29 J5 SOT3_0 (SDA3_0) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 109 - - - - SOT3_1 (SDA3_1) 3 3 C2 3 C2 SOT3_2 (SDA3_2) 45 40 J6 30 K6 SCK3_0 (SCL3_0) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 108 - - - - SCK3_1 (SCL3_1) 4 4 B3 4 B3 SCK3_2 (SCL3_2) 46 41 L7 31 J6
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 43 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 102 87 D7 67 C8 SIN4_1 75 65 F9 55 E10 SIN4_2 97 82 C8 - - SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 103 88 A6 68 C7 SOT4_1 (SDA4_1) 76 66 E11 56 E9 SOT4_2 (SDA4_2) 98 83 D9 - - SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 104 89 B6 69 B7 SCK4_1 (SCL4_1) 77 67 E10 - - SCK4_2 (SCL4_2) 99 84 A7 - - RTS4_0 Multi-function serial interface ch.4 RTS output pin 105 90 C6 70 B6 RTS4_1 79 69 E9 - - RTS4_2 101 86 C7 - - CTS4_0 Multi-function serial interface ch.4 CTS input pin 106 91 A5 71 C6 CTS4_1 78 68 F8 - - CTS4_2 100 85 B7 - -
44 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 116 96 C4 76 C4 SIN5_1 113 - - - - SIN5_2 20 15 F3 - - SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 115 95 B4 75 B4 SOT5_1 SOT5_2 (SDA5_2) 21 16 G1 - - SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 114 94 C5 74 C5 SCK5_1 SCK5_2 (SCL5_2) 22 17 G2 - -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 45 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 5 5 D1 5 D1 SIN6_1 17 12 E4 12 G2 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). 6 6 D2 6 D2 SOT6_1 (SDA6_1) 16 11 E3 11 G1 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 7 7 D3 7 D3 SCK6_1 (SCL6_1) 15 10 E2 10 E3 Multi- function Serial SIN7_0 Multi-function serial interface ch.7 input pin 11 - - - - SIN7_1 50 45 K8 35 K8 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 12 - - - - SOT7_1 (SDA7_1) 49 44 J7 34 J7 SCK7_0 (SCL7_0) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 13 - - - - SCK7_1 (SCL7_1) 48 43 H6 33 K7
46 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN8_0 Multi-function serial interface ch.8 input pin 97 82 C8 - - SOT8_0 (SDA8_0) Multi-function serial interface ch.8 output pin. This pin operates as SOT8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA8 when it is used in an I2C (operation mode 4). 94 79 B11 - - SCK8_0 (SCL8_0) Multi-function serial interface ch.8 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I2C (operation mode 4). 92 77 A9 - - Multi- function Serial SIN9_0 Multi-function serial interface ch.9 input pin 17 12 E4 - - SOT9_0 (SDA9_0) Multi-function serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA9 when it is used in an I2C (operation mode 4). 18 13 F1 - - SCK9_0 (SCL9_0) Multi-function serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I2C (operation mode 4). 19 14 F2 - - Multi- function Serial SIN10_0 Multi-function serial interface ch.10 input pin 23 18 F4 13 G3 SOT10_0 (SDA10_0) Multi-function serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA10 when it is used in an I2C (operation mode 4). 24 19 G3 14 H1 SCK10_0 (SCL10_0) Multi-function serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I2C (operation mode 4). 25 20 H1 15 H2
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 47 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN11_0 Multi-function serial interface ch.11 input pin 26 21 H2 16 H3 SOT11_0 (SDA11_0) Multi-function serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA11 when it is used in an I2C (operation mode 4). 27 22 G4 17 J1 SCK11_0 (SCL11_0) Multi-function serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I2C (operation mode 4). 28 23 H3 18 J2 Multi- function Serial SIN12_0 Multi-function serial interface ch.12 input pin 32 27 J4 - - SOT12_0 (SDA12_0) Multi-function serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA12 when it is used in an I2C (operation mode 4). 33 28 L5 - - SCK12_0 (SCL12_0) Multi-function serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I2C (operation mode 4). 34 29 K5 - - Multi- function Serial SIN13_0 Multi-function serial interface ch.13 input pin 35 30 J5 - - SOT13_0 (SDA13_0) Multi-function serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA13 when it is used in an I2C (operation mode 4). 36 31 H5 - - SCK13_0 (SCL13_0) Multi-function serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I2C (operation mode 4). 37 32 L6 - -
48 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Serial SIN14_0 Multi-function serial interface ch.14 input pin 50 - - - - SOT14_0 (SDA14_0) Multi-function serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA14 when it is used in an I2C (operation mode 4). 51 - - - - SCK14_0 (SCL14_0) Multi-function serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I2C (operation mode 4). 52 - - - - Multi- function Serial SIN15_0 Multi-function serial interface ch.15 input pin 82 - - - - SOT15_0 (SDA15_0) Multi-function serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA15 when it is used in an I2C (operation mode 4). 81 - - - - SCK15_0 (SCL15_0) Multi-function serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I2C (operation mode 4). 80 - - - -
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 49 CONFIDENTIAL Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Multi- function Timer DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of multi-function timer 0. 23 18 F4 13 G3 DTTI0X_1 79 69 E9 - - FRCK0_0 16-bit free-run timer ch.0 external clock input pin 18 13 F1 - - FRCK0_1 80 70 D11 - - FRCK0_2 63 53 J10 43 J10 IC00_0 16-bit input capture input pin of multi-function timer 0. ICxx describes channel number. 22 17 G2 - - IC00_1 75 65 F9 55 E10 IC00_2 64 54 J8 44 J8 IC01_0 21 16 G1 - - IC01_1 76 66 E11 56 E9 IC01_2 65 55 H10 45 H10 IC02_0 20 15 F3 - - IC02_1 77 67 E10 - - IC02_2 66 56 H9 46 H9 IC03_0 19 14 F2 - - IC03_1 78 68 F8 - - IC03_2 67 57 H7 47 G10 RTO00_0 (PPG00_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 24 19 G3 14 H1 RTO00_1 (PPG00_1) 86 71 D10 57 D10 RTO01_0 (PPG00_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 25 20 H1 15 H2 RTO01_1 RTO02_0 (PPG02_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 26 21 H2 16 H3 RTO02_1 RTO03_0 (PPG02_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 27 22 G4 17 J1 RTO03_1 RTO04_0 (PPG04_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 28 23 H3 18 J2 RTO04_1 RTO05_0 (PPG04_0) Waveform generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 29 24 J2 19 J4 RTO05_1 IGTRG_0 PPG IGMT mode external trigger input pin 46 41 L7 31 J6 IGTRG_1 116 96 C4 76 C4
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Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Quadrature Position/ Revolution Counter AIN0_0 QPRC ch.0 AIN input pin 14 9 E1 9 E2 AIN0_1 45 40 J6 30 K6 AIN0_2 2 2 C1 2 C1 BIN0_0 QPRC ch.0 BIN input pin 15 10 E2 10 E3 BIN0_1 46 41 L7 31 J6 BIN0_2 3 3 C2 3 C2 ZIN0_0 QPRC ch.0 ZIN input pin 16 11 E3 11 G1 ZIN0_1 47 42 K7 32 L7 ZIN0_2 4 4 B3 4 B3 Quadrature Position/ Revolution Counter AIN1_1 QPRC ch.1 AIN input pin 89 74 C10 60 C10 AIN1_2 48 43 H6 33 K7 BIN1_1 QPRC ch.1 BIN input pin 88 73 C11 59 C11 BIN1_2 49 44 J7 34 J7 ZIN1_1 QPRC ch.1 ZIN input pin 87 72 E8 58 D9 ZIN1_2 50 45 K8 35 K8 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 107 92 B5 72 A6 RTCCO_1 65 55 H10 45 H10 RTCCO_2 24 19 G3 14 H1 SUBOUT_0 Sub clock output pin 107 92 B5 72 A6 SUBOUT_1 65 55 H10 45 H10 SUBOUT_2 24 19 G3 14 H1 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 107 92 B5 72 A6 WKUP1 Deep standby mode return signal input pin 1 63 53 J10 43 J10 WKUP2 Deep standby mode return signal input pin 2 88 73 C11 59 C11 WKUP3 Deep standby mode return signal input pin 3 116 96 C4 76 C4 WKUP4 Deep standby mode return signal input pin 4 14 9 E1 9 E2 WKUP5 Deep standby mode return signal input pin 5 102 87 D7 67 C8 HDMI- CEC/ Remote Control Reception CEC0_0 HDMI-CEC/Remote Control Reception ch.0 input/output pin 48 43 H6 33 K7 CEC0_1 103 88 A6 68 C7 CEC1_0 HDMI-CEC/Remote Control Reception ch.1 input/output pin 116 96 C4 76 C4 CEC1_1 8 8 D5 8 E1
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 51 CONFIDENTIAL Pin function Pin name Function description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Reset INITX External Reset Input pin. A reset is valid when INITX=L. 43 38 K4 28 K4 Mode MD0 Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. 57 47 L8 37 L8 MD1 Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. 56 46 K9 36 K9 Power VCC Power supply pin 1 1 B1 1 B1 VCC Power supply pin 31 26 J1 - - VCC Power supply pin 40 35 K1 25 K1 VCC Power supply pin 61 51 K11 41 K11 VCC Power supply pin 91 76 A10 - - VCC Power supply pin 117 97 A4 77 A4 GND VSS GND pin - - - - F1 VSS GND pin - - - - F2 VSS GND pin - - - - F3 VSS GND pin - - B2 - B2 VSS GND pin 30 25 L1 20 L1 VSS GND pin - - K2 - K2 VSS GND pin - - J3 - J3 VSS GND pin - - H4 - - VSS GND pin - - - - L6 VSS GND pin 39 34 L4 24 L4 VSS GND pin 60 50 L11 40 L11 VSS GND pin - - K10 - K10 VSS GND pin - - J9 - J9 VSS GND pin - - H8 - - VSS GND pin - - B10 - B10 VSS GND pin - - C9 - C9 VSS GND pin - - - - D11 VSS GND pin 90 75 A11 - A11 VSS GND pin - - D8 - - VSS GND pin - - - - A7 VSS GND pin - - D4 - - VSS GND pin - - C3 - C3 VSS GND pin - - - - A5 VSS GND pin 120 100 A1 80 A1
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Pin Function Pin Name Function Description Pin No LQFP- 120 LQFP- 100 BGA- 112 LQFP- BGA- Clock X0 Main clock (oscillation) input pin 58 48 L9 38 L9 X0A Sub clock (oscillation) input pin 41 36 L3 26 L3 X1 Main clock (oscillation) I/O pin 59 49 L10 39 L10 X1A Sub clock (oscillation) I/O pin 42 37 K3 27 K3 CROUT_0 Built-in High-speed CR-osc clock output port 89 74 C10 60 C10 CROUT_1 107 92 B5 72 A6 ADC Power A VCC A/D converter analog power supply pin 70 60 H11 50 H11 A VRH A/D converter analog reference voltage input pin 71 61 F11 51 F11 ADC GND A VSS A/D converter GND pin 72 62 G11 52 G11 C pin C Power stabilization capacity pin 38 33 L2 23 L2
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 53 CONFIDENTIAL I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. Oscillation feedback resistor : Approximately 1 MΩ With standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA B CMOS level hysteresis input Pull-up resistor : Approximately 33 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Pull-up resistor Digital input Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control
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C N-ch Open drain output CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. Oscillation feedback resistor : Approximately 5MΩ With standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 55 CONFIDENTIAL Type Circuit Remarks E P-chP-ch N-ch R CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off F P-chP-ch N-ch R CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off G CMOS level hysteresis input Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Mode input
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H P-chP-ch N-ch R CMOS level output CMOS level hysteresis input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA Available to control PZR registers. When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Digital output Pull-up resistor control Digital input Standby mode control
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 57 CONFIDENTIAL Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semicondu ctor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-V oltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of op eration. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E
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Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or w here extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through -holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 59 CONFIDENTIAL Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
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- Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to c hemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 61 CONFIDENTIAL Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between A VCC pin and A VSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0 /X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
- Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF
- Lead type Load capacitance : Approximately 6 pF to 7 pF
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Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7uF would be recommended for this series. Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.
- Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Device C VSS CS GND Set as External clock input
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 63 CONFIDENTIAL Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and A VSS = VSS. Turning on : VCC →AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
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Block Diagram Cortex-M3 Core @40 MHz(Max) Flash I/F Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 24-pin + NMI Power-On Reset SRAM0 16/24/32 Kbyte SRAM1 16/24/32 Kbyte I D Sys CLK NVIC WatchDog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, PEx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator ADTGx RTS4 CTS4 MADx MADATAx On-Chip Flash 256+32 Kbyte/ 384+32 Kbyte/ 512+32 Kbyte Multi-Function Serial I/F 16ch. HW flow control(ch.4) External Bus I/F GPIO PIN-Function-Ctrl LVD TPIU* ROM Table ETM*SWJ-DP Main Osc PLL Sub Osc CR
4 MHz
CEC0, CEC1 LVD Ctrl Base Timer 16-bit 16ch./ 32-bit 8ch. HDMI-CEC/ Remote Reciver Control Real-Time Clock RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 2ch. 16-bit PPG 3ch. DTTI0X FRCK0 QPRC 2ch.BINx ZINx IC0x RTO0x AINx 12-bit A/D Converter Multi-function Timer × 1 MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT IGTRG Waveform Generator 3ch. CROUT Source Clock AHB-APB Bridge: APB0(Max 40 MHz) AHB-AHB Bridge AHB-APB Bridge : APB1 (Max 40 MHz) AHB-APB Bridge : APB2 (Max 40 MHz) Multi-layer AHB (Max 40 MHz) *: For the MB9AF154MB, MB9AF155MB, and MB9AF156MB, ETM is not available. Memory Size See Memory size in Product Lineup to confirm the memory size.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 65 CONFIDENTIAL Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0x4006_1000 0xE000_0000 0x4006_0000 DMAC 0x4003_F000 EXT-bus I/F 0x4003_C000 Reserved 0x4003_B000 RTC 0x4003_A000 Watch Counter 0x7000_0000 0x4003_9000 CRC 0x4003_8000 MFS 0x6000_0000 0x4003_5000 LVD/DS mode 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4000_0000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2400_0000 0x4002_E000 CR Trim 0x2200_0000 0x4002_8000 0x4002_7000 A/DC 0x4002_6000 QPRC 0x2008_0000 0x4002_5000 Base Timer 0x2000_0000 SRAM1 0x4002_4000 PPG 0x1FF8_0000 SRAM0 0x0020_8000 Reserved 0x0020_0000 Flash(Work area) 0x4002_1000 0x0010_4000 Reserved 0x4002_0000 MFT Unit0 0x0010_0000 Security/CR Trim 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x0000_0000 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved External Device Area Reserved Reserved Cortex-M3 Private Peripherals 0x4004_0000 Reserved 0x4003_6000 Reserved Reserved HDMI-CEC/ Remote Control Receiver32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved Reserved See "Memory Map (2)" for the memory size details. Reserved Reserved Flash(Main area) Reserved
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Memory Map (2) MB9AF156MB/NB/RB MB9AF155MB/NB/RB MB9AF154MB/NB/RB 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_8000 0x2000_6000 0x2000_4000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_C000 0x1FFF_A000 0x1FFF_8000 0x0020_8000 0x0020_8000 0x0020_8000 SA7(8KB) SA7(8KB) SA7(8KB) SA6(8KB) SA6(8KB) SA6(8KB) SA5(8KB) SA5(8KB) SA5(8KB) 0x0020_0000 SA4(8KB) 0x0020_0000 SA4(8KB) 0x0020_0000 SA4(8KB) 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0010_0000 Security 0x0008_0000 0x0006_0000 0x0004_0000 SA3(8KB) SA3(8KB) SA3(8KB) 0x0000_0000 SA2(8KB) 0x0000_0000 SA2(8KB) 0x0000_0000 SA2(8KB) SA8(48KB) Reserved Flash(Main area)
384 Kbytes
Flash(Main area)
256 Kbytes
Flash(Work area)
32 Kbytes
SA13(64KB) SA12(64KB) SA11(64KB) SA11(64KB) SA10(64KB) SA9(64KB) SA13(64KB) SA14(64KB) SA15(64KB) Flash(Work area) Flash(Main area)
512 Kbytes
SA8(48KB) SA9(64KB) SA10(64KB) SA11(64KB) SA12(64KB) Reserved Reserved Reserved SRAM0 Flash(Work area) SA10(64KB) SA9(64KB) SA8(48KB) SRAM1
24 Kbytes
16 Kbytes
For more information about Flash (Main area)/Flash (Work area), see MB9AB40N/A40N/340N/140N/150R, MB9B520M/320M/120M Series Flash Programming Manual.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 67 CONFIDENTIAL Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External bus interface 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x41FF_FFFF Reserved
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Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 This is the period when the INITX pin is the L level. INITX=1 This is the period when the INITX pin is the H level. SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Trace output Indicates that the trace function can be used. GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 69 CONFIDENTIAL List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby Rtc mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected
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Timer mode, RTC mode, or Stop mode state Deep standby Rtc mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z/ Internal input fixed at 0 Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at 0 H NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 71 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby Rtc mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - I JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected J Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected
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Timer mode, RTC mode, or Stop mode state Deep standby Rtc mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - N Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected O Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External interrupt enabled selected Maintain previous state Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 73 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby Rtc mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Q CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected R CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected S WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
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Electrical Characteristics 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1, *2 VCC VSS - 0.5 VSS + 4.6 V Analog power supply voltage*1, *3 AVCC VSS - 0.5 VSS + 4.6 V Analog reference voltage*1, *3 AVRH VSS - 0.5 VSS + 4.6 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 4.6 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V L level maximum output current*4 IOL - 10 mA L level average output current*5 IOLA V - 4 mA L level total maximum output current ∑IOL - 100 mA L level total average output current*6 ∑IOLA V - 50 mA H level maximum output current*4 IOH - - 10 mA H level average output current*5 IOHA V - - 4 mA H level total maximum output current ∑IOH - - 100 mA H level total average output current*6 ∑IOHA V - - 50 mA Power consumption PD - 300 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 75 CONFIDENTIAL 2. Recommended Operating Conditions (VSS = A VSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 1.65*2 3.6 V Analog power supply voltage AVCC - 1.65 3.6 V AVCC = VCC Analog reference voltage A VRH - 2.7 AVCC V AVCC ≥ 2.7 V AVCC AVCC V AVCC < 2.7 V Smoothing capacitor CS - 1 10 μF For built-in Regulator*1 Operating temperature TA - - 40 + 85 °C *1 : See C Pin in Handling Devices for the connection of the smoothing capacitor. *2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
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- DC Characteristics (1) Current rating (VCC = AVCC = 1.65V to 3.6V, VSS = A VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 Power supply current ICC VCC PLL Run mode CPU: 40 MHz, Peripheral: 40 MHz 17.5 23.7 mA *1, *5 CPU: 40 MHz, Peripheral: the clock stops NOP operation 8 11 mA *1, *5 High-speed CR Run mode CPU/ Peripheral: 4 MHz*2 1.9 3.1 mA *1 Sub Run mode CPU/ Peripheral: 32 kHz 120 810 μA *1, *6 Low-speed CR Run mode CPU/ Peripheral: 100 kHz 140 830 μA *1 ICCS PLL Sleep mode Peripheral: 40 MHz 11 15 mA *1, *5 High-speed CR Sleep mode Peripheral: 4 MHz*2 0.82 1.7 mA *1 Sub Sleep mode Peripheral: 32 kHz 105 800 μA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 125 810 μA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.6 V *4: TA=+85°C, VCC=3.6 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 77 CONFIDENTIAL Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*2 Power supply current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 2.0 2.7 mA *1, *3 TA = + 85°C, When LVD is off - 3.2 mA *1, *3 Sub Timer mode TA = + 25°C, When LVD is off 15 45 μA *1, *4 TA = + 85°C, When LVD is off - 440 μA *1, *4 ICCR RTC mode TA = + 25°C, When LVD is off 13 40 μA *1, *4 TA = + 85°C, When LVD is off - 380 μA *1, *4 ICCH Stop mode TA = + 25°C, When LVD is off 11 38 μA *1 TA = + 85°C, When LVD is off - 370 μA *1 ICCRD Deep Standby RTC mode TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off - 125 μA *1, *4, *5 TA = + 85°C, When LVD is off, When RAM is on 195 μA *1, *4, *5 ICCHD Deep Standby Stop mode TA = + 25°C, When LVD is off, When RAM is off 1.4 10 μA *1, *5 TA = + 25°C, When LVD is off, When RAM is on 8.6 23 μA *1, *5 TA = + 85°C, When LVD is off, When RAM is off - 120 μA *1, *5 TA = + 85°C, When LVD is off, When RAM is on 190 μA *1, *5 *1: When all ports are fixed. *2: VCC=3.6 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) *5: RAM on/off setting is on-chip SRAM only.
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- Low-Voltage Detection Current (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for reset VCC = 3.6 V 0.13 0.3 μA At not detect At operation for interrupt VCC = 3.6 V 0.13 0.3 μA At not detect
- Flash Memory Current (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 9.5 11.2 mA * *: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
- A/D Converter Current (VCC = A VCC = 1.65V to 3.6V , VSS = A VSS = 0V , TA = - 40°C to +85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD A VCC At 1unit operation 0.27 0.42 mA At stop 0.03 10 μA Reference power supply current ICCA VRH A VRH At 1unit operation A VRH=3.6 V 0.72 1.29 mA At stop 0.02 2.6 μA
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 79 CONFIDENTIAL (2) Pin Characteristics (VCC = AVCC = 1.65V to 3.6V, VSS = A VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 VCC ≥ 2.7 V VCC × 0.8 - VCC + 0.3 V VCC < 2.7 V VCC × 0.7 5V tolerant input pin VCC ≥ 2.7 V VCC × 0.8 - VSS + 5.5 V VCC < 2.7 V VCC × 0.7 L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 VCC ≥ 2.7 V VSS - 0.3 - VCC × 0.2 V VCC < 2.7 V VCC × 0.3
5 V tolerant
VCC ≥ 2.7 V VSS - 0.3 - VCC × 0.2 V VCC < 2.7 V VCC × 0.3 H level output voltage VOH 4mA type VCC ≥ 2.7 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 2.7 V, IOH = - 2 mA VCC - 0.45 L level output voltage VOL 4mA type VCC ≥ 2.7 V, IOL = 4 mA VSS - 0.4 V VCC < 2.7 V, IOL = 2 mA Input leak current IIL - - - 5 - + 5 μA CEC0_0, CEC0_1, CEC1_0, CEC1_1 VCC = AVCC = AVRH = VSS = AVSS = 0.0 V - - +1.8 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 2.7 V 21 33 66 kΩ VCC < 2.7 V - - 134 Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, A VRH - - 5 15 pF
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- AC Characteristics (1) Main Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 2.7V 4 48 MHz When crystal oscillator is connected VCC < 2.7V 4 20 - 4 48 MHz When using external clock Input clock cycle tCYLH - 20.83 250 ns When using external clock Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCM - - - 40 MHz Master clock fCC - - - 40 MHz Base clock (HCLK/FCLK) fCP0 - - - 40 MHz APB0 bus clock*2 fCP1 - - - 40 MHz APB1 bus clock*2 fCP2 - - - 40 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 25 - ns APB0 bus clock*2 tCYCP1 - - 25 - ns APB1 bus clock*2 tCYCP2 - - 25 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 81 CONFIDENTIAL (2) Sub Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency fCL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected* - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock *: For more information about crystal oscillator, see Sub crystal oscillator in Handling Devices. (3) Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TA = + 25°C, VCC ≥ 2.7V 3.94 4 4.06 MHz When trimming*1 TA = - 20°C to + 85°C, VCC ≥ 2.7V 3.92 4 4.08 TA = - 40°C to + 85°C, VCC ≥ 2.7V 3.88 4 4.12 TA = + 25°C, VCC < 2.7V 3.9 4 4.1 TA = - 40°C to + 85°C VCC < 2.7V 3.66 4 4.20 TA = - 40°C to + 85°C 2.8 4 5.2 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz X0A
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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 5 - 37 multiplier PLL macro oscillation clock frequency fPLLO 75 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 40 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. (4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for input clock of Main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 19 - 35 multiplier PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 40 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection High-speed CR clock (CLKHC) Main clock (CLKMO)
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 83 CONFIDENTIAL (5) Reset Input Characteristics (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns (6) Power-on Reset Timing (VCC= 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Max Power supply rising time tVCCR VCC 0 - ms Power supply shut down time tOFF 1 - ms Time until releasing Power-on reset tPRT 1.34 16.09 ms 0.2V VDH_minimum VCC_minimum tPRT Internal reset VCC CPU Operation start Reset active Release tVCCR 0.2V 0.2V tOFF Glossary ・ VCC_minimum : Minimum VCC of recommended operating conditions ・ VDH_minimum : Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset See 6. Low-Voltage Detection Characteristics
84 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
(7) External Bus Timing External bus clock output characteristics (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT* VCC ≥ 2.7 V - 40 MHz VCC < 2.7 V - 20 MHz *: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual. When external bus clock is not output, this characteristic does not give any effect on external bus operation. External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH Input signal Output signal MCLKOUT
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 85 CONFIDENTIAL Separate Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V MCSX ↓ → Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] VCC ≥ 2.7 V -9 +9 ns VCC < 2.7 V -12 +12 MOEX ↑ → Address hold time tOEH - AX MOEX, MAD[24:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MOEX ↓ delay time tCSL - OEL MOEX, MCSX[7:0] VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX, MDQM[1:0] VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX, MADA TA[15:0] VCC ≥ 2.7 V 20 - ns VCC < 2.7 V 38 - MOEX ↑ → Data hold time tDH - OE MOEX, MADA TA[15:0] VCC ≥ 2.7 V 0 - ns VCC < 2.7 V MWEX Min pulse width tWEW MWEX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V MWEX ↑ → Address output delay time tWEH - AX MWEX, MAD[24:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX, MCSX[7:0] VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 ns VCC < 2.7 V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MCSX ↓→ MDQM ↓ delay time tCSL-WDQML MCSX, MDQM[1:0] VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 ns VCC < 2.7 V MCLK×n-12 MCLK×n+12 MCSX ↓→ Data output time tCSL-DV MCSX, MADA TA[15:0] VCC ≥ 2.7 V MCLK-9 MCLK+9 ns VCC < 2.7 V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX, MADA TA[15:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
86 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 87 CONFIDENTIAL Separate Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MCSX delay time tCSL MCLK, MCSX[7:0] VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tCSH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MOEX delay time tREL MCLK, MOEX VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tREH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 Data set up → MCLK ↑ time tDS MCLK, MADA TA[15:0] VCC ≥ 2.7 V 19 - ns VCC < 2.7 V 37 MCLK ↑ → Data hold time tDH MCLK, MADA TA[15:0] VCC ≥ 2.7 V 0 - ns VCC < 2.7 V MWEX delay time tWEL MCLK, MWEX VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tWEH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 tDQMH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 MCLK ↑ → Data output time tODS MCLK, MADA TA[15:0] VCC ≥ 2.7 V MCLK+1 MCLK+18 ns VCC < 2.7 V MCLK+24 MCLK ↑ → Data hold time tOD MCLK, MADA TA[15:0] VCC ≥ 2.7 V 1 18 ns VCC < 2.7 V 24 Note: When the external load capacitance CL = 30 pF. Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX
88 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADA TA[15:0] VCC ≥ 2.7 V 0 +10 ns VCC < 2.7 V +20 Multiplexed address hold time tCHMADH VCC ≥ 2.7 V MCLK×n+0 MCLK×n+10 ns VCC < 2.7 V MCLK×n+0 MCLK×n+20 Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 89 CONFIDENTIAL Multiplexed Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 ns tCHAH VCC ≥ 2.7 V 1 9 ns VCC < 2.7 V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK, MADA TA[15:0] VCC ≥ 2.7 V 1 tOD ns VCC < 2.7 V MCLK ↑ → Multiplexed Data output time tCHMADX VCC ≥ 2.7 V 1 tOD ns VCC < 2.7 V Note: When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]
90 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
NAND Flash Memory Mode (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MNREX Min pulse width tNREW MNREX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V Data setup → MNREX↑time tDS – NRE MNREX, MADA TA[15:0] VCC ≥ 2.7 V 20 - ns VCC < 2.7 V 38 - MNREX↑→ Data hold time tDH – NRE MNREX, MADA TA[15:0] VCC ≥ 2.7 V 0 - ns VCC < 2.7 V MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 ns VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 MNWEX Min pulse width tNWEW MNWEX VCC ≥ 2.7 V MCLK×n-3 - ns VCC < 2.7 V MNWEX↓→ Data output time tNWEL – DV MNWEX, MADA TA[15:0] VCC ≥ 2.7 V - 9 + 9 ns VCC < 2.7 V -12 +12 MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADA TA[15:0] VCC ≥ 2.7 V 0 MCLK×m+9 ns VCC < 2.7 V MCLK×m+12 Note: When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 91 CONFIDENTIAL NAND Flash Memory Read NAND Flash Memory Address Write MCLK MNREX MADATA[15:0] Read MCLK MNALE MNCLE MADATA[15:0] MNWEX Write
92 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
NAND Flash Memory Command Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 93 CONFIDENTIAL External Ready Input Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MCLK ↑ MRDY input setup time tRDYI MCLK, MRDY VCC ≥ 2.7 V 19 - ns VCC < 2.7 V 37 When RDY is input
- · · Over 2cycles tRDYI When RDY is released 2 cycles tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY
94 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
(8) Base Timer Input Timing Timer input timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns tTIWH VIHS VIHS VILS VILS tTIWL Trigger input timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns tTRGH VIHS VIHS VILS VILS tTRGL Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. ECK TIN TGIN
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 95 CONFIDENTIAL (9) CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF.
96 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 97 CONFIDENTIAL CSIO (SPI = 0, SCINV = 1) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF.
98 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 99 CONFIDENTIAL CSIO (SPI = 1, SCINV = 0) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓→ SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF.
100 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
*: Changes when writing to TDR register tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 101 CONFIDENTIAL CSIO (SPI = 1, SCINV = 1) (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF.
102 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
UART external clock input (EXT = 1) (VCC = 1.65V to 3.6V, VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN SCK
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 103 CONFIDENTIAL (10) External Input Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTIxX Waveform generator INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt, NMI *3 500 - ns WKUPx *4 600 - ns Deep Standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Stop mode, in Timer mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
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(11) Quadrature Position/Revolution Counter timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC=0 ZIN pin L width tZLL QCR:CGSC=0 AIN/BIN rising and falling time from determined ZIN level tZABE QCR:CGSC=1 Determined ZIN level from AIN/BIN rising and falling time tABEZ QCR:CGSC=1 *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see Block Diagram in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 105 CONFIDENTIAL BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN
106 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
(12) I2C Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 30 pF, R = (VP/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDA T 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDA T 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDA T must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDA T ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 107 CONFIDENTIAL (13) ETM Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] VCC ≥ 2.7V 2 11 ns VCC < 2.7V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK VCC ≥ 2.7V - 40 MHz VCC < 2.7V - 20 MHz TRACECLK clock cycle tTRACE VCC ≥ 2.7V 25 - ns VCC < 2.7V 50 - ns Note: When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[3:0]
108 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
(14) JTAG Timing (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 2.7V 15 - ns VCC < 2.7V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 2.7V 15 - ns VCC < 2.7V TDO delay time tJTAGD TCK, TDO VCC ≥ 2.7V - 25 ns VCC < 2.7V - 45 Note: When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 109 CONFIDENTIAL 5. 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = A VCC = 1.65V to 3.6V , VSS = AVSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 2.4 ± 4.5 LSB Differential Nonlinearity - - - ± 2.3 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 7 ± 15 mV Full-scale transition voltage VFST ANxx - A VRH ± 7 A VRH ± 15 mV Conversion time*1 - - 2.0 - - μs AVCC ≥ 2.7 V 10 - - 1.65 V< AVCC < 1.8 V Sampling time*2 tS - 0.6 - 10 us AVCC ≥ 2.7 V 1.2 - 1.8 V< AVCC < 2.7 V 3.0 - 1.65 V< AVCC < 1.8 V Compare clock cycle*3 tCCK - 100 - 1000 ns AVCC ≥ 2.7 V 200 1.8 V< AVCC < 2.7 V 500 1.65 V< AVCC < 1.8 V State transition time to operation permission tSTT - - - 1.0 μs Analog input capacity CAIN - - - 9.4 pF Analog input resistor RAIN - - - 2.2 kΩ AVCC ≥ 2.7 V 5.5 1.8 V< AVCC < 2.7 V 10.5 1.65 V< AVCC < 1.8 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - A VRH V Reference voltage - A VRH 2.7 - AVCC V AVCC ≥ 2.7 V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V , HCLK=40 MHz sampling time: 0.6 μs, compare time: 1.4 μs 1.8 V < AVCC < 2.7 V, HCLK=40 MHz sampling time: 1.2 μs, compare time: 2.8 μs 1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).
110 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time[ns] RAIN: input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V CAIN: input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V REXT: Output impedance of external circuit[kΩ] (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle REXT RAIN CAIN Analog signal source ANxx Analog input pin Comparator
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 111 CONFIDENTIAL Definition of 12-bit A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVSS AVRH AVSS AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T
112 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
- Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHR*1 = 00000 1.38 1.50 1.60 V When voltage drops Released voltage VDH 1.43 1.55 1.65 V When voltage rises Detected voltage VDL SVHR*1 = 00001 1.43 1.55 1.65 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00010 1.47 1.60 1.73 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00011 1.52 1.65 1.78 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00100 1.56 1.70 1.84 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00101 1.61 1.75 1.89 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00110 1.66 1.80 1.94 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 00111 1.70 1.85 2.00 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01000 1.75 1.90 2.05 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01001 1.79 1.95 2.11 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01010 1.84 2.00 2.16 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01011 1.89 2.05 2.21 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01100 2.30 2.50 2.70 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01101 2.39 2.60 2.81 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01110 2.48 2.70 2.92 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 01111 2.58 2.80 3.02 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10000 2.67 2.90 3.13 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10001 2.76 3.00 3.24 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10010 2.85 3.10 3.35 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL SVHR*1 = 10011 2.94 3.20 3.46 V When voltage drops Released voltage VDH Same as SVHR = 00000 value V When voltage rises LVD stabilization wait time tLVDW - - - 5200 × tCYCP*2 μs LVD detection delay time tLVDDL - - - 200 μs *1: The SVHR bit of Low-Voltage Detection V oltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection Reset. *2: tCYCP indicates the APB2 bus clock cycle time.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 113 CONFIDENTIAL (2) Interrupt of Low-Voltage Detection (TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00100 1.56 1.70 1.84 V When voltage drops Released voltage VDH 1.61 1.75 1.89 V When voltage rises Detected voltage VDL SVHI = 00101 1.61 1.75 1.89 V When voltage drops Released voltage VDH 1.66 1.80 1.94 V When voltage rises Detected voltage VDL SVHI = 00110 1.66 1.80 1.94 V When voltage drops Released voltage VDH 1.70 1.85 2.00 V When voltage rises Detected voltage VDL SVHI = 00111 1.70 1.85 2.00 V When voltage drops Released voltage VDH 1.75 1.90 2.05 V When voltage rises Detected voltage VDL SVHI = 01000 1.75 1.90 2.05 V When voltage drops Released voltage VDH 1.79 1.95 2.11 V When voltage rises Detected voltage VDL SVHI = 01001 1.79 1.95 2.11 V When voltage drops Released voltage VDH 1.84 2.00 2.16 V When voltage rises Detected voltage VDL SVHI = 01010 1.84 2.00 2.16 V When voltage drops Released voltage VDH 1.89 2.05 2.21 V When voltage rises Detected voltage VDL SVHI = 01011 1.89 2.05 2.21 V When voltage drops Released voltage VDH 1.93 2.10 2.27 V When voltage rises Detected voltage VDL SVHI = 01100 2.30 2.50 2.70 V When voltage drops Released voltage VDH 2.39 2.60 2.81 V When voltage rises Detected voltage VDL SVHI = 01101 2.39 2.60 2.81 V When voltage drops Released voltage VDH 2.48 2.70 2.92 V When voltage rises Detected voltage VDL SVHI = 01110 2.48 2.70 2.92 V When voltage drops Released voltage VDH 2.58 2.80 3.02 V When voltage rises Detected voltage VDL SVHI = 01111 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHI = 10000 2.67 2.90 3.13 V When voltage drops Released voltage VDH 2.76 3.00 3.24 V When voltage rises Detected voltage VDL SVHI = 10001 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHI = 10010 2.85 3.10 3.35 V When voltage drops Released voltage VDH 2.94 3.20 3.46 V When voltage rises Detected voltage VDL SVHI = 10011 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises LVD stabilization wait time tLVDW - - - 5200 × tCYCP* μs LVD detection delay time tLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time.
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- Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 1.1 2.7 s Includes write time prior to internal erase Small Sector 0.3 0.9 Half word (16-bit) write time 30 528 μs Not including system-level overhead time Chip erase time 11.2 30.5 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. (2) Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* *: At average + 85C
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 115 CONFIDENTIAL 8. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. ・ Return Count Time (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs Low-speed CR Timer mode 350 700 μs Sub Timer mode 690 880 μs RTC mode, Stop mode 278 523 μs Deep Standby RTC mode Deep Standby Stop mode 318 603 μs When RAM is off 278 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.
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・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 117 CONFIDENTIAL (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. ・ Return Count Time (VCC = 1.65V to 3.6V , VSS = 0V , TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 148 263 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 148 263 μs Low-speed CR Timer mode 258 483 μs Sub Timer mode 322 516 μs RTC/Stop mode 278 523 μs Deep Standby RTC mode Deep Standby Stop mode 318 603 μs When RAM is off 278 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release
118 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
・ Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low -Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. ・ The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. ・ When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. ・ The internal resource reset means the watchdog reset and the CSV reset.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 119 CONFIDENTIAL Ordering Information Part number On-chip Flash memory On-chip MB9AF154MBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte Plastic LQFP 80-pin (0.5 mm pitch), (FPT-80P-M37) Tray MB9AF155MBPMC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte MB9AF156MBPMC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte MB9AF154MBBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte Plastic PFBGA 96-pin (0.5 mm pitch), (BGA-96P-M07) MB9AF155MBBGL-GE1 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte MB9AF156MBBGL-GE1 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte MB9AF154NBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte Plastic LQFP 100-pin (0.5 mm pitch), (FPT-100P-M23) MB9AF155NBPMC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte MB9AF156NBPMC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte MB9AF154NBBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte Plastic PFBGA 112-pin (0.8 mm pitch), (BGA-112P-M04) MB9AF155NBBGL-GE1 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte MB9AF156NBBGL-GE1 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte MB9AF154RBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte Plastic LQFP 120-pin (0.5 mm pitch), (FPT-120P-M37) MB9AF155RBPMC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte MB9AF156RBPMC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte
120 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Package Dimensions 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 mm × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.88 g Code (Reference) P-LFQFP120-16 × 16-0.50 120-pin plastic LQFP (FPT-120P-M37) (FPT-120P-M37) C 2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1 1 30 91 60 120 (.009± .002) M0.08(.003) ( ) 0.08(.003) "A" INDEX .059–.004 +.008 –0.10 +0.20 1.50 (Mounting height) 0˚~8˚ (.024± .006) 0.60± 0.15 0.25(.010) 0.10± 0.05 (.004± .002) Details of "A" part (Stand off) LEAD No. –0.03 +0.05 0.145 –.001 +.002 .006 Dimensions in mm (inches). Note: The values in parentheses are reference values Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 121 CONFIDENTIAL 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g 100-pin plastic LQFP (FPT-100P-M23) (FPT-100P-M23) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 12 5 100 0.145±0.055 (.006±.002) 0.08(.003) "A" INDEX 0°~8° 0.50±0.20 0.10±0.10 (Stand off) +.008 +0.20 (Mounting height) -0.101.50 .059 -.004( ) Dimensions in mm (inches). Note:The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part (.004±.004) (.009±.002) (.020±.008) (.024±.006)
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80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 80-pin plastic LQFP (FPT-80P-M37) (FPT-80P-M37) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 12 0 60 41 INDEX (.009± .002) M0.08(.003) 0.145± 0.055 (.006± .002) 0.08(.003) "A" (Stand off) Details of "A" part (.004± .002) 0.10± 0.05 (.024± .006) 0.60± 0.15 (.020± .008) 0.25(.010) 0.50± 0.20 (Mounting height).059–.004 +.008 –0.10 +0.20 1.50 0~8° C Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 123 CONFIDENTIAL 112-ball plastic PFBGA Ball pitch 0.80 mm Package width × package length 10.00 × 10.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size Ф 0.45 mm Mounting height 1.45 mm Max. Weight 0.22 g 112-ball plastic PFBGA (BGA-112P-M04) (BGA-112P-M04) C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3 (.049±.008) 1.25±0.20 (Seated height) F INDEX (INDEX AREA) 10.00±0.10 (.394±.004) (112-Ф0.18±.004) 112-Ф0.45±010 0.35±0.10 (.014±.004) (Stand off) 0.10(.004) S B A GHJKLE D C B A 0.80(.031) REF REF 0.80(.031) Ф0.08(.003) B ASM 0.20(.008) S B S AS0.20(.008) Dimensions in mm (inches). Note: The values in parentheses are reference values.
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96-pin plastic FBGA Lead pitch 0.5 mm Package width × package length 6.00 mm × 6.00 mm Lead shape Ball Sealing method Plastic mold 1.30 mm MAXMounting height Weight 0.08 g 96-pin plastic FBGA (BGA-96P-M07) (BGA-96P-M07) HA BCDEFGJKL C 2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1 TYP 0.20(.008) BS 0.20(.008) AS 6.00±0.10 (.236±.004) (INDEX AREA) S 1.15±0.15 INDEX M S Aø0.05(.002) 0.50(.020) TYP A B 5.00(.197) REF 5.00(.197) REF (Seated height) (.010±.004) 0.25±0.10 (Stand off) (.020) (96-ø.012±.004) 96-ø0.30±0.10 B Dimensions in mm (inches). Note: The values in parentheses are reference values.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 125 CONFIDENTIAL Major Changes Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 - - Preliminary → Data Sheet 2 FEATURES On-chip Memories Corrected the description of "Flash memory". 8 PRODUCT LINEUP Function Corrected the value of channel number of the "Base Timer". 62 HANDLING DEVICES • Added the description of "Crystal oscillator circuit".
- Added the description of "Sub crystal oscillator". BLOCK DIAGRAM Corrected the figure.
- TIOA: input → input/output
- TIOB: output → input 66 MEMORY MAP Memory Map (1) Corrected the value of address of "SRAM0". 67 Memory Map (2) Added the footnote. 71, 72 PIN STATUS IN EACH CPU STA TE
- List of Pin Status
- Corrected the Return from Deep standby mode state of "Pin status type H".
- Corrected the functon group of "Pin status type I". 77, 78 ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating
- Revised the value of "TBD".
- Revised the typical value of "Power supply voltage (ICCH, ICCT, ICCR)".
- Added the "Flash Memory Write/Erase current (ICCFLASH)".
- Added the footnote. 4. AC Characteristics (2) Sub Clock Input Characteristics
- Added the description of Note of "Input frequency (FCL)".
- Added the footnote. (3) Built-in CR Oscillation Characteristics
- Built-in high-speed CR
- Reviced the condition.
- Corrected the value.
- Added the item of "Frequency stabilization time".
- Added the footnote. 85, 86 (7) External Bus Timing
- Separate Bus Access Asynchronous SRAM Mode
- Corrected the value.
- Deleted the "MWEX ↓ → Data output time".
- Added the "MCSX ↓ → Data output time".
- Corrected the figure.
- Separate Bus Access Synchronous SRAM Mode
- Corrected the "MCLK↑ → Data output time".
- Added the "MCLK↑ → Data hold time".
- Corrected the figure. 95, 97, 99, 101 (9) CSIO Timming Corrected the description of section title. UART Timming → CSIO Timming Corrected the description of "Note". UART is connected → Multi-function Serial is connected 106 (12) I2C Timing Added the footnote. 109 5. 12-bit A/D Converter • Revised the parameter.
- Revised the symbol.
- Corrected the value. 111 Definition of 12-bit A/D Converter Terms • Revised the parameter.
- Revised the symbol. 112 6. Low-V oltage Detection Characteristics (1) Low-V oltage Detection Reset
- Corrected "Conditions" and "Value" in the table.
- Added the Item.
- Added the footnote. 113 (2) Interrupt of Low-V oltage Detection Added the Item. Revision 1.1 - - Company name and layout design change Revision 2.0 - - Corrected the Series name. MB9A150R Series → MB9A150RA Series - - Corrected the Product name as follows. MB9AF156MA, MB9AF155MA, MB9AF154MA MB9AF156NA, MB9AF155NA, MB9AF154NA MB9AF156RA, MB9AF155RA, MB9AF154RA 2 FEATURES
- External Bus Interface Added the Item.
- Maximum area size : Up to 256 Mbytes 2 •Multi-function Serial Interface Corrected the description of "I2C" 4 •Multi-function Timer Corrected the channel count of "A/D activation compare" 8 PRODUCT LINEUP
- Function Added the footnote
126 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
Page Section Change Results 9 PACKAGES Delete the following packages.
- FPT-100P-M36
- FPT-80P-M40 - PIN ASSIGNMENT FPT-100P-M36 Delete the Item 12 FPT-80P-M37 Corrected the description of section title. FPT-80P-M37/M40 →FPT-80P-M37 15 – 30 LIST OF PIN FUNCTION
- List of numbers Delete column of terminal number "QFP-100" 31 - 52 •List of pin functions Delete column of terminal number "QFP-100" 65 MEMORY MAP
- Memory Map (1) Corrected the address "External Device Area" 75 ELECTRICAL CHARACTERISTICS 2.Recommended Operating Conditions Add the footnote 76, 77 3.DC Characteristics (1)Current rating
- Corrected the Condition
- Delete the minmun value
- Corrected the remarks
- Add the footnote 101 (9)CSIO Timing
- Synchronous serial (SPI=1, SCINV=1) Corrected the figure of "MS bit=1" 101 (9) CSIO Timing
- External clock(EXT=1):asyntironous only Corrected the figure 102 (10)External Input Timing Add the terminal as follows
- FRCKx
- ICxx
- DTTIxX 105 (12)I2C Timing Corrected the description as follows.
- Typical mode → Standard-mode
- High-speed mode → Fast-mode 108 5.12-bit A/D Converter
- Electrical Characteristics for the A/D Converter
- Corrected the terminal name AN00 to AN23 → ANxx
- Corrected the minmum value of "Sampling time"
- Corrected the max and min value of "State transition time to oprerationpermission"
- Corrected the footnote 114 ORDERING INFORMA TON Corrected the "Part number" Revision 3.0 - - Corrected the Series name. MB9A150RA Series → MB9A150RB Series - - Corrected the Product name as follows. MB9AF156MB, MB9AF155MB, MB9AF154MB MB9AF156NB, MB9AF155NB, MB9AF154NB MB9AF156RB, MB9AF155RB, MB9AF154RB 66 Memory Map
- Memory map(2) Added the summary of Flash memory sector 76 - 78 Electrical Characteristics 3. DC Characteristics (1) Current rating
- Changed the table format
- Added Main TIMER mode current
- Moved A/D Converter Current Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL
- Added the figure of Main PLL connection Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing
- Added Time until releasing Power-on reset
- Changed the figure of timing 95 - 102 Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing
- Modified from UART Timing to CSIO/UART Timing
- Changed from Internal shift clock operation to Master mode
- Changed from External shift clock operation to Slave mode 109 Electrical Characteristics 5. 12bit A/D Converter
- Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
- Added the value of conversion time at A VCC < 2.7 V 115 - 118 Electrical Characteristics 8. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode 119 Ordering Information Changed notation of part number 120 - 124 Package Dimensions Deleted FPT-100P-M36 and FPT-80P-M40
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 127 CONFIDENTIAL
128 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
April 28, 2015, MB9A150RB_DS706-00047-3v0-E 129 CONFIDENTIAL
130 MB9A150RB_DS706-00047-3v0-E, April 28, 2015
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