MB9A110A

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MB9A110A-DS706-00011-3v0-E, December 16, 2014 CONFIDENTIAL Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office.

32-bit ARM® Cortex®-M3 based Microcontroller MB9AF111LA/MA/NA, MB9AF112LA/MA/NA, MB9AF114LA/MA/NA, MB9AF115MA/NA, MB9AF116MA/NA Data Sheet (Full Production) Publication Number MB9A110A-DS706-00011 Revision 3.0 Issue Date December 16, 2014 CONFIDENTIAL This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specif ication corrections, or modifications to the valid combinations offered may occur.  DESCRIPTION The MB9A110A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9A110A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE1 product categories in " FM3 Family PERIPHERAL MANUAL ". Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

2 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 FEATURES  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 40MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory]  Up to 512 Kbyte  Read cycle: 0wait-cycle  Security function for code protection [SRAM] This Series contain a total of up to 32Kbyte on-chip SRAM. On-chip SRAM is composed of two independent SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 16 Kbytes  SRAM1: Up to 16 Kbytes  Multi-function Serial Interface (Max 8channels)  4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*  Various error detection functions available (parity errors, framing errors, and overrun errors) * : MB9AF111LA, F312LA and F314LA do not support Hardware Flow control [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [LIN]  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generation (can be changed 13-16bit length)  LIN break delimiter generation (can be changed 1-4bit length)  Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C] Standard-mode (Max 100kbps) / Fast-mode (Max 400Kbps) supported

December 16, 2014, MB9A110A-DS706-00011-3v0-E 3 CONFIDENTIAL  External Bus Interface*  Supports SRAM, NOR Flash device  Up to 8 chip selects  8/16-bit Data width  Up to 25-bit Address bit  Maximum area size : Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY function * : MB9AF111LA, F312LA and F314LA do not support External Bus Interface  DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32bit(4Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536  A/D Converter (Max 16channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 3units*  Conversion time: 1.0μs@5V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) * : MB9AF111LA, F112LA , F114LA built-in 2units  Base Timer (Max 8channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16/32-bit reload timer  16/32-bit PWC timer

4 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 Multi-function Timer (Max 2units) The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3ch/unit  Input capture × 4ch/unit  Output compare × 6ch/unit  A/D activation compare × 3ch/unit  Waveform generator × 3ch/unit  16-bit PPG timer × 3ch/unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead timer function  Input capture function  A/D converter activate function  DTIF (Motor emergency stop) interrupt function  Quadrature Position/Revolution Counter (QPRC) (Max 2units) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers  Dual Timer (32/16bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each timer channel.  Free-running  Periodic (=Reload)  One-shot  Watch Counter The Watch counter is used for wake up from Low-Power Consumption mode.  Interval timer: up to 64s(Max)@ Sub Clock : 32.768kHz  Watch dog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a, "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except STOP mode.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 5 CONFIDENTIAL  External Interrupt Controller Unit  Up to 16 external interrupt input pins.  Include one non-maskable interrupt (NMI) input pin.  General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 83 fast General Purpose I/O Ports @ 100pin Package  Some ports are 5V tolerant I/O (MB9AF115MA/NA, MB9AF116MA/NA only) Please see "PIN DESCRIPTION" to confirm the corresponding pins.  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock : 4MHz to 48MHz  Sub Clock : 32.768kHz  Built-in high-speed CR Clock : 4MHz  Built-in low-speed CR Clock : 100kHz  Main PLL Clock [Resets]  Reset requests from INITX pins  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detector reset  Clock supervisor reset  Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  External clock failure (clock stop) is detected, reset is asserted.  External frequency anomaly is detected, interrupt or reset is asserted.

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 Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage that has been set, Low-V oltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation  Low-Power Consumption Mode Three Low-Power Consumption modes supported.  SLEEP  TIMER  STOP  Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM).* *: MB9AF111LA/MA, F312LA/MA, F314LA/MA, F315MA and F316MA support only SWJ-DP.  Power Supply  VCC = 2.7V to 5.5V: Correspond to the wide range voltage.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 7 CONFIDENTIAL  PRODUCT LINEUP  Memory size Product name MB9AF111LA/MA/NA MB9AF112LA/MA/NA MB9AF114LA/MA/NA On-chip Flash memory 64Kbytes 128Kbytes 256Kbytes On-chip SRAM 16Kbytes 16Kbytes 32Kbytes Product name MB9AF115MA/NA MB9AF116MA/NA On-chip Flash memory 384Kbytes 512Kbytes On-chip SRAM 32Kbytes 32Kbytes  Function Product name MB9AF111LA MB9AF112LA MB9AF114LA MB9AF111MA MB9AF112MA MB9AF114MA MB9AF115MA MB9AF116MA MB9AF111NA MB9AF112NA MB9AF114NA MB9AF115NA MB9AF116NA Pin count 64 80 100 CPU Cortex-M3 Freq. 40MHz Power supply voltage range 2.7V to 5.5V DMAC 8ch. External Bus Interface - Addr:21-bit (Max) Data:8-bit CS:4 (Max) Support: SRAM, NOR Flash Addr:25-bit (Max) Data:8/16-bit CS:8 (Max) Support: SRAM, NOR Flash Multi-function Serial Interface (UART/CSIO/LIN/I2C) 8ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO Base Timer (PWC/ Reload timer/PWM/PPG) 8ch. (Max) MF- Timer A/D activation compare 3ch. 1 unit 2 units (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. QPRC 2ch. (Max) Dual Timer 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 8pins (Max)+ NMI × 1 11pins (Max)+ NMI × 1 16pins (Max)+ NMI × 1 I/O ports 51pins (Max) 66pins (Max) 83pins (Max) 12-bit A/D converter 9ch. (2 units) 12ch. (3 units) 16ch. (3 units) CSV (Clock Super Visor) Yes LVD (Low-V oltage Detector) 2ch. Built-in High-speed 4MHz

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Debug Function SWJ-DP SWJ-DP/ETM Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for accuracy of built-in CR.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 9 CONFIDENTIAL  PACKAGES Product name Package MB9AF111LA MB9AF112LA MB9AF114LA MB9AF111MA MB9AF112MA MB9AF114MA MB9AF115MA MB9AF116MA MB9AF111NA MB9AF112NA MB9AF114NA MB9AF115NA MB9AF116NA LQFP:FPT-64P-M38 (0.5mm pitch)  - - LQFP:FPT-64P-M39 (0.65mm pitch)  - - QFN:LCC-64P-M24 (0.5mm pitch)  - - LQFP:FPT-80P-M37 (0.5mm pitch) -  - LQFP:FPT-100P-M23 (0.5mm pitch) - -  QFP:FPT-100P-M06 (0.65mm pitch) - -  BGA:BGA-112P-M04 (0.8mm pitch) - - *  : Supported * : MB9AF115NA, MB9AF116NA are planning Note: Refer to "PACKAGE DIMENSIONS" for detailed information on each package.

10 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 PIN ASSIGNMENT  FPT-100P-M23 (TOP VIEW) VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 100 VCC 1 75 VSS P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 2 74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 3 73 P21/SIN0_0/INT06_1/BIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 4 72 P22/SOT0_0/TIOB7_1/ZIN1_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 5 71 P23/SCK0_0/TIOA7_1/RTO00_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 6 70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 7 69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1 P56/INT08_2/DTTI1X_0/MADATA06_1 8 68 P1D/AN13/CTS4_1/IC03_1/MAD21_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 9 67 P1C/AN12/SCK4_1/IC02_1/MAD20_1 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 66 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 64 P19/AN09/SCK2_2/MAD17_1 P34/FRCK0_0/TIOB4_1/MADATA11_1 13 63 P18/AN08/SOT2_2/MAD16_1 P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 14 62 AVSS P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 15 61 AVRH P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 16 60 AVCC P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/DTTI0X_0/ADTG_2 18 58 P16/AN06/SCK0_1/MAD14_1 P3A/RTO00_0/TIOA0_1 19 57 P15/AN05/SOT0_1/IC03_2/MAD13_1 P3B/RTO01_0/TIOA1_1 20 56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3C/RTO02_0/TIOA2_1 21 55 P13/AN03/SCK1_1/IC01_2/MAD11_1 P3D/RTO03_0/TIOA3_1 22 54 P12/AN02/SOT1_1/IC00_2/MAD10_1 P3E/RTO04_0/TIOA4_1 23 53 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 P3F/RTO05_0/TIOA5_1 24 52 P10/AN00 VSS 25 51 VCC VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1 P43/TIOA3_0/RTO13_1/ADTG_7 P44/TIOA4_0/RTO14_1/MAD00_1 P45/TIOA5_0/RTO15_1/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 11 CONFIDENTIAL  FPT-100P-M06 (TOP VIEW) P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 VCC VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC VSS P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P21/SIN0_0/INT06_1/BIN1_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 81 50 P22/SOT0_0/TIOB7_1/ZIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 82 49 P23/SCK0_0/TIOA7_1/RTO00_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 83 48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 84 47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 85 46 P1D/AN13/CTS4_1/IC03_1/MAD21_1 P56/INT08_2/DTTI1X_0/MADATA06_1 86 45 P1C/AN12/SCK4_1/IC02_1/MAD20_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 87 44 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88 43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89 42 P19/AN09/SCK2_2/MAD17_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90 41 P18/AN08/SOT2_2/MAD16_1 P34/FRCK0_0/TIOB4_1/MADATA11_1 91 40 AVSS P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 92 39 AVRH P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 93 38 AVCC P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 94 37 P17/AN07/SIN2_2/INT04_1/MAD15_1 P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 95 36 P16/AN06/SCK0_1/MAD14_1 P39/DTTI0X_0/ADTG_2 96 35 P15/AN05/SOT0_1/IC03_2/MAD13_1 P3A/RTO00_0/TIOA0_1 97 34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3B/RTO01_0/TIOA1_1 98 33 P13/AN03/SCK1_1/IC01_2/MAD11_1 P3C/RTO02_0/TIOA2_1 99 32 P12/AN02/SOT1_1/IC00_2/MAD10_1 P3D/RTO03_0/TIOA3_1 100 31 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 P3E/RTO04_0/TIOA4_1 P3F/RTO05_0/TIOA5_1 VSS VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1 P43/TIOA3_0/RTO13_1/ADTG_7 P44/TIOA4_0/RTO14_1/MAD00_1 P45/TIOA5_0/RTO15_1/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P10/AN00 QFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

12 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 FPT-80P-M37 (TOP VIEW) VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P07/ADTG_0/MCLKOUT_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 1 60 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 2 59 P21/SIN0_0/INT06_1/BIN1_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 3 58 P22/SOT0_0/TIOB7_1/ZIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 4 57 P23/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 5 56 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 6 55 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 7 54 P19/AN09/SCK2_2/MAD17_1 P56/INT08_2/DTTI1X_0/MADATA06_1 8 53 P18/AN08/SOT2_2/MAD16_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 9 52 AVSS P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 51 AVRH P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 50 AVCC P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 49 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/DTTI0X_0/ADTG_2 13 48 P16/AN06/SCK0_1/MAD14_1 P3A/RTO00_0/TIOA0_1 14 47 P15/AN05/SOT0_1/IC03_2/MAD13_1 P3B/RTO01_0/TIOA1_1 15 46 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3C/RTO02_0/TIOA2_1 16 45 P13/AN03/SCK1_1/IC01_2/MAD11_1 P3D/RTO03_0/TIOA3_1 17 44 P12/AN02/SOT1_1/IC00_2/MAD10_1 P3E/RTO04_0/TIOA4_1 18 43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 P3F/RTO05_0/TIOA5_1 19 42 P10/AN00 VSS 20 41 VCC P44/TIOA4_0/MAD00_1 P45/TIOA5_0/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 13 CONFIDENTIAL  FPT-64P-M38/M39 (TOP VIEW) VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/SIN0_0/INT06_1 P50/INT00_0/AIN0_2/SIN3_1 2 47 P22/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 46 P23/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1 10 39 P15/AN05/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1 12 37 P13/AN03/SCK1_1/IC01_2 P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/AIN0_1 P4A/TIOB1_0/BIN0_1 P4B/TIOB2_0/ZIN0_1 P4C/TIOB3_0/SCK7_1/AIN1_2 P4D/TIOB4_0/SOT7_1/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

14 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 BGA-112P-M04 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC P0E B VCC VSS P52 P61 P0F P0C P08 TDO/ SWO P0B P07 TMS/ SWDIO TRSTX VCC VSS TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 P05 VSS P20 P21 D P53 P54 P55 VSS AN15 E P30 P31 P32 P33 Index P22 AN14 AN12 P56 P63 P0A VSS P06 P23 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C G P37 P38 P3A P3D AN08 AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E P43 P49 P4D AN02 VSS AN01 P4A MD0 X0 X1 VSS MD1 VSS VCC L VSS C X0A VSS P41 P45 PFBGA - 112 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 15 CONFIDENTIAL  LCC-64P-M24 (TOP VIEW) VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/SIN0_0/INT06_1 P50/INT00_0/AIN0_2/SIN3_1 2 47 P22/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 46 P23/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1 10 39 P15/AN05/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1 12 37 P13/AN03/SCK1_1/IC01_2 P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/AIN0_1 P4A/TIOB1_0/BIN0_1 P4B/TIOB2_0/ZIN0_1 P4C/TIOB3_0/SCK7_1/AIN1_2 P4D/TIOB4_0/SOT7_1/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

16 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 LIST OF PIN FUNCTIONS  List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 1 79 B1 1 1 VCC - 2 80 C1 2 P50 E H INT00_0 AIN0_2 SIN3_1 RTO10_0 (PPG10_0) MADA TA00_1 3 81 C2 3 P51 E H INT01_0 BIN0_2 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) MADA TA01_1 4 82 B3 4 P52 E H INT02_0 ZIN0_2 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) MADA TA02_1 5 83 D1 5 - P53 E H SIN6_0 TIOA1_2 INT07_2 RTO13_0 (PPG12_0) MADA TA03_1 6 84 D2 6 - P54 E I SOT6_0 (SDA6_0) TIOB1_2 RTO14_0 (PPG14_0) MADA TA04_1

December 16, 2014, MB9A110A-DS706-00011-3v0-E 17 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 7 85 D3 7 - P55 E I SCK6_0 (SCL6_0) ADTG_1 RTO15_0 (PPG14_0) MADA TA05_1 8 86 D5 8 - P56 E H INT08_2 DTTI1X_0 MADA TA06_1 9 87 E1 9 5 P30 E H AIN0_0 TIOB0_1 INT03_2 - MADA TA07_1 10 88 E2 10 6 P31 E H BIN0_0 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 - MADA TA08_1 11 89 E3 11 7 P32 E H ZIN0_0 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 - MADA TA09_1 12 90 E4 12 8 P33 E H INT04_0 TIOB3_1 SIN6_1 ADTG_6 - MADA TA10_1 13 91 F1 - - P34 E I FRCK0_0 TIOB4_1 MADA TA11_1

18 MB9A110A-DS706-00011-3v0-E, December 16, 2014

type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 14 92 F2 - - P35 E H IC03_0 TIOB5_1 INT08_1 MADA TA12_1 15 93 F3 - - P36 E H IC02_0 SIN5_2 INT09_1 MADA TA13_1 16 94 G1 - - P37 E H IC01_0 SOT5_2 (SDA5_2) INT10_1 MADA TA14_1 17 95 G2 - - P38 E H IC00_0 SCK5_2 (SCL5_2) INT11_1 MADA TA15_1 18 96 F4 13 9 P39 E I DTTI0X_0 ADTG_2 19 97 G3 14 10 P3A G I RTO00_0 (PPG00_0) TIOA0_1 20 98 H1 15 11 P3B G I RTO01_0 (PPG00_0) TIOA1_1 21 99 H2 16 12 P3C G I RTO02_0 (PPG02_0) TIOA2_1 22 100 G4 17 13 P3D G I RTO03_0 (PPG02_0) TIOA3_1 - - B2 - - VSS -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 19 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 23 1 H3 18 14 P3E G I RTO04_0 (PPG04_0) TIOA4_1 24 2 J2 19 15 P3F G I RTO05_0 (PPG04_0) TIOA5_1 25 3 L1 20 16 VSS - 26 4 J1 - - VCC - 27 5 J4 - - P40 G H TIOA0_0 RTO10_1 (PPG10_1) INT12_1 28 6 L5 - - P41 G H TIOA1_0 RTO11_1 (PPG10_1) INT13_1 29 7 K5 - - P42 G I TIOA2_0 RTO12_1 (PPG12_1) 30 8 J5 - - P43 G I TIOA3_0 RTO13_1 (PPG12_1) ADTG_7 31 9 H5 P44 G I TIOA4_0 MAD00_1 - RTO14_1 (PPG14_1) 32 10 L6 P45 G I TIOA5_0 MAD01_1 - RTO15_1 (PPG14_1) - - K2 - - VSS - - - J3 - - VSS - - - H4 - - VSS -

20 MB9A110A-DS706-00011-3v0-E, December 16, 2014

type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 33 11 L2 23 17 C - 34 12 L4 24 - VSS - 35 13 K1 25 18 VCC - 36 14 L3 26 19 P46 D M X0A 37 15 K3 27 20 P47 D N X1A 38 16 K4 28 21 INITX B C 39 17 K6 29 - P48 E H DTTI1X_1 INT14_1 SIN3_2 MAD02_1 40 18 J6 30 P49 E I TIOB0_0 AIN0_1 IC10_1 SOT3_2 (SDA3_2) MAD03_1 41 19 L7 31 P4A E I TIOB1_0 BIN0_1 IC11_1 SCK3_2 (SCL3_2) MAD04_1 42 20 K7 32 P4B E I TIOB2_0 ZIN0_1 - IC12_1 MAD05_1 43 21 H6 33 P4C E / I* I TIOB3_0 SCK7_1 (SCL7_1) AIN1_2 - IC13_1 MAD06_1

December 16, 2014, MB9A110A-DS706-00011-3v0-E 21 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 44 22 J7 34 P4D E / I* I TIOB4_0 SOT7_1 (SDA7_1) BIN1_2 - FRCK1_1 MAD07_1 45 23 K8 35 27 P4E E / I* I TIOB5_0 INT06_2 SIN7_1 ZIN1_2 - MAD08_1 46 24 K9 36 28 MD1 C P PE0 47 25 L8 37 29 MD0 J D 48 26 L9 38 30 X0 A A PE2 49 27 L10 39 31 X1 A B PE3 50 28 L11 40 32 VSS - 51 29 K11 41 33 VCC - 52 30 J11 42 34 P10 F K AN00 53 31 J10 43 35 P11 F L AN01 SIN1_1 INT02_1 FRCK0_2 - MAD09_1 54 32 J8 44 36 P12 F K AN02 SOT1_1 (SDA1_1) IC00_2 - MAD10_1 - - K10 - - VSS - - - J9 - - VSS -

22 MB9A110A-DS706-00011-3v0-E, December 16, 2014

type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 55 33 H10 45 37 P13 F K AN03 SCK1_1 (SCL1_1) IC01_2 - MAD11_1 56 34 H9 46 P14 F L AN04 INT03_1 IC02_2 - SIN0_1 MAD12_1 57 35 H7 47 P15 F K AN05 IC03_2 SOT0_1 (SDA0_1) MAD13_1 58 36 G10 48 - P16 F K AN06 SCK0_1 (SCL0_1) MAD14_1 59 37 G9 49 40 P17 F L AN07 SIN2_2 INT04_1 - MAD15_1 60 38 H11 50 41 A VCC - 61 39 F11 51 42 A VRH - 62 40 G11 52 43 A VSS - 63 41 G8 53 44 P18 F K AN08 SOT2_2 (SDA2_2) - MAD16_1 64 42 F10 54 P19 F K AN09 SCK2_2 (SCL2_2) - MAD17_1 - - H8 - - VSS -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 23 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 65 43 F9 55 - P1A F L AN10 SIN4_1 INT05_1 IC00_1 MAD18_1 66 44 E11 56 - P1B F K AN11 SOT4_1 (SDA4_1) IC01_1 MAD19_1 67 45 E10 - - P1C F K AN12 SCK4_1 (SCL4_1) IC02_1 MAD20_1 68 46 F8 - - P1D F K AN13 CTS4_1 IC03_1 MAD21_1 69 47 E9 - - P1E F K AN14 RTS4_1 DTTI0X_1 MAD22_1 70 48 D11 - - P1F F K AN15 ADTG_5 FRCK0_1 MAD23_1 - - B10 - - VSS - - - C9 - - VSS -

24 MB9A110A-DS706-00011-3v0-E, December 16, 2014

type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 71 49 D10 57 46 P23 E I SCK0_0 (SCL0_0) TIOA7_1 - - RTO00_1 (PPG00_1) 72 50 E8 58 47 P22 E I SOT0_0 (SDA0_0) TIOB7_1 - ZIN1_1 73 51 C11 59 48 P21 E H SIN0_0 INT06_1 - BIN1_1 74 52 C10 60 - P20 E H INT05_0 CROUT_0 AIN1_1 MAD24_1 75 53 A11 - - VSS - 76 54 A10 - - VCC - 77 55 A9 61 49 P00 E E TRSTX - MCSX7_1 78 56 B9 62 50 P01 E E TCK SWCLK 79 57 B11 63 51 P02 E E TDI - MCSX6_1 80 58 A8 64 52 P03 E E TMS SWDIO 81 59 B8 65 53 P04 E E TDO SWO 82 60 C8 - - P05 E F TRACED0 TIOA5_2 SIN4_2 INT00_1 MCSX5_1 - - D8 - - VSS -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 25 CONFIDENTIAL Pin No Pin name I/O circuit type Pin state type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 83 61 D9 - - P06 E F TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 MCSX4_1 84 62 A7 P07 E G ADTG_0 MCLKOUT_1 TRACED2 SCK4_2 (SCL4_2) 85 63 B7 - - P08 E G TRACED3 TIOA0_2 CTS4_2 MCSX3_1 86 64 C7 - - P09 E G TRACECLK TIOB0_2 RTS4_2 MCSX2_1 87 65 D7 67 P0A E / I* H SIN4_0 INT00_2 - FRCK1_0 MCSX1_1 88 66 A6 68 P0B E / I* I SOT4_0 (SDA4_0) TIOB6_1 - IC10_0 MCSX0_1 89 67 B6 69 P0C E / I* I SCK4_0 (SCL4_0) TIOA6_1 - IC11_0 MALE_1 - - D4 - - VSS - - - C3 - - VSS -

26 MB9A110A-DS706-00011-3v0-E, December 16, 2014

type LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 90 68 C6 70 - P0D E I RTS4_0 TIOA3_2 IC12_0 MDQM0_1 91 69 A5 71 - P0E E I CTS4_0 TIOB3_2 IC13_0 MDQM1_1 92 70 B5 72 57 P0F E J NMIX CROUT_1 93 71 D6 73 - P63 E H INT03_0 MWEX_1 94 72 C5 74 58 P62 E I SCK5_0 (SCL5_0) ADTG_3 - MOEX_1 95 73 B4 75 59 P61 E I SOT5_0 (SDA5_0) TIOB2_2 96 74 C4 76 60 P60 E / I* H SIN5_0 TIOA2_2 INT15_1 - MRDY_1 97 75 A4 77 61 VCC - 98 76 A3 78 62 P80 H O 99 77 A2 79 63 P81 H O 100 78 A1 80 64 VSS - * : 5V tolerant I/O on MB9AF115MA/NA and MB9AF116MA/NA

December 16, 2014, MB9A110A-DS706-00011-3v0-E 27 CONFIDENTIAL  List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- ADC ADTG_0 A/D converter external trigger input pin 84 62 A7 66 - ADTG_1 7 85 D3 7 - ADTG_2 18 96 F4 13 9 ADTG_3 94 72 C5 74 58 ADTG_4 - - - - - ADTG_5 70 48 D11 - - ADTG_6 12 90 E4 12 8 ADTG_7 30 8 J5 - - ADTG_8 - - - - - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 52 30 J11 42 34 AN01 53 31 J10 43 35 AN02 54 32 J8 44 36 AN03 55 33 H10 45 37 AN04 56 34 H9 46 38 AN05 57 35 H7 47 39 AN06 58 36 G10 48 - AN07 59 37 G9 49 40 AN08 63 41 G8 53 44 AN09 64 42 F10 54 45 AN10 65 43 F9 55 - AN11 66 44 E11 56 - AN12 67 45 E10 - - AN13 68 46 F8 - - AN14 69 47 E9 - - AN15 70 48 D11 - - Base Timer TIOA0_0 Base timer ch.0 TIOA pin 27 5 J4 - - TIOA0_1 19 97 G3 14 10 TIOA0_2 85 63 B7 - - TIOB0_0 Base timer ch.0 TIOB pin 40 18 J6 30 22 TIOB0_1 9 87 E1 9 5 TIOB0_2 86 64 C7 - - Base Timer TIOA1_0 Base timer ch.1 TIOA pin 28 6 L5 - - TIOA1_1 20 98 H1 15 11 TIOA1_2 5 83 D1 5 - TIOB1_0 Base timer ch.1 TIOB pin 41 19 L7 31 23 TIOB1_1 10 88 E2 10 6 TIOB1_2 6 84 D2 6 -

28 MB9A110A-DS706-00011-3v0-E, December 16, 2014

TIOA2_0 Base timer ch.2 TIOA pin 29 7 K5 - - TIOA2_1 21 99 H2 16 12 TIOA2_2 96 74 C4 76 60 TIOB2_0 Base timer ch.2 TIOB pin 42 20 K7 32 24 TIOB2_1 11 89 E3 11 7 TIOB2_2 95 73 B4 75 59 Base Timer TIOA3_0 Base timer ch.3 TIOA pin 30 8 J5 - - TIOA3_1 22 100 G4 17 13 TIOA3_2 90 68 C6 70 - TIOB3_0 Base timer ch.3 TIOB pin 43 21 H6 33 25 TIOB3_1 12 90 E4 12 8 TIOB3_2 91 69 A5 71 - Base Timer TIOA4_0 Base timer ch.4 TIOA pin 31 9 H5 21 - TIOA4_1 23 1 H3 18 14 TIOA4_2 - - - - - TIOB4_0 Base timer ch.4 TIOB pin 44 22 J7 34 26 TIOB4_1 13 91 F1 - - TIOB4_2 - - - - - Base Timer TIOA5_0 Base timer ch.5 TIOA pin 32 10 L6 22 - TIOA5_1 24 2 J2 19 15 TIOA5_2 82 60 C8 - - TIOB5_0 Base timer ch.5 TIOB pin 45 23 K8 35 27 TIOB5_1 14 92 F2 - - TIOB5_2 83 61 D9 - - Base Timer TIOA6_1 Base timer ch.6 TIOA pin 89 67 B6 69 56 TIOB6_1 Base timer ch.6 TIOB pin 88 66 A6 68 55 Base Timer TIOA7_0 Base timer ch.7 TIOA pin - - - - - TIOA7_1 71 49 D10 57 46 TIOA7_2 - - - - - TIOB7_0 Base timer ch.7 TIOB pin - - - - - TIOB7_1 72 50 E8 58 47 TIOB7_2 - - - - -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 29 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- Debugger SWCLK Serial wire debug interface clock input 78 56 B9 62 50 SWDIO Serial wire debug interface data input / output 80 58 A8 64 52 SWO Serial wire viewer output 81 59 B8 65 53 TCK J-TAG test clock input 78 56 B9 62 50 TDI J-TAG test data input 79 57 B11 63 51 TDO J-TAG debug data output 81 59 B8 65 53 TMS J-TAG test mode state input/output 80 58 A8 64 52 TRACECLK Trace CLK output of ETM 86 64 C7 - - TRACED0 Trace data output of ETM 82 60 C8 - - TRACED1 83 61 D9 - - TRACED2 84 62 A7 - - TRACED3 85 63 B7 - - TRSTX J-TAG test reset input 77 55 A9 61 49 External Bus MAD00_1 External bus interface address bus 31 9 H5 21 - MAD01_1 32 10 L6 22 - MAD02_1 39 17 K6 29 - MAD03_1 40 18 J6 30 - MAD04_1 41 19 L7 31 - MAD05_1 42 20 K7 32 - MAD06_1 43 21 H6 33 - MAD07_1 44 22 J7 34 - MAD08_1 45 23 K8 35 - MAD09_1 53 31 J10 43 - MAD10_1 54 32 J8 44 - MAD11_1 55 33 H10 45 - MAD12_1 56 34 H9 46 - MAD13_1 57 35 H7 47 - MAD14_1 58 36 G10 48 - MAD15_1 59 37 G9 49 - MAD16_1 63 41 G8 53 - MAD17_1 64 42 F10 54 - MAD18_1 65 43 F9 55 - MAD19_1 66 44 E11 56 - MAD20_1 67 45 E10 - - MAD21_1 68 46 F8 - - MAD22_1 69 47 E9 - - MAD23_1 70 48 D11 - - MAD24_1 74 52 C10 60 -

30 MB9A110A-DS706-00011-3v0-E, December 16, 2014

MCSX0_1 External bus interface chip select output pin 88 66 A6 68 - MCSX1_1 87 65 D7 67 - MCSX2_1 86 64 C7 - - MCSX3_1 85 63 B7 - - MCSX4_1 83 61 D9 - - MCSX5_1 82 60 C8 - - MCSX6_1 79 57 B11 63 - MCSX7_1 77 55 A9 61 - MDQM0_1 External bus interface byte mask signal output 90 68 C6 70 - MDQM1_1 91 69 A5 71 - MOEX_1 External bus interface read enable signal for SRAM 94 72 C5 74 - MWEX_1 External bus interface write enable signal for SRAM 93 71 D6 73 - MADA TA00_1 External bus interface data bus 2 80 C1 2 - MADA TA01_1 3 81 C2 3 - MADA TA02_1 4 82 B3 4 - MADA TA03_1 5 83 D1 5 - MADA TA04_1 6 84 D2 6 - MADA TA05_1 7 85 D3 7 - MADA TA06_1 8 86 D5 8 - MADA TA07_1 9 87 E1 9 - MADA TA08_1 10 88 E2 10 - MADA TA09_1 11 89 E3 11 - MADA TA10_1 12 90 E4 12 - MADA TA11_1 13 91 F1 - - MADA TA12_1 14 92 F2 - - MADA TA13_1 15 93 F3 - - MADA TA14_1 16 94 G1 - - MADA TA15_1 17 95 G2 - - MALE_1 Address Latch enable signal for multiplex 89 67 B6 69 - MRDY_1 External RDY input signal 96 74 C4 76 - MCLKOUT_1 External bus clock output 84 62 A7 66 -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 31 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- External Interrupt INT00_0 External interrupt request 00 input pin 2 80 C1 2 2 INT00_1 82 60 C8 - - INT00_2 87 65 D7 67 54 INT01_0 External interrupt request 01 input pin 3 81 C2 3 3 INT01_1 83 61 D9 - - INT02_0 External interrupt request 02 input pin 4 82 B3 4 4 INT02_1 53 31 J10 43 35 INT03_0 External interrupt request 03 input pin 93 71 D6 73 - INT03_1 56 34 H9 46 38 INT03_2 9 87 E1 9 5 INT04_0 External interrupt request 04 input pin 12 90 E4 12 8 INT04_1 59 37 G9 49 40 INT04_2 10 88 E2 10 6 INT05_0 External interrupt request 05 input pin 74 52 C10 60 - INT05_1 65 43 F9 55 - INT05_2 11 89 E3 11 7 INT06_1 External interrupt request 06 input pin 73 51 C11 59 48 INT06_2 45 23 K8 35 27 INT07_2 External interrupt request 07 input pin 5 83 D1 5 - INT08_1 External interrupt request 08 input pin 14 92 F2 - - INT08_2 8 86 D5 8 - INT09_1 External interrupt request 09 input pin 15 93 F3 - - INT10_1 External interrupt request 10 input pin 16 94 G1 - - INT11_1 External interrupt request 11 input pin 17 95 G2 - - INT12_1 External interrupt request 12 input pin 27 5 J4 - - INT13_1 External interrupt request 13 input pin 28 6 L5 - - INT14_1 External interrupt request 14 input pin 39 17 K6 29 - INT15_1 External interrupt request 15 input pin 96 74 C4 76 60 NMIX Non-Maskable Interrupt input 92 70 B5 72 57

32 MB9A110A-DS706-00011-3v0-E, December 16, 2014

General-purpose I/O port 0 77 55 A9 61 49 P01 78 56 B9 62 50 P02 79 57 B11 63 51 P03 80 58 A8 64 52 P04 81 59 B8 65 53 P05 82 60 C8 - - P06 83 61 D9 - - P07 84 62 A7 66 - P08 85 63 B7 - - P09 86 64 C7 - - P0A 87 65 D7 67 54 P0B 88 66 A6 68 55 P0C 89 67 B6 69 56 P0D 90 68 C6 70 - P0E 91 69 A5 71 - P0F 92 70 B5 72 57 P10 General-purpose I/O port 1 52 30 J11 42 34 P11 53 31 J10 43 35 P12 54 32 J8 44 36 P13 55 33 H10 45 37 P14 56 34 H9 46 38 P15 57 35 H7 47 39 P16 58 36 G10 48 - P17 59 37 G9 49 40 P18 63 41 G8 53 44 P19 64 42 F10 54 45 P1A 65 43 F9 55 - P1B 66 44 E11 56 - P1C 67 45 E10 - - P1D 68 46 F8 - - P1E 69 47 E9 - - P1F 70 48 D11 - - P20 General-purpose I/O port 2 74 52 C10 60 - P21 73 51 C11 59 48 P22 72 50 E8 58 47 P23 71 49 D10 57 46

December 16, 2014, MB9A110A-DS706-00011-3v0-E 33 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- GPIO P30 General-purpose I/O port 3 9 87 E1 9 5 P31 10 88 E2 10 6 P32 11 89 E3 11 7 P33 12 90 E4 12 8 P34 13 91 F1 - - P35 14 92 F2 - - P36 15 93 F3 - - P37 16 94 G1 - - P38 17 95 G2 - - P39 18 96 F4 13 9 P3A 19 97 G3 14 10 P3B 20 98 H1 15 11 P3C 21 99 H2 16 12 P3D 22 100 G4 17 13 P3E 23 1 H3 18 14 P3F 24 2 J2 19 15 P40 General-purpose I/O port 4 27 5 J4 - - P41 28 6 L5 - - P42 29 7 K5 - - P43 30 8 J5 - - P44 31 9 H5 21 - P45 32 10 L6 22 - P46 36 14 L3 26 19 P47 37 15 K3 27 20 P48 39 17 K6 29 - P49 40 18 J6 30 22 P4A 41 19 L7 31 23 P4B 42 20 K7 32 24 P4C 43 21 H6 33 25 P4D 44 22 J7 34 26 P4E 45 23 K8 35 27 P50 General-purpose I/O port 5 2 80 C1 2 2 P51 3 81 C2 3 3 P52 4 82 B3 4 4 P53 5 83 D1 5 - P54 6 84 D2 6 - P55 7 85 D3 7 - P56 8 86 D5 8 - P60 General-purpose I/O port 6 96 74 C4 76 60 P61 95 73 B4 75 59 P62 94 72 C5 74 58 P63 93 71 D6 73 - P80 General-purpose I/O port 8 98 76 A3 78 62 P81 99 77 A2 79 63 PE0 General-purpose I/O port E 46 24 K9 36 28 PE2 48 26 L9 38 30 PE3 49 27 L10 39 31

34 MB9A110A-DS706-00011-3v0-E, December 16, 2014

SIN0_0 Multifunction serial interface ch.0 input pin 73 51 C11 59 48 SIN0_1 56 34 H9 46 - SOT0_0 (SDA0_0) Multifunction serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 72 50 E8 58 47 SOT0_1 (SDA0_1) 57 35 H7 47 - SCK0_0 (SCL0_0) Multifunction serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). 71 49 D10 57 46 SCK0_1 (SCL0_1) 58 36 G10 48 - Multi Function Serial SIN1_1 Multifunction serial interface ch.1 input pin 53 31 J10 43 35 SOT1_1 (SDA1_1) Multifunction serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 54 32 J8 44 36 SCK1_1 (SCL1_1) Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). 55 33 H10 45 37

December 16, 2014, MB9A110A-DS706-00011-3v0-E 35 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- Multi Function Serial SIN2_2 Multifunction serial interface ch.2 input pin 59 37 G9 49 40 SOT2_2 (SDA2_2) Multifunction serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 63 41 G8 53 44 SCK2_2 (SCL2_2) Multifunction serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). 64 42 F10 54 45 Multi Function Serial SIN3_1 Multifunction serial interface ch.3 input pin 2 80 C1 2 2 SIN3_2 39 17 K6 29 - SOT3_1 (SDA3_1) Multifunction serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 3 81 C2 3 3 SOT3_2 (SDA3_2) 40 18 J6 30 - SCK3_1 (SCL3_1) Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 82 B3 4 4 SCK3_2 (SCL3_2) 41 19 L7 31 -

36 MB9A110A-DS706-00011-3v0-E, December 16, 2014

SIN4_0 Multifunction serial interface ch.4 input pin 87 65 D7 67 54 SIN4_1 65 43 F9 55 - SIN4_2 82 60 C8 - - SOT4_0 (SDA4_0) Multifunction serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 88 66 A6 68 55 SOT4_1 (SDA4_1) 66 44 E11 56 - SOT4_2 (SDA4_2) 83 61 D9 - - SCK4_0 (SCL4_0) Multifunction serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). 89 67 B6 69 56 SCK4_1 (SCL4_1) 67 45 E10 - - SCK4_2 (SCL4_2) 84 62 A7 - - RTS4_0 Multifunction serial interface ch.4 RTS output pin 90 68 C6 70 - RTS4_1 69 47 E9 - - RTS4_2 86 64 C7 - - CTS4_0 Multifunction serial interface ch.4 CTS input pin 91 69 A5 71 - CTS4_1 68 46 F8 - - CTS4_2 85 63 B7 - - Multi Function Serial SIN5_0 Multifunction serial interface ch.5 input pin 96 74 C4 76 60 SIN5_2 15 93 F3 - - SOT5_0 (SDA5_0) Multifunction serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 95 73 B4 75 59 SOT5_2 (SDA5_2) 16 94 G1 - - SCK5_0 (SCL5_0) Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). 94 72 C5 74 58 SCK5_2 (SCL5_2) 17 95 G2 - -

December 16, 2014, MB9A110A-DS706-00011-3v0-E 37 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- Multi Function Serial SIN6_0 Multifunction serial interface ch.6 input pin 5 83 D1 5 - SIN6_1 12 90 E4 12 8 SOT6_0 (SDA6_0) Multifunction serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 6 84 D2 6 - SOT6_1 (SDA6_1) 11 89 E3 11 7 SCK6_0 (SCL6_0) Multifunction serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). 7 85 D3 7 - SCK6_1 (SCL6_1) 10 88 E2 10 6 Multi Function Serial SIN7_1 Multifunction serial interface ch.7 input pin 45 23 K8 35 27 SOT7_1 (SDA7_1) Multifunction serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 44 22 J7 34 26 SCK7_1 (SCL7_1) Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4). 43 21 H6 33 25

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DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of multi-function timer 0 18 96 F4 13 9 DTTI0X_1 69 47 E9 - - FRCK0_0 16-bit free-run timer external clock input pin 13 91 F1 - - FRCK0_1 70 48 D11 - - FRCK0_2 53 31 J10 43 35 IC00_0 16-bit input capture input pin of multi-function timer 0. ICxx describes channel number. 17 95 G2 - - IC00_1 65 43 F9 55 - IC00_2 54 32 J8 44 36 IC01_0 16 94 G1 - - IC01_1 66 44 E11 56 - IC01_2 55 33 H10 45 37 IC02_0 15 93 F3 - - IC02_1 67 45 E10 - - IC02_2 56 34 H9 46 38 IC03_0 14 92 F2 - - IC03_1 68 46 F8 - - IC03_2 57 35 H7 47 39 RTO00_0 (PPG00_0) Waveform generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG 0 output mode. 19 97 G3 14 10 RTO00_1 (PPG00_1) 71 49 D10 - - RTO01_0 (PPG00_0) Waveform generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG 0 output mode. 20 98 H1 15 11 RTO02_0 (PPG02_0) Waveform generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG 0 output mode. 21 99 H2 16 12 RTO03_0 (PPG02_0) Waveform generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG 0 output mode. 22 100 G4 17 13 RTO04_0 (PPG04_0) Waveform generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG 0 output mode. 23 1 H3 18 14 RTO05_0 (PPG04_0) Waveform generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG 0 output mode. 24 2 J2 19 15

December 16, 2014, MB9A110A-DS706-00011-3v0-E 39 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- Multi Function Timer DTTI1X_0 Input signal of waveform generator to control outputs RTO10 to RTO15 of multi-function timer 1 8 86 D5 8 - DTTI1X_1 39 17 K6 29 - FRCK1_0 16-bit free-run timer ch.1 external clock input pin 87 65 D7 67 - FRCK1_1 44 22 J7 34 - IC10_0 16-bit input capture input pin of multi-function timer 1. ICxx describes channel number. 88 66 A6 68 - IC10_1 40 18 J6 30 - IC11_0 89 67 B6 69 - IC11_1 41 19 L7 31 - IC12_0 90 68 C6 70 - IC12_1 42 20 K7 32 - IC13_0 91 69 A5 71 - IC13_1 43 21 H6 33 - RTO10_0 (PPG10_0) Waveform generator output of multi-function timer 1. This pin operates as PPG10 when it is used in PPG 1 output mode. 2 80 C1 2 - RTO10_1 (PPG10_1) 27 5 J4 - - RTO11_0 (PPG10_0) Waveform generator output of multi-function timer 1. This pin operates as PPG10 when it is used in PPG 1 output mode. 3 81 C2 3 - RTO11_1 (PPG10_1) 28 6 L5 - - RTO12_0 (PPG12_0) Waveform generator output of multi-function timer 1. This pin operates as PPG12 when it is used in PPG 1 output mode. 4 82 B3 4 - RTO12_1 (PPG12_1) 29 7 K5 - - RTO13_0 (PPG12_0) Waveform generator output of multi-function timer 1. This pin operates as PPG12 when it is used in PPG 1 output mode. 5 83 D1 5 - RTO13_1 (PPG12_1) 30 8 J5 - - RTO14_0 (PPG14_0) Waveform generator output of multi-function timer 1. This pin operates as PPG14 when it is used in PPG 1 output mode. 6 84 D2 6 - RTO14_1 (PPG14_1) 31 9 H5 21 - RTO15_0 (PPG14_0) Waveform generator output of multi-function timer 1. This pin operates as PPG14 when it is used in PPG 1 output mode. 7 85 D3 7 - RTO15_1 (PPG14_1) 32 10 L6 22 -

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AIN0_0 QPRC ch.0 AIN input pin 9 87 E1 9 5 AIN0_1 40 18 J6 30 22 AIN0_2 2 80 C1 2 2 BIN0_0 QPRC ch.0 BIN input pin 10 88 E2 10 6 BIN0_1 41 19 L7 31 23 BIN0_2 3 81 C2 3 3 ZIN0_0 QPRC ch.0 ZIN input pin 11 89 E3 11 7 ZIN0_1 42 20 K7 32 24 ZIN0_2 4 82 B3 4 4 Quadrature Position/ Revolution Counter AIN1_1 QPRC ch.1 AIN input pin 74 52 C10 60 - AIN1_2 43 21 H6 33 25 BIN1_1 QPRC ch.1 BIN input pin 73 51 C11 59 - BIN1_2 44 22 J7 34 26 ZIN1_1 QPRC ch.1 ZIN input pin 72 50 E8 58 - ZIN1_2 45 23 K8 35 27

December 16, 2014, MB9A110A-DS706-00011-3v0-E 41 CONFIDENTIAL Module Pin name Function Pin No LQFP- 100 QFP- 100 BGA- 112 LQFP- LQFP- QFN- RESET INITX External Reset Input. A reset is valid when INITX= "L" 38 16 K4 28 21 Mode MD0 Mode 0 pin. During normal operation, MD0= "L" must be input. During serial programming to flash memory, MD0= "H" must be input. 47 25 L8 37 29 MD1 Mode 1 pin. During serial programming to flash memory, MD1= "L" must be input. 46 24 K9 36 28 POWER VCC Power supply pin 1 79 B1 1 1 VCC Power supply pin 26 4 J1 - - VCC Power supply pin 35 13 K1 25 18 VCC Power supply pin 51 29 K11 41 33 VCC Power supply pin 76 54 A10 - - VCC Power supply pin 97 75 A4 77 61 GND VSS GND pin - - B2 - - VSS GND pin 25 3 L1 20 16 VSS GND pin - - K2 - - VSS GND pin - - J3 - - VSS GND pin - - H4 - - VSS GND pin 34 12 L4 24 - VSS GND pin 50 28 L11 40 32 VSS GND pin - - K10 - - VSS GND pin - - J9 - - VSS GND pin - - H8 - - VSS GND pin - - B10 - - VSS GND pin - - C9 - - VSS GND pin 75 53 A11 - - VSS GND pin - - D8 - - VSS GND pin - - D4 - - VSS GND pin - - C3 - - VSS GND pin 100 78 A1 80 64 CLOCK X0 Main clock (oscillation) input pin 48 26 L9 38 30 X0A Sub clock (oscillation) input pin 36 14 L3 26 19 X1 Main clock (oscillation) I/O pin 49 27 L10 39 31 X1A Sub clock (oscillation) I/O pin 37 15 K3 27 20 CROUT_0 Built-in high-speed CR-osc clock output port 74 52 C10 60 - CROUT_1 92 70 B5 72 57 Analog POWER A VCC A/D converter analog power supply pin 60 38 H11 50 41 A VRH A/D converter analog reference voltage input pin 61 39 F11 51 42 Analog GND A VSS A/D converter GND pin 62 40 G11 52 43 C pin C Power supply stabilization capacity pin 33 11 L2 23 17

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 I/O CIRCUIT TYPE Type Circuit Remarks A  It is possible to select the main oscillation / GPIO function When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA B  CMOS level hysteresis input  Pull-up resistor : Approximately 50kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Pull-up resistor Digital input Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

December 16, 2014, MB9A110A-DS706-00011-3v0-E 43 CONFIDENTIAL Type Circuit Remarks C N-ch  Open drain output  CMOS level hysteresis input D  It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

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E  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off  +B input is available F  CMOS level output  CMOS level hysteresis input  With input control  Analog input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off  +B input is available Standby mode control Digital output Pull-up resistor control Digital output Digital input P-ch P-ch N-ch Digital output Digital output Pull-up resistor control Input control Standby mode control Analog input Digital input P-ch P-ch N-ch R R

December 16, 2014, MB9A110A-DS706-00011-3v0-E 45 CONFIDENTIAL Type Circuit Remarks G  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -12mA, IOL = 12mA  +B input is available H  CMOS level output  CMOS level hysteresis input  With standby mode control  IOH = -20.5mA, IOL = 18.5mA Standby mode control Digital output Digital output Digital input N-ch Standby mode control Digital output Pull-up resistor control Digital output Digital input P-ch P-ch N-ch R R

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I P-ch N-ch  CMOS level output  CMOS level hysteresis input  5V tolerant  With standby mode control  IOH = -4mA, IOL = 4mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off J Mode Input CMOS level hysteresis input Digital input Standby mode control Digital output Digital output R

December 16, 2014, MB9A110A-DS706-00011-3v0-E 47 CONFIDENTIAL  HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semicondu ctor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-V oltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of op eration. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E

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Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or w here extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through -holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 49 CONFIDENTIAL Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a p ackage that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

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Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

December 16, 2014, MB9A110A-DS706-00011-3v0-E 51 CONFIDENTIAL  HANDLING DEVICES  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypas s capacitor between each Power supply pin and GND pin, between A VCC pin and A VSS pin near this device.  Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recom mended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board.  Using an external clock When using an external clock, the clock signal should be driven to the X0,X0A pin only and the X1,X1A pin should be kept open.  Handling when using Multi function serial pin as I2C pin If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.  Example of Using an External Clock Device X0(X0A) X1(X1A) Open

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 C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series.  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.  Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect A VCC = VCC and A VSS = VSS. Turning on : VCC → AVCC → A VRH Turning off : A VRH → AVCC → VCC  Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communicati on. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Device C VSS CS GND

December 16, 2014, MB9A110A-DS706-00011-3v0-E 53 CONFIDENTIAL  BLOCK DIAGRAM AHB-APB Bridge : APB1 (Max 40 MHz) Flash I/FCortex-M3 Core @40 MHz(Max) Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch Multi-Function Timer x 2 Multi-Function Serial I/F 8ch. (with FIFO ch.4 to 7) & HW flow control(ch.4)*2 16-bit Free-Run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 3ch. 16-bit PPG 3ch. Watch Counter Unit 0 GPIO CSV LVD External Interrupt Controller 16-pin + NMI Power-On Reset TPIU*1 ROM Table ETM*1 SRAM0 Kbyte SWJ-DP SRAM1 Kbyte I D Sys MB9AF111LA/MA/NA, F112LA/MA/NA, F114LA/MA/NA, F115MA/NA, F116MA/NA Base Timer 16-bit 8ch. / 32-bit 4ch. NVIC WatchDog Timer (Software) Security 12-bit A/D Converter x 3 Unit 1 Unit 2*2 TRSTX,TCK, TDI,TMS TRACED[3:0], TRACECLK AN[15:0] TIOA[7:0] TIOB[7:0] IC0[3:0] DTTI[1:0]X RTO0[5:0] FRCK[1:0] C TDO SCK[7:0] SIN[7:0] SOT[7:0] INT[15:0] NMIX P0[F:0], P1[F:0], Px[x:0] INITX MODE-Ctrl IRQ-Monitor PIN-Function-Ctrl MD[1:0] Regulator QPRC 2ch. AIN[1:0] BIN[1:0] ZIN[1:0] LVD Ctrl CRC Accelerator IC1[3:0] ADTGx RTS4 CTS4 External Bus I/F*2 MAD[24:0] MADATA[15:0] MCSX[7:0], MOEX,MWEX, MALE, MRDY, MCLKOUT, MDQM[1:0] RTO1[5:0] On-Chip Flash 64/128/256/384/512 Kbyte AHB-AHB Bridge AHB-APB Bridge: APB0(Max 40 MHz) Multi-layer AHB (Max 40 MHz) AHB-APB Bridge : APB2 (Max 40 MHz) X0A PLL CLK CR 100kHz Source Clock CROUT Main Osc Sub Osc CR 4MHz AVCC, AVSS,AVRH *1: For the MB9AF111LA/MA, F112LA/MA, MB9AF114LA/MA, MB9AF115MA and MB9AF116MA, ETM is not available. *2: For the MB9AF111LA, F112LA and MB9AF114LA, the External Bus Interface and 12-bit A/D Converter (unit 2) are not available. And the Multi-function Serial Interface does not support hardware flow control in these products.

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 MEMORY SIZE See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 55 CONFIDENTIAL  MEMORY MAP  Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0x4006_1000 0xE000_0000 0x4006_0000 DMAC 0x4005_0000 0x4003_F000 EXT-bus I/F 0x4003_B000 0x4003_A000 Watch Counter 0x7000_0000 0x4003_9000 CRC 0x4003_8000 MFS 0x6000_0000 0x4003_7000 0x4003_5000 LVD 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4000_0000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2400_0000 0x4002_E000 CR Trim 0x2200_0000 0x4002_8000 0x4002_7000 A/DC 0x4002_6000 QPRC 0x2008_0000 0x4002_5000 Base Timer 0x2000_0000 SRAM1 PPG 0x1FF8_0000 SRAM0 0x4002_2000 0x0010_2000 0x4002_1000 MFT Unit1 0x0010_0000 Security/CR Trim 0x4002_0000 MFT Unit0 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x0000_0000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved Reserved Cortex-M3 Private Peripherals Reserved See the next page "nMemory Map (2),(3)" for the memory size details. Reserved Reserved Flash Reserved Reserved Reserved Reserved Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved Reserved Reserved32Mbytes Bit band alias Reserved External Device Area

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 Memory Map (2) MB9AF116MA/NA MB9AF115MA/NA MB9AF114LA/MA/NA 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_4000 0x2000_4000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_C000 0x1FFF_C000 0x1FFF_C000 0x0010_2000 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0010_0000 Security 0x0008_0000 0x0006_0000 0x0004_0000 0x0000_0000 SA4-7(8KBx4) 0x0000_0000 SA4-7(8KBx4) 0x0000_0000 SA4-7(8KBx4) Flash 384Kbytes SA10-11(64KBx2) Reserved SRAM0 16Kbytes SRAM1 16Kbytes Reserved SRAM1 16Kbytes SRAM0 16Kbytes Flash 256Kbytes SA8-9(48KBx2) SA8-9(48KBx2) SA8-9(48KBx2) Reserved SRAM1 16Kbytes SRAM0 16Kbytes Reserved Reserved Reserved Reserved Reserved Reserved SA10-15(64KBx6) Flash 512Kbytes SA10-13(64KBx4) *: See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 57 CONFIDENTIAL  Memory Map (3) MB9AF112LA/MA/NA MB9AF111LA/MA/NA 0x2008_0000 0x2008_0000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x1FFF_E000 0x1FFF_E000 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0002_0000 0x0001_0000 0x0000_0000 SA4-7(8KBx4) 0x0000_0000 SA4-7(8KBx4) Reserved SRAM1 8Kbytes Reserved SRAM1 8Kbytes ReservedReserved Flash 128Kbytes SRAM0 8Kbytes SRAM0 8Kbytes Flash 64Kbytes Reserved SA8-9(48KBx2) SA8-9(16KBx2) Reserved * : See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.

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 Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000H 0x4000_0FFFH AHB Flash Memory I/F register 0x4000_1000H 0x4000_FFFFH Reserved 0x4001_0000H 0x4001_0FFFH APB0 Clock/Reset Control 0x4001_1000H 0x4001_1FFFH Hardware Watchdog timer 0x4001_2000H 0x4001_2FFFH Software Watchdog timer 0x4001_3000H 0x4001_4FFFH Reserved 0x4001_5000H 0x4001_5FFFH Dual-Timer 0x4001_6000H 0x4001_FFFFH Reserved 0x4002_0000H 0x4002_0FFFH APB1 Multi-function timer unit0 0x4002_1000H 0x4002_1FFFH Multi-function timer unit1 0x4002_2000H 0x4002_3FFFH Reserved 0x4002_4000H 0x4002_4FFFH PPG 0x4002_5000H 0x4002_5FFFH Base Timer 0x4002_6000H 0x4002_6FFFH Quadrature Position/Revolution Counter (QPRC) 0x4002_7000H 0x4002_7FFFH A/D Converter 0x4002_8000H 0x4002_DFFFH Reserved 0x4002_E000H 0x4002_EFFFH Built-in CR trimming 0x4002_F000H 0x4002_FFFFH Reserved 0x4003_0000H 0x4003_0FFFH APB2 External Interrupt 0x4003_1000H 0x4003_1FFFH Interrupt Source Check Register 0x4003_2000H 0x4003_2FFFH Reserved 0x4003_3000H 0x4003_3FFFH GPIO 0x4003_4000H 0x4003_4FFFH Reserved 0x4003_5000H 0x4003_5FFFH Low-V oltage Detector 0x4003_6000H 0x4003_6FFFH Reserved 0x4003_7000H 0x4003_7FFFH Reserved 0x4003_8000H 0x4003_8FFFH Multi-function serial Interface 0x4003_9000H 0x4003_9FFFH CRC 0x4003_A000H 0x4003_AFFFH Watch Counter 0x4003_B000H 0x4003_EFFFH Reserved 0x4003_F000H 0x4003_FFFFH External Bus interface 0x4004_0000H 0x4004_FFFFH AHB Reserved 0x4005_0000H 0x4005_FFFFH Reserved 0x4006_0000H 0x4006_0FFFH DMAC register 0x4006_1000H 0x4006_1FFFH Reserved 0x4006_2000H 0x4006_2FFFH Reserved 0x4006_3000H 0x4006_3FFFH Reserved 0x4006_4000H 0x41FF_FFFFH Reserved

December 16, 2014, MB9A110A-DS706-00011-3v0-E 59 CONFIDENTIAL  PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.

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 List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Main crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Main crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" C INITX input pin Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E JTAG selected Hi-Z Pull-up/ Input enabled Pull-up/ Input enabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z/ Internal input fixed at "0" F Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output External interrupt enabled selected Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0"

December 16, 2014, MB9A110A-DS706-00011-3v0-E 61 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 G Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" H External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" I GPIO selected, resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" J NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0"

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Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 K Analog input selected Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled GPIO selected, or resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" L External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Analog input selected Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled GPIO selected, or resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" M GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

December 16, 2014, MB9A110A-DS706-00011-3v0-E 63 CONFIDENTIAL Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX=0 INITX=1 INITX=1 INITX=1 - - - - SPL=0 SPL=1 N GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enabled Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" O GPIO pin Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" P Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/Input enabled *1 : Oscillation is stopped at sub timer mode, low-speed CR timer mode, and stop mode. *2 : Oscillation is stopped at stop mode.

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 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1, *2 VCC VSS - 0.5 VSS + 6.5 V Analog power supply voltage*1, *3 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage*1, *3 A VRH VSS - 0.5 VSS + 6.5 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5V) V VSS - 0.5 VSS + 6.5 V 5V tolerant Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5V) V Clamp maximum current ICLAMP -2 +2 mA *7 Clamp total maximum current Σ[ICLAMP] +20 mA *7 "L" level maximum output current*4 IOL - 10 mA 4mA type 20 mA 12mA type 39 mA P80, P81 "L" level average output current*5 IOLA V - 4 mA 4mA type 12 mA 12mA type 18.5 mA P80, P81 "L" level total maximum output current ∑IOL - 100 mA "L" level total average output current*6 ∑IOLA V - 50 mA "H" level maximum output current*4 IOH - - 10 mA 4mA type - 20 mA 12mA type - 39 mA P80, P81 "H" level average output current*5 IOHA V - - 4 mA 4mA type - 12 mA 12mA type - 20.5 mA P80, P81 "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current*6 ∑IOHA V - - 50 mA Power consumption PD - 300 mW Storage temperature TSTG - 55 + 150 °C *1 : These parameters are based on the condition that VSS = A VSS = 0.0V. *2 : Vcc must not drop below VSS - 0.5V . *3 : Be careful not to exceed VCC + 0.5 V , for example, when the power is turned on. *4 : The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6 : The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 65 CONFIDENTIAL *7 : ・ See "LIST OF PIN FUNCTIONS" and "I/O CIRCUIT TYPE" about +B input available pin. ・ Use within recommended operating conditions. ・ Use at DC voltage (current) the +B input. ・ The +B signal should always be applied a limiting resistance placed between the +B signal and the device. ・ The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ・ Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and A VCC pin, and this may affect other devices. ・ Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. ・ The following is a recommended circuit example (I/O equivalent circuit). <WARNING> Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. R +B input (0V to 16V) Protection Diode P-ch VCC VCC Limiting resistor N-ch AVCC Analog input Digital input Digital output

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Recommended Operating Conditions (Vss = A Vss = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage Vcc - 2.7*2 5.5 V Analog power supply voltage A Vcc - 2.7 5.5 V A Vcc = Vcc Analog reference voltage A VRH - 2.7 A Vcc V Smoothing capacitor CS - 1 10 μF For built-in regulator*1 Operating temperature FPT-100P-M23 FPT-80P-M37 FPT-64P-M38 FPT-64P-M39 LCC-64P-M24 BGA-112P-M04 Ta - - 40 + 105 °C FPT-100P-M06 Ta When mounted on four-layer PCB - 40 + 105 °C When mounted on double-sided single-layer PCB - 40 + 105 °C Icc ≤ 35mA - 40 + 85 °C Icc > 35mA *1 : See " · C Pin" in "HANDLING DEVICES" for the connection of the smoothing capacitor. *2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. U sers considering application outside the listed conditions are advised to contact their representatives beforehand.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 67 CONFIDENTIAL 3. DC Characteristics  Current rating (Vcc = AVcc = 2.7V to 5.5V , Vss = A Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 RUN mode current Icc VCC PLL RUN mode CPU : 40MHz, Peripheral : 40MHz, Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 32 41 mA *1 CPU : 40MHz, Peripheral : 40MHz, Flash 3Wait FRWTR.RWT = 00 FSYNDN.SD = 011 21 28 mA *1 High-speed CR RUN mode CPU/ Peripheral : 4MHz*2 Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 3.9 7.7 mA *1 Sub RUN mode CPU/ Peripheral : 32kHz Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 0.15 3.2 mA *1 Low-speed CR RUN mode CPU/ Peripheral : 100kHz Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 0.2 3.3 mA *1 SLEEP mode current Iccs PLL SLEEP mode Peripheral : 40MHz *5 10 15 mA *1 High-speed CR SLEEP mode Peripheral : 4MHz*2 1.2 4.4 mA *1 Sub SLEEP mode Peripheral : 32kHz *6 0.1 3.1 mA *1 Low-speed CR SLEEP mode Peripheral : 100kHz 0.1 3.1 mA *1 *1 : When all ports are fixed. *2 : When setting it to 4MHz by trimming. *3 : Ta=+25°C, VCC=5.5V *4 : Ta=+105°C, VCC=5.5V *5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

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(Vcc = A Vcc = 2.7V to 5.5V , Vss = A Vss = 0V , Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*2 TIMER mode current ICCT VCC Main TIMER mode Ta = + 25°C, When LVD is off 2.5 3 mA *1 Ta = + 105°C, When LVD is off - 6 mA *1 Sub TIMER mode Ta = + 25°C, When LVD is off 60 230 μA *1 Ta = + 105°C, When LVD is off - 3.1 mA *1 STOP mode current ICCH STOP mode Ta = + 25°C, When LVD is off 35 200 μA *1 Ta = + 105°C, When LVD is off - 3 mA *1 *1 : When all ports are fixed. *2 : VCC=5.5V *3 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Low-Voltage Detection Current (VCC = 2.7V to 5.5V , VSS = 0V , Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for interrupt Vcc = 5.5V 4 7 μA At not detect
Flash Memory Current (VCC = 2.7V to 5.5V , VSS = 0V , Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 11.4 13.1 mA
A/D Converter Current (VCC = AVCC = 2.7V to 5.5V , VSS = AVSS = A VRL = 0V , Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD A VCC At 1unit operation 0.57 0.72 mA At stop 0.06 20 μA Reference power supply current ICCA VRH A VRH At 1unit operation A VRH=5.5V 1.1 1.96 mA At stop 0.06 4 μA

December 16, 2014, MB9A110A-DS706-00011-3v0-E 69 CONFIDENTIAL  Pin Characteristics (Vcc = A Vcc = 2.7V to 5.5V , Vss = A Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max "H" level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0,1 - Vcc × 0.8 - Vcc + 0.3 V 5V tolerant I/O pin - Vcc × 0.8 - Vss + 5.5 V "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0,1 - Vss - 0.3 - Vcc × 0.2 V "H" level output voltage VOH 4mA type Vcc ≥ 4.5 V IOH = - 4mA Vcc - 0.5 - Vcc V Vcc < 4.5 V IOH = - 2mA 12mA type Vcc ≥ 4.5 V IOH = - 12mA Vcc - 0.5 - Vcc V Vcc < 4.5 V IOH = - 8mA P80, P81 Vcc ≥ 4.5 V IOH = - 20.5mA Vcc - 0.4 - Vcc V Vcc < 4.5 V IOH = - 13.0mA "L" level output voltage VOL 4mA type Vcc ≥ 4.5 V IOL = 4mA Vss - 0.4 V Vcc < 4.5 V IOL = 2mA 12mA type Vcc ≥ 4.5 V IOL = 12mA Vss - 0.4 V Vcc < 4.5 V IOL = 8mA P80, P81 Vcc ≥ 4.5 V IOL = 18.5mA Vss - 0.4 V Vcc < 4.5 V IOL = 10.5mA Input leak current IIL - - - 5 - + 5 μA Pull-up resistor value RPU Pull-up pin Vcc ≥ 4.5 V 25 50 100 kΩ Vcc < 4.5 V 30 80 200 Input capacitance CIN Other than Vcc, Vss, A Vcc, A Vss, A VRH - - 5 15 pF

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AC Characteristics (1) Main Clock Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency FCH Vcc ≥ 4.5V 4 48 MHz When crystal oscillator is connected Vcc < 4.5V 4 20 Vcc ≥ 4.5V 4 48 MHz When using external clock Vcc < 4.5V 4 20 Input clock cycle tCYLH Vcc ≥ 4.5V 20.83 250 ns When using external clock Vcc < 4.5V 50 250 Input clock pulse width - PWH/tCYLH PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF tCR - - 5 ns When using external clock Internal operating clock*1 frequency FCM - - - 40 MHz Master clock FCC - - - 40 MHz Base clock (HCLK/FCLK) FCP0 - - - 40 MHz APB0 bus clock*2 FCP1 - - - 40 MHz APB1 bus clock*2 FCP2 - - - 40 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 25 - ns APB0 bus clock*2 tCYCP1 - - 25 - ns APB1 bus clock*2 tCYCP2 - - 25 - ns APB2 bus clock*2 *1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". *2 : For about each APB bus which each peripheral is connected to, see "BLOCK DIAGRAM" in this data sheet.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 71 CONFIDENTIAL (2) Sub Clock Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency FCL X0A X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL PWL/tCYLL 45 - 55 % When using external clock (3) Built-in CR Oscillation Characteristics  Built-in high-speed CR (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRH Ta = + 25°C 3.96 4 4.04 MHz When trimming*1 Ta = 0°C to + 70°C 3.84 4 4.16 Ta = - 40°C to + 105°C 3.8 4 4.2 Ta = - 40°C to + 105°C 3 4 5 When not trimming Frequency stability time tCRWT - - - 90 μs *2 *1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2 : Frequency stable time is time to stable of the frequency of the High-speed CR. clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.  Built-in low-speed CR (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRL - 50 100 150 kHz X0A

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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time (LOCK UP time)*1 tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiple rate - 13 - 75 multiple PLL macro oscillation clock frequency fPLLO 200 - 300 MHz Main PLL clock frequency*2 FCLKPLL - - 40 MHz *1 : Time from when the PLL starts operating until the oscillation stabilizes. *2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". (4-2) Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock of the main PLL) (Vcc = 2.7V to 5.5V , Vss = 0V , Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time (LOCK UP time)*1 tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiple rate - 50 - 71 multiple PLL macro oscillation clock frequency fPLLO 190 - 300 MHz Main PLL clock frequency*2 FCLKPLL - - 40 MHz *1 : Time from when the PLL starts operating until the oscillation stabilizes. *2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection High-speed CR clock (CLKHC) Main clock (CLKMO)

December 16, 2014, MB9A110A-DS706-00011-3v0-E 73 CONFIDENTIAL (5) Reset Input Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns (6) Power-on Reset Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Max Power supply rising time Tr Vcc 0 - ms Power supply shut down time Toff 1 - ms Time until releasing Power-on reset Tprt 0.446 0.744 ms 0.2V VDH_minimum VCC_minimum Tprt Internal RST VCC CPU Operation start RST Active Release Tr 0.2V 0.2V Toff Glossary ・ VCC_minimum : Minimum VCC of recommended operating conditions ・ VDH_minimum : Minimum release voltage of Low-Voltage detection reset. See "8. Low-Voltage Detection Characteristics"

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(7) External Bus Timing  External bus clock output Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT Vcc ≥ 4.5 V - 40 MHz Vcc < 4.5 V - 32 MHz Minimum clock cycle time - Vcc ≥ 4.5 V 25 - ns Vcc < 4.5 V 31.25 - ns Note: The external bus clock output is a divided clock of HCLK. For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL" When external bus clock is not output, this characteristic does not give any effect on external bus operation.  External bus signal input/output Characteristics (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH MCLKOUT Input signal Output signal

December 16, 2014, MB9A110A-DS706-00011-3v0-E 75 CONFIDENTIAL  Separate Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX Vcc ≥ 4.5V MCLK×n-3 - ns Vcc < 4.5V MCSX ↓→ Address output delay time tCSL – AV MCSX[7:0] MAD[24:0] Vcc ≥ 4.5V -9 + 9 ns Vcc < 4.5V -12 + 12 MOEX ↑ → Address hold time tOEH - AX MOEX MAD[24:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓→ MOEX ↓ delay time tCSL - OEL MOEX MCSX[7:0] Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX MDQM[1:0] Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX MADA TA[15:0] Vcc ≥ 4.5V 20 - ns Vcc < 4.5V 38 - MOEX ↑ → Data hold time tDH - OE MOEX MADA TA[15:0] Vcc ≥ 4.5V 0 - ns Vcc < 4.5V MWEX Min pulse width tWEW MWEX Vcc ≥ 4.5V MCLK×n-3 - ns Vcc < 4.5V MWEX ↑ → Address output delay time tWEH - AX MWEX MAD[24:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX MCSX[7:0] Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL-WDQML MCSX MDQM[1:0] Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5V MCLK×n-12 MCLK×n+12 MCSX ↓ → Data output time tCSL - DV MCSX MADA TA[15:0] Vcc ≥ 4.5V MCLK-9 MCLK+9 ns Vcc < 4.5V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX MADA TA[15:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16).

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MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

December 16, 2014, MB9A110A-DS706-00011-3v0-E 77 CONFIDENTIAL  Separate Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Address delay time tAV MCLK MAD[24:0] Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 MCSX delay time tCSL MCLK MCSX[7:0] Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 tCSH Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 MOEX delay time tREL MCLK MOEX Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 tREH Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 Data set up → MCLK ↑ time tDS MCLK MADA TA[15:0] Vcc ≥ 4.5V 19 - ns Vcc < 4.5V 37 MCLK ↑→ Data hold time tDH MCLK MADA TA[15:0] Vcc ≥ 4.5V 0 - ns Vcc < 4.5V MWEX delay time tWEL MCLK MWEX Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 tWEH Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 MDQM[1:0] delay time tDQML MCLK MDQM[1:0] Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 tDQMH Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 MCLK ↑ → Data output time tODS MCLK, MADA TA[15:0] VCC ≥ 4.5V MCLK+1 MCLK+18 ns VCC < 4.5V MCLK+24 MCLK ↑ → Data output time tOD MCLK MADA TA[15:0] Vcc ≥ 4.5V 1 18 ns Vcc < 4.5V 1 24 Note: When the external load capacitance CL = 30pF. Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

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 Multiplexed Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed Address delay time tALE-CHMADV MALE MADA TA[15:0] Vcc ≥ 4.5V 0 10 ns Vcc < 4.5V 20 Multiplexed Address hold time tCHMADH Vcc ≥ 4.5V MCLK×n+0 MCLK×n+10 ns Vcc < 4.5V MCLK×n+0 MCLK×n+20 Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

December 16, 2014, MB9A110A-DS706-00011-3v0-E 79 CONFIDENTIAL  Multiplexed Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK ALE Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 ns tCHAH Vcc ≥ 4.5V 1 9 ns Vcc < 4.5V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK MADA TA[15:0] Vcc ≥ 4.5V 1 tOD ns Vcc < 4.5V MCLK ↑ → Multiplexed Data output time tCHMADX Vcc ≥ 4.5V 1 tOD ns Vcc < 4.5V Note: When the external load capacitance CL = 30pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

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 External Ready Input Timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MCLK ↑ MRDY input setup time tRDYI MCLK MRDY Vcc ≥ 4.5V 19 - ns Vcc < 4.5V 37  When RDY is input

· · Over 2cycles tRDYI  When RDY is released 2 cycles tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

December 16, 2014, MB9A110A-DS706-00011-3v0-E 81 CONFIDENTIAL (8) Base Timer Input Timing  Timer input timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH tTIWL TIOAn/TIOBn (when using as ECK,TIN) - 2tCYCP - ns tTIWH VIHS VIHS VILS VILS tTIWL  Trigger input timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns tTRGH VIHS VIHS VILS VILS tTRGL Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this data sheet. TGIN ECK TIN

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(9) CSIO/UART Timing  CSIO (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tcycp - 4tcycp - ns SCK ↓ → SOT delay time tSLOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tcycp - 10 - 2tcycp - 10 - ns Serial clock "H" pulse width tSHSL SCKx tcycp + 10 - tcycp + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx SINx 10 - 10 - ns SCK ↑→ SIN hold time tSHIXE SCKx SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 83 CONFIDENTIAL tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI Master mode tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE Slave mode SCK SOT SIN SCK SOT SIN

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 CSIO (SPI = 0, SCINV = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tcycp - 4tcycp - ns SCK ↑ → SOT delay time tSHOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tcycp - 10 - 2tcycp - 10 - ns Serial clock "H" pulse width tSHSL SCKx tcycp + 10 - tcycp + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 85 CONFIDENTIAL tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI Master mode tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE Slave mode SCK SOT SIN SCK SOT SIN

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 CSIO (SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tcycp - 4tcycp - ns SCK ↑→ SOT delay time tSHOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx SOTx 2tcycp - 30 - 2tcycp - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tcycp - 10 - 2tcycp - 10 - ns Serial clock "H" pulse width tSHSL SCKx tcycp + 10 - tcycp + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 87 CONFIDENTIAL tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI Master mode tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE Slave mode *: Changes when writing to TDR register SCK SOT SIN SCK SOT SIN

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 CSIO (SPI = 1, SCINV = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tcycp - 4tcycp - ns SCK ↓→ SOT delay time tSLOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx SINx 50 - 30 - ns SCK ↑ →SIN hold time tSHIXI SCKx SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx SOTx 2tcycp - 30 - 2tcycp - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tcycp - 10 - 2tcycp - 10 - ns Serial clock "H" pulse width tSHSL SCKx tcycp + 10 - tcycp + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 89 CONFIDENTIAL tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI Master mode tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE Slave mode  UART external clock input (EXT = 1) (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Min Max Unit Remarks Serial clock "L" pulse width tSLSH CL = 30pF tcycp + 10 - ns Serial clock "H" pulse width tSHSL tcycp + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSHSL VIL VIL VIL VIH VIH VIH tR tFtSLSH SCK SOT SIN SCK SOT SIN SCK

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(10) External input timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH tINL ADTG - 2tCYCP* - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP* - ns Wave form generator INTxx, NMIX Except Timer mode, Stop mode 2tCYCP + 100* - ns External interrupt NMI Timer mode, Stop mode 500 - ns * : tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "BLOCK DIAGRAM" in this data sheet.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 91 CONFIDENTIAL (11) Quadrature Position/Revolution Counter timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Min Max AIN pin "H" width tAHL - 2tCYCP * - ns AIN pin "L" width tALL - BIN pin "H" width tBHL - BIN pin "L" width tBLL - BIN rise time from AIN pin "H" level tAUBU PC_Mode2 or PC_Mode3 AIN fall time from BIN pin "H" level tBUAD PC_Mode2 or PC_Mode3 BIN fall time from AIN pin "L" level tADBD PC_Mode2 or PC_Mode3 AIN rise time from BIN pin "L" level tBDAU PC_Mode2 or PC_Mode3 AIN rise time from BIN pin "H" level tBUAU PC_Mode2 or PC_Mode3 BIN fall time from AIN pin "H" level tAUBD PC_Mode2 or PC_Mode3 AIN fall time from BIN pin "L" level tBDAD PC_Mode2 or PC_Mode3 BIN rise time from AIN pin "L" level tADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC = "0" ZIN pin "L" width tZLL QCR:CGSC = "0" AIN/BIN rise and fall time from determined ZIN level tZABE QCR:CGSC = "1" Determined ZIN level from AIN/BIN rise and fall time tABEZ QCR:CGSC = "1" * : tCYCP indicates the APB bus clock cycle time. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see " BLOCK DIAGRAM" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

92 MB9A110A-DS706-00011-3v0-E, December 16, 2014

December 16, 2014, MB9A110A-DS706-00011-3v0-E 93 CONFIDENTIAL (12) I2C timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓→ SCL ↓ tHDSTA 4.0 - 0.6 - μs SCLclock "L" width tLOW 4.7 - 1.3 - μs SCLclock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDA T 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDA T 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDA T must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal. *3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDA T ≥ 250 ns". *4 : tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

94 MB9A110A-DS706-00011-3v0-E, December 16, 2014

(13) ETM timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK TRACED[3:0] Vcc ≥ 4.5V 2 9 ns Vcc < 4.5V 2 15 TRACECLK frequency 1/tTRACE TRACECLK Vcc ≥ 4.5V - 40 MHz Vcc < 4.5V - 32 MHz TRACECLK Clock cycle time tTRACE Vcc ≥ 4.5V 25 - ns Vcc < 4.5V 31.25 - ns Note: When the external load capacitance CL = 30pF. HCLK TRACECLK TRACED[3:0]

December 16, 2014, MB9A110A-DS706-00011-3v0-E 95 CONFIDENTIAL (14) JTAG timing (Vcc = 2.7V to 5.5V , Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK TMS,TDI Vcc ≥ 4.5V 15 - ns Vcc < 4.5V TMS, TDI hold time tJTAGH TCK TMS,TDI Vcc ≥ 4.5V 15 - ns Vcc < 4.5V TDO delay time tJTAGD TCK TDO Vcc ≥ 4.5V - 25 ns Vcc < 4.5V - 45 Note: When the external load capacitance CL = 30pF. TCK TMS/TDI TDO

96 MB9A110A-DS706-00011-3v0-E, December 16, 2014

12-bit A/D Converter  Electrical Characteristics for the A/D Converter (Vcc = A Vcc = 2.7V to 5.5V , Vss = A Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 1.7 ± 4.5 LSB A VRH = 2.7V to 5.5V Differential Nonlinearity - - - ± 1.7 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 8 ± 15 mV Full-scale transition voltage VFST ANxx - A VRH±8 A VRH±15 mV Conversion time - - 1.0*1 - - μs A Vcc ≥ 4.5V 1.2*1 A Vcc < 4.5V Sampling time Ts - *2 - - ns A Vcc ≥ 4.5V *2 - - A Vcc < 4.5V Compare clock cycle*3 Tcck - 50 - 2000 ns State transition time to operation permission Tstt - - - 1.0 μs Analog input capacity CAIN - - - 12.9 pF Analog input resistor RAIN - - - 2 kΩ A Vcc ≥ 4.5V 3.8 A Vcc < 4.5V Interchannel disparity - - - - 4 LSB Analog port input current - ANxx - - 5 μA Analog input voltage - ANxx A VSS - A VRH V Reference voltage - A VRH 2.7 - A VCC V *1 : The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is the following. A Vcc ≥ 4.5V , HCLK=40MHz sampling time: 300ns, compare time: 700ns A Vcc < 4.5V , HCLK=40MHz sampling time: 500ns, compare time: 700ns Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this data sheet. *2 : A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1) *3 : The compare time (Tc) is the value of (Equation 2)

December 16, 2014, MB9A110A-DS706-00011-3v0-E 97 CONFIDENTIAL (Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9 Ts : Sampling time RAIN : input resistor of A/D = 2kΩ 4.5 ≤ AVCC ≤ 5.5 input resistor of A/D = 3.8kΩ 2.7 ≤ AVCC < 4.5 CAIN : input capacity of A/D = 12.9pF 2.7 ≤ AVCC ≤ 5.5 Rext : Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc : Compare time Tcck : Compare clock cycle Rext RAIN CAIN Analog signal source ANxx Analog input pin Comparator

98 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 Definition of 12-bit A/D Converter Terms  Resolution : Analog variation that is recognized by an A/D converter.  Integral Nonlinearity : Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST – VZT 4094 N : A/D converter digital output value. VZT : Voltage at which the digital output changes from 0x000 to 0x001. VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVSS AVRH AVSS AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

December 16, 2014, MB9A110A-DS706-00011-3v0-E 99 CONFIDENTIAL 6. Low-voltage detection characteristics  Low-voltage detection reset (Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.25 2.45 2.65 V When voltage drops Released voltage VDH - 2.30 2.50 2.70 V When voltage rises  Interrupt of low-voltage detection (Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 0000 2.58 2.8 3.02 V When voltage drops Released voltage VDH 2.67 2.9 3.13 V When voltage rises Detected voltage VDL SVHI = 0001 2.76 3.0 3.24 V When voltage drops Released voltage VDH 2.85 3.1 3.34 V When voltage rises Detected voltage VDL SVHI = 0010 2.94 3.2 3.45 V When voltage drops Released voltage VDH 3.04 3.3 3.56 V When voltage rises Detected voltage VDL SVHI = 0011 3.31 3.6 3.88 V When voltage drops Released voltage VDH 3.40 3.7 3.99 V When voltage rises Detected voltage VDL SVHI = 0100 3.40 3.7 3.99 V When voltage drops Released voltage VDH 3.50 3.8 4.10 V When voltage rises Detected voltage VDL SVHI = 0111 3.68 4.0 4.32 V When voltage drops Released voltage VDH 3.77 4.1 4.42 V When voltage rises Detected voltage VDL SVHI = 1000 3.77 4.1 4.42 V When voltage drops Released voltage VDH 3.86 4.2 4.53 V When voltage rises Detected voltage VDL SVHI = 1001 3.86 4.2 4.53 V When voltage drops Released voltage VDH 3.96 4.3 4.64 V When voltage rises LVD stabilization wait time TLVDW - - - 2240 × tcycp * μs * : tCYCP indicates the APB2 bus clock cycle time.

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Flash Memory Write/Erase Characteristics (1) Write / Erase time (Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 0.7 3.7 s Includes write time prior to internal erase Small Sector 0.3 1.1 Half word (16 bit) write time 12 384 μs Not including system-level overhead time. Chip erase time 64K/128K/256KByte 5.2 23.6 s Includes write time prior to internal erase 384K/512KByte 8 38.4 s * : The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. (2) Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* 100,000 5* * : At average + 85C

December 16, 2014, MB9A110A-DS706-00011-3v0-E 101 CONFIDENTIAL 8. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. ・ Return Count Time (VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Ticnt tCYCC ns High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 40 80 μs Low-speed CR TIMER mode 453 737 μs Sub TIMER mode 453 737 μs STOP mode 453 737 μs * : The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by external interrupt*) Ext.INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU * : External interrupt is set to detecting fall edge.

102 MB9A110A-DS706-00011-3v0-E, December 16, 2014

・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal Resource INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU * : Internal resource interrupt is not included in return factor by the kind of Low -Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode. ・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".

December 16, 2014, MB9A110A-DS706-00011-3v0-E 103 CONFIDENTIAL (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. ・ Return Count Time (VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Trcnt 308 444 μs High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 308 444 μs Low-speed CR TIMER mode 428 684 μs Sub TIMER mode 428 684 μs STOP mode 428 684 μs * : The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by INITX) INITX Trcnt Internal RST CPU Operation Start RST Active Release

104 MB9A110A-DS706-00011-3v0-E, December 16, 2014

・ Operation example of return from low power consumption mode (by internal resource reset*) Internal Resource RST Trcnt Internal RST CPU Operation Start RST Active Release *: Internal resource reset is not includ ed in return factor by the kind of Low-Power consumption mode. Notes: ・ The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL. ・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL". ・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing in 4. AC Characteristics in ■ELECTRICAL CHARACTERISTICS" for the detail on the time during the power-on reset/low -voltage detection reset. ・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. ・ The internal resource reset means the watchdog reset and the CSV reset.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 105 CONFIDENTIAL  ORDERING INFORMATION Part number On-chip Flash memory On-chip MB9AF111LAPMC1-G-JNE2 64Kbyte 16Kbyte Plastic  LQFP (0.5mm pitch), 64-pin (FPT-64P-M38) Tray MB9AF112LAPMC1-G-JNE2 128Kbyte 16Kbyte MB9AF114LAPMC1-G-JNE2 256Kbyte 32Kbyte MB9AF111LAPMC-G-JNE2 64Kbyte 16Kbyte Plastic  LQFP (0.65mm pitch), 64-pin (FPT-64P-M39) MB9AF112LAPMC-G-JNE2 128Kbyte 16Kbyte MB9AF114LAPMC-G-JNE2 256Kbyte 32Kbyte MB9AF111LAQN-G-A VE2 64Kbyte 16Kbyte Plastic  QFN (0.5mm pitch), 64-pin (LCC-64P-M24) MB9AF112LAQN-G-A VE2 128Kbyte 16Kbyte MB9AF114LAQN-G-A VE2 256Kbyte 32Kbyte MB9AF111MAPMC-G-JNE2 64Kbyte 16Kbyte Plastic  LQFP (0.5mm pitch), 80-pin (FPT-80P-M37) MB9AF112MAPMC-G-JNE2 128Kbyte 16Kbyte MB9AF114MAPMC-G-JNE2 256Kbyte 32Kbyte MB9AF115MAPMC-G-JNE2 384Kbyte 32Kbyte MB9AF116MAPMC-G-JNE2 512Kbyte 32Kbyte MB9AF111NAPMC-G-JNE2 64Kbyte 16Kbyte Plastic  LQFP (0.5mm pitch), 100-pin (FPT-100P-M23) MB9AF112NAPMC-G-JNE2 128Kbyte 16Kbyte MB9AF114NAPMC-G-JNE2 256Kbyte 32Kbyte MB9AF115NAPMC-G-JNE2 384Kbyte 32Kbyte MB9AF116NAPMC-G-JNE2 512Kbyte 32Kbyte MB9AF111NAPF-G-JNE1 64Kbyte 16Kbyte Plastic  QFP (0.65mm pitch), 100-pin (FPT-100P-M06) MB9AF112NAPF-G-JNE1 128Kbyte 16Kbyte MB9AF114NAPF-G-JNE1 256Kbyte 32Kbyte MB9AF115NAPF-G-JNE1 384Kbyte 32Kbyte MB9AF116NAPF-G-JNE1 512Kbyte 32Kbyte MB9AF111NABGL-GE1 64Kbyte 16Kbyte Plastic  PFBGA (0.8mm pitch), 112-pin (BGA-112P-M04) MB9AF112NABGL-GE1 128Kbyte 16Kbyte MB9AF114NABGL-GE1 256Kbyte 32Kbyte

106 MB9A110A-DS706-00011-3v0-E, December 16, 2014

 PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g 100-pin plastic LQFP (FPT-100P-M23) (FPT-100P-M23) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 1 25 100 0.145±0.055 (.006±.002) 0.08(.003) "A" INDEX 0°~8° 0.50±0.20 0.10±0.10 (Stand off) +.008 +0.20 (Mounting height) -0.101.50 .059 -.004( ) Dimensions in mm (inches). Note:The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part (.004±.004) (.009±.002) (.020±.008) (.024±.006)

December 16, 2014, MB9A110A-DS706-00011-3v0-E 107 CONFIDENTIAL 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 100-pin plastic QFP (FPT-100P-M06) (FPT-100P-M06) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7 1 30 5180 100 (.551±.008) 17.90±0.40 (.705±.016) INDEX (.013±.002) M0.13(.005) "A" 0.17±0.06 (.007±.002) 0.10(.004) Details of "A" part (.035±.006) 0.88±0.15 (.031±.008) 0.80±0.20 0.25(.010)3.00 +0.35 –0.20 +.014 –.008.118 (Mounting height) 0.25±0.20 (.010±.008) (Stand off) 0~8° *14.00±0.20 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

108 MB9A110A-DS706-00011-3v0-E, December 16, 2014

80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 80-pin plastic LQFP (FPT-80P-M37) (FPT-80P-M37) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 1 20 60 41 INDEX (.009± .002) M0.08(.003) 0.145± 0.055 (.006 ± .002) 0.08(.003) "A" (Stand off) Details of "A" part (.004 ± .002) 0.10 ± 0.05 (.024± .006) 0.60 ± 0.15 (.020± .008) 0.25(.010) 0.50 ± 0.20 (Mounting height) .059–.004 +.008 –0.10 +0.20 1.50 0~8° C Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 109 CONFIDENTIAL 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g 64-pin plastic LQFP (FPT-64P-M38) (FPT-64P-M38) "A" 0.08(.003) 0.145 ± 0.055 (.006 ± .002) INDEX 3348 161

2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2

(Stand off) Details of "A" part 0.10 ± 0.10 (.004±.004) 0.60 ± 0.15 0.25(.010) C 0.50±0.20 (.020±.008) (Mounting height) .059–.004 +.008 –0.10 +0.20 1.50 0~8° Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. (.009±.002) (.024±.006)

110 MB9A110A-DS706-00011-3v0-E, December 16, 2014

64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g 64-pin plastic LQFP (FPT-64P-M39) (FPT-64P-M39) "A" 0.10(.004) 0.145±0.055 (.006±.002) INDEX 3348 161 2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2 Details of "A" part 0.10±0.10 0.60±0.15 (.024±.006) 0.25(.010)BSC C .059–.004 +.008 –0.10 +0.20 1.50 0~8˚ 0.50±0.20 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) Pins width and pins thickness include plating thickness. (.013±.002) (.020±.008) (.004±.004)

December 16, 2014, MB9A110A-DS706-00011-3v0-E 111 CONFIDENTIAL 112-ball plastic PFBGA Ball pitch 0.80 mm Package width × package length 10.00 × 10.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size Ф 0.45 mm Mounting height 1.45 mm Max. Weight 0.22 g 112-ball plastic PFBGA (BGA-112P-M04) (BGA-112P-M04) C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3 (.049±.008) 1.25±0.20 (Seated height) F INDEX (INDEX AREA) 10.00±0.10 (.394±.004) (112-Ф0.18±.004) 112-Ф0.45±010 0.35±0.10 (.014±.004) (Stand off) 0.10(.004) S B A GHJKLE DC BA 0.80(.031) REF REF 0.80(.031) Ф0.08(.003) BASM 0.20(.008) SB S AS0.20(.008) Dimensions in mm (inches). Note: The values in parentheses are reference values.

112 MB9A110A-DS706-00011-3v0-E, December 16, 2014

64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight - 64-pin plastic QFN (LCC-64P-M24) (LCC-64P-M24) C 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1 (.354±.004) 9.00±0.10 (.236±.004) 6.00±0.10 (.236±.004) 6.00±0.10 (.354±.004) 9.00±0.10 0.40±0.05 (.016±.002) 0.50 (.020) (TYP) 0.25±0.05 (.010±.002) 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) INDEX AREA Dimensions in mm (inches). Note: The values in parentheses are reference values.

December 16, 2014, MB9A110A-DS706-00011-3v0-E 113 CONFIDENTIAL  MAJOR CHANGES Page Section Change Results Revision 1.0 - - Initial release Revision 2.0 - -

Revised series name and part number: MB9A110 Series→MB9A110A Series MB9AF111L → MB9AF111LA MB9AF112L → MB9AF112LA MB9AF114L → MB9AF114LA MB9AF111M → MB9AF111MA MB9AF112M → MB9AF112MA MB9AF114M → MB9AF114MA MB9AF115M → MB9AF115MA MB9AF116M → MB9AF116MA MB9AF111N → MB9AF111NA MB9AF112N → MB9AF112NA MB9AF114N → MB9AF114NA MB9AF115N → MB9AF115NA MB9AF116N → MB9AF116NA
Added the package. LCC-64P-M24 PRODUCT LINEUP
Function Multi-function Serial Interface (UART/CSIO/LIN/I2C) Added the following description. ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO
External Interrupts Corrected the following description. 7pins (Max) → 8pins (Max) 34 to SIGNAL DESCRIPTION Multi-function Serial (ch.0 to ch.7) Corrected the description for function.
Added "LIN pin"
Deleted "UART pin" 42, 43 I/O CIRCUIT TYPE • Corrected the following schematic for "TypeB". CMOS level hysteresis input → Digital input
Corrected the following schematic for "TypeC". Control Pin → Digital output HANDLING DEVICES
Power supply pins Corrected the description. 54 MEMORY SIZE Added " MEMORY SIZE". ELECTRICAL CHARACTERISTICS 4. AC Characteristics (1) Main Clock Input Characteristics Added the items FCM to the Internal operating clock frequency. 71 (4-2) Operating Conditions of Main PLL  Added the description. (7) External Bus Timing
External bus clock output Characteristics (8) Base Timer Input Timing
Trigger input timing Added the Note. 88 (10) External input timing  Corrected the footnote. 6. 12-bit A/D Converter
Electrical characteristics for the A/D converter
Corrected the value of "Full-scale transition voltage". Min: -20 → A VRH-20 Max: +20 → A VRH+20
Corrected the value of "Compare clock cycle". Max: 10000 → 2000
Corrected the value of "Reference voltage". Min: A VSS → 2.7 Revision 2.1 - - Company name and layout design change Revision 3.0 3 FEATURES External Bus Interface Added the description of Maximum area size 9 PACKAGES Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20 44, 46 I/O CIRCUIT TYPE Added the description of I2C to the type of E, F and I 44, 45 I/O CIRCUIT TYPE Added about +B input 51 HANDLING DEVICES Added "Stabilizing power supply voltage"

114 MB9A110A-DS706-00011-3v0-E, December 16, 2014

Page Section Change Results 51 HANDLING DEVICES Crystal oscillator circuit Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." 52 HANDLING DEVICES C Pin Changed the description 53 BLOCK DIAGRAM Modified the block diagram 54 MEMORY SIZE Changed to the following description See "Memory size" in "PRODUCT LINEUP" to confirm the memory size. 55 MEMORY MAP

Memory map(1) Modified the area of "Extarnal Device Area" 56, 57 MEMORY MAP
Memory map(2)(3) Added the summary of Flash memory sector and the note 64, 65 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings
Added the Clamp maximum current
Added the output current of P80 and P81
Added about +B input 66 ELECTRICAL CHARACTERISTICS 2. Recommended Operation Conditions
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage 67, 68 ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current rating
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current ELECTRICAL CHARACTERISTICS 4. AC Characteristics (3) Built-in CR Oscillation Characteristics Added Frequency stability time at Built-in high-speed CR ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4-1)(4-2) Operating Conditions of Main PLL
Added Main PLL clock frequency
Added the figure of Main PLL connection ELECTRICAL CHARACTERISTICS 4. AC Characteristics (6) Power-on Reset Timing
Added Time until releasing Power-on reset
Changed the figure of timing 75-77 ELECTRICAL CHARACTERISTICS 4. AC Characteristics (7) External Bus Timing Modified Data output time 82-89 ELECTRICAL CHARACTERISTICS 4. AC Characteristics (8) CSIO/UART Timing
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode 96 ELECTRICAL CHARACTERISTICS 5. 12bit A/D Converter
Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage 101 ELECTRICAL CHARACTERISTICS 9. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode 105 ORDERING INFORMATION Change to full part number 106 PACKAGE DIMENSIONS Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20

December 16, 2014, MB9A110A-DS706-00011-3v0-E 115 CONFIDENTIAL

116 MB9A110A-DS706-00011-3v0-E, December 16, 2014

December 16, 2014, MB9A110A-DS706-00011-3v0-E 117 CONFIDENTIAL

118 MB9A110A-DS706-00011-3v0-E, December 16, 2014

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Product Information

MB9A110A specifications and overview.

Summary

This document states the current technical specifications regarding

Description

This document states the current technical specifications regarding

Source title MB9A110A Datasheet(PDF) - SPANSION

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