MB90346APFV

MB90340 FUJITSU | Alldatasheet

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DS07-13730-3EFUJITSU SEMICONDUCTOR DATA SHEET 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90340 Series MB90F342A(S), MB90F342CA(S), MB90F343A(S), MB90F343CA(S), MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90341A(S), MB90341CA(S), MB90342A(S), MB90342CA(S), MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S), MB90348CA(S), MB90349A(S), MB90349CA(S), MB90V340A-101/102 n DESCRIPTION The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automotive and other industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 mm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 512 Kbytes. The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free running timers. 4 UARTs constitute additional functionality for communication purposes. * : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F 2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. n PACKAGES 100-pin Plastic QFP 100-pin Plastic LQFP (FPT-100P-M06) (FPT-100P-M05)

• ••• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without S- suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi- plied PLL clock).
• Built-in Clock Modulation circuit
• ••• 16 Mbyte CPU memory space
• 24-bit internal addressing
• ••• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• ••• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• ••• Increased processing speed
• 4-byte instruction queue
• ••• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• ••• Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI 2OS) : up to 16 channels
• DMA : up to 16 channels
• ••• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (time-base timer mode that is transfered from main clock mode)
• PLL timer mode (time-base timer mode that is transfered from PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• ••• Process
• C M O S t e c h n o l o g y
• ••• I/O port
• General-purpose input/output port (CMOS output) - 80 ports (devices without S-suffix) - 82 ports (devices with S-suffix) (Continued)

(Continued)

• ••• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer - 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7) - 16- bit input capture: (ICU) : 8 channels - 16-bit output compare : (OCU) : 8 channels
• ••• Full-CAN interface : up to 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
• ••• UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• ••• I 2C interface* : up to 2 channels (devices with C-suffix only)
• Up to 400 Kbits/s transfer rate
• ••• DTP/External interrupt : up to 16 channels, CAN wakeup : up to 2 channels
• Module for activation of expanded intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• ••• Delay interrupt generator module
• Generates interrupt request for task switching.
• ••• 8/10-bit A/D converter : 16/24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 ms (at 24-MHz machine clock, including sampling time)
• ••• Program patch function
• Address matching detection for 6 address pointers.
• ••• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• ••• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• ••• FLASH memory security function
• Protects the content of FLASH memory (FLASH memory device only)
• ••• External bus interface
• ••• Clock monitor function * : I 2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com- ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

(Continued) Part Number Parameter MB90F342A(S), MB90F342CA(S), MB90F343A(S)*1, MB90F343CA(S)*1, MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90341A(S)* 1, MB90341CA(S)*1, MB90342A(S)*1, MB90342CA(S)*1, MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S)*1, MB90348CA(S)*1, MB90349A(S)*1, MB90349CA(S)*1 MB90V340A-101/102 CPU F 2MC-16LX CPU System clock On-chip PLL clock multiplier (·1, ·2, ·3, ·4, ·6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz osc. PLL · 6) ROM MASK ROM, Flash memory

512 Kbytes : MB90F345A(S), MB90F345CA(S)

384 Kbytes : MB90F343A(S), MB90F343CA(S)

256 Kbytes : MB90F342A(S), MB90F342CA(S), MB90F349A(S),

MB90F349CA(S), MB90342A(S), MB90342CA(S), MB90349A(S), MB90349CA(S)

128 Kbytes : MB90F347A(S), MB90F347CA(S), MB90341A(S),

MB90341CA(S),MB90348A(S), MB90348CA(S), MB90347A(S), MB90347CA(S)

64 Kbytes : MB90F346A(S), MB90F346CA(S), MB90346A(S),

MB90346CA(S) External RAM

20 Kbytes : MB90F343A(S), MB90F343CA(S), MB90F345A(S),

MB90F345CA(S)

16 Kbytes : MB90F342A(S), MB90F342CA(S), MB90F349A(S),

MB90F349CA(S), MB90341A(S), MB90341CA(S), MB90342A(S), MB90342CA(S), MB90348A(S), MB90348CA(S), MB90349A(S), MB90349CA(S)

6 Kbytes : MB90F347A(S), MB90F347CA(S), MB90347A(S),

MB90347CA(S)

2 Kbytes : MB90F346A(S), MB90F346CA(S), MB90346A(S),

MB90346CA(S)

30 Kbytes

power supply*2 ¾ Yes Technology 0.35 mm CMOS with regulator for internal power supply + Flash memory with Charge pump for programming voltage 0.35 mm CMOS with regulator for internal power supply Operating voltage range 3.5 V - 5.5 V : at normal operating (not using A/D converter) 4.0 V - 5.5 V : at using A/D converter/Flash programming 4.5 V - 5.5 V : at using external bus

5 V – 10%

Temperature range -40 °C to +105 °C ¾ Package QFP-100, LQFP-100 PGA-299 UART 4 channels 5 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device I 2C (400 Kbps) devices with ‘C’-suffix : 2ch devices without ‘C’-suffix : ¾ 2 channels

(Continued) Part Number Parameter MB90F342A(S), MB90F342CA(S), MB90F343A(S)*1, MB90F343CA(S)*1, MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90341A(S)* 1, MB90341CA(S)*1, MB90342A(S)*1, MB90342CA(S)*1, MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S)*1, MB90348CA(S)*1, MB90349A(S)*1, MB90349CA(S)*1 MB90V340A-101/102 A/D Converter devices with ‘C’-suffix : 24ch devices without ‘C’-suffix : 16ch 24 input channels 10-bit or 8-bit resolution Conversion time : Min 3 ms include sample time (per one channel) 16-bit Reload Timer (4 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function 16-bit I/O Timer (2 channels) Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 0, 4) Operation clock freq. : fsys, fsys/2 1, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 16-bit Output Compare (8 channels) Signals an interrupt when 16-bit I/O Timer match output compare registers. A pair of compare registers can be used to generate an output signal. 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Signals an interrupt upon external event 8/16-bit Programmable Pulse Generator (8 channels) Supports 8-bit and 16-bit operation modes Sixteen 8-bit reload counters Sixteen 8-bit reload registers for L pulse width Sixteen 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operation clock freq. : fsys, fsys/2 1, fsys/22, fsys/23, fsys/24 or 128 ms@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) CAN Interface 2 channels : MB90F342A(S), MB90F342CA(S), MB90F345A(S), MB90F345CA(S), MB90341A(S), MB90341CA(S), MB90342A(S), MB90342CA(S) 1 channel : MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S), MB90348CA(S), MB90349A(S), MB90349CA(S) 3 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps

(Continued) *1 : These devices are under development. *2 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Part Number Parameter MB90F342A(S), MB90F342CA(S), MB90F343A(S)*1, MB90F343CA(S)*1, MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90341A(S)* 1, MB90341CA(S)*1, MB90342A(S)*1, MB90342CA(S)*1, MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S)*1, MB90348CA(S)*1, MB90349A(S)*1, MB90349CA(S)*1 MB90V340A-101/102 External Interrupt (16 channels) Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, expanded inteligent I/O services (EI2OS) and DMA D/A converter ¾ 2 channels Up to100 kHz Subclock for low power operation without subclock : devices with ‘S’-suffix or MB90V340A-101 with subclock : devices without ‘S’-suffix or MB90V340A-102 I/O Ports Virtually all external pins can be used as general purpose I/O port All push-pull outputs Bit-wise settable as input/output or peripheral signal Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default) TTL input level settable for external bus (32-pin only for external bus) Flash Memory Supports automatic programming, Embedded Algorithm TM *3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (except for MB90F346A(S) and MB90F346CA (S) )

• MB90V340A-101/MB90V340A-102 (Continued) (TOP VIEW) (FPT-100P-M06) * : X0A, X1A : MB90V340A-102 P40, P41 : MB90V340A-101 100 P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15/SCK4 P16/AD14/SOT4 P15/AD13/SIN4 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 3018 P75/AN21/INT5 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA 1/ TX 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 MD0 MD1 MD2 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P34/HRQ/OUT4 P56/AN14/DA00 P55/AN13 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47/SCL1 P46/SDA1 P45/SCL0/FRCK1 P44/SDA0/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A* P40/X0A* P37/CLK/OUT7 P36/RDY/OUT6 QFP - 100 21201716 19 181514131211 26 25242322 27 28 29435 629 71 0 80 515871 70 67 6669 68 65 64 63 62 6176 75 74 73 72777879 54 535556 5259 5760 P57/AN15/DA01 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P60/AN0/PPG0(1) P61/AN1/PPG2(3) P62/AN2/PPG4(5) P63/AN3/PPG6(7) P64/AN4/PPG8(9) P65/AN5/PPGA(B) P66/AN6/PPGC(D) P67/AN7/PPGE(F) Vss P70/AN16/INT0 P71/AN17/INT1 AVcc AVRH AVRL AVss RST P31/RD/IN5 P32/WRL/WR/RX2/INT10R P33/WRH/TX2 P35/HAK/OUT5

(Continued) (TOP VIEW) (FPT-100P-M05) * : X0A, X1A : MB90V340A-102 P40, P41 : MB90V340A-101 P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15/SCK4 P16/AD14/SOT4 P15/AD13/SIN4 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15/DA01 P00/AD00/INT8 PA 1/T X 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 MD0 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P34/HRQ/OUT4 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47/SCL1 P46/SDA1 P45/SCL0/FRCK1 P44/SDA0/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A* P40/X0A* P37/CLK/OUT7 P36/RDY/OUT6 LQFP - 100 99P24/A20/IN0 100P25/A21/IN1

28 P56/AN14/DA00

27 P55/AN13

26 P54/AN12/TOT3

49 MD2

50 MD1

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5859 55 5657 54 53 52 51 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 8 17 21 2019 22 23 24 25 RST P31/RD/IN5 P32/WRL/WR/RX2/INT10R P33/WRH/TX2 P35/HAK/OUT5

• MB90F342A(S) / MB90F343A(S) / MB90F345A(S) / MB90F346A(S) / MB90F347A(S) / MB90F349A(S) / MB90341A(S) / MB90342A(S) /MB90346A(S) / MB90347A(S) / MB90348A(S) / MB90349A(S) (Continued) (TOP VIEW) (FPT-100P-M06) * : X0A, X1A : MB90F342A/F343A/F345A/F346A/F347A/F349A/341A/342A/346A/347A/348A/349A MB90F342AS/F343AS/F345AS/F346AS/F347AS/F349AS P40, P41 : MB90341AS/342AS/346AS/347AS/348AS/349AS 100 50P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15 P16/AD14 P15/AD13 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P75/INT5 P74/INT4 P73/INT3 P72/INT2 P71/INT1 P70/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA 1/T X 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/INT7 P76/INT6 MD0 MD1 MD2 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P32/WRLX/WRX/INT10R P34/HRQ/OUT4 P56/AN14 P55/AN13 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47 P46 P45/FRCK1 P44/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A * P40/X0A * P37/CLK/OUT7 P36/RDY/OUT6 QFP - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 RST P31/RD/IN5 P33/WRH P35/HAK/OUT5

(Continued) (TOP VIEW) (FPT-100P-M05) * : X0A, X1A : MB90F342A/F343A/F345A/F346A/F347A/F349A/341A/342A/346A/347A/348A/349A MB90F342AS/F343AS/F345AS/F346AS/F347AS/F349AS P40, P41 : MB90341AS/342AS/346AS/347AS/348AS/349AS P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15 P16/AD14 P15/AD13 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P00/AD00/INT8 PA 1/ TX 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/INT7 P76/INT6 MD0 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P32/WRL/WR/INT10R P34/HRQ/OUT4 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47 P46 P45/FRCK1 P44/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A* P40/X0A* P37/CLK/OUT7 P36/RDY/OUT6 99P24/A20/IN0 100P25/A21/IN1

28 P56/AN14

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 P75/INT5 P74/INT4 P73/INT3 P72/INT2 P71/INT1 P70/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15 RST P31/RD/IN5 P33/WRH P35/HAK/OUT5

• MB90F342CA(S) / MB90F343CA(S) / MB90F345CA(S) / MB90F346CA(S) / MB90F347CA(S) / MB90F349CA(S) / MB90341CA(S) / MB90342CA(S) /MB90346CA(S) / MB90347CA(S) / MB90348CA(S) / MB90349CA(S) (Continued) (TOP VIEW) (FPT -100P-M06 ) 100 50P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15 P16/AD14 P15/AD13 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P75/AN21/INT5 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA 1/T X 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 MD0 MD1 MD2 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P34/HRQ/OUT4 P56/AN14 P55/AN13 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47/SCL1 P46/SDA1 P45/SCL0/FRCK1 P44/SDA0/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A* P40/X0A* P37/CLK/OUT7 P36/RDY/OUT6 QFP - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P61/AN1/PPG2(3) AVss P57/AN15 AVcc P60/AN0/PPG0(1) AVRL AVRH Vss P62/AN2/PPG4(5) P63/AN3/PPG6(7) RST P31/RD/IN5 P33/WRH P35/HAK/OUT5 P32/WRL/WR/INT10R * : X0A, X1A : MB90F342CA/F343CA/F345CA/F346CA/F347CA/F349CA MB90341CA/342CA/346CA/347CA/348CA/349CA P40, P41 : MB90F342CAS/F343CAS/F345CAS/F346CAS/F347CAS/F349CAS MB90341CAS/342CAS/346CAS/347CAS/348CAS/349CAS

(Continued) (TOP VIEW) (FPT-100P-M05) P04/AD04/INT12 P23/A19/PPGF(E) P22/A18/PPGD(C) P21/A17/PPGB(A) P20/A16/PPG9(8) P17/AD15 P16/AD14 P15/AD13 Vss Vcc P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/NT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P00/AD00/INT8 PA 1/ TX 0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 MD0 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P34/HRQ/OUT4 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47/SCL1 P46/SDA1 P45/SCL0/FRCK1 P44/SDA0/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41/X1A* P40/X0A* P37/CLK/OUT7 P36/RDY/OUT6 99P24/A20/IN0 100P25/A21/IN1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15 RST P31/RD/IN5 P33/WRH P35/HAK/OUT5 P32/WRL/WR/INT10R * : X0A, X1A : MB90F342CA/F343CA/F345CA/F346CA/F347CA/F349CA MB90341CA/342CA/346CA/347CA/348CA/349CA P40, P41 : MB90F342CAS/F343CAS/F345CAS/F346CAS/F347CAS/F349CAS MB90341CAS/342CAS/346CAS/347CAS/348CAS/349CAS

(Continued) Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 90 92 X1 A Oscillation output 91 93 X0 Oscillation input 52 54 RST E Reset input 75 to 82 77 to 84 P00 to P07 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. INT8 to INT15 External interrupt request input pins for INT8 to INT15. 83 85 P10 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD08 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. TIN1 Event input pin for the reload timer 1 84 86 P11 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD09 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. TOT1 Output pin for the reload timer 1 85 87 P12 N General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD10 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SIN3 Serial data input pin for UART3 INT11R External interrupt request input pin for INT11 86 88 P13 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD11 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SOT3 Serial data output pin for UART3 87 89 P14 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD12 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SCK3 Clock I/O pin for UART3

(Continued) Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 92 94 P15 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD13 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SIN4 Serial data input pin for UART4 (EVA devices) 93 95 P16 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD14 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SOT4 Serial data output pin for UART4 (EVA devices) 94 96 P17 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD15 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. SCK4 Clock I/O pin for UART4 (EVA devices only) 95 to 98 97 to 100 P20 to P23 G General purpose I/O. The register can be set to select whether to use a pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. A16 to A19 Output pins for A16 to A19 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A16 to A19). PPG9,PPGB, PPGD,PPGF Output pins for PPGs 99 to 2 1 to 4 P24 to P27 G General purpose I/O. The register can be set to select whether to use a pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. A20 to A23 Output pins for A20 to A23 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A20 to A23). IN0 to IN3 Data sample input pins for input captures ICU0 to ICU3 P30 G General purpose I/O.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. ALE Address latch enable output pin. This function is enabled when the external bus is enabled. IN4 Data sample input pin for input capture ICU4

(Continued) Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 P31 G General purpose I/O.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. RD Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. IN5 Data sample input pin for input capture ICU5 P32 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the WR /WRL pin output disabled. WRL / WR Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are en- abled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to write-strobe 8 bits of the data bus in 8-bit access. RX2 RX input pin for CAN2 Interface (EVA devices) INT10R External interrupt request input pin for INT10 P33 G General purpose I/O. The register can be set to select whether to use a pull-up resistor.This function is enabled either in single-chip mode or with the WRH pin output disabled. WRH Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. TX2 TX Output pin for CAN2 (EVA devices) P34 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. HRQ Hold request input pin. This function is enabled when both the ex- ternal bus and the hold function are enabled. OUT4 Waveform output pin for output compare OCU4 81 0 P35 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. HAK Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. OUT5 Waveform output pin for output compare OCU6 91 1 P36 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the external ready function disabled. RDY Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. OUT6 Waveform output pin for output compare OCU5

(Continued) Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 10 12 P37 G General purpose I/O. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the CLK output disabled. CLK CLK output pin. This function is enabled when both the external bus and CLK output are enabled. OUT7 Waveform output pin for output compare OCU7 11, 12 13, 14 P40, P41 F General purpose I/O (devices with S-suffix or MB90V340A-101) X0A , X1A B Oscillator input pins for sub-clock (devices without S-suffix or MB90V340A-102) 16 18 P42 F General purpose I/O IN6 Data sample input pin for input capture ICU6 RX1 RX input pin for CAN1 Interface (MB90F342A/F343A/F345A/341A/342A only) INT9R External interrupt request input pin for INT9 17 19 P43 F General purpose I/O IN7 Data sample input pin for input capture ICU7 TX1 TX Output pin for CAN1 (MB90F342A/F343A/F345A/341A/342A only) 18 20 P44 H General purpose I/O SDA0 Serial data I/O pin for I 2C 0 (devices with C-suffix) FRCK0 Input for the 16-bit I/O Timer 0 19 21 P45 H General purpose I/O SCL0 Serial clock I/O pin for I 2C 0 (devices with C-suffix) FRCK1 Input for the 16-bit I/O Timer 1 20 22 P46 H General purpose I/O SDA1 Serial data I/O pin for I 2C 1 (devices with C-suffix) 21 23 P47 H General purpose I/O SCL1 Serial clock I/O pin for I 2C 1 (devices with C-suffix) 22 24 P50 O General purpose I/O AN8 Analog input pin for the A/D converter SIN2 Serial data input pin for UART2 23 25 P51 I General purpose I/O AN9 Analog input pin for the A/D converter SOT2 Serial data output pin for UART2 24 26 P52 I General purpose I/O AN10 Analog input pin for the A/D converter SCK2 Clock I/O pin for UART2

(Continued) Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 25 27 P53 I General purpose I/O AN11 Analog input pin for the A/D converter TIN3 Event input pin for the reload timers 3 26 28 P54 I General purpose I/O AN12 Analog input pin for the A/D converter TOT3 Output pin for the reload timer 3 27 29 P55 I General purpose I/O AN13 Analog input pin for the A/D converter 28, 29 30, 31 P56 to P57 J General purpose I/O AN14 to AN15 Analog input pin for the A/D converter DA00 to DA01 D/A converter analog output pins (MB90V340 only) 34 to 41 36 to 43 P60 to P67 I General purpose I/O AN0 to AN7 Analog input pins for the A/D converter PPG0, 2, 4, 6, 8, A, C, E Output pins for PPGs 43 to 48, 53, 54 45 to 50, 55, 56 P70 to P77 I General purpose I/O AN16 to AN23 Analog input pins for the A/D converter (devices with C-suffix) INT0 to INT7 External interrupt request input pins for INT0 to INT7 55 57 P80 F General purpose I/O TIN0 Event input pin for the reload timers 0 ADTG Trigger input pin for the A/D converter INT12R External interrupt request input pin for INT12 56 58 P81 F General purpose I/O TOT0 Output pin for the reload timer 0 CKOT Output pin for the clock monitor INT13R External interrupt request input pin for INT13 57 59 P82 M General purpose I/O SIN0 Serial data input pin for UART0 TIN2 Event input pin for the reload timers 2 INT14R External interrupt request input pin for INT14 58 60 P83 F General purpose I/O SOT0 Serial data output pin for UART0 TOT2 Output pin for the reload timer 2 59 61 P84 F General purpose I/O SCK0 Clock I/O pin for UART0 INT15R External interrupt request input pin for INT15

(Continued) *1 : FPT-100P-M06 *2 : FPT-100P-M05 Pin No. Pin name Circuit type Function LQFP100* 2 QFP100* 1 60 62 P85 M General purpose I/O SIN1 Serial data input pin for UART1 61 63 P86 F General purpose I/O SOT1 Serial data output pin for UART1 62 64 P87 F General purpose I/O SCK1 Clock I/O pin for UART1 65 to 68 67 to 70 P90 to P93 F General purpose I/O PPG1, 3, 5, 7 Output pins for PPGs 69 to 72 71 to 74 P94 to P97 F General purpose I/O OUT0 to OUT3 Waveform output pins for output compares OCU0 to OCU3. This function is enabled when the OCU enables waveform output. 73 75 PA0 F General purpose I/O RX0 RX input pin for CAN0 Interface INT8R External interrupt request input pin for INT8 74 76 PA1 F General purpose I/O TX0 TX Output pin for CAN0 30 32 AV CC K Vcc power input pin for analog circuits 31 33 AVRH L Reference voltage input for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AV CC . 32 34 AVRL K Lower reference voltage input for the A/D Converter 33 35 AV SS K Vss power input pin for analog circuits 50, 51 52, 53 MD1, MD0 C Input pins for specifying the operating mode. 49 51 MD2 D Input pin for specifying the operating mode. V CC ¾ Power (3.5 V to 5.5 V) input pins V SS ¾ Power (0V) input pins 15 17 C K This is the power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 mF ceramic capacitor.

(Continued) Type Circuit Remarks A Oscillation circuit

• High-speed oscillation feedback resistor = approx. 1 MW B Oscillation circuit
• Low-speed oscillation feedback resistor = approx. 10 MW C Mask ROM and EVA device:
• CMOS Hysteresis input pin Flash device:
• CMOS input pin D Mask ROM and EVA device:
• CMOS Hysteresis input pin
• Pull-down resistor valule: approx. 50 kW Flash device:
• CMOS input pin
• No Pull-down E CMOS Hysteresis input pin
• Pull-up resistor valule: approx. 50 kW Standby control signal Xout Standby control signal X1A X0A Xout Hysteresis inputs R Pull-down Resistor Hysteresis inputs R Pull-up Resistor Hysteresis inputs R

(Continued) Type Circuit Remarks F

• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• CMOS hysteresis inputs (With the standby- time input shutdown function)
• Automotive input (With the standby-time input shutdown function) G
• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• CMOS hysteresis inputs (With the standby- time input shutdown function)
• Automotive input (With the standby-time input shutdown function)
• TTL input (With the standby-time input shutdown function)
• Programmalble pullup resistor: 50 kW approx. H
• CMOS level output (IOL = 3 mA, IOH = -3 mA)
• CMOS hysteresis inputs (With the standby- time input shutdown function)
• Automotive input (With the standby-time input shutdown function) Hysteresis inputs Automotive inputs Standby control for input shutdown Pout Nout R pull-up control Hysteresis inputs Automotive inputs TTL input Standby control for input shutdown Pout Nout R Hysteresis inputs Automotive inputs Standby control for input shutdown Pout Nout R

(Continued) Type Circuit Remarks I

• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• CMOS hysteresis inputs (With the standby- time input shutdown function)
• Automotive input (With the standby-time in- put shutdown function)
• A/D analog input J
• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• D/A analg output
• CMOS hysteresis inputs (With the standby- time input shutdown function)
• Automotive input (With the standby-time in- put shutdown function)
• A/D analog input K
• Power supply input protection circuit L
• A/D converter reference voltage power supply input pin, with the protection circuit
• Flash devices do not have a protection circuit against VCC for pin AVRH Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input Pout Nout R Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input Analog output Pout Nout R ANE AVR ANE

(Continued) Type Circuit Remarks M

• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• CMOS inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time input shutdown function) N
• CMOS level output (IOL = 4 mA, IOH = -4 mA)
• CMOS inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time input shutdown function)
• TTL input (With the standby-time input shutdown function) Programmable pullup registor:50 kW approx O
• CMOS level output(IOL = 4 mA, IOH = -4 mA)
• CMOS inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time input shutdown function)
• A/D analog input CMOS inputs Automotive inputs Standby control for input shutdown Pout Nout R pull-up control CMOS inputs Automotive inputs TTL input Standby control for input shutdown Pout Nout R CMOS inputs Automotive inputs Standby control for input shutdown Analog input Pout Nout R

Special care is required for the following when handling the device :

• Preventing latch-up
• T reatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (V CC /VSS )
• Pull-up/down resistors
• Crystal Oscillator Circuit
• T urning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on (External-bus mode)
• Notes on using CAN Function
• Flash security Function 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS .
• T h e A VCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC , AVRH) exceed the digital power-supply voltage. 2. Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kW . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. Using external clock T o use external clock, drive the X0 pin and leave X1 pin open. 4. Precautions for when not using a sub clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. MB90340 Series Open

1. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 6. Power supply pins (VCC /VSS )

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. T o reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the V CC and VSS pins to the power supply and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 mF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device 7. Pull-up/down resistors The MB90340 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external components where needed. 8. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. 9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC , AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the digital power supply (VCC ) . T urn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 10. Connection of Unused Pins of A/D Converter if A/D Converter is used Connect unused pins of A/D converter to AVCC = VCC , AVSS = AVRH = AVRL = VSS . Vcc Vss Vss Vcc Vss VccMB90340 Series Vcc Vss VccVss

1. Notes on Energization T o prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more ms (0.2 V to 2.7 V) 12. Stabilization of power supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 13. Initialization In the device, there are internal registers which are initialized only by a power-on reset. T o initialize these registers, turn on the power again. 14. Port 0 to port 3 output during Power-on (External-bus mode) As shown below, when power is turned on in External-Bus mode, in spite of reset inpu, there is a possibility that output signal of Port 0 to Port 3 might be unstable. 15. Notes on using CAN Function T o use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR). If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers. Please refer to Hardware Manual of MB90340 series for detail of CAN Direct Mode Register. 16. Flash security Function (except for MB90F346A) The security bit is located in the area of the flash memory. If protection code 01 H is written in the security bit, the flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. Flash memory size Address for security bit MB90F347 MMB90F347A Embedded 1 Mbit Flash Memory FE0001 H MB90F342A MB90F349A Embedded 2 Mbit Flash Memory FC0001 H MB90F343A Embedded 3 Mbit Flash Memory F90001 H MB90F345A Embedded 4 Mbit Flash Memory F80001 H Port0 to 3 outputs might be unstable Port0 to 3 outputs = Hi-Z Port0 ~ Port3 VCC 1/2VCC

X0,X1 RST SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG TIN3 to TIN0 TOT3 to TOT0 IN7 to IN0 OUT7 to OUT0 RX2 to RX0 TX2 to TX0 INT15 to INT8 External Bus Interface AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK X0A,X1A* 5 ch 10-bit DAC 2 ch DA01, DA00 IO Timer 1 FRCK0 FRCK1 8/16-bit PPG 16 ch PPGF to PPG0 I2C Interface SDA1, SDA0 SCL1, SCL0 3 ch 5 ch 2 ch DMAC * : Only for MB90V340A-102 Clock Monitor CKOT (INT15R to INT8R) INT7 to INT0

MB90F342A(S), MB90F342CA(S), MB90F343A(S), MB90F343CA(S), MB90F345A(S), MB90F345CA(S), , MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S), MB90341A(S), MB90341CA(S), MB90342A(S), MB90342CA(S), MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S), MB90348A(S), MB90348CA(S), MB90349A(S), MB90349CA(S) RAM ROM/Flash UART Prescaler 10-bit ADC 16/24 ch 16-bit Reload Timer 4 ch IO Timer 0 Clock Controller Input Capture 8 ch Output Compare 8 ch CAN Controller External Interrupt 16LX CPU F2MC-16 Bus X0,X1 RST SOT3 to SOT0 SCK3 to SCK0 SIN3 to SIN0 AVCC AVSS AN15 to AN0 AVRH AVRL ADTG TIN3 to TIN0 TOT3 to TOT0 IN7 to IN0 OUT7 to OUT0 RX0, RX1*3 TX0, TX1*3 INT15 to INT8 External Bus Interface AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK X0A,X1A*1

64 K/128 K

1 ch/2 ch*3 4 ch I2C Interface SDA1, SDA0*2 SCL1, SCL0*2 2 ch AN23 to AN16*2

2 K/6 K/16 K/

256 K/384 K/

*1 : Only for devices without ‘S’ Suffix *2 : Only for devices with ‘C’ Suffix *3 : Supported by MB90341A(S), 341CA(S), 342A(S), 342CA(S), F342A(S), F342CA(S), F343A(S), F343CA(S), F345A(S), F345CA(S) only Clock Monitor CKOT (INT15R to INT8R) INT7 to INT0 512 K

MB90F345A(S), F345CA(S) MB90F343A(S), F343CA(S) FFFFFF H FF0000H FEFFFF H FE0000 H FDFFFF H FD0000 H FBFFFF H FB0000 H FAFFFF H FA0000 H F9FFFF H F90000H 00FFFF H 008000H 007FFF H 007900H 0050FFH 000100H 0000EF H 000000H FCFFFF H FC0000 H F8FFFF H F80000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) External access area External access area External access area External access area Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral ROM (image of FF bank) ROM (image of FF bank) ROM (image of FF bank) RAM 20 K RAM 20 K RAM 30 K : No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000 H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000 H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFF H is visible only in bank FF . FFFFFF H FF0000H FEFFFF H FE0000 H FDFFFF H FD0000 H FCFFFF H FC0000 H 0000EF H 000000H 00FFFF H 007FFF H 007900H 003FFF H 000100H 008000H MB90349A(S), 349CA(S) MB90342A(S), 342CA(S) MB90F349A(S), F349CA(S) MB90F342A(S), F342CA(S) FFFFFF H FF0000H FEFFFF H FE0000 H 0000EF H 000000H 00FFFF H 003FFF H 000100H MB90348A(S), 348CA(S) MB90341A(S), 341CA(S) FFFFFF H FF0000H FEFFFF H FE0000 H 0000EF H 000000H 00FFFF H 007FFF H 007900H 000100H 008000H MB90347A(S), 347CA(S) MB90F347(S), F347C(S) MB90F347A(S), F347CA(S) 0018FFH FFFFFF H FF0000H 0000EF H 000000H 00FFFF H 007FFF H 007900H 000100H 008000H MB90346A(S), 346CA(S) MB90F346A(S), F346CA(S) 0008FFH 007FFF H 007900H 008000H FEFFFF H FE0000 H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FF bank) ROM (FE bank) ROM (FF bank) ROM (FE bank) External access area Peripheral Peripheral Peripheral ROM (image of FF bank) ROM (FF bank) ROM (image of FF bank) ROM (image of FF bank) ROM (image of FF bank) External access area External access area External access area Peripheral Peripheral Peripheral Peripheral Peripheral RAM 16 K RAM 16 K RAM 6 K RAM 2 K External access areaExternal access area External access area External access area : No access

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A XXXXXXXX 0BH Port 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111 0C H Port 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111 0D H Port 7 Analog Input Enable Register ADER7 R/W Port 7, A/D 11111111 0EH Input level select register 0 ILSR0 R/W Ports XXXXXXXX 0FH Input level select register 1 ILSR1 R/W Ports XXXX0XXX 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 00000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A 00000100 1BH Reserved 1C H Port 0 Pullup control register PUCR0 R/W Port 0 00000000 1D H Port 1 Pullup control register PUCR1 R/W Port 1 00000000 1EH Port 2 Pullup control register PUCR2 R/W Port 2 00000000 1FH Port 3 Pullup control register PUCR3 W, R/W Port 3 00000000

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 20H Serial Mode Register 0 SMR0 W,R/W UART0 00000000 21H Serial Control Register 0 SCR0 W,R/W 00000000 22H Reception/Transmission Data Register 0RDR0/ TDR0 R/W 00000000 23H Serial Status Register 0 SSR0 R,R/W 00001000 24H Extended Communication Control Register 0 ECCR0 R,W,R/ W 000000XX 25H Extended Status/Control Register 0 ESCR0 R/W 00000100 26H Baud Rate generator Register 00 BGR00 R/W 00000000 27H Baud Rate generator Register 01 BGR01 R/W 00000000 28H Serial Mode Register 1 SMR1 W,R/W UART1 00000000 29H Serial Control Register 1 SCR1 W,R/W 00000000 2AH Reception/Transmission Data Register 1RDR1/ TDR1 R/W 00000000 2BH Serial Status Register 1 SSR1 R,R/W 00001000 2C H Extended Communication Control Register 1 ECCR1 R,W, R/W 000000XX 2D H Extended Status/Control Register 1 ESCR1 R/W 00000100 2EH Baud Rate generator Register 10 BGR10 R/W 00000000 2FH Baud Rate generator Register 11 BGR11 R/W 00000000 30H PPG 0 operation mode control register PPGC0 W,R/W 16-bit PPG 0/1 0X000XX1 31H PPG 1 operation mode control register PPGC1 W,R/W 0X000001 32H PPG 0/PPG 1 count clock select register PPG01 R/W 000000X0 33H Reserved 34H PPG 2 operation mode control register PPGC2 W,R/W 16-bit PPG 2/3 0X000XX1 35H PPG 3 operation mode control register PPGC3 W,R/W 0X000001 36H PPG 2/PPG 3 count clock select register PPG23 R/W 000000X0 37H Reserved 38H PPG 4 operation mode control register PPGC4 W,R/W 16-bit PPG 4/5 0X000XX1 39H PPG 5 operation mode control register PPGC5 W,R/W 0X000001 3AH PPG 4/PPG 5 clock select register PPG45 R/W 000000X0 3BH Address detect control register 1 PACSR1 R/W Address Match Detection 1 00000000 3C H PPG 6 operation mode control register PPGC6 W,R/W 16-bit PPG 6/7 0X000XX1 3D H PPG 7 operation mode control register PPGC7 W,R/W 0X000001 3EH PPG 6/PPG 7 count clock control register PPG67 R/W 000000X0 3FH Reserved

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 40H PPG 8 operation mode control register PPGC8 W,R/W 16-bit PPG 8/9 0X000XX1 41H PPG 9 operation mode control register PPGC9 W,R/W 0X000001 42H PPG 8/PPG 9 count clock control register PPG89 R/W 000000X0 43H Reserved 44H PPG A operation mode control register PPGCA W,R/W 16-bit PPG A/B 0X000XX1 45H PPG B operation mode control register PPGCB W,R/W 0X000001 46H PPG A/PPG B count clock select register PPGAB R/W 000000X0 47H Reserved 48H PPG C operation mode control register PPGCC W,R/W 16-bit PPG C/D 0X000XX1 49H PPG D operation mode control register PPGCD W,R/W 0X000001 4AH PPG C/PPG D count clock select register PPGCD R/W 000000X0 4BH Reserved 4C H PPG E operation mode control register PPGCE W,R/W 16-bit PPG E/F 0X000XX1 4D H PPG F operation mode control register PPGCF W,R/W 0X000001 4EH PPG E/PPG F count clock select register PPGEF R/W 000000X0 4FH Reserved 50H Input Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000 51H Input Capture Edge 0/1 ICE01 R/W, R XXX0X0XX 52H Input Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000 53H Input Capture Edge 2/3 ICE23 R XXXXXXXX 54H Input Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 00000000 55H Input Capture Edge 4/5 ICE45 R XXXXXXXX 56H Input Capture Control Status 6/7 ICS67 R/W Input Capture 6/7 00000000 57H Input Capture Edge 6/7 ICE67 R/W, R XXX000XX 58H Output Compare Control Status 0 OCS0 R/W Output Compare 0/1 0000XX00 59H Output Compare Control Status 1 OCS1 R/W 0XX00000 5AH Output Compare Control Status 2 OCS2 R/W Output Compare 2/3 0000XX00 5BH Output Compare Control Status 3 OCS3 R/W 0XX00000 5C H Output Compare Control Status 4 OCS4 R/W Output Compare 4/5 0000XX00 5D H Output Compare Control Status 5 OCS5 R/W 0XX00000 5EH Output Compare Control Status 6 OCS6 R/W Output Compare 6/7 0000XX00 5FH Output Compare Control Status 7 OCS7 R/W 0XX00000

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 60H Timer Control Status 0 TMCSR0 R/W 16-bit Reload Timer 0 00000000 61H Timer Control Status 0 TMCSR0 R/W XXXX0000 62H Timer Control Status 1 TMCSR1 R/W 16-bit Reload Timer 1 00000000 63H Timer Control Status 1 TMCSR1 R/W XXXX0000 64H Timer Control Status 2 TMCSR2 R/W 16-bit Reload Timer 2 00000000 65H Timer Control Status 2 TMCSR2 R/W XXXX0000 66H Timer Control Status 3 TMCSR3 R/W 16-bit Reload Timer 3 00000000 67H Timer Control Status 3 TMCSR3 R/W XXXX0000 68H A/D Control Status 0 ADCS0 R/W A/D Converter 000XXXX0 69H A/D Control Status 1 ADCS1 R/W 0000000X 6AH A/D Data 0 ADCR0 R 00000000 6BH A/D Data 1 ADCR1 R XXXXXX00 6C H ADC Setting 0 ADSR0 R/W 00000000 6D H ADC Setting 1 ADSR1 R/W 00000000 6EH Reserved 6FH ROM Mirror Function Select ROMM W ROM Mirror XXXXXXX1 70H to 8FH Reserved for CAN Interface 0/1. Refer to “n CAN CONTROLLERS” 90H to 9AH Reserved 9BH DMA Descriptor Channel Specified DCSR R/W DMA 00000000 9C H DMA Status L DSRL R/W 00000000 9D H DMA Status H DSRH R/W 00000000 9EH Address Detect Control Register 0 PACSR0 R/W Address Match Detection 0 00000000 9FH Delayed Interrupt/release DIRR R/W Delayed Interrupt XXXXXXX0 A0H Low-power Mode Control Register LPMCR W,R/W Low Power Control Circuit 00011000 A1H Clock Selection Register CKSCR R,R/W Low Power Control Circuit 11111100 A2H , A3H Reserved A4H DMA Stop Status DSSR R/W DMA 00000000 A5H Automatic ready function select reg. ARSR W External Memory Access 0011XX00 A6H External address output control reg. HACR W 00000000 A7H Bus control signal selection register ECSR W 0000000X A8H Watchdog Control Register WDTC R,W Watchdog Timer XXXXX111 A9H Time Base Timer Control Register TBTC W,R/W Time Base Timer 1XX00100

(Continued) Address Register Abbrevia- tion Access Resource name Initial value AA H Watch Timer Control register WTC R,R/W Watch Timer 1X001000 AB H Reserved AC H DMA Enable L DERL R/W DMA 00000000 AD H DMA Enable H DERH R/W 00000000 AE H Flash Control Status (FlashDevices only. Otherwise reserved) FMCS R,R/W Flash Memory 000X0000 AF H Reserved B0H Interrupt control register 00 ICR00 W,R/W Interrupt Control 00000111 B1H Interrupt control register 01 ICR01 W,R/W 00000111 B2H Interrupt control register 02 ICR02 W,R/W 00000111 B3H Interrupt control register 03 ICR03 W,R/W 00000111 B4H Interrupt control register 04 ICR04 W,R/W 00000111 B5H Interrupt control register 05 ICR05 W,R/W 00000111 B6H Interrupt control register 06 ICR06 W,R/W 00000111 B7H Interrupt control register 07 ICR07 W,R/W 00000111 B8H Interrupt control register 08 ICR08 W,R/W 00000111 B9H Interrupt control register 09 ICR09 W,R/W 00000111 BA H Interrupt control register 10 ICR10 W,R/W 00000111 BB H Interrupt control register 11 ICR11 W,R/W 00000111 BC H Interrupt control register 12 ICR12 W,R/W 00000111 BD H Interrupt control register 13 ICR13 W,R/W 00000111 BE H Interrupt control register 14 ICR14 W,R/W 00000111 BF H Interrupt control register 15 ICR15 W,R/W 00000111 C0 H D/A Converter data 0 DAT0 R/W D/A Converter XXXXXXXX C1 H D/A Converter data 1 DAT1 R/W XXXXXXXX C2 H D/A Control 0 DACR0 R/W XXXXXXX0 C3 H D/A Control 1 DACR1 R/W XXXXXXX0 C4 H , C5H Reserved C6 H External Interrupt Enable 0 ENIR0 R/W External Interrupt 0 00000000 C7 H External Interrupt Source 0 EIRR0 R/W XXXXXXXX C8 H External Interrupt Level Setting 0 ELVR0 R/W 00000000 C9 H External Interrupt Level Setting 0 ELVR0 R/W 00000000

(Continued) Address Register Abbrevia- tion Access Resource name Initial value CA H External Interrupt Enable 1 ENIR1 R/W External Interrupt 1 00000000 CB H External Interrupt Source 1 EIRR1 R/W XXXXXXXX CC H External Interrupt Level Setting 1 ELVR1 R/W 00000000 CD H External Interrupt Level Setting 1 ELVR1 R/W 00000000 CE H External Interrupt Source Select EISSR R/W 00000000 CF H PLL/Subclock Control register PSCCR W PLL XXXX0000 D0 H DMA Buffer Addrss Pointer L BAPL R/W DMA XXXXXXXX D1 H DMA Buffer Addrss Pointer M BAPM R/W XXXXXXXX D2 H DMA Buffer Addrss Pointer H BAPH R/W XXXXXXXX D3 H DMA Control DMACS R/W XXXXXXXX D4 H I/O Register Address Pointer L IOAL R/W XXXXXXXX D5 H I/O Register Address Pointer H IOAH R/W XXXXXXXX D6 H Data Counter L DCTL R/W XXXXXXXX D7 H Data Counter H DCTH R/W XXXXXXXX D8 H Serial Mode Register 2 SMR2 W,R/W UART2 00000000 D9 H Serial Control Register 2 SCR2 W,R/W 00000000 DA H Reception/Transmission Data Register 2 RDR2/ TDR2 R/W 00000000 DB H Serial Status Register 2 SSR2 R,R/W 00001000 DC H Extended Communication Control Register 2 ECCR2 R,W, R/W 000000XX DD H Extended Status Control Register 2 ESCR2 R/W 00000100 DE H Baud Rate Generator Register 20 BGR20 R/W 00000000 DF H Baud Rate Generator Register 21 BGR21 R/W 00000000 E0H to EFH Reserved for CAN Interface 2. Refer to “n CAN CONTROLLERS” F0H to FFH External

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 7900H Reload Register L0 PRLL0 R/W 16-bit PPG 0/1 XXXXXXXX 7901H Reload Register H0 PRLH0 R/W XXXXXXXX 7902H Reload Register L1 PRLL1 R/W XXXXXXXX 7903H Reload Register H1 PRLH1 R/W XXXXXXXX 7904H Reload Register L2 PRLL2 R/W 16-bit PPG 2/3 XXXXXXXX 7905H Reload Register H2 PRLH2 R/W XXXXXXXX 7906H Reload Register L3 PRLL3 R/W XXXXXXXX 7907H Reload Register H3 PRLH3 R/W XXXXXXXX 7908H Reload Register L4 PRLL4 R/W 16-bit PPG 4/5 XXXXXXXX 7909H Reload Register H4 PRLH4 R/W XXXXXXXX 790AH Reload Register L5 PRLL5 R/W XXXXXXXX 790BH Reload Register H5 PRLH5 R/W XXXXXXXX 790C H Reload Register L6 PRLL6 R/W 16-bit PPG 6/7 XXXXXXXX 790D H Reload Register H6 PRLH6 R/W XXXXXXXX 790EH Reload Register L7 PRLL7 R/W XXXXXXXX 790FH Reload Register H7 PRLH7 R/W XXXXXXXX 7910H Reload Register L8 PRLL8 R/W 16-bit PPG 8/9 XXXXXXXX 7911H Reload Register H8 PRLH8 R/W XXXXXXXX 7912H Reload Register L9 PRLL9 R/W XXXXXXXX 7913H Reload Register H9 PRLH9 R/W XXXXXXXX 7914H Reload Register LA PRLLA R/W 16-bit PPG A/B XXXXXXXX 7915H Reload Register HA PRLHA R/W XXXXXXXX 7916H Reload Register LB PRLLB R/W XXXXXXXX 7917H Reload Register HB PRLHB R/W XXXXXXXX 7918H Reload Register LC PRLLC R/W 16-bit PPG C/D XXXXXXXX 7919H Reload Register HC PRLHC R/W XXXXXXXX 791AH Reload Register LD PRLLD R/W XXXXXXXX 791BH Reload Register HD PRLHD R/W XXXXXXXX 791C H Reload Register LE PRLLE R/W 16-bit PPG E/F XXXXXXXX 791D H Reload Register HE PRLHE R/W XXXXXXXX 791EH Reload Register LF PRLLF R/W XXXXXXXX 791FH Reload Register HF PRLHF R/W XXXXXXXX 7920H Input Capture 0 IPCP0 R Input Capture 0/1 XXXXXXXX 7921H Input Capture 0 IPCP0 R XXXXXXXX 7922H Input Capture 1 IPCP1 R XXXXXXXX 7923H Input Capture 1 IPCP1 R XXXXXXXX

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 7924H Input Capture 2 IPCP2 R Input Capture 2/3 XXXXXXXX 7925H Input Capture 2 IPCP2 R XXXXXXXX 7926H Input Capture 3 IPCP3 R XXXXXXXX 7927H Input Capture 3 IPCP3 R XXXXXXXX 7928H Input Capture 4 IPCP4 R Input Capture 4/5 XXXXXXXX 7929H Input Capture 4 IPCP4 R XXXXXXXX 792AH Input Capture 5 IPCP5 R XXXXXXXX 792BH Input Capture 5 IPCP5 R XXXXXXXX 792C H Input Capture 6 IPCP6 R Input Capture 6/7 XXXXXXXX 792D H Input Capture 6 IPCP6 R XXXXXXXX 792EH Input Capture 7 IPCP7 R XXXXXXXX 792FH Input Capture 7 IPCP7 R XXXXXXXX 7930H Output Compare 0 OCCP0 R/W Output Compare 0/1 XXXXXXXX 7931H Output Compare 0 OCCP0 R/W XXXXXXXX 7932H Output Compare 1 OCCP1 R/W XXXXXXXX 7933H Output Compare 1 OCCP1 R/W XXXXXXXX 7934H Output Compare 2 OCCP2 R/W Output Compare 2/3 XXXXXXXX 7935H Output Compare 2 OCCP2 R/W XXXXXXXX 7936H Output Compare 3 OCCP3 R/W XXXXXXXX 7937H Output Compare 3 OCCP3 R/W XXXXXXXX 7938H Output Compare 4 OCCP4 R/W Output Compare 4/5 XXXXXXXX 7939H Output Compare 4 OCCP4 R/W XXXXXXXX 793AH Output Compare 5 OCCP5 R/W XXXXXXXX 793BH Output Compare 5 OCCP5 R/W XXXXXXXX 793C H Output Compare 6 OCCP6 R/W Output Compare 6/7 XXXXXXXX 793D H Output Compare 6 OCCP6 R/W XXXXXXXX 793EH Output Compare 7 OCCP7 R/W XXXXXXXX 793FH Output Compare 7 OCCP7 R/W XXXXXXXX 7940H Timer Data 0 TCDT0 R/W I/O Timer 0 00000000 7941H Timer Data 0 TCDT0 R/W 00000000 7942H Timer Control Status 0 TCCSL0 R/W 00000000 7943H Timer Control Status 0 TCCSH0 R/W 0XXXXXXX 7944H Timer Data 1 TCDT1 R/W I/O Timer 1 00000000 7945H Timer Data 1 TCDT1 R/W 00000000 7946H Timer Control Status 1 TCCSL1 R/W 00000000 7947H Timer Control Status 1 TCCSH1 R/W 0XXXXXXX

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 7948H Timer 0/Reload 0 TMR0/ TMRLR0 R/W 16-bit Reload Timer 0 XXXXXXXX 7949H R/W XXXXXXXX 794AH Timer 1/Reload 1 TMR1/ TMRLR1 R/W 16-bit Reload Timer 1 XXXXXXXX 794BH R/W XXXXXXXX 794C H Timer 2/Reload 2 TMR2/ TMRLR2 R/W 16-bit Reload Timer 2 XXXXXXXX 794D H R/W XXXXXXXX 794EH Timer 3/Reload 3 TMR3/ TMRLR3 R/W 16-bit Reload Timer 3 XXXXXXXX 794FH R/W XXXXXXXX 7950H Serial Mode Register 3 SMR3 W,R/W UART3 00000000 7951H Serial Control Register 3 SCR3 W,R/W 00000000 7952H Reception/Transmission Data Register 3 RDR3/ TDR3 R/W 00000000 7953H Serial Status Register 3 SSR3 R,R/W 00001000 7954H Extended Communication Control Register 3 ECCR3 R,W, R/W 000000XX 7955H Extended Status Control Register ESCR3 R/W 00000100 7956H Baud Rate Generator Register 30 BGR30 R/W 00000000 7957H Baud Rate Generator Register 31 BGR31 R/W 00000000 7958H Serial Mode Register 4 SMR4 W,R/W UART4 00000000 7959H Serial Control Register 4 SCR4 W,R/W 00000000 795AH Reception/Transmission Data Register 4 RDR4/ TDR4 R/W 00000000 795BH Serial Status Register 4 SSR4 R,R/W 00001000 795C H Extended Communication Control Register 4 ECCR4 R,W, R/W 000000XX 795D H Extended Status Control Register ESCR4 R/W 00000100 795EH Baud Rate Generator Register 40 BGR40 R/W 00000000 795FH Baud Rate generator Register 41 BGR41 R/W 00000000 7960H to 796BH Reserved 796C H Clock output enable register CLKR R/W Clock Monitor XXXX0000 796D H Reserved 796EH CAN Direct Mode Register CDMR R/W CAN clock sync XXXXXXX0 796FH CAN switch register CANSWR R/W CAN 0/1 XXXXXX00

(Continued) Address Register Abbrevia- tion Access Resource name Initial value 7970H I2C bus status register 0 IBSR0 R I2C Interface 0 00000000 7971H I2C bus control register 0 IBCR0 W,R/W 00000000 7972H I2C 10 bit slave address register 0 ITBAL0 R/W 00000000 7973H ITBAH0 R/W 00000000 7974H I2C 10 bit slave address mask register 0 ITMKL0 R/W 11111111 7975H ITMKH0 R/W 00111111 7976H I2C 7 bit slave address register 0 ISBA0 R/W 00000000 7977H I2C 7 bit slave address mask register 0 ISMK0 R/W 01111111 7978H I2C data register 0 IDAR0 R/W 00000000 7979H , 797AH Reserved 797BH I2C clock control register 0 ICCR0 R/W I 2C Interface 0 00011111 797C H to 797FH Reserved 7980H I2C bus status register 1 IBSR1 R I2C Interface 1 00000000 7981H I2C bus control register 1 IBCR1 W,R/W 00000000 7982H I2C 10 bit slave address register 1 ITBAL1 R/W 00000000 7983H ITBAH1 R/W 00000000 7984H I2C 10 bit slave address mask register 1 ITMKL1 R/W 11111111 7985H ITMKH1 R/W 00111111 7986H I2C 7 bit slave address register 1 ISBA1 R/W 00000000 7987H I2C 7 bit slave address mask register 1 ISMK1 R/W 01111111 7988H I2C data register 1 IDAR1 R/W 00000000 7989H , 798AH Reserved 798BH I2C clock control register 1 ICCR1 R/W I 2C Interface 1 00011111 798C H to 79C1 H Reserved 79C2 H Clock Modulator Control Register CMCR R,R/W Clock Modulator 0001X000 79C3 H to 79DF H Reserved

(Continued) Notes : • Initial value of “X” represents unknown value.

• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. Address Register Abbrevia- tion Access Resource name Initial value 79E0H Detect Address Setting 0 PADR0 R/W Address Match Detection 0 XXXXXXXX 79E1H Detect Address Setting 0 PADR0 R/W XXXXXXXX 79E2H Detect Address Setting 0 PADR0 R/W XXXXXXXX 79E3H Detect Address Setting 1 PADR1 R/W XXXXXXXX 79E4H Detect Address Setting 1 PADR1 R/W XXXXXXXX 79E5H Detect Address Setting 1 PADR1 R/W XXXXXXXX 79E6H Detect Address Setting 2 PADR2 R/W XXXXXXXX 79E7H Detect Address Setting 2 PADR2 R/W XXXXXXXX 79E8H Detect Address Setting 2 PADR2 R/W XXXXXXXX 79E9H to 79EF H Reserved 79F0H Detect Address Setting 3 PADR3 R/W Address Match Detection 1 XXXXXXXX 79F1H Detect Address Setting 3 PADR3 R/W XXXXXXXX 79F2H Detect Address Setting 3 PADR3 R/W XXXXXXXX 79F3H Detect Address Setting 4 PADR4 R/W XXXXXXXX 79F4H Detect Address Setting 4 PADR4 R/W XXXXXXXX 79F5H Detect Address Setting 4 PADR4 R/W XXXXXXXX 79F6H Detect Address Setting 5 PADR5 R/W XXXXXXXX 79F7H Detect Address Setting 5 PADR5 R/W XXXXXXXX 79F8H Detect Address Setting 5 PADR5 R/W XXXXXXXX 79F9H to 79FFH Reserved 7A00H to 7AFF H Reserved for CAN Interface 0. Refer to “n CAN CONTROLLERS” 7B00H to 7BFF H Reserved for CAN Interface 0. Refer to “n CAN CONTROLLERS” 7C00 H to 7CFF H Reserved for CAN Interface 1. Refer to “n CAN CONTROLLERS” 7D00 H to 7DFF H Reserved for CAN Interface 1. Refer to “n CAN CONTROLLERS” 7E00H to 7EFF H Reserved for CAN Interface 2. Refer to “n CAN CONTROLLERS” 7F00H to 7FFF H Reserved for CAN Interface 2. Refer to “n CAN CONTROLLERS”

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask
• T wo acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz) List of Control Registers (1) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 000070H 000080H 0000E0H Message buffer valid register BVALR R/W 00000000 00000000000071H 000081H 0000E1H 000072H 000082H 0000E2H Transmit request register TREQR R/W 00000000 00000000000073H 000083H 0000E3H 000074H 000084H 0000E4H Transmit cancel register TCANR W 00000000 00000000000075H 000085H 0000E5H 000076H 000086H 0000E6H Transmission complete register TCR R/W 00000000 00000000000077H 000087H 0000E7H 000078H 000088H 0000E8H Receive complete register RCR R/W 00000000 00000000000079H 000089H 0000E9H 00007AH 00008AH 0000EA H Remote request receiving register RRTRR R/W 00000000 0000000000007BH 00008BH 0000EB H 00007C H 00008C H 0000EC H Receive overrun register ROVRR R/W 00000000 0000000000007D H 00008D H 0000ED H 00007EH 00008EH 0000EE H Reception interrupt enable register RIER R/W 00000000 0000000000007FH 00008FH 0000EF H

List of Control Registers (2) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007B00H 007D00 H 007F00H Control status register CSR R/W, W R/W, R 0XXXX0X1 00XXX000007B01H 007D01 H 007F01H 007B02H 007D02 H 007F02H Last event indicator register LEIR R/W 000X0000 XXXXXXXX007B03H 007D03 H 007F03H 007B04H 007D04 H 007F04H Receive and transmit error counter RTEC R 00000000 00000000007B05H 007D05 H 007F05H 007B06H 007D06 H 007F06H Bit timing register BTR R/W 11111111 X1111111007B07H 007D07 H 007F07H 007B08H 007D08 H 007F08H IDE register IDER R/W XXXXXXXX XXXXXXXX007B09H 007D09 H 007F09H 007B0A H 007D0A H 007F0A H Transmit RTR register TRTRR R/W 00000000 00000000007B0B H 007D0B H 007F0B H 007B0C H 007D0C H 007F0C H Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX007B0D H 007D0D H 007F0D H 007B0E H 007D0E H 007F0E H Transmit interrupt enable register TIER R/W 00000000 00000000007B0F H 007D0F H 007F0FH 007B10H 007D10 H 007F10H Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX007B11H 007D11 H 007F11H 007B12H 007D12 H 007F12H XXXXXXXX XXXXXXXX007B13H 007D13 H 007F13H 007B14H 007D14 H 007F14H Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX007B15H 007D15 H 007F15H 007B16H 007D16 H 007F16H XXXXXXXX XXXXXXXX007B17H 007D17 H 007F17H 007B18H 007D18 H 007F18H Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX007B19H 007D19 H 007F19H 007B1A H 007D1A H 007F1A H XXXXXXXX XXXXXXXX007B1B H 007D1B H 007F1B H

List of Message Buffers (ID Registers) (1) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007A00H to 007A1F H 007C00 H to 007C1F H 007E00H to 007E1F H General- purpose RAM ¾ R/W XXXXXXXX to XXXXXXXX 007A20H 007C20 H 007E20H ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX007A21H 007C21 H 007E21H 007A22H 007C22 H 007E22H XXXXXXXX XXXXXXXX007A23H 007C23 H 007E23H 007A24H 007C24 H 007E24H ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX007A25H 007C25 H 007E25H 007A26H 007C26 H 007E26H XXXXXXXX XXXXXXXX007A27H 007C27 H 007E27H 007A28H 007C28 H 007E28H ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX007A29H 007C29 H 007E29H 007A2A H 007C2A H 007E2A H XXXXXXXX XXXXXXXX007A2B H 007C2B H 007E2B H 007A2C H 007C2C H 007E2C H ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX007A2D H 007C2D H 007E2D H 007A2E H 007C2E H 007E2E H XXXXXXXX XXXXXXXX007A2F H 007C2F H 007E2F H 007A30H 007C30 H 007E30H ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX007A31H 007C31 H 007E31H 007A32H 007C32 H 007E32H XXXXXXXX XXXXXXXX007A33H 007C33 H 007E33H 007A34H 007C34 H 007E34H ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX007A35H 007C35 H 007E35H 007A36H 007C36 H 007E36H XXXXXXXX XXXXXXXX007A37H 007C37 H 007E37H 007A38H 007C38 H 007E38H ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX007A39H 007C39 H 007E39H 007A3A H 007C3A H 007E3A H XXXXXXXX XXXXXXXX007A3B H 007C3B H 007E3B H 007A3C H 007C3C H 007E3C H ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX007A3D H 007C3D H 007E3D H 007A3E H 007C3E H 007E3E H XXXXXXXX XXXXXXXX007A3F H 007C3F H 007E3F H

List of Message Buffers (ID Registers) (2) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007A40H 007C40 H 007E40H ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX007A41H 007C41 H 007E41H 007A42H 007C42 H 007E42H XXXXXXXX XXXXXXXX007A43H 007C43 H 007E43H 007A44H 007C44 H 007E44H ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX007A45H 007C45 H 007E45H 007A46H 007C46 H 007E46H XXXXXXXX XXXXXXXX007A47H 007C47 H 007E47H 007A48H 007C48 H 007E48H ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX007A49H 007C49 H 007E49H 007A4A H 007C4A H 007E4A H XXXXXXXX XXXXXXXX007A4B H 007C4B H 007E4B H 007A4C H 007C4C H 007E4C H ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX007A4D H 007C4D H 007E4D H 007A4E H 007C4E H 007E4E H XXXXXXXX XXXXXXXX007A4F H 007C4F H 007E4F H 007A50H 007C50 H 007E50H ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX007A51H 007C51 H 007E51H 007A52H 007C52 H 007E52H XXXXXXXX XXXXXXXX007A53H 007C53 H 007E53H 007A54H 007C54 H 007E54H ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX007A55H 007C55 H 007E55H 007A56H 007C56 H 007E56H XXXXXXXX XXXXXXXX007A57H 007C57 H 007E57H 007A58H 007C58 H 007E58H ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX007A59H 007C59 H 007E59H 007A5A H 007C5A H 007E5A H XXXXXXXX XXXXXXXX007A5B H 007C5B H 007E5B H 007A5C H 007C5C H 007E5C H ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX007A5D H 007C5D H 007E5D H 007A5E H 007C5E H 007E5E H XXXXXXXX XXXXXXXX007A5F H 007C5F H 007E5F H

List of Message Buffers (DLC Registers and Data Registers) (1) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007A60H 007C60 H 007E60H DLC register 0 DLCR0 R/W XXXXXXXX 007A61H 007C61 H 007E61H 007A62H 007C62 H 007E62H DLC register 1 DLCR1 R/W XXXXXXXX 007A63H 007C63 H 007E63H 007A64H 007C64 H 007E64H DLC register 2 DLCR2 R/W XXXXXXXX 007A65H 007C65 H 007E65H 007A66H 007C66 H 007E66H DLC register 3 DLCR3 R/W XXXXXXXX 007A67H 007C67 H 007E67H 007A68H 007C68 H 007E68H DLC register 4 DLCR4 R/W XXXXXXXX 007A69H 007C69 H 007E69H 007A6A H 007C6A H 007E6A H DLC register 5 DLCR5 R/W XXXXXXXX 007A6B H 007C6B H 007E6B H 007A6C H 007C6C H 007E6C H DLC register 6 DLCR6 R/W XXXXXXXX 007A6D H 007C6D H 007E6D H 007A6E H 007C6E H 007E6E H DLC register 7 DLCR7 R/W XXXXXXXX 007A6F H 007C6F H 007E6F H 007A70H 007C70 H 007E70H DLC register 8 DLCR8 R/W XXXXXXXX 007A71H 007C71 H 007E71H 007A72H 007C72 H 007E72H DLC register 9 DLCR9 R/W XXXXXXXX 007A73H 007C73 H 007E73H 007A74H 007C74 H 007E74H DLC register 10 DLCR10 R/W XXXXXXXX 007A75H 007C75 H 007E75H 007A76H 007C76 H 007E76H DLC register 11 DLCR11 R/W XXXXXXXX 007A77H 007C77 H 007E77H 007A78H 007C78 H 007E78H DLC register 12 DLCR12 R/W XXXXXXXX 007A79H 007C79 H 007E79H 007A7A H 007C7A H 007E7A H DLC register 13 DLCR13 R/W XXXXXXXX 007A7B H 007C7B H 007E7B H 007A7C H 007C7C H 007E7C H DLC register 14 DLCR14 R/W XXXXXXXX 007A7D H 007C7D H 007E7D H 007A7E H 007C7E H 007E7E H DLC register 15 DLCR15 R/W XXXXXXXX 007A7F H 007C7F H 007E7F H

List of Message Buffers (DLC Registers and Data Registers) (2) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007A80H to 007A87H 007C80 H to 007C87 H 007E80H to 007E87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 007A88H to 007A8F H 007C88 H to 007C8F H 007E88H to 007E8F H Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 007A90H to 007A97H 007C90 H to 007C97 H 007E90H to 007E97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 007A98H to 007A9F H 007C98 H to 007C9F H 007E98H to 007E9F H Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 007AA0 H to 007AA7 H 007CA0 H to 007CA7 H 007EA0 H to 007EA7 H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 007AA8 H to 007AAF H 007CA8 H to 007CAF H 007EA8 H to 007EAF H Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 007AB0 H to 007AB7 H 007CB0 H to 007CB7 H 007EB0 H to 007EB7 H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 007AB8 H to 007ABF H 007CB8 H to 007CBF H 007EB8 H to 007EBF H Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 007AC0 H to 007AC7 H 007CC0 H to 007CC7 H 007EC0 H to 007EC7 H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 007AC8 H to 007ACF H 007CC8 H to 007CCF H 007EC8 H to 007ECF H Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 007AD0 H to 007AD7 H 007CD0 H to 007CD7 H 007ED0 H to 007ED7 H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 007AD8 H to 007ADF H 007CD8 H to 007CDF H 007ED8 H to 007EDF H Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 007AE0 H to 007AE7 H 007CE0 H to 007CE7 H 007EE0 H to 007EE7 H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 007AE8 H to 007AEF H 007CE8 H to 007CEF H 007EE8 H to 007EEF H Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX

List of Message Buffers (DLC Registers and Data Registers) (3) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 007AF0 H to 007AF7 H 007CF0 H to 007CF7 H 007EF0 H to 007EF7 H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 007AF8 H to 007AFF H 007CF8 H to 007CFF H 007EF8 H to 007EFF H Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX

n INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER (Continued) Interrupt cause EI2OS clear DMA ch number Interrupt vector Interrupt control register Number Address Number Address Reset N ¾ #08 FFFFDC H ¾¾ INT9 instruction N ¾ #09 FFFFD8 H ¾¾ Exception N ¾ #10 FFFFD4 H ¾¾ CAN 0 RX N ¾ #11 FFFFD0 H ICR00 0000B0 H CAN 0 TX/NS N ¾ #12 FFFFCC H CAN 1 RX / Input Capture 6 Y1 ¾ #13 FFFFC8 H ICR01 0000B1 H CAN 1 TX/NS / Input Capture 7 Y1 ¾ #14 FFFFC4 H CAN 2 RX / I2C0 N ¾ #15 FFFFC0 H ICR02 0000B2 H CAN 2 TX/NS N ¾ #16 FFFFBC H 16-bit Reload Timer 0 Y1 0 #17 FFFFB8 H ICR03 0000B3 H 16-bit Reload Timer 1 Y1 1 #18 FFFFB4 H 16-bit Reload Timer 2 Y1 2 #19 FFFFB0 H ICR04 0000B4 H 16-bit Reload Timer 3 Y1 ¾ #20 FFFFAC H PPG 0/1/4/5 N ¾ #21 FFFFA8 H ICR05 0000B5 H PPG 2/3/6/7 N ¾ #22 FFFFA4 H PPG 8/9/C/D N ¾ #23 FFFFA0 H ICR06 0000B6 H PPG A/B/E/F N ¾ #24 FFFF9C H Time Base Timer N ¾ #25 FFFF98 H ICR07 0000B7 H External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94 H Watch Timer N ¾ #27 FFFF90 H ICR08 0000B8 H External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8C H A/D Converter Y1 5 #29 FFFF88 H ICR09 0000B9 H I/O Timer 0 / I/O Timer 1 N ¾ #30 FFFF84 H Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80 H ICR10 0000BA H Output Compare 0/1/4/5 Y1 7 #32 FFFF7C H Input Capture 0 to 3 Y1 8 #33 FFFF78 H ICR11 0000BB H Output Compare 2/3/6/7 Y1 9 #34 FFFF74 H UART 0 RX Y2 10 #35 FFFF70 H ICR12 0000BC H UART 0 TX Y1 11 #36 FFFF6C H UART 1 RX / UART 3 RX Y2 12 #37 FFFF68 H ICR13 0000BD H UART 1 TX / UART 3 TX Y1 13 #38 FFFF64 H

(Continued) Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O Service, the other one cannot use interrupts. Interrupt cause EI2OS clear DMA ch number Interrupt vector Interrupt control register Number Address Number Address UART 2 RX / UART 4 RX Y2 14 #39 FFFF60 H ICR14 0000BE H UART 2 TX / UART 4 TX Y1 15 #40 FFFF5C H Flash Memory N ¾ #41 FFFF58 H ICR15 0000BF H Delayed interrupt N ¾ #42 FFFF54 H

n ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0 V) (Continued) Parameter Symbol Rating Unit Remarks Min Max Power supply voltage VCC VSS - 0.3 V SS + 6.0 V AV CC VSS - 0.3 V SS + 6.0 V V CC = AVCC *1 AVRH, AVRL VSS - 0.3 V SS + 6.0 V AV CC ‡ AVRH, AVCC ‡ AVRL, AVRH ‡ AVRL Input voltage V I VSS - 0.3 V SS + 6.0 V *2 Output voltage V O VSS - 0.3 V SS + 6.0 V *2 Maximum Clamp Current I CLAMP -4.0 +4.0 mA *4 Total Maximum Clamp Current S|ICLAMP | ¾ 40 mA *4 “L” level maximum output current I OL ¾ 15 mA *3 “L” level average output current I OLAV ¾ 4m A * 3 “L” level maximum overall output currentSIOL ¾ 100 mA *3 “L” level average overall output currentSIOLAV ¾ 50 mA *3 “H” level maximum output current I OH ¾- 15 mA *3 “H” level average output current I OHAV ¾- 4m A * 3 “H” level maximum overall output currentSIOH ¾- 100 mA *3 “H” level average overall output currentSIOHAV ¾- 50 mA *3 Power consumption P D ¾ 340 mW MB90F347 Operating temperature T A -40 +105 °C Storage temperature T STG -55 +150 °C

(Continued) *1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V . VI should not exceed the specified ratings. However if the maximun current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3: Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P A0 to P A1 *4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 (EVA device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA 0 t o PA 1

• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the V CC pin, and this may affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits: WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. P-ch N-ch VCC R
• Input/output equivalent circuits +B input (0 V to 16 V) Limiting resistance Protective diode

1. Recommended Conditions (VSS = AVSS = 0 V) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Remarks Min Typ Max Power supply voltage V CC , AV CC 4.0 5.0 5.5 V Under normal operation 3.5 5.0 5.5 V Under normal operation, when not using the A/D converter and not Flash programming. 4.5 5.0 5.5 V When External bus is used. 3.0 ¾ 5.5 V Maintains RAM data in stop mode Smooth capacitor C S 0.1 ¾ 1.0 mF Use a ceramic capacitor or capac- itor of better AC characteristics. Capacitor at the V CC should be greater than this capacitor. Operating temperature T A -40 ¾+ 105 °C C C S C Pin Connection Diagram

1. DC Characteristics (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0 V) (Continued) Parameter Sym- bol Pin Condition Value Unit RemarksMin Typ Max Input H voltage (At V CC =

5 V – 10% )

VIHS ¾¾ 0.8 VCC ¾ VCC + 0.3 V Port inputs if CMOS hysteresis input levels are selected (except P12, P44, P45, P46, P47, P50, P82, P83) V IHA ¾¾ 0.8 VCC ¾ VCC + 0.3 V Port inputs if AUTOMOTIVE input levels are selected VIHT ¾¾ 2.0 ¾ VCC + 0.3 V Port inputs if TTL input levels are selected VIHS ¾¾ 0.7 VCC ¾ VCC + 0.3 V P12, P50, P82, P85 inputs if CMOS input levels are selected VIHI ¾¾ 0.7 VCC ¾ VCC + 0.3 V P44, P45, P46, P47 in- puts if CMOS hysteresis input levels are selected V IHR ¾¾ 0.8 VCC ¾ VCC + 0.3 V RST input pin (CMOS hysteresis) VIHM ¾¾ VCC - 0.3 ¾ VCC + 0.3 V MD input pin Input L voltage (At VCC = VILS ¾¾ VSS - 0.3 ¾ 0.2 VCC V Port inputs if CMOS hysteresis input levels are selected (except P12, P44, P45, P46, P47, P50, P82, P83) V ILA ¾¾ VSS - 0.3 ¾ 0.5 VCC V Port inputs if AUTOMOTIVE input levels are selected V ILT ¾¾ VSS - 0.3 ¾ 0.8 V Port inputs if TTL input levels are selected VILS ¾¾ VSS - 0.3 ¾ 0.3 VCC V P12, P50, P82, P85 inputs if CMOS input levels are selected V ILI ¾¾ VSS - 0.3 ¾ 0.3 VCC V P44, P45, P46, P47 in- puts if CMOS hysteresis input levels are selected VILR ¾¾ VSS - 0.3 ¾ 0.2 VCC V RST input pin (CMOS hysteresis) VILM ¾¾ VSS - 0.3 ¾ VSS + 0.3 V MD input pin Output H voltage VOH Normal outputs VCC = 4.5 V, IOH = -4.0 mA VCC - 0.5 ¾¾ V Output H voltage VOHI I2C current outputs VCC = 4.5 V, IOH = -3.0 mA VCC - 0.5 ¾¾ V Output L voltage VOL Normal outputs VCC = 4.5 V, IOL = 4.0 mA ¾¾ 0.4 V Output L voltage VOLI I2C current outputs VCC = 4.5 V, IOL = 3.0 mA ¾¾ 0.4 V

(Continued) (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0 V) * : The power supply current is measured with an external clock. Parameter Sym- bol Pin Condition Value Unit RemarksMin Typ Max Input leak current IIL ¾ VCC = 5.5 V, VSS < VI < VCC -1 ¾ 1 mA Pull-up resistance R UP P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST ¾ 25 50 100 k W Pull-down resistance R DOWN MD2 ¾ 25 50 100 k W Except Flash devices Power supply current* ICC VCC VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. ¾ 55 70 mA V CC = 5.0 V, Internal frequency : 24 MHz, At writing FLASH memory. ¾ 70 85 mA Flash devices VCC = 5.0 V, Internal frequency : 24 MHz, At erasing FLASH memory. ¾ 75 90 mA Flash devices ICCS VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. ¾ 25 35 mA I CTS VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timer mode ¾ 0.3 0.8 mA ICTSPLL6 VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timer mode, external frequency = 4 MHz ¾ 47 m A I CCL VCC = 5.0V Internal frequency: 8 kHz, At sub operation T A = +25°C ¾ 70 140 mA ICCLS VCC = 5.0V Internal frequency: 8 kHz, At sub sleep T A = +25°C ¾ 20 50 mA ICCT VCC = 5.0V Internal frequency: 8 kHz, At watch mode T A = +25°C ¾ 10 35 mA ICCH VCC = 5.0 V, At Stop mode, T A = +25°C ¾ 72 5 mA Input capacity C IN Other than C, AV CC , AVSS , AVRH, AVRL, VCC , VSS , ¾¾ 51 5 p F

1. AC Characteristics (1) Clock Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0 V) * : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned in “Relation among external clock frequency and machine clock frequency”. Parameter Symbol Pin Value Unit Remarks Min Typ Max Clock frequency fC X0, X1 3 ¾ 16 MHz When using an oscillation circuit X0, X1 3 ¾ 24 MHz When using an external clock* fCL X0A, X1A — 32.768 100 kHz Clock cycle time tCYL X0, X1 62.5 ¾ 333 ns When using an oscillation circuit X0, X1 41.67 ¾ 333 ns When using an external clock tCYLL X0A, X1A 10 30.5 — ms Input clock pulse width PWH , PWL X0 10 ¾¾ ns Duty ratio is about 30% to 70% .PWHL , PWLL X0A 5 15.2 ¾m s Input clock rise and fall time tCR , tCF X0 ¾¾ 5 ns When using external clock Internal operating clock frequency (machine clock) fCP ¾ 1.5 ¾ 24 MHz When using main clock fCPL ¾¾ 8.192 50 kHz When using sub clock Internal operating clock cycle time (machine clock) tCP ¾ 41.67 ¾ 666 ns When using main clock tCPL ¾ 20 122.1 ¾m s When using sub clock tCYL tCF tCR

0.8 VCC

0.2 VCC

Guaranteed operation range of MB90340 series * : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz External clock frequency and Machine clock frequency 5.5 3.5 1.5 4 Power supply voltage VCC (V) Guaranteed operation range Guaranteed PLL operation range 4.0 Guaranteed A/D Converter operation range Machine clock fCP (MHz) 4.0 3 4 12 24 Internal clock fCP (MHz) External clock fC (MHz) * x 4 x 3 x 2 x 1 x 1/2 (PLL off) Guaranteed oscillation frequency range 1.5 x 6

(2) Reset Standby Input (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0.0 V) * : Oscillation time of oscillator is the time that the amplitude reaches 90% . In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of ms to several ms. With an external clock, the oscillation time is 0 ms. Parameter Symbol Pin Value Unit Remarks Min Max Reset input time t RSTL RST 500 ¾ ns Under normal operation Oscillation time of oscillator* + 100 ms ¾ ns In Stop mode, Sub Clock mode, Sub Sleep mode and Watch mode 100 ¾m s In Time Timer mode tRSTL 0.2 VCC 0.2 VCC 100 ms RST 90% of amplitude Instruction execution Oscillation stabilization waiting time Oscillation time of oscillator Internal operation clock Internal reset Under normal operation: In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

(3) Power On Reset (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0.0 V) (4) Clock Output Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Parameter Symbol Pin Condition Value Unit Remarks Min Max Power on rise time tR VCC 0.05 30 ms Power off time t OFF VCC 1 ¾ ms Due to repetitive operation Parameter Symbol Pin Condition Value Unit Remarks Min Max Cycle time t CYC CLK ¾ 62.5 ¾ ns f CP = 16 MHz 41.76 ¾ ns f CP = 24 MHz CLK › fi CLK fl tCHCL CLK ¾ 20 ¾ ns f CP = 16 MHz 13 ¾ ns f CP = 24 MHz VCC VCC VSS 3 V tR tOFF 2.7 V 0.2 V 0.2 V0.2 V Holds RAM data If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. We recommend a rise of 50 mV/ms maximum. CLK 2.4 V tCYC 2.4 V 0.8 V tCHCL

(5) Bus Timing (Read) (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Parameter Sym- bol Pin Condition Value Unit RemarksMin Max ALE pulse width t LHLL ALE tCP /2 - 10 ¾ ns Valid address Þ ALE fl time tAVLL ALE, A23 to A16, AD15 to AD00 tCP /2 - 20 ¾ ns ALE fl Þ Address valid time tLLAX ALE, AD15 to AD00 t CP /2 - 15 ¾ ns Valid address Þ RD fl time tAVRL A23 to A16, AD15 to AD00, RD tCP - 15 ¾ ns Valid address Þ Valid data input tAVDV A23 to A16, AD15 to AD00 ¾ 5 tCP /2 - 60 ns RD pulse width t RLRH RD 3 tCP /2 - 20 ¾ ns RD fl Þ Valid data input tRLDV RD , AD15 to AD00 ¾ 3 tCP /2 - 50 ns RD › Þ Data hold time t RHDX RD , AD15 to AD00 0 ¾ ns RD fl Þ ALE › time t RHLH RD , ALE t CP /2 - 15 ¾ ns RD › Þ Address valid time tRHAX RD , A23 to A16 t CP /2 - 10 ¾ ns Valid address Þ CLK › time tAVCH A23 to A16, AD15 to AD00, CLK tCP /2 - 16 ¾ ns RD fl Þ CLK › time t RLCH RD , CLK t CP /2 - 15 ¾ ns ALE fl Þ RD fl time t LLRL ALE, RD tCP /2 - 15 ¾ ns A23 to A16 0.8 V 2.4 V2.4 V 0.8 V tRHAX AD15 to AD00 0.8 V 2.4 V 2.4 V 0.8 V Address VIL VIH VIH VIL Read data tRHDX tRLDV tAVDV CLK tAVCH 2.4 V tRLCH 2.4 V ALE 2.4 V tLHLL 2.4 V tRHLH 0.8 V tLLAX 2.4 V tAVLL RD tLLRL tRLRH 0.8 V 2.4 V tAVRL

(6) Bus Timing (Write) (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Parameter Symbol Pin Condition Value Unit Remarks Min Max Valid address Þ WR fl time tAVWL A23 to A16, AD15 to AD00, WR tCP -15 ¾ ns WR pulse width t WLWH WR 3 tCP /2 - 20 ¾ ns Valid data output Þ WR › time tDVWH AD15 to AD00, WR 3 tCP /2 - 20 ¾ ns WR › Þ Data hold time t WHDX AD15 to AD00, WR 15 ¾ ns WR › Þ Address valid time tWHAX A23 to A16, WR tCP /2 - 10 ¾ ns WR › Þ ALE › time t WHLH WR , ALE t CP /2 - 15 ¾ ns WR fl Þ CLK › time t WLCH WR , CLK t CP /2 - 15 ¾ ns CLK tWLCH 2.4 V ALE tWHLH 2.4 V WR (WRL, WRH) tWLWH 0.8 V 2.4 V tAVWL A23 to A16 0.8 V 2.4 V2.4 V 0.8 V tWHAX AD15 to AD00 2.4 V 0.8 V Address 0.8 V 2.4 V Write data tDVWH 0.8 V 2.4 V tWHDX

(7) Ready Input Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Note : If the RDY setup time is insufficient, use the auto-ready function. Parameter Sym- bol Pin Test Condition Rated Value Units Remarks Min Max RDY setup time t RYHS RDY 45 ¾ ns f CP = 16 MHz 32 ¾ ns f CP = 24 MHz RDY hold time t RYHH RDY 0 ¾ ns CLK 2.4 V ALE RD/WR RDY When WAIT is not used. VIH VIH tRYHH RDY When WAIT is used. tRYHS VIL

(8) Hold Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed. Parameter Symbol Pin Condition Value Units Remarks Min Max Pin floating Þ HAK fl time tXHAL HAK 30 t CP ns HAK › time Þ Pin valid time tHAHV HAK tCP 2 tCP ns HAK Each pin High-Z tHAHVtXHAL 2.4 V 0.8 V 2.4 V 2.4 V 0.8 V 0.8 V

(9) UART0/1/2/3/4 (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , VSS = 0.0 V, fCP £ 24 MHz) Notes : • AC characteristic in CLK synchronized mode.

• C L is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns) Parameter Symbol Pin Condition Value Unit Remarks Min Max Serial clock cycle time t SCYC SCK0 to SCK4 Internal clock operation output pins are C L = 80 pF + 1 TTL. 8 tCP ¾ ns SCK fl fi SOT delay time t SLOV SCK0 to SCK4, SOT0 to SOT4 -80 +80 ns Valid SIN fi SCK › tIVSH SCK0 to SCK4, SIN0 to SIN4 100 ¾ ns SCK › fi Valid SIN hold time tSHIX SCK0 to SCK4, SIN0 to SIN4 60 ¾ ns Serial clock “H” pulse width tSHSL SCK0 to SCK4 External clock operation output pins are C L = 80 pF + 1 TTL. 4 tCP ¾ ns Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 t CP ¾ ns SCK fl fi SOT delay time t SLOV SCK0 to SCK4, SOT0 to SOT4 ¾ 150 ns Valid SIN fi SCK › tIVSH SCK0 to SCK4, SIN0 to SIN4 60 ¾ ns SCK › fi Valid SIN hold time tSHIX SCK0 to SCK4, SIN0 to SIN4 60 ¾ ns Internal Shift Clock Mode SCK 2.4 V tSCYC 0.8 V SOT 0.8 V 2.4 V 0.8 V tSLOV SIN VIL VIH tIVSH VIL VIH tSHIX

(10) Trigger Input Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = 0.0 V) Parameter Symbol Pin Condition Value Unit Remarks Min Max Input pulse width tTRGH tTRGL INT0 to INT15, INT0R to INT15R, ADTG ¾ 5 tCP ¾ ns External Shift Clock Mode SCK VIH tSLSH VIL SOT 0.8 V 2.4 V tSLOV SIN VIL VIH tIVSH VIL VIH tSHIX VIH VIL tSHSL VIL VIH tTRGH VIL VIH tTRGL INT0 to INT15, INT0R to INT15R, ADTG

(11) Timer Related Resource Input Timing (TA = -40 °C to +105 °C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = 0 V) (12) Timer Related Resource Output Timing (TA = –40°C to +105°C, VCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = 0.0 V) Parameter Symbol Pin Condition Value Unit Remarks Min Max Input pulse width tTIWH TIN0 to TIN3, IN0 to IN7 ¾ 4 tCP ¾ ns tTIWL Parameter Symbol Pin Condition Value Unit Remarks Min Max CLK › Þ TOUT change time tTO TOT0 to TOT3, PPG0 to PPGF ¾ 30 ¾ ns VIL VIH tTIWH VIL VIH tTIWL TIN0 to TIN3, IN0 to IN7 CLK 2.4 V 0.8 V 2.4 V tTO TOT0 to TOT3, PPG0 to PPGF

(13) I2C Timing (TA = –40°C to +105°C, VCC = 5.0 V – 10% , VSS = 0.0 V) *1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDA T have only to be met if the device does not stretch the “L” width (tLOW ) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDA T ‡ 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. Parameter Symbol Condition Standard-mode Fast-mode*4 Unit Min Max Min Max SCL clock frequency f SCL R = 1.7 kW , C = 50 pF*1 0 100 0 400 kHz Hold time (repeated) START condition SDA flfi SCL fl tHDSTA 4.0 ¾ 0.6 ¾m s “L” width of the SCL clock t LOW 4.7 ¾ 1.3 ¾m s “H” width of the SCL clock t HIGH 4.0 ¾ 0.6 ¾m s Set-up time for a repeated START condition SCL ›fi SDA fl tSUSTA 4.7 ¾ 0.6 ¾m s Data hold time SCL flfi SDA fl› tHDDAT 0 3.45* 2 00 . 9 * 3 ms Data set-up time SDA fl›fi SCL › tSUDAT 250 ¾ 100 ¾ ns Set-up time for STOP condition SCL ›fi SDA › tSUSTO 4.0 ¾ 0.6 ¾m s Bus free time between a STOP and START condition tBUS 4.7 ¾ 1.3 ¾m s SDA SCL tLOW tSUDAT tHDSTA tBUS tHDSTA tHDDAT tHIGH tSUSTA tSUSTO

1. A/D Converter (TA = -40 °C to +105 °C, 3.0 V £ AVRH - AVRL, VCC = AVCC = 5.0 V – 10% , fCP £ 24 MHz, VSS = AVSS = 0 V) * : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) . Note : The accuracy gets worse as AVRH - AVRL becomes smaller. Parameter Symbol Pin Value Unit Remarks Min Typ Max Resolution ¾¾ ¾ ¾ 10 bit Total error ¾¾ ¾ ¾ – 3.0 LSB Nonlinearity error¾¾ ¾ ¾ – 2.5 LSB Differential nonlinearity error¾¾ ¾ ¾ – 1.9 LSB Zero reading voltage VOT AN0 to AN23 AVRL - 1.5 AVRL + 0.5 AVRL + 2.5 LSB Full scale reading voltage VFST AN0 to AN23 AVRH - 3.5 AVRH - 1.5 AVRH + 0.5 LSB Compare time ¾¾ 1.0 ¾ 16,500 ms 4.5 V £ AVCC £ 5.5 V 2.0 4.0 V £ AVCC < 4.5 V Sampling time ¾¾ 0.5 ¾ ¥ ms 4.5 V £ AVCC £ 5.5 V 1.2 4.0 V £ AVCC < 4.5 V Analog port input current IAIN AN0 to AN23 -0.3 ¾ +0.3 mA Analog input voltage range VAIN AN0 to AN23 AVRL ¾ AVRH V Reference voltage range ¾ AVRH AVRL + 2.7 ¾ AV CC V ¾ AVRL 0 ¾ AVRH - 2.7 V Power supply current IA AV CC ¾ 3.5 7.5 mA IAH AV CC ¾¾ 5 mA* Reference voltage current IR AVRH ¾ 600 900 mA IRH AVRH ¾¾ 5 mA* Offset between input channels ¾ AN0 to AN23 ¾¾ 4L S B

1. Definition of A/D Converter Terms (Continued) Resolution : Analog variation that is recognized by an A/D converter. Non linearity error : Deviation between a line across zero-transition line ( “00 0000 0000” ‹ fi “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ‹ fi “11 1111 1111” ) and actual conversion characteristics. Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Total error : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Zero reading voltage : Input voltage which results in the minimum conversion value. Full scale reading voltage : Input voltage which results in the maximum conversion value. 3FF 3FE 3FD 004 003 002 001 AVRL AVRH VNT

1.5 LSB

0.5 LSB

{1 LSB · (N - 1) + 0.5 LSB} Actual conversion characteristics (Actually-measured value) Actual conversion characteristics Ideal characteristics Digital output Analog input Total error Total error of digital output “N” = VNT - {1 LSB · (N - 1) + 0.5 LSB}

1 LSB [LSB]

1 LSB = (Ideal value) AVRH - AVRL

1024 [V] VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH - 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N - 1) to N.

(Continued) 3FF 3FE 3FD 004 003 002 001 AVRL AVRH AVRL AVRH N + 1 N N - 1 N - 2 VOT (actual measurement value) {1 LSB · (N - 1) + VOT } Actual conversion characteristics VFST (actual measurement value) V NT (actual measurement value) Actual conversion characteristics Ideal characteristics Actual conversion characteristics Actual conversion characteristics Ideal characteristics Digital output Digital output Analog inputAnalog input VNT (actual measurement value) V (N + 1) T (actual measurement value) Non linearity error Differential linearity error Non linearity error of digital output N = VNT - {1 LSB · (N - 1) + VOT } Differential linearity error of digital output N = V (N+1 ) T - VNT

1 LSB -1 LSB [LSB]

1022 [V]1 LSB = VOT : Voltage at which digital output transits from “000H ” to “001H .” VFST : Voltage at which digital output transits from “3FEH ” to “3FFH .”

1. Notes on A/D Converter Section Use the device with external circuits of the following output impedance for analog inputs : Recommended output impedance of external circuits are : Approx. 1.5 kW or lower (4.0 V £ AVCC £ 5.5 V , sampling period £ 0.5 ms) If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. 8. Flash Memory Program/Erase Characteristics * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . Parameter Conditions Value Unit Remarks Min Typ Max Sector erase time TA = +25 °C VCC = 5.0 V ¾ 11 5 s Excludes programming prior to erasure Chip erase time ¾ 9 ¾ s Excludes programming prior to erasure Word (16 bit width) programming time ¾ 16 3,600 ms Except for the over head time of the system Programs/Erase cycle ¾ 10,000 ¾¾ cycle Flash Data Retension Time Average TA = +85 °C 20 ¾¾ Year * C Comparator Analog input R 4.5 V £ AVCC £ 5.5 V : R := 2.52 kW , C := 10.7 pF 4.0 V £ AVCC < 4.5 V : R := 13.6 kW , C := 10.7 pF

• Analog input circuit model Note : Use the values in the figure only as a guideline.

• MB90F346A, MB90F346AS, MB90F346CA, MB90F346CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (A) 100 VCC (V) f = 8 kHz ICCS (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (A) VCC (V) f = 8 kHz ICTS (A) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (A) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (A) VCC (V)

• MB90F347A, MB90F347AS, MB90F347CA, MB90F347CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (A) 100 VCC (V) f = 8 kHz ICCS (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (A) VCC (V) f = 8 kHz ICTS (A) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (A) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (A) VCC (V)

• MB90F349A, MB90F349AS, MB90F349CA, MB90F349CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (mA) 100 VCC (V) f = 8 kHz ICCS (mA) VCC (V) f = 24 MHz f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (mA) VCC (V) f = 8 kHz ICTS (mA) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (mA) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (mA) VCC (V)

• MB90F342A, MB90F342AS, MB90F342CA, MB90F342CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (mA) 100 VCC (V) f = 8 kHz ICCS (mA) VCC (V) f = 24 MHz f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (mA) VCC (V) f = 8 kHz ICTS (mA) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (mA) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (mA) VCC (V)

• MB90F345A, MB90F345AS, MB90F345CA, MB90F345CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (A) 100 VCC (V) f = 8 kHz ICCS (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (A) VCC (V) f = 8 kHz ICTS (A) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (A) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (A) VCC (V)

• MB90346A, MB90346AS, MB90346CA, MB90346CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (mA) 100 VCC (V) ICCS (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (mA) VCC (V) f = 8 kHz ICTS (mA) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (mA) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (mA) VCC (V)

• MB90347A, MB90347AS, MB90347CA, MB90347CAS ICC - VCC ICCL - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICCS - VCC ICCLS - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTS - VCC ICCT - VCC TA = +25 °C, at external clock operating f = Internal operation frequency TA = +25 °C, at external clock operating f = Internal operation frequency ICTSPLL6 - VCC ICCH - VCC TA = +25 °C, at external clock operating f = Internal operation frequency T A = +25 °C, at stop ICC (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCL (mA) 100 VCC (V) ICCS (mA) VCC (V) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz ICCLS (mA) VCC (V) f = 8 kHz ICTS (mA) 400 150 100 VCC (V) 200 300 f = 2 MHz 350 250 ICCT (mA) VCC (V) f = 8 kHz ICTSPLL6 (mA) VCC (V) f = 24 MHz ICCH (mA) VCC (V)

• I/O characteristics (VCC -VOH ) - IOH VOL - IOL TA = +25 °C, VCC = 4.5 V T A = +25 °C, VCC = 4.5 V Automotive VIN - VCC CMOS V IN - VCC TA = +25 °C UART-SIN pin, other than I2C pin TA = +25 °C TTL VIN - VCC CMOS V IN - VCC TA = +25 °C UART-SIN pin, I2C pin TA = +25 °C VCC VOH (mV) 800 300 100 200 IOH (mA) 400 500 600 024 7 1 0 700 13 6 58 9 VOL (mV) 1000 300 100 200 IOL (mA) 400 500 600 900 700 800 024 7 1 013 6 58 9 VIN (V) 5.0 1.5 0.5 1.0 VCC (V) 0.0 2.0 3.0 3.5 2.5 4.0

4.5 VIHA

VIN (V) 5.0 2.5 1.5 2.0 VCC (V) 0.0 3.0 4.0 4.5 3.5 1.0 0.5 VIHS VILS VIN (V) 2.5 0.8 0.3 0.5 VCC (V) 0.0 1.0 2.0 2.3 1.5 1.3 1.8 VIHT VILT VIN (V) 5.0 2.5 0.5 1.0 VCC (V) 0.0 3.0 4.0 4.5 3.5 1.5 2.0 VIHS VILS

(Continued) Part number Package Remarks MB90F342APF 100-pin Plastic QFP (FPT-100P-M06) MB90F342ASPF MB90F342CAPF MB90F342CASPF MB90F342APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F342ASPFV MB90F342CAPFV MB90F342CASPFV MB90F343APF 100-pin Plastic QFP (FPT-100P-M06) MB90F343ASPF MB90F343CAPF MB90F343CASPF MB90F343APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F343ASPFV MB90F343CAPFV MB90F343CASPFV MB90F345APF 100-pin Plastic QFP (FPT-100P-M06) MB90F345ASPF MB90F345CAPF MB90F345CASPF MB90F345APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F345ASPFV MB90F345CAPFV MB90F345CASPFV MB90F346APF 100-pin Plastic QFP (FPT-100P-M06) MB90F346ASPF MB90F346CAPF MB90F346CASPF MB90F346APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F346ASPFV MB90F346CAPFV MB90F346CASPFV

(Continued) Part number Package Remarks MB90F347APF 100-pin Plastic QFP (FPT-100P-M06) MB90F347ASPF MB90F347CAPF MB90F347CASPF MB90F347APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F347ASPFV MB90F347CAPFV MB90F347CASPFV MB90F349APF 100-pin Plastic QFP (FPT-100P-M06) MB90F349ASPF MB90F349CAPF MB90F349CASPF MB90F349APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F349ASPFV MB90F349CAPFV MB90F349CASPFV MB90341APF 100-pin Plastic QFP (FPT-100P-M06) MB90341ASPF MB90341CAPF MB90341CASPF MB90341APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90341ASPFV MB90341CAPFV MB90341CASPFV MB90342APF 100-pin Plastic QFP (FPT-100P-M06) MB90342ASPF MB90342CAPF MB90342CASPF MB90342APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90342ASPFV MB90342CAPFV MB90342CASPFV

(Continued) Part number Package Remarks MB90346APF 100-pin Plastic QFP (FPT-100P-M06) MB90346ASPF MB90346CAPF MB90346CASPF MB90346APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90346ASPFV MB90346CAPFV MB90346CASPFV MB90347APF 100-pin Plastic QFP (FPT-100P-M06) MB90347ASPF MB90347CAPF MB90347CASPF MB90347APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90347ASPFV MB90347CAPFV MB90347CASPFV MB90348APF 100-pin Plastic QFP (FPT-100P-M06) MB90348ASPF MB90348CAPF MB90348CASPF MB90348APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90348ASPFV MB90348CAPFV MB90348CASPFV MB90349APF 100-pin Plastic QFP (FPT-100P-M06) MB90349ASPF MB90349CAPF MB90349CASPF MB90349APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90349ASPFV MB90349CAPFV MB90349CASPFV MB90V340A-101 299-pin Ceramic PGA (PGA-299C-A01) For evaluation MB90V340A-102

(Continued) 100-pin Plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness including plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2002 FUJITSU LIMITED F100008S-c-5-5 1 30 5180 100 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) INDEX (.013±.002) M0.13(.005) "A" 0.17±0.06 (.007±.002) 0.10(.004) Details of "A" part (.035±.006) 0.88±0.15 (.031±.008) 0.80±0.20 0.25(.010)3.00 +0.35 –0.20 +.014 –.008.118 (Mounting height) 0.25±0.20 (.010±.008) (Stand off) 0~8˚

(Continued) 100-pin Plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2003 FUJITSU LIMITED F100007S-c-4-6 12 5 76 50 100 (.008±.002) (.0057±.0022) 0.08(.003) "A" INDEX .059–.004 +.008 –0.10 +0.20 1.50 (Mounting height) 0˚~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 0.10±0.10 (.004±.004) Details of "A" part (Stand off)

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