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Copyright©2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.9 For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit Microcontroller CMOS F2MC-16LX MB90335 Series MB90337/F337/V330A ■ DESCRIPTION The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F 2MC* family, the instruction se t supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by intro- ducing a 32-bit accumulator. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES

  • Clock
  • Built-in oscillation circuit and PLL clock frequency multiplication circuit  Oscillation clock  The main clock is the oscillation clock divi ded into 2 (for oscillation 6 MHz : 3 MHz)  Clock for USB is 48 MHz  Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable  Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V

CC = 3.3 V)

  • The maximum memory space: 16 Mbytes
  • 24-bit addressing
  • Bank addressing (Continued) DS07-13735-4E

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  • Instruction system  Data types: Bit, Byte, Word, Long word  Addressing mode (23 types)  Enhanced high-precision computing with 32-bit accumulator  Enhanced Multiply/Divide instructions with sign and the RETI instruction
  • Instruction system compatible with high-level language (C language) and multi-task  Employing system stack pointer  Instruction set symmetry and barrel shift instructions
  • Program Patch Function (2 address pointer)
  • 4-byte instruction queue
  • Interrupt function  Priority levels are programmable  20 interrupts function
  • Data transfer function  Extended intelligent I/O service function (EI 2OS) : Maximum of 16 channels  μDMAC : Maximum 16 channels
  • Low Power Consumption Mode  Sleep mode (with the CPU operating clock stopped)  Time-base timer mode (with the oscillato r clock and time-base timer operating)  Stop mode (with the oscillator clock stopped)  CPU intermittent operation m ode (with the CPU operating at fixed intervals of set cycles)
  • Package  LQFP-64P (FPT -64P-M23 : 0.65 mm pin pitch)
  • Process : CMOS technology
  • Operation guaranteed temperature: − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use) (Continued)

(Continued)

  • Internal peripheral function (resource)  I/O port : Max 45 ports  Time-base timer : 1channel  Watchdog timer : 1 channel  16-bit reload timer : 1 channel  Multi-functional timer  8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse are freely programmable.  16-bit PWC timer : 1 channel Timer function and pulse width measurement function  UART: 2 channels  Equipped with a full duplex (8-bit long) double buffer  Selectable asynchronous transfer or clock-sy nchronous serial (extended I/O serial) transfer.  Extended I/O serial interface : 1 channel  DTP/External interrupt circuit (8 channels)  Activate the extended intelligent I/O service by external interrupt input  Interrupt output by external interrupt input  Delayed interrupt output module  Outputs an interrupt request for task switching  USB: 1 channel  USB function (supports USB 2.0 Full Speed)  Supports Full Speed/Up to 6 endpoints can be specified.  Dual port RAM (supports FIFO mode).  Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible  USB HOST function 2C Interface: 1 channel  Supports Intel SM bus standards and Phillips I 2C bus standards  Two-wire data transfer protocol specification  Master and slave transmission/reception

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■ PRODUCT LINEUP * : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. ■ PACKAGES AND PRODUCT MODELS : Yes : No Note : See “■ PACKAGE DIMENSIONS” for details. Part number MB90V330A MB90F337 MB90337 Type For evaluation Built-in Flash Memory Built-in MASK ROM ROM capacity No 64 Kbytes RAM capacity 28 Kbytes 4 Kbytes Emulator-specific power supply * Used bit ⎯ CPU functions Number of basic instructions Minimum instruction execution time Addressing type Program Patch Function Maximum memory space : 351 instructions : 41.7 ns / at oscillation of 6 MHz (When 4 times are used : Machine clock of 24 MHz) : 23 types : For 2 address pointers : 16 Mbytes Ports I/O Ports(CMOS) Max 45 ports UART Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels 16-bit reload timer 16-bit reload timer operation Built-in 1 channel Multi-functional timer 8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels) 16-bit PWC timer × 1 channel DTP/External interrupt 8 channels Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable I 2C 1 channel Extended I/O serial interface 1 channel USB 1 channel USB function (correspond to USB 2.0 Full Speed) USB HOST function Withstand voltage of 5 V 8 ports (Excluding UTEST and I/O for I 2C) Low Power Consumption Mode Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode Process CMOS Operating voltage V CC 3.3 V ± 0.3 V (at maximum machine clock 24 MHz) FPT-64P-M23 (LQFP) PGA-299C-A01 (PGA)

■ PIN ASSIGNMENT (TOP VIEW) (FPT-64P-M23) UTEST Vss DVM DVP Vcc Vss HVM HVP Vcc HCON P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 Vss P24/PPG0 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P51 P41/TOT0 P40/TIN0 P67/INT7/SDA0 P66/INT6/SCL0 P65/INT5/PWC P64/INT4/SCK P63/INT3/SOT P62/INT2/SIN P61/INT1 P60/INT0 P27/PPG3 P26/PPG2 P25/PPG1 P50 Vcc P52 P53 Vss MD2 MD1 MD0 RST P54 P00 P01 P02 P03 P04 P05 P06 P07

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■ PIN DESCRIPTION (Continued) Pin no. Pin name I/O Circuit type* Status at reset/ function Function 46 , 47 X0, X1 A Oscillation status It is a terminal which connects the oscillator. When connecting an external clock, leave the X1 pin side unconnected. 23 RST F Reset input External reset input pin. 25 to 32 P00 to P07 I Port input (Hi-Z) General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.) 33 to 40 P10 to P17 I General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) 41 to 44 P20 to P23 D General purpose input/output port. 45 P24 D General purpose input/output port. PPG0 Functions as output pins of PPG timers ch.0. 51 to 53 P25 to P27 D General purpose input/output port. PPG1 to PPG3 Functions as output pins of PPG timers ch.1 to ch.3. 62 P40 H General purpose input/output port. TIN0 Function as event input pin of 16-bit reload timer. 63 P41 H General purpose input/output port. TOT0 Function as output pin of 16-bit reload timer. 11 P42 H General purpose input/output port. SIN0 Functions as a data input pin for UART ch.0. 12 P43 H General purpose input/output port. SOT0 Functions as a data output pin for UART ch.0. 13 P44 H General purpose input/output port. SCK0 Functions as a clock I/O pin for UART ch.0. 14 P45 H General purpose input/output port. SIN1 Functions as a data input pin for UART ch.1. 15 P46 H General purpose input/output port. SOT1 Functions as a data output pin for UART ch.1. 16 P47 H General purpose input/output port. SCK1 Functions as a clock I/O pin for UART ch.1. 50 P50 K General purpose input/output port. 64 P51 K General purpose input/output port. 17, 18 P52, P53 K General purpose input/output port. 24 P54 K General purpose input/output port.

(Continued) * : For circuit information, refer to “■ I/O CIRCUIT TYPE”. Pin no. Pin name I/O Circuit type* Status at reset/ function Function 54, 55 P60, P61 C Port input (Hi-Z) General purpose input/output port (withstand voltage of 5 V) . INT0, INT1 Functions as the input pin fo r external interrupt ch.0 and ch.1. P62 C General purpose input/output port (withstand voltage of 5 V) . INT2 Functions as the input pin for external interrupt ch.2. SIN Data input pin for extended I/O serial interface. P63 C General purpose input/output port (withstand voltage of 5 V) . INT3 Functions as the input pin for external interrupt ch.3. SOT Data output pin for extended I/O serial interface. P64 C General purpose input/output port (withstand voltage of 5 V) . INT4 Functions as the input pin for external interrupt ch.4. SCK Clock I/O pin for extended I/O serial interface. P65 C General purpose input/output port (withstand voltage of 5 V) . INT5 Functions as the input pin for external interrupt ch.5. PWC Functions as the PWC input pin. P66 C General purpose input/output port (withstand voltage of 5 V) . INT6 Functions as the input pin for external interrupt ch.6. SCL0 Functions as the input/output pin for I2C interface clock. The port output must be placed in Hi-Z state during I2C interface operation. P67 C General purpose input/output port (withstand voltage of 5 V) . INT7 Functions as the input pin for external interrupt ch.7. SDA0 Functions as the I2C interface data input/output pin. The port out- put must be placed in Hi-Z state during I2C interface operation.

1 UTEST C UTEST

USB test pin. Connect this to a pull-down resistor during normal usage. 3D V M J USB input (SUSPEND) USB function D − pin. 4 DVP J USB function D + pin. 7 HVM J USB HOST D − pin. 8 HVP J USB HOST D + pin. 10 HCON E High output External pull-up resistor connection pin. 21, 22 MD1, MD0 B Mode input Input pin for selecting operation mode.20 MD2 G 5, 9, 49 Vcc ⎯ Power supply Power supply pin. 2, 6, 19, 48 Vss Power supply pin (GND).

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■ I/O CIRCUIT TYPE (Continued) Type Circuit Remarks A  Oscillation feedback resistor of approx. 1 MΩ  With standby control B CMOS hysteresis input C  CMOS hysteresis input  N-ch open drain output D  CMOS output  CMOS hysteresis input (With input interception function at standby) Notes : • Share one output buffer because both output of I/O port and internal resource are used.

  • Share one input buffer because both input of I/O port and internal resource are used. E CMOS output F CMOS hysteresis input with pull-up resistor of approx. 50 kΩ G  CMOS hysteresis input with pull-down resistor of approx. 50 kΩ  Flash product is not provided with pull- down resistor. Standby control signal Clock input CMOS hysteresis input NoutN-ch CMOS hysteresis input Standby control signal Pout Nout P-ch N-ch CMOS hysteresis input Standby control signal Pout Nout P-ch N-ch R CMOS hysteresis input R CMOS hysteresis input

(Continued) Type Circuit Remarks H  CMOS output  CMOS hysteresis input (With input interception function at standby) With open drain control signal I  CMOS output C M O S i n p u t (With input interception function at standby)  Programmable input pull-up resistor JU SB I/O pin K  CMOS output C M O S i n p u t (With input interception function at standby) Pout Nout P-ch N-ch Open drain control signal Standby control signal CMOS hysteresis input Pout Nout P-ch N-ch Control signal R CMOS input Standby control signal D + input D - input Differential input Full D + output Full D - output Low D + output Low D - output Direction Speed Pout Nout P-ch N-ch CMOS input Standby control signal

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■ HANDLING DEVICES 1. Preventing latch-up and turning on power supply latch-up may occur on CMOS IC under the following conditions:

  • If a voltage higher than VCC or lower than VSS is applied to input and output pins.
  • A voltage higher than the rated voltage is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using CMOS IC, take great care to prevent the occurrence of latch-up. 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent dam- age. Unused input pins should al ways be pulled up or down through resistance of at least 2 k Ω. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. 3. About the attention when the external clock is used Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. 4. Treatment of power supply pins (V CC/VSS) In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a cerami c bypass capacitor of approximately 0.1 μ F between VCC and VSS pins near this device. 5. About crystal oscillator circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. 6. Caution on Operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. X1OPEN  Using external clock
  1. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at tempor ary changes such as power supply switching. 8. Writing to flash memory For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V. 9. Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error. If an error is detected, retransmit the data.

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■ BLOCK DIAGRAM F2MC-16LX CPU RAM ROM UART/SIO ch.0, ch.1 I2C SIO μDMAC P00 P07 P10 P17 P20 P27 P40 P47 P50 P54 P60 P67 X0, X1 RST MD0 to MD2 SIN0, SIN1 SOT0, SOT1 SCK0, SCK1 SCL0 SDA0 INT0 to INT7 DVP DVM HVP HVM HCON UTEST TOT0 TIN0 PPG0 to PPG3 PWC SIN SOT SCK * : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral function (resources) cannot serve as I/O ports. 16-bit reload timer External interrupt 16-bit PWC 8/16-bit PPG timer ch.0 to ch.3* Clock control circuit Interrupt controller Internal data bus I/O port (port 0, 1, 2, 4, 5, 6) USB (function) (HOST)

■ MEMORY MAP Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

  • The ROM mirror function is effective for using the C compiler small model.
  • The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00.
  • When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. FFFFFFH 00FFFFH 007FFFH 007900H 007100H 008000H FF0000H 000100H 0000FBH 000000H FFFFFFH 00FFFFH 007FFFH 007900H 001100H 008000H FF0000H 000100H 0000FBH 000000H FFFFFFH 00FFFFH 007FFFH 007900H 001100H 008000H FF0000H 000100H 0000FBH 000000H MB90V330A MB90F337 MB90337 Register Register Register Single chip mode (with ROM mirror function) Peripheral area ROM (FF bank) ROM area (image of FF bank) RAM area (28 Kbytes) Peripheral area Peripheral area ROM (FF bank) ROM area (image of FF bank) RAM area (4 Kbytes) Peripheral area Peripheral area ROM (FF bank) ROM area (image of FF bank) RAM area (4 Kbytes) Peripheral area

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■ F2MC-16L CPU PROGRAMMING MODEL  Dedicated register  General purpose registers  Processor status AH AL DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit USP SSP PS PC Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register R1 R0 R3 R2 R5 R4 R7 R6 RW0 RW1 RW2 RW3 16-bit 000180H + RP × 10H RW4 RW5 RW6 RW7 RL0 RL1 RL2 RL3 MSB LSB ILM 15 13 PS RP CCR 12 8 70Bit

■ I/O MAP (Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000000H PDR0 Port 0 Data Register R/W Port 0 XXXXXXXX B 000001H PDR1 Port 1 Data Register R/W Port 1 XXXXXXXX B 000002H PDR2 Port 2 Data Register R/W Port 2 XXXXXXXX B 000003H Prohibited 000004H PDR4 Port 4 Data Register R/W Port 4 XXXXXXXX B 000005H PDR5 Port 5 Data Register R/W Port 5 - - - XXXXX B 000006H PDR6 Port 6 Data Register R/W Port 6 XXXXXXXX B 000007H to 00000FH Prohibited 000010H DDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0 B 000011H DDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0 B 000012H DDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0 B 000013H Prohibited 000014H DDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0 B 000015H DDR5 Port 5 Direction Register R/W Port 5 - - - 0 0 0 0 0 B 000016H DDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0 B 000017H to 00001AH Prohibited 00001BH ODR4 Port 4 Output Pin Register R/W Port 4 (Open-drain control) 0 0 0 0 0 0 0 0B 00001CH RDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0 B 00001DH RDR1 Port 1 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0 B 00001EH Prohibited00001FH 000020H SMR0 Serial Mode Register 0 R/W UART0 0 0 1 0 0 0 0 0B 000021H SCR0 Serial Control Register 0 R/W 0 0 0 0 0 1 0 0B 000022H SIDR0 Serial Input Data Register 0 R XXXXXXXXB SODR0 Serial Output Data Register 0 W 000023H SSR0 Serial Status Register 0 R/W 0 0 0 0 1 0 0 0B 000024H UTRLR0 UART Prescaler Reload Register 0 R/W Communication Prescaler (UART0) 0 0 0 0 0 0 0 0B 000025H UTCR0 UART Prescaler Control Re gister 0 R/W 0 0 0 0 - 0 0 0 B 000026H SMR1 Serial Mode Register 1 R/W UART1 0 0 1 0 0 0 0 0B 000027H SCR1 Serial Control Register 1 R/W 0 0 0 0 0 1 0 0B 000028H SIDR1 Serial Input Data Register 1 R XXXXXXXXB SODR1 Serial Output Data Register 1 W 000029H SSR1 Serial Status Register 1 R/W 0 0 0 0 1 0 0 0B

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(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 00002AH UTRLR1 UART Prescaler Reload Register 1 R/W Communication Prescaler (UART1) 0 0 0 0 0 0 0 0B 00002BH UTCR1 UART Prescaler Control Register 1 R/W 0 0 0 0 - 0 0 0B 00002CH to 00003BH Prohibited 00003CH ENIR DTP/Interrupt Enable Register R/W DTP/External interrupt 0 0 0 0 0 0 0 0B 00003DH EIRR DTP/Interrupt source Register R/W 0 0 0 0 0 0 0 0B 00003EH ELVR Request Level Setting Register Lower R/W 0 0 0 0 0 0 0 0B 00003FH Request Level Setting Register Upper R/W 0 0 0 0 0 0 0 0B 000040H to 000045H Prohibited 000046H PPGC0 PPG0 Operation Mode Control Register R/W PPG ch.0 0X0 0 0XX1 B 000047H PPGC1 PPG1 Operation Mode Control Register R/W PPG ch.1 0X0 0 0 0 0 1 B 000048H PPGC2 PPG2 Operation Mode Control Register R/W PPG ch.2 0X0 0 0XX1 B 000049H PPGC3 PPG3 Operation Mode Control Register R/W PPG ch.3 0X0 0 0 0 0 1 B 00004AH Prohibited00004BH 00004CH PPG01 PPG0 and PPG1 Output Control Regi ster R/W PPG ch.0/ch.1 0 0 0 0 0 0XX B 00004DH Prohibited 00004EH PPG23 PPG2 and PPG3 Output Control Regi ster R/W PPG ch.2/ch.3 0 0 0 0 0 0 XX B 00004FH to 000057H Prohibited 000058H SMCS Serial Mode Control Status Register R/W Extended Serial I/O XXXX0 0 0 0B 000059H 0 0 0 0 0 0 1 0B 00005AH SDR Serial Data Register R/W XXXXXXXXB 00005BH SDCR Communication Prescaler Control Register R/W Communication Prescaler 0XXX0 0 0 0B 00005CH PWCSR PWC Control Status Register R/W 16-bit PWC Timer 0 0 0 0 0 0 0 0B 00005DH 0 0 0 0 0 0 0 XB 00005EH PWCR PWC Data Buffer Register R/W 0 0 0 0 0 0 0 0B 00005FH 0 0 0 0 0 0 0 0B 000060H DIVR PWC Dividing Ratio Control Register R/W - - - - - - 0 0B 000061H Prohibited 000062H TMCSR0 Timer Control Status Register R/W 16-bit Reload Timer 0 0 0 0 0 0 0 0B 000063H XXXX 0 0 0 0B 000064H TMR0 16-bit Timer Register Lower R XXXXXXXXB TMRLR0 16-bit Reload Register Lower W XXXXXXXXB 000065H TMR0 16-bit Timer Register Upper R XXXXXXXXB TMRLR0 16-bit Reload Register Upper W XXXXXXXXB

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000066H to 00006EH Prohibited 00006FH ROMM ROM Mirroring Function Selection Register W ROM Mirror Function Selection Module - - - - - - 1 1B 000070H IBSR0 I 2C Bus Status Register R I2C Bus Interface 0 0 0 0 0 0 0 0B 000071H IBCR0 I 2C Bus Control Register R/W 0 0 0 0 0 0 0 0B 000072H ICCR0 I 2C Bus Clock Control Register R/W XX 0 XXXXXB 000073H IADR0 I 2C Bus Address Register R/W XXXXXXXXB 000074H IDAR0 I 2C Bus Data Register R/W XXXXXXXXB 000075H to 00009AH Prohibited 00009BH DCSR DMA Descriptor Channel Specification Register R/W μDMAC 0 0 0 0 0 0 0 0 B 00009CH DSRL DMA Status Register Lower R/W 0 0 0 0 0 0 0 0B 00009DH DSRH DMA Status Register Upper R/W 0 0 0 0 0 0 0 0B 00009EH PACSR Program Address Detection Control Status Register R/W Address Match Detection 0 0 0 0 0 0 0 0 B 00009FH DIRR Delayed Interrupt Source generate/ release Register R/W Delayed Interrupt - - - - - - - 0 B 0000A0H LPMCR Low Power Consumption Mode Control Register R/W Low Power Consumption control circuit 0 0 0 1 1 0 0 0B 0000A1H CKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0 B 0000A2H Prohibited0000A3H 0000A4H DSSR DMA Stop Status Register R/W μDMAC 0 0 0 0 0 0 0 0 B 0000A5H to 0000A7H Prohibited 0000A8H WDTC Watchdog Timer Control Regist er R/W Watchdog Timer X - XXX 1 1 1 B 0000A9H TBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0 B 0000AAH Prohibited0000ABH 0000ACH DERL DMA Enable Register Lower R/W μDMAC 0 0 0 0 0 0 0 0B 0000ADH DERH DMA Enable Register Upper R/W 0 0 0 0 0 0 0 0B 0000AEH FMCS Flash Memory Control Status Register R/W Flash Memory I/F 0 0 0 X 0 0 0 0 B 0000AFH Prohibited

18 DS07-13735-4E

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000B0H ICR00 Interrupt Control Register 00 R/W Interrupt Controller 0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1B 0000B6H ICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt Control Register 07 R/W 0 0 0 0 0 1 1 1B 0000B8H ICR08 Interrupt Control Register 08 R/W 0 0 0 0 0 1 1 1B 0000B9H ICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1B 0000BAH ICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1B 0000BBH ICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 Interrupt Control Register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 Interrupt Control Register 13 R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1B 0000BFH ICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1B 0000C0H HCNT0 Host Control Register 0 R/W USB HOST 0 0 0 0 0 0 0 0B 0000C1H HCNT1 Host Control Register 1 R/W 0 0 0 0 0 0 0 1B 0000C2H HIRQ Host Interruption Register R/W 0 0 0 0 0 0 0 0B 0000C3H HERR Host Error Status Register R/W 0 0 0 0 0 0 1 1B 0000C4H HSTATE Host State Status Register R/W XX 0 1 0 0 1 0B 0000C5H HFCOMP SOF Interrupt FRAME Compare Reg- ister R/W 0 0 0 0 0 0 0 0 B 0000C6H HRTIMER Retry Timer Setting Register R/W 0 0 0 0 0 0 0 0B 0000C7H R/W 0 0 0 0 0 0 0 0B 0000C8H R/W XXXXXX 0 0B 0000C9H HADR Host Address Register R/W X 0 0 0 0 0 0 0B 0000CAH HEOF EOF Setting Register R/W 0 0 0 0 0 0 0 0 B 0000CBH R/W XX 0 0 0 0 0 0B 0000CCH HFRAME FRAME Setting Register R/W 0 0 0 0 0 0 0 0 B 0000CDH R/W XXXXX 0 0 0B 0000CEH HTOKEN Host Token End Point Register R/W 0 0 0 0 0 0 0 0B 0000CFH Prohibited 0000D0H UDCC UDC Control Register R/W USB Function 1 0 1 0 0 0 0 0B 0000D1H R/W 0 0 0 0 0 0 0 0B

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000D2H EP0C EP0 Control Register R/W USB Function 0 1 0 0 0 0 0 0B 0000D3H R/W XXXX 0 0 0 0B 0000D4H EP1C EP1 Control Register R/W 0 0 0 0 0 0 0 0 B 0000D5H R/W 0 1 1 0 0 0 0 1B 0000D6H EP2C EP2 Control Register R/W 0 1 0 0 0 0 0 0 B 0000D7H R/W 0 1 1 0 0 0 0 0B 0000D8H EP3C EP3 Control Register R/W 0 1 0 0 0 0 0 0 B 0000D9H R/W 0 1 1 0 0 0 0 0B 0000DAH EP4C EP4 Control Register R/W 0 1 0 0 0 0 0 0 B 0000DBH R/W 0 1 1 0 0 0 0 0B 0000DCH EP5C EP5 Control Register R/W 0 1 0 0 0 0 0 0 B 0000DDH R/W 0 1 1 0 0 0 0 0B 0000DEH TMSP Time Stamp Register R 0 0 0 0 0 0 0 0 B 0000DFH R XXXXX0 0 0B 0000E0H UDCS UDC Status Register R/W XX0 0 0 0 0 0B 0000E1H UDCIE UDC Interrupt Enable Register R/W 0 0 0 0 0 0 0 0B 0000E2H EP0IS EP0I Status Register R/W XXXXXXXX B 0000E3H R/W 1 0 XXX 1 XXB 0000E4H EP0OS EP0O Status Register R/W, R 0 XXXXXXX B 0000E5H R/W 1 0 0 XX 0 0 0B 0000E6H EP1S EP1 Status Register R XXXXXXXX B 0000E7H R/W 1 0 0 0 0 0 0 XB 0000E8H EP2S EP2 Status Register R XXXXXXXX B 0000E9H R/W 1 0 0 0 0 0 0 0B 0000EAH EP3S EP3 Status Register R XXXXXXXX B 0000EBH R/W 1 0 0 0 0 0 0 0B 0000ECH EP4S EP4 Status Register R XXXXXXXX B 0000EDH R/W 1 0 0 0 0 0 0 0B 0000EEH EP5S EP5 Status Register R XXXXXXXX B 0000EFH R/W 1 0 0 0 0 0 0 0B 0000F0H EP0DT EP0 Data Register R/W XXXXXXXX B 0000F1H R/W XXXXXXXXB 0000F2H EP1DT EP1 Data Register R/W XXXXXXXX B 0000F3H R/W XXXXXXXXB 0000F4H EP2DT EP2 Data Register R/W XXXXXXXX B 0000F5H R/W XXXXXXXXB 0000F6H EP3DT EP3 Data Register R/W XXXXXXXX B 0000F7H R/W XXXXXXXXB 0000F8H EP4DT EP4 Data Register R/W XXXXXXXX B 0000F9H R/W XXXXXXXXB

20 DS07-13735-4E

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000FAH EP5DT EP5 Data Register R/W USB Function XXXXXXXXB 0000FBH R/W XXXXXXXXB 0000FCH to 0000FFH Prohibited 000100H to 001100H RAM Area 001FF0H PADR0 Program Address Detection Register ch.0 Lower R/W Address Match Detection XXXXXXXXB 001FF1H Program Address Detection Register ch.0 Middle R/W XXXXXXXX B 001FF2H Program Address Detection Register ch.0 Upper R/W XXXXXXXX B 001FF3H PADR1 Program Address Detection Register ch.1 Lower R/W XXXXXXXX B 001FF4H Program Address Detection Register ch.1 Middle R/W XXXXXXXX B 001FF5H Program Address Detection Register ch.1 Upper R/W XXXXXXXX B 007900H PRLL0 PPG Reload Register Lower ch.0 R/W PPG ch.0 XXXXXXXXB 007901H PRLH0 PPG Reload Register Upper ch.0 R/W XXXXXXXXB 007902H PRLL1 PPG Reload Register Lower ch.1 R/W PPG ch.1 XXXXXXXXB 007903H PRLH1 PPG Reload Register Upper ch.1 R/W XXXXXXXXB 007904H PRLL2 PPG Reload Register Lower ch.2 R/W PPG ch.2 XXXXXXXXB 007905H PRLH2 PPG Reload Register Upper ch.2 R/W XXXXXXXXB 007906H PRLL3 PPG Reload Register Lower ch.3 R/W PPG ch.3 XXXXXXXXB 007907H PRLH3 PPG Reload Register Upper ch.3 R/W XXXXXXXXB 007908H to 00790BH Prohibited 00790CH FWR0 Flash Memory Program Control Register 0 R/W Flash 0 0 0 0 0 0 0 0 B 00790DH FWR1 Flash Memory Program Control Register 1 R/W Flash 0 0 0 0 0 0 0 0 B 00790EH SSR0 Sector Conversion Setting Register R/W Flash 0 0 XXXXX0 B 00790FH to 00791FH Prohibited

(Continued)  Explanation on read/write  Explanation of initial values Note : No I/O instruction can be used for registers located between 007900H and 007FFFH. Address Register abbreviation Register Read/ Write Resource name Initial Value 007920H DBAPL DMA Buffer Address Pointer Lower 8-bit R/W μDMAC XXXXXXXXB 007921H DBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXXB 007922H DBAPH DMA Buffer Address Pointer Upper 8-bit R/W XXXXXXXXB 007923H DMACS DMA Control Register R/W XXXXXXXXB 007924H DIOAL DMA I/O Register Address Pointer Lower 8-bit R/W XXXXXXXX B 007925H DIOAH DMA I/O Register Address Pointer Upper 8-bit R/W XXXXXXXX B 007926H DDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXXB 007927H DDCTH DMA Data Counter Upper 8-bit R/W XXXXXXXXB 007928H to 007FFFH Prohibited R/W : Readable and Writable R : Read only W : Write only 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. - : Initial value is undefined (None).

22 DS07-13735-4E

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS (Continued) Interrupt source EI2OS support μDMAC Interrupt vector Interrupt control register Priority Number*1 Address ICR Address Reset × × #08 08 H FFFFDCH ⎯⎯ High INT 9 instruction × × #09 09 H FFFFD8H ⎯⎯ Exceptional treatment × × #10 0A H FFFFD4H ⎯⎯ USB Function1 × 0, 1 #11 0B H FFFFD0H ICR00 0000B0 H USB Function2 × 2 to 6* 2 #12 0C H FFFFCCH USB Function3 × × #13 0D H FFFFC8H ICR01 0000B1 H USB Function4 × × #14 0E H FFFFC4H USB HOST1 × × #15 0F H FFFFC0H ICR02 0000B2 H USB HOST2 × × #16 10 H FFFFBCH I2C ch.0 × × #17 11 H FFFFB8H ICR03 0000B3 H DTP/External interrupt ch.0/ch.1 × #18 12 H FFFFB4H No ⎯⎯ #19 13 H FFFFB0H ICR04 0000B4 H DTP/External interrupt ch.2/ch.3 × #20 14 H FFFFACH No ⎯⎯ #21 15 H FFFFA8H ICR05 0000B5 H DTP/External interrupt ch.4/ch.5 × #22 16 H FFFFA4H PWC/Reload timer ch.0 14 #23 17 H FFFFA0H ICR06 0000B6 H DTP/External interrupt ch.6/ch.7 × #24 18 H FFFF9CH No ⎯⎯ #25 19 H FFFF98H ICR07 0000B7 H No ⎯⎯ #26 1A H FFFF94H No ⎯⎯ #27 1B H FFFF90H ICR08 0000B8 H No ⎯⎯ #28 1C H FFFF8CH No ⎯⎯ #29 1D H FFFF88H ICR09 0000B9 H PPG ch.0/ch.1 × × #30 1E H FFFF84H No ⎯⎯ #31 1F H FFFF80H ICR10 0000BA H PPG ch.2/ch.3 × × #32 20 H FFFF7CH No ⎯⎯ #33 21 H FFFF78H ICR11 0000BB H No ⎯⎯ #34 22 H FFFF74H No ⎯⎯ #35 23 H FFFF70H ICR12 0000BC H No ⎯⎯ #36 24 H FFFF6CH UART (Send completed) ch.0/ch.1 13 #37 25 H FFFF68H ICR13 0000BD H Extended serial I/O × 9 #38 26 H FFFF64H UART(Reception completed) ch.0/ch.1 12 #39 27 H FFFF60H ICR14 0000BE H Time-base timer × × #40 28 H FFFF5CH Flash memory status × × #41 29 H FFFF58H ICR15 0000BF H Delay interrupt output module × × #42 2A H FFFF54H Low

(Continued) : Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. With a stop request). : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used. × : Unavailable *1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : Ch.2 and ch.3 can be used in USB HOST operation. Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS.

  • The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR).
  • If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “ 0 ” in the appropriate resource, and take measures by software polling. ■ CONTENT OF USB INTERRUPTION FACTOR * : End Point 1and 2 can be used in USB HOST operation. USB interrupt factor Details USB function 1 End Point 0-IN, End Point 0-OUT USB function 2 End Point 1-5 * USB function 3 SUSP, SOF, BRST, WKOP, COHF USB function 4 SPIT USB HOST1 DIRQ, CHHIRQ, URIRQ, RWKIRQ USB HOST2 SOFIRQ, CMPIRQ

24 DS07-13735-4E

■ USB 1. USB Function The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol. Features of USB function  Supports USB 2.0 Full Speed  Supports full speed (12 Mbps).  The device status is auto-answer.  Bit stripping, bit stuffing, and automa tic generation and check of CRC5 and CRC16.  Toggle check by data synchronization bit.  Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands).  The class vendor commands can be rece ived as data and responded via firmware.  Supports up to a maximum of six EndPoints (EndPoint0 is fixed to control transfer).  Two built-in transfer data buffers for each end point (one IN buffer and one OUT buffer for end point 0).  Supports automatic transfer mode for transfer da ta via DMA (except buffers for EndPoint0).

  1. USB HOST USB HOST provides minimal host operations required and is a function that enables data to be transferred between devices without PC intervention.
  • Features of USB HOST  Automatic detection of Low Speed/Full Speed transfer  Low Speed/Full Speed transfer support  Automatic detection of co nnection and cutting device  Reset sending function support to USB-bus  Support of IN/OUT/SETUP/SOF token  In-token handshake packet automatic transmission (excluding STALL)  Handshake packet automatic detection at out-token  Supports a maximum packet length of 256 bytes  Error (CRC error/toggle error/time-out) various supports  Wake-Up function support
  • Restrictions on USB HOST : Supported × : Not supported * : Only supports full speed, and supports hubs up to one level. USB HOST HUB support * Transfer Bulk transfer Control transfer Interrupt transfer Isochronous transfer × Transfer speed Low Speed Full Speed PRE packet support × SOF packet support Error CRC error Toggle error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection

26 DS07-13735-4E

■ SECTOR CONFIGURATION OF FLASH MEMORY SA0 (4 Kbytes) SA1 (4 Kbytes) SA2 (4 Kbytes) SA3 (4 Kbytes) FF0000H FF0FFFH FF1000H FF1FFFH FF2000H FF2FFFH 70000H 70FFFH 71000H 71FFFH 72000H 72FFFH SA4 (16 Kbytes) SA5 (16 Kbytes) SA6 (4 Kbytes) FF3000H FF3FFFH FF4000H FF7FFFH FF8000H FFBFFFH FFC000H FFCFFFH 73000H 73FFFH 74000H 77FFFH 78000H 7BFFFH 7C000H 7CFFFH SA7 (4 Kbytes) SA8 (4 Kbytes) SA9 (4Kbytes) FFD000H FFDFFFH FFE000H FFEFFFH FFF000H FFFFFFH 7D000H 7DFFFH 7E000H 7EFFFH 7F000H 7FFFFH Lower BankUpper Bank Flash Memory CPU address Writer address * * : Fl ash memory writer address indicates the address equivalent to the CPU address when data is written to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. 512 Kbits flash memory is located in FFH bank in the CPU memory map.

■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings *1 : The parameter is based on VSS = 0.0 V. *2 : V I and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : Applicable to pins : P60 to P67, UTEST (Continued) Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1 VCC VSS − 0.3 V SS + 4.0 V Input voltage*1 VI VSS − 0.3 V SS + 4.0 V *2 VSS − 0.3 V SS + 6.0 V N-ch open-drain (Withstand voltage I/O of 5 V)*3 − 0.5 V SS + 4.5 V USB I/O Output voltage*1 VO VSS − 0.3 V SS + 4.0 V *2 − 0.5 V SS + 4.5 V USB I/O Maximum clamp current I CLAMP − 2.0 +2.0 mA *4 Total maximum clamp current Σ⏐I CLAMP⏐⎯ 20 mA *4 “L” level maximum output current I OL1 ⎯ 10 mA Other than USB I/O* 5 IOL2 ⎯ 43 mA USB I/O* 5 “L” level average output current I OLAV1 ⎯ 4m A * 6 IOLAV2 ⎯ 15/4.5 mA USB-IO (Full speed/Low speed) * “L” level maximum total output current ΣI OL ⎯ 100 mA “L” level average total output current ΣI OLAV ⎯ 50 mA *7 “H” level maximum output current I OH1 ⎯ − 10 mA Other than USB I/O* 5 IOH2 ⎯ − 43 mA USB I/O* 5 “H” level average output current I OHAV1 ⎯ − 4m A * 6 IOHAV2 ⎯− 15/−4.5 mA USB-IO (Full speed/Low speed) * “H” level maximum total output current ΣI OH ⎯ − 100 mA “H” level average total output current ΣI OHAV ⎯ − 50 mA *7 Power consumption Pd ⎯ 270 mW Operating temperature T A − 40 + 85 °C Storage temperature Tstg − 55 + 150 °C − 55 + 125 °C USB I/O

28 DS07-13735-4E

(Continued) *4 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P54

  • Use within recommended operating conditions.
  • Use at DC voltage (current)
  • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
  • The value of the limiting resistan ce should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
  • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
  • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
  • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
  • Care must be taken not to leave the +B input pin open.
  • Note that analog system input/out put pins other than P60 to P67, DVP , DVM, HVP , HVM, UTEST, HCON
  • Sample recommended circuits: *5 : A peak value of an applicable one pi n is specified as a maximum output current. *6 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *7 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. P-ch N-ch VCC R  Input/output equivalent circuits +B input (0 V to 16 V) Limiting resistance Protective diode
  1. Recommended Operating Conditions (VSS = 0.0 V) * : Applicable to pins : P60 to P67, UTEST WARNING: The recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Value Unit Remarks Min Max Power supply voltage V CC 3.0 3.6 V At normal operation (When using USB) 2.7 3.6 V At normal operation (When not using USB) 1.8 3.6 V Hold state of stop operation Input “H” voltage VIH 0.7 VCC VCC + 0.3 V CMOS input pin VIHS1 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHS2 0.8 VCC VSS + 5.3 V N-ch open-drain (Withstand voltage I/O of 5 V)* VIHM VCC − 0.3 V CC + 0.3 V MD pin input VIHUSB 2.0 V CC + 0.3 V USB pin input Input “L” voltage VIL VSS − 0.3 0.3 V CC V CMOS input pin VILS VSS − 0.3 0.2 V CC V CMOS hysteresis input pin VILM VSS − 0.3 V SS + 0.3 V MD pin input VILUSB VSS 0.8 V USB pin input Differential input sensitivity V DI 0.2 ⎯ V USB pin input Differential common mode input voltage range V CM 0.8 2.5 V USB pin input Operating temperature T A − 40 + 85 °C When not using USB 0 + 70 °C When using USB

30 DS07-13735-4E

  1. DC Characteristics (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) (Continued) Parameter Sym- bol Pin name Conditions Value Unit RemarksMin Typ Max Output “H” voltage VOH Output pins other than P60 to P67, HVP , HVM, DVP , DVM I OH = −4.0 mA VCC − 0.5 ⎯ Vcc V HVP , HVM, DVP , DVM RL = 15 kΩ ± 5% 2.8 ⎯ 3.6 V Output “L” voltage V OL Output pins other than HVP , HVM, DVP , DVM IOL = 4.0 mA Vss ⎯ Vss + 0.4 V HVP , HVM, DVP , DVM RL = 1.5 kΩ ± 5% 0 ⎯ 0.3 V Input leak current I IL Input pins other than P60 to P67, HVP , HVM, DVP , DVM VCC = 3.3 V, Vss < VI < VCC − 10 ⎯ + 10 μA HVP , HVM, DVP , DVM ⎯− 5 ⎯ + 5 μA Pull-up resistance R PULL P00 to P07, P10 to P17 V CC = 3.3 V, TA = + 25 °C 25 50 100 k Ω Open drain output leak current I LIOD P60 to P67 ⎯⎯ 0.1 10 μA Power supply current I CC VCC VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At USB operating (USTP = 0) ⎯ 55 65 mA MB90F337 ⎯ 50 60 mA MB90337 V CC = 3.3 V, Internal frequency 24 MHz, At normal operating At non-operating USB (USTP = 1) ⎯ 50 60 mA MB90F337 ⎯ 45 55 mA MB90337 I CCS VCC = 3.3 V, Internal frequency 24 MHz, At sleep mode ⎯ 25 40 mA I CTS VCC = 3.3 V, Internal frequency 24 MHz, At timer mode ⎯ 3.5 10 mA V CC = 3.3 V, Internal frequency 3 MHz, At timer mode ⎯ 1.0 2.0 mA I CCH TA = +25 °C, At stop mode ⎯ 14 0 μA

(Continued) (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Note : P60 to P67 are N-ch open-drain pins usually used as CMOS. Parameter Sym- bol Pin name Conditions Value Unit RemarksMin Typ Max Input capacitance CIN Other than Vcc and Vss ⎯⎯ 51 5 p F Pull-up resistor Rup RST ⎯ 25 50 100 k Ω Pull-down resistor R down MD2 VCC = 3.0 V At TA = +25 °C 25 50 100 k Ω MB90337 USB I/O output impedance Z USB DVP, DVM HVP, HVM ⎯ 3 ⎯ 14 Ω

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  1. AC Characteristics (1) Clock input timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Sym- bol Pin name Value Unit Remarks Min Typ Max Clock frequency f CH X0, X1 ⎯ 6 ⎯ MHz When oscillator is used 6 ⎯ 24 MHz External clock input Clock cycle time tHCYL X0, X1 ⎯ 166.7 ⎯ ns When oscillator is used 166.7 ⎯ 41.7 ns External clock input Input clock pulse width PWH PWL X0 10 ⎯⎯ ns A reference duty ratio is 30% to 70%. Input clock rise time and fall time tcr tcf X0 ⎯⎯ 5 ns At external clock Internal operating clock frequency f CP ⎯ 3 ⎯ 24 MHz When main clock is used Internal operating clock cycle time t CP ⎯ 42 ⎯ 333 ns When main clock is used

0.8 VCC

0.2 VCC

  • Clock Timing

The AC standards provide that the following measurement reference voltages.

  • PLL operation guarantee range Relation between power supply voltage and internal operation clock frequency Note : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V. Relation between internal operation clock frequency and external clock frequency 3.6 3.0 2.7 3 6 12 24 Internal clock fCP (MHz) Power supply voltage VCC (V) PLL operation guarantee range Normal operation assurance range Internal clock fCP (MHz) External clock FC (MHz) 4 x 2 x 1 x External clock

2.4 V 0.8 V

0.7 VCC

0.3 VCC

  • Input signal waveform Hysteresis input pin Hysteresis input/other than MD input pin
  • Output signal waveform Output pin

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(2) Reset (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) * : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock. Parameter Sym- bol Pin name Conditions Value Unit Remarks Min Max Reset input time tRSTL RST ⎯ 500 ⎯ ns At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode Oscillation time of oscillator* + 500 ns ⎯μ s At stop mode RST 500 ns tRSTL 0.2 VCC 0.2 VCC RST tRSTL 0.2 VCC 0.2 VCC

  • During stop mode Internal operation clock Internal reset Oscillation time of oscillator Oscillation stabilization wait time Execute instruction 90% of amplitude
  • During normal operation, time-base timer mode, main sleep mode and PLL sleep mode

(3) Power-on reset (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Notes : • VCC must be lower than 0.2 V before the power supply is turned on.  The above standard is a value for performing a power-on reset.  In the device, there are internal registers which is initialized only by a power-on reset. When the initialization of these items is expected, turn on the power supply according to the standards. Note : Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Power supply rising time t R VCC 0.05 30 ms Power supply shutdown time t OFF VCC 1 ⎯ ms Waiting time until power-on VCC tR 0.2 V0.2 V 2.7 V tOFF 0.2 V VCC 3.0 V VSS RAM data hold The rising edge should be 50 mV/ms or less.

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(4) UART0, UART1 I/O extended serial timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Notes : • Above rating is the case of CLK synchronous mode.

  • CL is a load capacitance value on pins for testing.
  • tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”. Parameter Symbol Pin name Conditions Value UnitMin Max Serial clock cycle time tSCYC SCKx Internal shift clock Mode output pin is C L = 80 pF + 1 TTL 8 tCP ⎯ ns SCK ↓ → SOT delay time t SLOV SCKx SOTx − 80 + 80 ns Valid SIN → SCK ↑ tIVSH SCKx SINx 100 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCKx SINx 60 ⎯ ns Serial clock H pulse width t SHSL SCKx, SINx External shift clock Mode output pin is C L = 80 pF + 1 TTL 4 tCP ⎯ ns Serial clock L pulse width t SLSH SCKx, SINx 4 tCP ⎯ ns SCK ↓ → SOT delay time t SLOV SCKx SOTx ⎯ 150 ns Valid SIN → SCK ↑ t IVSH SCKx SINx 60 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCKx SINx 60 ⎯ ns
  • Internal shift clock mode
  • External shift clock mode SCK SOT SIN tSCYC tSLOV tIVSH tSHIX 0.8 V 0.8 V 2.4 V 2.4 V 0.8 V

0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC 2.4 V 0.8 V

(5) I2C timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) *1 : fCP is internal operating clock frequency. Refer to “ (1) Clock input timing”. *2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance. *3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *4 : Refer to “• Note of SDA, SCL set-up time”. Parameter Symbol Conditions Value Unit Min Max SCL clock frequency f SCL Power-supply of external pull-up resistor at 5.0 V R = 1.2 kΩ, C = 50 pF* Power-supply of external pull-up resistor at 3.6 V R = 1.0 kΩ, C = 50 pF* 0 100 kHz (Repeat) [start] condition hold time SDA ↓ → SCL ↓ t HDSTA 4.0 ⎯μ s SCL clock “L” width t LOW 4.7 ⎯μ s SCL clock “H” width t HIGH 4.0 ⎯μ s Repeat [start] condition setup time SCL ↑ → SDA ↓ t SUSTA 4.7 ⎯μ s Data hold time SCL ↓ → SDA ↓ ↑ t HDDAT 03 . 4 5 * 3 μs Data setup time SDA ↓ ↑ → SCL ↑ t SUDAT Power-supply of external pull-up resistor at 5.0 V f CP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V f CP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 250*4 ⎯ ns Power-supply of external pull-up resistor at 5.0 V f CP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V f CP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2 200*4 ⎯ [Stop] condition setup time SCL ↑ → SDA ↑ t SUSTO Power-supply of external pull-up resistor at 5.0 V R = 1.2 kΩ, C = 50 pF* Power-supply of external pull-up resistor at 3.6 V R = 1.0 kΩ, C = 50 pF* 4.0 ⎯μ s Bus free time between [stop] condition and [start] condition t BUS 4.7 ⎯μ s

38 DS07-13735-4E

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. SDA SCL 6 tcp

  • Note of SDA, SCL set-up time Input data set-up time SDA SCL tLOW tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO tHDSTA tHIGH tBUS
  • Timing definition

(6) Timer Input Timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Note : tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”. (7) Timer output timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) (8) Trigger Input Timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C) Note : tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”. Parameter Symbol Pin name Conditions Value Unit Min Max Input pulse width tTIWH tTIWL PWC ⎯ 4 tCP ⎯ ns Parameter Symbol Pin name Conditions Value Unit Min Max CLK ↑ → TOUT change time PPG0 to PPG3 change time tTO PPGx ⎯ 30 ⎯ ns Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL INTx ⎯ 5 tCP ⎯ ns At normal operating 1 ⎯μ s At Stop mode 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWH tTIWL PWC CLK PPGx 2.4 V tTO 2.4 V 0.8 V 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTRGH tTRGL INTx

40 DS07-13735-4E

  1. USB characteristics (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to +70 °C) * : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.
  • Data signal timing (Full Speed)
  • Data signal timing (Low Speed) Parameter Symbol Sym- bol Value Unit Remarks Min Max Input characteristics Input High level voltage VIH 2.0 ⎯ V Input Low level voltage VIL ⎯ 0.8 V Differential input sensitivity V DI 0.2 ⎯ V Differential common mode range V CM 0.8 2.5 V Output characteristics Output High level voltage V OH 2.8 3.6 V I OH = −200 μA Output Low level voltage V OL 0.0 0.3 V I OL = 2 mA Cross over voltage VCRS 1.3 2.0 V Rise time tFR 4 20 ns Full Speed tLR 75 300 ns Low Speed Fall time tFF 4 20 ns Full Speed tLF 75 300 ns Low Speed Rising/falling time matching tRFM 90 111.11 % (TFR/TFF) tRLM 80 125 % (TLR/TLF) Output impedance Z DRV 28 44 Ω Including Rs = 27 Ω Series resistance RS 25 30 Ω Recommended value = 27 Ω at using USB*DVM/HVM 90% tFR 10% 90% 10% tFF VCRS DVP/HVP Rise time Fall time HVP 90% tLR 10% 90% 10% tLF VCRS HVM Rise time Fall time
  • Load condition (Full Speed)
  • Load condition (Low Speed) DVP/HVP RS = 27 Ω CL = 50 pF DVM/HVM RS = 27 Ω ZUSB ZUSB CL = 50 pF Testing point Testing point HVP RS = 27 Ω CL = 50 pF ∼ 150 pF HVM RS = 27 Ω CL = 50 pF ∼ 150 pF ZUSB ZUSB Testing point Testing point

42 DS07-13735-4E

  1. Flash memory write/erase characteristics * : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) Parameter Condition Value Unit Remarks Min Typ Max Sector erase time (4 Kbytes sector) TA = + 25 °C VCC = 3.0 V ⎯ 0.2 0.5 s Excludes 00H programming prior to erasure. Sector erase time (16 Kbytes sector) ⎯ 0.5 7.5 s Excludes 00H programming prior to erasure. Chip erase time ⎯ 2.6 ⎯ s Excludes 00H programming prior to erasure. Word (8 bits width) programming time ⎯ 16 3600 μs Except for over head time of system Program/erase cycle ⎯ 10000 ⎯⎯ cycle Flash data retention time Average T A = + 85 °C 20 ⎯⎯ year *

■ ORDERING INFORMATION Part number Package Remarks MB90F337PMC MB90337PMC 64-pin plastic LQFP (FPT-64P-M23) MB90V330ACR 299-pin ceramic PGA (PGA-299C-A01) For evaluation

44 DS07-13735-4E

■ PACKAGE DIMENSION Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.0 × 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP64-12×12-0.65 64-pin plastic LQFP (FPT-64P-M23) (FPT-64P-M23) C 2003 FUJITSU LIMITED F64034S-c-1-1 0.65(.026) 0.10(.004) 1 16 3249 3348 INDEX 0.32±0.05 (.013±.002) M0.13(.005) 0.145±0.055 (.0057±.0022) "A" .059 –.004 +.008 –0.10 +0.20 1.50 0~8˚ 0.25(.010) (Mounting height) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) Details of "A" part (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3)P i ns width do not include tie bar cutting remainder.

■ MAIN CHANGES IN THIS EDITION The vertical lines marked in the left side of the page show the changes. Page Section Change Results ⎯⎯ Changed the USB. USB Mini-Host → USB HOST 11 ■ HANDLING DEVICES Added the it em “9. Serial communication”. ⎯ ■ PERIPHERAL RESOURCES Deleted the section. 24, 25 ■ USB Changed the item name from “PERIPHERAL RESOURCES” to “USB Function”. 2. USB HOST Changed the title of the table: Differences between the USB HOST and USB Mini-HOST → Restrictions on USB HOST Changed “HUB support”. → * Added the following under the table: “* : Only supports full speed, and supports hubs up to one level.” 26 ■ SECTOR CONFIGURATION OF FLASH MEMORY Changed the item name from “PERIPHERAL RESOURCES” to “SECTOR CONFIGURATION OF FLASH MEMORY”. 30 ■ ELECTRICAL CHARACTERISTICS 3. DC Characteristics Corrected the column of pin name of Input leak current param- eter. Output pins → Input pins

46 DS07-13735-4E

FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD.

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Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD.

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#05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Y an An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F ., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONI CS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department