MB90333A

MB90330 FUJITSU | Alldatasheet

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DS07-13734-1EFUJITSU SEMICONDUCTOR DATA SHEET 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90330 Series MB90333A/F334A/V330A ■ DESCRIPTION The MB90330 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also Mini-HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the A T architecture of the F 2MC* family, the instruction set supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by intro- ducing a 32-bit accumulator. * : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. ■ FEATURES

Clock
Built-in oscillation circuit and PLL clock frequency multiplication circuit Oscillation clock The main clock is the oscillation clock divi ded into 2 (for oscillation 6 MHz : 3 MHz) Clock for USB is 48 MHz Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V

CC = 3.3 V . (Continued) ■ PACKAGES 120-pin Plastic LQFP 120-pin Plastic LQFP (FPT-120P-M05) (FPT-120P-M21)

(Continued)

The maximum memory space : 16 MB
24-bit addressing
Bank addressing
Instruction system Data types : Bit, Byte, Word and Long word Addressing mode (23 types) Enhanced high-precision computi ng with 32-bit accumulator Enhanced Multiply/Divide instructions with sign and the RETI instruction
Instruction system compatible with high-level language (C language) and multi-task Employing system stack pointer Instruction set symmetry and barrel shift instructions
Program Patch Function (2 address pointer)
4-byte instruction queue
Interrupt function Priority levels are programmable 32 interrupts function
Data transfer function Extended intelligent I/O service function (EI 2OS) : Maximum of 16 channels µDMAC : Maximum 16 channels
Low Power Consumption Mode Sleep mode (with the CPU operating clock stopped) Time-base timer mode (with the oscillato r clock and time-base timer operating) Stop mode (with the oscillator clock stopped) CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) Watch mode (with 32 kHz oscillato r clock and watch timer operating)
Package LQFP-120P (FPT -120P-M05 : 0.40 mm pin pitch) LQFP-120P (FPT -120P-M21 : 0.50 mm pin pitch)
Process : CMOS technology
Operation guaranteed temperature : − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)

■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)

I/O port : Max 94 ports
Time-base timer : 1 channel
Watchdog timer : 1 channel
Watch timer : 1channel
16-bit reload timer : 3 channels
Multi-functional timer 16-bit free run timer : 1 channel Output compare : 4 channels An interrupt request can be output when the 16-bit free-run timer value matches the compare register value. Input capture : 4channels Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the input capture data register to the 16-bit free-run timer value to output an interrupt request. 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) the period and duty of the output pulse can be set by the program. 16-bit PWC timer : 1 channel Timer function and pulse width measurement function
UART : 4 channels Full-duplex double buffer (8-bit length) Asynchronous transfer or clock-synchronous seri al (I/O extended serial) transfer can be set.
I/O extended serial interface : 1 channel
DTP/External interrupt circuit (8 channels) Activate the extended intelligent I/O service by external interrupt input Interrupt output by external interrupt input
Delay interrupt output module Output an interrupt request for task switching
8/10-bit A/D converter : 16 channels 8-bit resolution or 10-bit resolution can be set.
USB : 1 channel USB function (conform to USB2.0 Full Speed) Full Speed is supported/Endpoint are specifiable up to six. Dual port RAM (The FIFO mode is supported). T ransfer type : Control, Interrupt, Bulk, or Isochronous transfer possible USB Mini-HOST function
I2C* Interface : 3 channels Supports Intel SM bus standard and Phillips I2C bus standards T wo-wire data transfer protocol specification Master and slave transmission/reception * : I 2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

■ PRODUCT LINEUP * : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. Part number MB90V330A MB90F334A MB90333A Type For evaluation Built-in Flash memory Built-in Mask ROM ROM capacity No 384 KB 256 KB RAM capacity 28 KB 24 KB 16 KB Emulator-specific power supply * Used bit ⎯ CPU functions Number of basic instructions Minimum instruction execution time Addressing type Program Patch Function Maximum memory space : 351 instructions : 41.6 ns/at oscillation of 6 MHz (When 4 times are used : Machine clock of

24 MHz)

: 23 types : For 2 address pointers : 16 MB Ports I/O Ports (CMOS) 94 ports UART Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable It can also be used for I/O serial Built-in special baud-rate generator Built-in 4 channels 16-bit reload timer 16-bit reload timer operation Built-in 3 channels Multi-functional timer 16-bit free run timer × 1 channel Output compare × 4 channels Input capture × 4 channels 8/16-bit PPG timer (8-bit mode × 6 channels, 16-bit mode × 3 channels) 16-bit PWC timer × 1 channel 8/10-bit A/D converter 16 channels (input multiplex) 8-bit resolution or 10-bit resolution can be set. Conversion time : 7.16 µs at minimum (24 MHz machine clock at maximum) DTP/External interrupt 8 channels Interrupt factor : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable I 2C 3 channels I/O extended serial interface 1 channel USB 1 channel USB function (conform to USB2.0 Full Speed) USB Mini-HOST function External bus interface For multi-bus/non-multi-bus Withstand voltage of 5 V 16 ports (excluding VBUS and I/O for I 2C) Low Power Consumption Mode Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/ Watch mode Process CMOS Operating voltage 3.3 V ± 0.3 V (at maximum machine clock 24 MHz)

■ PACKAGES AND PRODUCT MODELS : Yes × : No Note : For detailed information on each package, see “■ P ACKAGE DIMENSIONS”. FPT-120P-M05 (LQFP-0.40 mm) × FPT-120P-M21 (LQFP-0.50 mm) × PGA-299C-A01 (PGA) × ×

■ PIN ASSIGNMENT (TOP VIEW) (FPT-120P-M05 / FPT-120P-M21) P30/A00/TIN1 P31/A01/TOT1 P32/A02/TIN2 P33/A03/TOT2 P34/A04 P35/A05 P36/A06 P37/A07 P40/A08/TIN0 P41/A09/TOT0 P42/A10/SIN0 P43/A11/SOT0 X0A X1A Vcc Vss P44/A12/SCK0 P45/A13/SIN1 P46/A14/SOT1 P47/A15/SCK1 P60/INT0 P61/INT1 P62/INT2/SIN P63/INT3/SOT P64/INT4/SCK P65/INT5/PWC P66/INT6/SCL0 P67/INT7/SDA0 P90/SIN2 P91/SOT2 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 P27/A23/PPG P26/A22/PPG2 P25/A21/PPG1 P24/A20/PPG0 P23/A19 P22/A18 P21/A17 P20/A16 P17/AD15/D1 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 Vss Vcc P13/AD11/D1 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 P57/CLK P56/RDY P92/SCK2 P93/SIN3 P94/SOT3 P95/SCK3 P96/ADTG/FRCK AVcc AVRH AVss P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 Vss P80/AN8 P81/AN9 P82/AN10 P83/AN11 P84/AN12 P85/AN13 P86/AN14 P87/AN15 PA0/IN0 PA1/IN1 PA2/IN2 PA3/IN3 PA4/OUT0 RST MD0 MD1 MD2 P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE HCON Vcc HVP HVM Vss Vcc DVP DVM Vss VBUS PB6/PPG5 PB5/PPG4 PB4 PB3/SDA2 PB2/SCL2 PB1/SDA1 PB0/SCL1 PA7/OUT3 PA6/OUT2 PA5/OUT1

■ PIN DESCRIPTION (Continued) Pin no. Pin name Circuit type* FunctionLQFP 108, 107 X0, X1 A Terminals to connect the oscillator. When connecting an external clock, leave the X1 pin side unconnected. 13, 14 X0A, X1A A 32 kHz oscillation terminals. 90 RST F External reset input pin. 93 to 100 P00 to P07 H General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.) AD00 to AD07 Function as an I/O pin for the low-order external address and data bus in multiplex mode. D00 to D07 Function as an output pin for the low-order external data bus in non- multiplex mode. 101 to 104 P10 to P13 H General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) AD08 to AD11 Function as an I/O pin for the high-order external address and data bus in multiplex mode. D08 to D11 Function as an output pin for the high-order external data bus in non- multiplex mode. 109 to 112 P14 to P17 H General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) AD12 to D15 Function as an I/O pin for the high-order external address and data bus in multiplex mode. D12 to D15 Function as an output pin for the high-order external data bus in non- multiplex mode. 113 to 116 P20 to P23 D This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. A16 to A19 When the bits of external address output control register (HACR) are set to “0” in multiplex mode, these pins function as address high output pins (A16 to A19). A16 to A19 When the bits of external address output control register (HACR) are set to “0” in non-multiplex mode, these pins function as address high output pins (A16 to A19).

(Continued) Pin no. Pin name Circuit type* FunctionLQFP 117 to 120 P24 to P27 D This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. A20 to A23 When the bits of external address output control register (HACR) are set to “0” in multiplex mode, these pins function as address high output pins (A20 to A23). A20 to A23 When the bits of external address output control register (HACR) are set to “0” in non-multiplex mode, these pins function as address high output pins (A20 to A23). PPG0 to PPG3 Function as ch0 to ch3 output pins for the 8-bit PPG timer. P30 D General purpose input/output port. A00 Function as the external addre ss pin in non-multi-bus mode. TIN1 Function as an event input pi n for 16-bit reload timer ch1. P31 D General purpose input/output port. A01 Function as the external addre ss pin in non-multi-bus mode. TOT1 Function as the output pin for 16-bit reload timer ch1. P32 D General purpose input/output port. A02 Function as the external addre ss pin in non-multi-bus mode. TIN2 Function as an event input pi n for 16-bit reload timer ch2. P33 D General purpose input/output port. A03 Function as the external addre ss pin in non-multi-bus mode. TOT2 Function as the output pin for 16-bit reload timer ch2. 5 to 8 P34 to P37 D General purpose input/output port. A04 to A07 Function as the external address pin in non-multi-bus mode. P40 G General purpose input/output port. A08 Function as the external addre ss pin in non-multi-bus mode. TIN0 Function as an event input pi n for 16-bit reload timer ch0. P41 G General purpose input/output port. A09 Function as the external addre ss pin in non-multi-bus mode. TOT0 Function as the output pin for 16-bit reload timer ch0. P42 G General purpose input/output port. A10 Function as the external addre ss pin in non-multi-bus mode. SIN0 Function as a data input pin for UART ch0. P43 G General purpose input/output port. A11 Function as the external addre ss pin in non-multi-bus mode. SOT0 Function as a data output pin for UART ch0. P44 G General purpose input/output port. A12 Function as the external addre ss pin in non-multi-bus mode. SCK0 Function as a clock I/O pin for UART ch0.

(Continued) Pin no. Pin name Circuit type* FunctionLQFP P45 G General purpose input/output port. A13 Function as the external address pin in non-multi-bus mode. SIN1 Function as a data input pin for UART ch1. P46 G General purpose input/output port. A14 Function as the external address pin in non-multi-bus mode. SOT1 Function as a data output pin for UART ch1. P47 G General purpose input/output port. A15 Function as the external address pin in non-multi-bus mode. SCK1 Function as a clock I/O pin for UART ch1. P50 L General purpose input/output port. ALE Function as the address latch enable signal (ALE) pin in external bus mode. 82 P51 L General purpose input/output port. RD Function as the read strobe output (RD) pin in external bus mode. P52 L General purpose input/output port. WRL Function as the data write strobe output (WRL) pin on the lower side in external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is “0”. P53 L General purpose input/output port. WRH Function as the data write strobe output (WRH) pin on the higher side in bus width 16-bit external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is “0”. P54 L General purpose input/output port. HRQ Function as the hold request input (HRQ) pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is “0”. P55 L General purpose input/output port. HAK Function as the hold acknowledge output (HAK) pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is “0”. P56 L General purpose input/output port. RDY Function as the external ready input (RDY) pin in external bus mode. This pin functions as a general-purpose I/O port when the RYE bit in the EPCR register is “0”. P57 L General purpose input/output port. CLK Function as the machine cycle clock output (CLK) pin in external bus mode. This pin functions as a general-purpose I/O port when the CKE bit in the EPCR register is “0”. 21, 22 P60, P61 C General purpose input/output port. (With stand voltage of 5 V) INT0, INT1 Function as external interrupt ch0 and ch1 input pins.

(Continued) Pin no. Pin name Circuit type* FunctionLQFP P62 C General purpose input/output ports. (Withstand voltage of 5 V) INT2 Function as an external interrupt ch2 input pin. SIN Simple serial I/O data input pin. P63 C General purpose input/output port. (Withstand voltage of 5 V) INT3 Function as an external interrupt ch3 input pin. SOT Simple serial I/O data output pin. P64 C General purpose input/output port. (Withstand voltage of 5 V) INT4 Function as an external interrupt ch4 input pin. SCK Simple serial I/O clock input/output pin. P65 C General purpose input/output port. (Withstand voltage of 5 V) INT5 Function as an external interrupt ch5 input pin. PWC Function as the PWC input pin. P66 C General purpose input/output port. (Withstand voltage of 5 V) INT6 Function as an external interrupt ch6 input pin. SCL0 Function as the ch0 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. P67 C General purpose input/output port. (Withstand voltage of 5 V) INT7 Function as an external interrupt ch7 input pin. SDA0 Function as the ch0 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. 39 to 46 P70 to P77 I General purpose input/output port. AN0 to AN7 Function as input pins for analog ch0 to ch7. 48 to 55 P80 to P87 I General purpose input/output port. AN8 to AN15 Function as input pi ns for analog ch8 to ch15. 29 P90 D General purpose input/output port. SIN2 Function as a data input pin for UART ch2. 30 P91 D General purpose input/output port. SOT2 Function as a data output pin for UART ch2. 31 P92 D General purpose input/output port. SCK2 Function as a clock I/O pin for UART ch2. 32 P93 D General purpose input/output port. SIN3 Function as a data input pin for UART ch3. 33 P94 D General purpose input/output port. SOT3 Function as a data output pin for UART ch3. 34 P95 D General purpose input/output port. SCK3 Function as a clock I/O pin for UART ch3. P96 C General purpose input/output port. (Withstand voltage of 5 V) ADTG Function as the external trigger input pin when the A/D converter is being used. FRCK Function as the external clock input pi n when the free-run timer is being used.

: For circuit information, see “■ I/O CIRCUIT TYPE”. Pin no. Pin name Circuit type* FunctionLQFP 56 to 59 PA0 to PA3 C General purpose input/output port. (Withstand voltage of 5 V) IN0 to IN3 Function as the input ca pture ch0 to ch3 trigger inputs. 60 to 63 PA4 to PA7 C General purpose input/output port. (Withstand voltage of 5 V) OUT0 to OUT3 Function as the output co mpare ch0 to ch3 event output pins. PB0 C General purpose input/output port. (Withstand voltage of 5 V) SCL1 Function as the ch1 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. PB1 C General purpose input/output port. (Withstand voltage of 5 V) SDA1 Function as the ch1 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. PB2 C General purpose input/output port. (Withstand voltage of 5 V) SCL2 Function as the ch2 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. PB3 C General purpose input/output port. (Withstand voltage of 5 V) SDA2 Function as the ch2 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. 68 PB4 C General purpose input/output port. (Withstand voltage of 5 V) 69, 70 PB5, PB6 D General purpose input/output port. PPG4, PPG5 Function as ch4 and ch5 out put pins for the 8-bit PPG timer. 71 VBUS C Terminal for state detection of USB cable. (Withstand voltage of 5 V) 73 DVM K USB function D − pin. 74 DVP K USB function D + pin. 77 HVM K USB Mini-HOST D − pin. 78 HVP K USB Mini-HOST D + pin. 80 HCON E External pull-up resistor connect pin. 36 AVcc ⎯ A/D converter power supply pin. 37 AVRH J A/D converter external reference power supply pin. 38 AVss ⎯ A/D converter power supply pin. 87 to 89 MD2 to MD0 B Operation mode select input pin. 15 Vcc ⎯ Power supply pin. 75 Vcc ⎯ Power supply pin. 79 Vcc ⎯ Power supply pin. 105 Vcc ⎯ Power supply pin. 16 Vss ⎯ Power supply pin (GND). 47 Vss ⎯ Power supply pin (GND). 72 Vss ⎯ Power supply pin (GND). 76 Vss ⎯ Power supply pin (GND). 106 Vss ⎯ Power supply pin (GND).

■ I/O CIRCUIT TYPE (Continued) Type Circuit Remarks A High-rate oscillation feedback resistor, approx.1 MΩ Low-rate oscillation feedback resistor, approx.10 MΩ With standby control B CMOS hysteresis input C CMOS hysteresis input Nch open drain output D CMOS output CMOS hysteresis input (With input interception function at standby) Notes : • Share one output buffer because both output of I/O port and internal resource are used.

Share one input buffer because both input of I/O port and internal resource are used. E CMOS output F CMOS hysteresis input with pull-up resistor X1A X0A Standby control signal Clock input Hysteresis input NoutNch Hysteresis input Standby control signal Pout Nout Pch Nch Hysteresis input Standby control signal Pout Nout Pch Nch R Hysteresis input

(Continued) Type Circuit Remarks G CMOS output CMOS hysteresis input (With input interception function at standby) With open drain control signal H CMOS output CMOS input (With input interception function at standby) With input pull-up register control I CMOS output CMOS hysteresis input (With input interception function at standby) Analog input (The A/D converter analog input is enabled when the corresponding bit in the analog input enable register (ADER) is 1.) Notes: • Because the output of the I/O port and the output of internal resources are used combinedly, one output buffer is shared.

Because the input of the I/O port and the input of internal resources are used combinedly, one input buffer is shared. J A/D converter (AVRH) voltage input pin Pout Nout Pch Nch Open drain control signal Standby control signal Hysteresis input Pout Nout Pch R Nch CTL CMOS input Standby control signal Pout Nout Pch Nch Hysteresis input Standby control signal A/D converter analog input Pch Nch Pch Nch A/D converter analog input enable signal AVRH input

(Continued) Type Circuit Remarks K U S B I / O p i n L CMOS output CMOS input With standby control D + input D - input Differential input Full D + output Full D - output Low D + output Low D - output Direction Speed Pout Nout Pch Nch CMOS input Standby control signal

■ HANDLING DEVICES 1. Preventing latchup and turning on power supply Latchup may occur on CMOS IC under the following conditions:

If a voltage higher than VCC or lower than VSS is applied to input and output pins.
A voltage higher than the rated voltage is applied between VCC and VSS.
If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the anal og power supply at the same time as V CC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating. 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latchup, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k Ω. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. 3. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 4. About the attention when the external clock is used
Using external clock 5. Treatment of power supply pins (V CC/VSS) In products with multiple VCC or VSS pins, the pins of the same potentia l are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the V CC and VSS pins of this device at the low impedance. It is also advisable to connect a cerami c bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. 6. About Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1 pins and X0A/X1A pins, the crys tal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded by ground plane because stable operation can be expected with such a layout. X1OPEN

Caution on Operations during PLL Clock Mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-runni ng frequency of the PLL in ternal automatic oscillator circuit. Performance of this operation, however, cannot be guaranteed. 8. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at temporary ch anges such as power supply switching. 9. When the dual-supply is used as a single-supply device If you are using only a single-system of the MB90330 seri es that come in the dual-system product, use it with X0A = VSS : X1A = OPEN. 10. Writing to flash memory For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V . For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V .

■ BLOCK DIAGRAM F2MC-16LX CPU RAM ROM UART/SIO ch0 to ch3 I2C ch0 to ch2 P00 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 X0, X1 X0A,X1A RST MD0 to MD2 SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3 SCL0 to SCL2 SDA0 to SDA2 INT0 to INT7 AVCC AVRH AVSS AN0 to AN15 ADTG DVP DVM HVP HVM HCON VBUS TOT0 to TOT2 TIN0 to TIN2 PPG0 to PPG5 FRCK IN0 to IN3 OUT0 to OUT3 PWC SIN SOT SCK P80 P87 P70 P77 P90 P96 PB0 PB6 PA0 PA7 * : Channel for use in 8-bit mode. 3 channels (ch1, ch3, ch5) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral function (resources) cannot serve as I/O ports. 8/10-bit A/D converter 16-bit reload timer ch0 to ch2 USB (Function) (Mini-HOST) External interrupt µDMAC SIO 16-bit PWC Output compare ch0 to ch3 16-bit free-run timer Input capture ch0 to ch3 8/16-bit PPG timer ch0 to ch5* Clock control circuit Interrupt controller Internal data bus

■ MEMORY MAP Memory map of MB90330 series (1/3) FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 007100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90V330A FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 006100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90F334A FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 004100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90333A ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (image of FF bank) ROM (image of FF bank) ROM (image of FF bank) Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area RAM area (28KB) RAM area (24KB) RAM area (16KB) Register Register Register Single chip mode (with ROM mirror function)

Memory map of MB90330 series (2/3) FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 007100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90V330A FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 006100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90F334A FFFFFFH FBFFFFH 00FFFFH 007FFFH 000000H F90000H 0000FBH 000100H 004100H 007900H 008000H F80000H F8FFFFH F9FFFFH FA0000H FAFFFFH FB0000H FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H MB90333A ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (image of FF bank) ROM (image of FF bank) ROM (image of FF bank) Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area RAM area (28KB) RAM area (24KB) RAM area (16KB) Register Register Register External area External area External areaExternal areaExternal area External areaExternal areaExternal area Internal ROM external bus mode (with ROM mirror function) *1 : In the area of F80000 H to F8FFFFH and FC0000H to FCFFFFH at MB90F334, a value of “1” is read at read operating. *2 : In the area of FA0000 H to FAFFFFH and FC0000H to FCFFFFH at MB90333, a value of “1” is read at read operating.

Memory map of MB90330 series (3/3) Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

The ROM mirror function is effective for using the C compiler small model.
The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 KB, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00.
When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. FFFFFFH 007FFFH 000000H 0000FBH 000100H 007100H 007900H 008000H MB90V330A FFFFFFH 007FFFH 000000H 0000FBH 000100H 006100H 007900H 008000H MB90F334A FFFFFFH 007FFFH 000000H 0000FBH 000100H 004100H 007900H 008000H MB90333A Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area Peripheral area RAM area (28KB) RAM area (24KB) RAM area (16KB) Register Register Register External areaExternal areaExternal area External areaExternal areaExternal area External ROM external bus mode

■ F2MC-16L CPU PROGRAMMING MODEL

Dedicated register
General purpose register
Processor status AH AL DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit USP SSP PS PC Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register R1 R0 R3 R2 R5 R4 R7 R6 RW0 RW1 RW2 RW3 16-bit 000180H + RP × 10H RW4 RW5 RW6 RW7 RL RL1 RL2 RL3 MSB LSB ILM 15 13 PS RP CCR 12 8 70Bit

■ I/O MAP (Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000000H PDR0 Port 0 Data Register R/W Port 0 XXXXXXXX B 000001H PDR1 Port 1 Data Register R/W Port 1 XXXXXXXX B 000002H PDR2 Port 2 Data Register R/W Port 2 XXXXXXXX B 000003H PDR3 Port 3 Data Register R/W Port 3 XXXXXXXX B 000004H PDR4 Port 4 Data Register R/W Port 4 XXXXXXXX B 000005H PDR5 Port 5 Data Register R/W Port 5 XXXXXXXX B 000006H PDR6 Port 6 Data Register R/W Port 6 XXXXXXXX B 000007H PDR7 Port 7 Data Register R/W Port 7 XXXXXXXX B 000008H PDR8 Port 8 Data Register R/W Port 8 XXXXXXXX B 000009H PDR9 Port 9 Data Register R/W Port 9 - XXXXXXX B 00000AH PDRA Port A Data Register R/W Port A XXXXXXXX B 00000BH Prohibited 00000CH PDRB Port B Data Register R/W Port B - XXXXXXX B 00000DH DDRB Port B Direction Register R/W Port B - 0 0 0 0 0 0 0 B 00000EH Prohibited00000FH 000010H DDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0 B 000011H DDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0 B 000012H DDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0 B 000013H DDR3 Port 3 Direction Register R/W Port 3 0 0 0 0 0 0 0 0 B 000014H DDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0 B 000015H DDR5 Port 5 Direction Register R/W Port 5 0 0 0 0 0 0 0 0 B 000016H DDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0 B 000017H DDR7 Port 7 Direction Register R/W Port 7 0 0 0 0 0 0 0 0 B 000018H DDR8 Port 8 Direction Register R/W Port 8 0 0 0 0 0 0 0 0 B 000019H DDR9 Port 9 Direction Register R/W Port 9 - 0 0 0 0 0 0 0 B 00001AH DDRA Port A Direction Register R/W Port A 0 0 0 0 0 0 0 0 B 00001BH ODR4 Port 4 Output Pin Register R/W Port 4 (open drain control) 0 0 0 0 0 0 0 0B 00001CH RDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0 B 00001DH RDR1 Port 1 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0 B 00001EH ADER0 Analog Input Enable Register 0 R/W Port 7, 8, A/D 1 1 1 1 1 1 1 1 B 00001FH ADER1 Analog Input Enable Register 1 R/W Port 7, 8, A/D 1 1 1 1 1 1 1 1 B 000020H SMR0 Serial Mode Register ch0 R/W UART0 0 0 1 0 0 0 0 0B 000021H SCR0 Serial Control Register ch0 R/W 0 0 0 0 0 1 0 0 B 000022H SIDR0 Serial Input Data Register ch0 R XXXXXXXXB SODR0 Serial Output Data Register ch0 W 000023H SSR0 Serial Status Register ch0 R/W 0 0 0 0 1 0 0 0 B 000024H UTRLR0 UART Prescaler Reload Register ch0 R/W Communication Prescaler (UART0) 0 0 0 0 0 0 0 0B 000025H UTCR0 UART Prescaler Control Re gister ch0 R/W 0 0 0 0 - 0 0 0 B

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000026H SMR1 Serial Mode Register ch1 R/W UART1 0 0 1 0 0 0 0 0B 000027H SCR1 Serial Control Register ch1 R/W 0 0 0 0 0 1 0 0 B 000028H SIDR1 Serial Input Data Register ch1 R XXXXXXXXB SODR1 Serial Output Data Register ch1 W 000029H SSR1 Serial Status Register ch1 R/W 0 0 0 0 1 0 0 0 B 00002AH UTRLR1 UART Prescaler Reload Register ch1 R/W Communication Prescaler (UART1) 0 0 0 0 0 0 0 0B 00002BH UTCR1 UART Prescaler Control Register ch1 R/W 0 0 0 0 - 0 0 0 B 00002CH SMR2 Serial Mode Register ch2 R/W UART2 0 0 1 0 0 0 0 0B 00002DH SCR2 Serial Control Register ch2 R/W 0 0 0 0 0 1 0 0 B 00002EH SIDR2 Serial Input Data Register ch2 R XXXXXXXXB SODR2 Serial Output Data Register ch2 W 00002FH SSR2 Serial Status Register ch2 R/W 0 0 0 0 1 0 0 0 B 000030H UTRLR2 UART Prescaler Reload Register ch2 R/W Communication Prescaler (UART2) 0 0 0 0 0 0 0 0B 000031H UTCR2 UART Prescaler Control Register ch2 R/W 0 0 0 0 - 0 0 0 B 000032H SMR3 Serial Mode Register ch3 R/W UART3 0 0 1 0 0 0 0 0B 000033H SCR3 Serial Control Register ch3 R/W 0 0 0 0 0 1 0 0 B 000034H SIDR3 Serial Input Data Register ch3 R XXXXXXXXB SODR3 Serial Output Data Register ch3 W 000035H SSR3 Serial Status Register ch3 R/W 0 0 0 0 1 0 0 0 B 000036H UTRLR3 UART Prescaler Reload Register ch3 R/W Communication Prescaler (UART3) 0 0 0 0 0 0 0 0B 000037H UTCR3 UART Prescaler Control Register ch3 R/W 0 0 0 0 - 0 0 0 B 000038H to 00003BH Prohibited 00003CH ENIR DTP/Interrupt Enable Register R/W DTP/External Interrupt 0 0 0 0 0 0 0 0B 00003DH EIRR DTP/Interrupt Source Register R/W 0 0 0 0 0 0 0 0 B 00003EH ELVR Request Level Setting Register Lower R/W 0 0 0 0 0 0 0 0 B 00003FH Request Level Setting Register Upper R/W 0 0 0 0 0 0 0 0 B 000040H ADCS0 A/D Control Status Register Lower R/W 8/10-bit A/D Converter 0 0 - - - - - 0B 000041H ADCS1 A/D Control Status Regi ster Upper R/W 0 0 0 0 0 0 0 0 B 000042H ADCR0 A/D Data Register Lower R/W XXXXXXXX B 000043H ADCR1 A/D Data Register Upper R/W 0 0 1 0 1 XXX B 000044H Prohibited 000045H ADMR A/D Conversion Channel Selection Register R/W 8/10-bit A/D Converter 0 0 0 0 0 0 0 0B 000046H PPGC0 PPG0 Operation Mode Control Register R/W PPG ch0 0X0 0 0XX1 B 000047H PPGC1 PPG1 Operation Mode Control Register R/W PPG ch1 0X0 0 0 0 0 1 B 000048H PPGC2 PPG2 Operation Mode Control Register R/W PPG ch2 0X0 0 0XX1 B

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000049H PPGC3 PPG3 Operation Mode Control Re gister R/W PPG ch3 0X0 0 0 0 0 1 B 00004AH PPGC4 PPG4 Operation Mode Control Register R/W PPG ch4 0X0 0 0XX1 B 00004BH PPGC5 PPG5 Operation Mode Control Re gister R/W PPG ch5 0X0 0 0 0 0 1 B 00004CH PPG01 PPG0 and PPG1 Output Control Register R/W PPG ch0/1 0 0 0 0 0 0XX B 00004DH Prohibited 00004EH PPG23 PPG2 and PPG3 Output Control Register R/W PPG ch2/3 0 0 0 0 0 0 XX B 00004FH Prohibited 000050H PPG45 PPG4 and PPG5 Output Control Register R/W PPG ch4/5 0 0 0 0 0 0 XX B 000051H Prohibited 000052H ICS01 Input Capture Control Status Register 01 R/W Input Capture ch0/1 0 0 0 0 0 0 0 0B 000053H ICS23 Input Capture Control Status Register 23 R/W Input Capture ch2/3 0 0 0 0 0 0 0 0B 000054H OCS0 Output Compare Control Register ch0 Lower R/W Output Compare ch0/1 0 0 0 0 - - 0 0B 000055H OCS1 Output Compare Control Register ch1 Upper R/W - - - 0 0 0 0 0 B 000056H OCS2 Output Compare Control Register ch2 Lower R/W Output Compare ch2/3 0 0 0 0 - - 0 0B 000057H OCS3 Output Compare Control Register ch3 Upper R/W - - - 0 0 0 0 0 B 000058H SMCS Serial Mode Control Status Register R/W Extended Serial I/O XXXX0 0 0 0B 000059H 0 0 0 0 0 0 1 0B 00005AH SDR Serial Data Register R/W XXXXXXXX B 00005BH SDCR Communication Prescaler Control Register R/W Communication Prescaler 0XXX0 0 0 0B 00005CH PWCSR PWC Control Status Register R/W 16-bit PWC Timer 0 0 0 0 0 0 0 0B 00005DH 0 0 0 0 0 0 0 XB 00005EH PWCR PWC Data Buffer Register R/W 0 0 0 0 0 0 0 0B 00005FH 0 0 0 0 0 0 0 0B 000060H DIVR PWC Dividing Ratio Register R/W - - - - - - 0 0 B 000061H Prohibited 000062H TMCSR0 Timer Control Status Register ch0 R/W 16-bit Reload Timer ch0 0 0 0 0 0 0 0 0B 000063H XXXX 0 0 0 0B 000064H TMR0 16-bit Timer Register ch0 Lower R XXXXXXXX B TMRLR0 16-bit Reload Register ch0 Lower W XXXXXXXX B 000065H TMR0 16-bit Timer Register ch0 Upper R XXXXXXXX B TMRLR0 16-bit Reload Register ch0 Upper W XXXXXXXX B

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000066H TMCSR1 Timer Control Status Register ch1 R/W 16-bit Reload Timer ch1 0 0 0 0 0 0 0 0B 000067H XXXX 0 0 0 0B 000068H TMR1 16-bit Timer Register ch1 Lower R XXXXXXXX B TMRLR1 16-bit Reload Register ch1 Lower W XXXXXXXX B 000069H TMR1 16-bit Timer Register ch1 Upper R XXXXXXXX B TMRLR1 16-bit Reload Regi ster ch1 Upper W XXXXXXXX B 00006AH TMCSR2 Timer Control Status Register ch2 R/W 16-bit Reload Timer ch2 0 0 0 0 0 0 0 0B 00006BH XXXX 0 0 0 0B 00006CH TMR2 16-bit Timer Register ch2 Lower R XXXXXXXX B TMRLR2 16-bit Reload Register ch2 Lower W XXXXXXXX B 00006DH TMR2 16-bit Timer Register ch2 Upper R XXXXXXXX B TMRLR2 16-bit Reload Regi ster ch2 Upper W XXXXXXXX B 00006EH Prohibited 00006FH ROMM ROM Mirror Function Selection Register W ROM Mirror Function Selection Module - - - - - - 1 1B 000070H IBSR0 I 2C Bus Status Register ch0 R I2C Bus Interface ch0 0 0 0 0 0 0 0 0B 000071H IBCR0 I 2C Bus Control Register ch0 R/W 0 0 0 0 0 0 0 0 B 000072H ICCR0 I 2C Bus Clock Selection Register ch0 R/W XX 0 XXXXX B 000073H IADR0 I 2C Bus Address Register ch0 R/W XXXXXXXX B 000074H IDAR0 I 2C Bus Data Register ch0 R/W XXXXXXXX B 000075H Prohibited 000076H IBSR1 I 2C Bus Status Register ch1 R I2C Bus Interface ch1 0 0 0 0 0 0 0 0B 000077H IBCR1 I 2C Bus Control Register ch1 R/W 0 0 0 0 0 0 0 0 B 000078H ICCR1 I 2C Bus Clock Selection Register ch1 R/W XX 0 XXXXX B 000079H IADR1 I 2C Bus Address Register ch1 R/W XXXXXXXX B 00007AH IDAR1 I 2C Bus Data Register ch1 R/W XXXXXXXX B 00007BH Prohibited 00007CH IBSR2 I 2C Bus Status Register ch2 R I2C Bus Interface ch2 0 0 0 0 0 0 0 0B 00007DH IBCR2 I 2C Bus Control Register ch2 R/W 0 0 0 0 0 0 0 0 B 00007EH ICCR2 I 2C Bus Clock Selection Register ch2 R/W XX 0 XXXXX B 00007FH IADR2 I 2C Bus Address Register ch2 R/W XXXXXXXX B 000080H IDAR2 I 2C Bus Data Register ch2 R/W XXXXXXXX B 000081H to 000085H Prohibited

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 000086H TCDT Timer Data Register Lower R/W 16-bit Free-Run Timer 0 0 0 0 0 0 0 0B 000087H Timer Data Register Upper R/W 0 0 0 0 0 0 0 0 B 000088H TCCS Timer Control Status Register Lower R/W 0 0 0 0 0 0 0 0 B 000089H Timer Control Status Register Upper R/W 0 - - 0 0 0 0 0 B 00008AH CPCLR Compare Clear Register Lower R/W XXXXXXXX B 00008BH Compare Clear Register Upper R/W XXXXXXXX B 00008CH to 00009AH Prohibited 00009BH DCSR DMA Descriptor Channel Specification Register R/W µDMAC 0 0 0 0 0 0 0 0B 00009CH DSRL DMA Status Register Lower R/W 0 0 0 0 0 0 0 0 B 00009DH DSRH DMA Status Register Upper R/W 0 0 0 0 0 0 0 0 B 00009EH PACSR Program Address Detection Control Status Register R/W Address Match Detection 0 0 0 0 0 0 0 0B 00009FH DIRR Delay Interruption Factor Generation/ Release Register R/W Delay Interrupt - - - - - - - 0 B 0000A0H LPMCR Low Power Consumption Mode Register R/W Low Power Consumption Control Circuit 0 0 0 1 1 0 0 0B 0000A1H CKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0 B 0000A2H Prohibited0000A3H 0000A4H DSSR DMA Stop Status Register R/W µDMAC 0 0 0 0 0 0 0 0 B 0000A5H ARSR Automatic Ready Function Selection Register W External Pin 0 0 1 1- - 0 0B 0000A6H HACR External Address Output Control 0000A7H EPCR Bus Control Signal Control Register W 1 0 0 0 ∗ 1 0 -B 0000A8H WDTC Watchdog Control Register R/ W Watchdog Timer X - XXX 1 1 1 B 0000A9H TBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0 B 0000AAH WTC Watch Timer Control Register R/W Watch Timer 1 0 0 0 1 0 0 0 B 0000ABH Prohibited 0000ACH DERL DMA Enable Register Lower R/W µDMAC 0 0 0 0 0 0 0 0B 0000ADH DERH DMA Enable Register Upper R/W 0 0 0 0 0 0 0 0 B 0000AEH FMCR Flash Memory Control Status Register R/W Flash Memory I/F 0 0 0 X 0 0 0 0B 0000AFH Prohibited

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000B0H ICR00 Interrupt Control Register 00 R/W Interrupt Controller 0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1 B 0000B2H ICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1 B 0000B3H ICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1 B 0000B4H ICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1 B 0000B5H ICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1 B 0000B6H ICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1 B 0000B7H ICR07 Interrupt Control Register 07 R/W 0 0 0 0 0 1 1 1 B 0000B8H ICR08 Interrupt Control Register 08 R/W 0 0 0 0 0 1 1 1 B 0000B9H ICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1 B 0000BAH ICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1 B 0000BBH ICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1 B 0000BCH ICR12 Interrupt Control Register 12 R/W 0 0 0 0 0 1 1 1 B 0000BDH ICR13 Interrupt Control Register 13 R/W 0 0 0 0 0 1 1 1 B 0000BEH ICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1 B 0000BFH ICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1 B 0000C0H HCNT0 USB Host Control Register 0 R/W USB Mini-HOST 0 0 0 0 0 0 0 0B 0000C1H HCNT1 USB Host Control Register 1 R/W 0 0 0 0 0 0 0 1 B 0000C2H HIRQ USB Host Interruption Register R/W 0 0 0 0 0 0 0 0 B 0000C3H HERR USB Host Error Status Register R/W 0 0 0 0 0 0 1 1 B 0000C4H HSTATE USB Host State Status Register R/W XX 0 1 0 0 1 0 B 0000C5H HFCOMP USB SOF Interrupt FRAME Compare Register R/W 0 0 0 0 0 0 0 0 B 0000C6H HRTIMER USB Retry Timer Setting Register 0 R/W 0 0 0 0 0 0 0 0 B 0000C7H USB Retry Timer Setting Register 1 R/W 0 0 0 0 0 0 0 0 B 0000C8H USB Retry Timer Setting Register 2 R/W XXXXXX 0 0 B 0000C9H HADR USB Host Address Register R/W X 0 0 0 0 0 0 0 B 0000CAH HEOF USB EOF Setting Register 0 R/W 0 0 0 0 0 0 0 0 B 0000CBH USB EOF Setting Register 1 R/W XX 0 0 0 0 0 0 B 0000CCH HFRAME USB FRAME Setting Register 0 R/W 0 0 0 0 0 0 0 0 B 0000CDH USB FRAME Setting Register 1 R/W XXXXX 0 0 0 B 0000CEH HTOKEN USB Host Token End Poin t Register R/W 0 0 0 0 0 0 0 0 B 0000CFH Prohibited 0000D0H UDCC UDC Control Register R/W USB Function 1 0 1 0 0 0 0 0 B 0000D1H Prohibited

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000D2H EP0C EP0 Control Register R/W USB Function X 1 0 0 0 0 0 0B 0000D3H R/W XXXX 0 0 0 X B 0000D4H EP1C EP1 Control Register R/W 0 0 0 0 0 0 0 0 B 0000D5H R/W 0 1 1 0 0 0 0 1 B 0000D6H EP2C EP2 Control Register R/W 0 1 0 0 0 0 0 0 B 0000D7H R/W 0 1 1 0 0 0 0 0 B 0000D8H EP3C EP3 Control Register R/W 0 1 0 0 0 0 0 0 B 0000D9H R/W 0 1 1 0 0 0 0 0 B 0000DAH EP4C EP4 Control Register R/W 0 1 0 0 0 0 0 0 B 0000DBH R/W 0 1 1 0 0 0 0 0 B 0000DCH EP5C EP5 Control Register R/W 0 1 0 0 0 0 0 0 B 0000DDH R/W 0 1 1 0 0 0 0 0 B 0000DEH TMSP Time Stamp Register R 0 0 0 0 0 0 0 0 B 0000DFH R/W 0 0 0 0 0 0 0 0 B 0000E0H UDCS UDC Status Register R/W 0 0 0 0 0 0 0 0 B 0000E1H UDCIE UDC Interrupt Enable Register R/W 0 0 0 0 0 0 0 0 B 0000E2H EP0IS EP0I Status Register R/W XXXXXXXX B 0000E3H R/W 1 0 XXX 1 XX B 0000E4H EP0OS EP0O Status Register R/W XXXXXXXX B 0000E5H R/W 1 0 0 XX 0 0 X B 0000E6H EP1S EP1 Status Register R XXXXXXXX B 0000E7H R/W 1 0 0 0 0 0 0 X B 0000E8H EP2S EP2 Status Register R XXXXXXXX B 0000E9H R/W 1 0 0 0 0 0 0 X B 0000EAH EP3S EP3 Status Register R XXXXXXXX B 0000EBH R/W 1 0 0 0 0 0 0 X B 0000ECH EP4S EP4 Status Register R XXXXXXXX B 0000EDH R/W 1 0 0 0 0 0 0 X B 0000EEH EP5S EP5 Status Register R XXXXXXXX B 0000EFH R/W 1 0 0 0 0 0 0 X B 0000F0H EP0DT EP0 Data Register R/W XXXXXXXX B 0000F1H R/W XXXXXXXX B 0000F2H EP1DT EP1 Data Register R/W XXXXXXXX B 0000F3H R/W XXXXXXXX B 0000F4H EP2DT EP2 Data Register R/W XXXXXXXX B 0000F5H R/W XXXXXXXX B 0000F6H EP3DT EP3 Data Register R/W XXXXXXXX B 0000F7H R/W XXXXXXXX B

(Continued) Address Register abbreviation Register Read/ Write Resource name Initial Value 0000F8H EP4DT EP4 Data Register R/W USB Function XXXXXXXXB 0000F9H R/W XXXXXXXX B 0000FAH EP5DT EP5 Data Register R/W XXXXXXXX B 0000FBH R/W XXXXXXXX B 0000FCH to 0000FFH Prohibited 000100H to RAM Area 001FF0H PADR0 Program Address Detection Register ch0 Lower R/W Address Match Detection XXXXXXXXB 001FF1H Program Address Detection Register ch0 Middle R/W XXXXXXXX B 001FF2H Program Address Detection Register ch0 Upper R/W XXXXXXXX B 001FF3H PADR1 Program Address Detection Register ch1 Lower R/W XXXXXXXX B 001FF4H Program Address Detection Register ch1 Middle R/W XXXXXXXX B 001FF5H Program Address Detection Register ch1 Upper R/W XXXXXXXX B to 0078FFH Unused Area 007900H PRLL0 PPG Reload Register Lower ch0 R/W PPG ch0 XXXXXXXXB 007901H PRLH0 PPG Reload Register Upper ch0 R/W XXXXXXXX B 007902H PRLL1 PPG Reload Register Lower ch1 R/W PPG ch1 XXXXXXXXB 007903H PRLH1 PPG Reload Register Upper ch1 R/W XXXXXXXX B 007904H PRLL2 PPG Reload Register Lower ch2 R/W PPG ch2 XXXXXXXXB 007905H PRLH2 PPG Reload Register Upper ch2 R/W XXXXXXXX B 007906H PRLL3 PPG Reload Register Lower ch3 R/W PPG ch3 XXXXXXXXB 007907H PRLH3 PPG Reload Register Upper ch3 R/W XXXXXXXX B 007908H PRLL4 PPG Reload Register Lower ch4 R/W PPG ch4 XXXXXXXXB 007909H PRLH4 PPG Reload Register Upper ch4 R/W XXXXXXXX B 00790AH PRLL5 PPG Reload Register Lower ch5 R/W PPG ch5 XXXXXXXXB 00790BH PRLH5 PPG Reload Register Upper ch5 R/W XXXXXXXX B 00790CH to 00790FH Prohibited

(Continued) Explanation on read/write Explanation on initial values Note : No I/O instruction can be used for registers located between 007900H and 007FFFH. Address Register abbreviation Register Read/ Write Resource name Initial Value 007910H IPCP0 Input Capture Data Register Lower ch0 R Input Capture ch0/1 XXXXXXXXB 007911H Input Capture Data Register Upper ch0 R XXXXXXXX B 007912H IPCP1 Input Capture Data Register Lower ch1 R XXXXXXXX B 007913H Input Capture Data Register Upper ch1 R XXXXXXXX B 007914H IPCP2 Input Capture Data Register Lower ch2 R Input Capture ch2/3 XXXXXXXXB 007915H Input Capture Data Register Upper ch2 R XXXXXXXX B 007916H IPCP3 Input Capture Data Register Lower ch3 R XXXXXXXX B 007917H Input Capture Data Register Upper ch3 R XXXXXXXX B 007918H OCCP0 Output Compare Register Lower ch0 R/W Output Compare ch0/1 XXXXXXXXB 007919H Output Compare Register Upper ch0 R/W XXXXXXXX B 00791AH OCCP1 Output Compare Register Lower ch1 R/W XXXXXXXX B 00791BH Output Compare Register Upper ch1 R/W XXXXXXXX B 00791CH OCCP2 Output Compare Register Lower ch2 R/W Output Compare ch2/3 XXXXXXXXB 00791DH Output Compare Register Upper ch2 R/W XXXXXXXX B 00791EH OCCP3 Output Compare Register Lower ch3 R/W XXXXXXXX B 00791FH Output Compare Register Upper ch3 R/W XXXXXXXX B 007920H DBAPL DMA Buffer Address Pointer Lower 8-bit R/W µDMAC XXXXXXXXB 007921H DBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXX B 007922H DBAPH DMA Buffer Address Pointer Upper 8-bit R/W XXXXXXXX B 007923H DMACS DMA Control Register R/W XXXXXXXX B 007924H DIOAL DMA I/O Register Address Pointer Lower 8-bit R/W XXXXXXXX B 007925H DIOAH DMA I/O Register Address Pointer Upper 8-bit R/W XXXXXXXX B 007926H DDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXX B 007927H DDCTH DMA Data Counter Upper 8-bit R/W XXXXXXXX B 007928H to 007FFFH Prohibited R/W : Readable and Writable R : Read only W : Write only 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. - : Initial value is undefined (None) . ∗ : Initial value of this bit is “1” or “0”.

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS (Continued) Interrupt source EI2OS support µDMAC Interrupt vector Interrupt control register Priority Number* Address ICR Address Reset × × #08 08 H FFFFDCH ⎯⎯ High INT 9 instruction × × #09 09 H FFFFD8H ⎯⎯ Exceptional treatment × × #10 0A H FFFFD4H ⎯⎯ USB Function1 × 0, 1 #11 0B H FFFFD0H ICR00 0000B0 H USB Function2 × 2 to 6 #12 0C H FFFFCCH USB Function3 × × #13 0D H FFFFC8H ICR01 0000B1 H USB Function4 × × #14 0E H FFFFC4H USB Mini-HOST1 × × #15 0F H FFFFC0H ICR02 0000B2 H USB Mini-HOST2 × × #16 10 H FFFFBCH I2C ch0 × × #17 11 H FFFFB8H ICR03 0000B3 H DTP/External interrupt ch0/1 × #18 12 H FFFFB4H I2C ch1 × × #19 13 H FFFFB0H ICR04 0000B4 H DTP/Extetrnal interrupt ch2/3 × #20 14 H FFFFACH I2C ch2 × × #21 15 H FFFFA8H ICR05 0000B5 H DTP/External interrupt ch4/5 × #22 16 H FFFFA4H PWC/Reload timer ch0 14 #23 17 H FFFFA0H ICR06 0000B6 H DTP/External interrupt ch6/7 × #24 18 H FFFF9CH Input capture ch0/1 7 #25 19 H FFFF98H ICR07 0000B7 H Reload timer ch1 × #26 1A H FFFF94H Input capture ch2/3 8 #27 1B H FFFF90H ICR08 0000B8 H Reload timer ch2 × #28 1C H FFFF8CH Output compare ch0/1 × #29 1D H FFFF88H ICR09 0000B9 H PPG ch0/1 × × #30 1E H FFFF84H Output compare ch2/3 × #31 1F H FFFF80H ICR10 0000BA H PPG ch2/3 × × #32 20 H FFFF7CH UART (Send completed) ch2/3 11 #33 21 H FFFF78H ICR11 0000BB H PPG ch4/5 × × #34 22 H FFFF74H UART (Reception completed) ch2/3 10 #35 23 H FFFF70H ICR12 0000BC H A/D converter/Free-run timer 15 #36 24 H FFFF6CH UART (Send completed) ch0/1 13 #37 25 H FFFF68H ICR13 0000BD H Extended serial I/O × 9 #38 26 H FFFF64H UART (Reception completed) ch0/1 12 #39 27 H FFFF60H ICR14 0000BE H Time-base timer/Watch timer × × #40 28 H FFFF5CH Flash memory status × × #41 29 H FFFF58H ICR15 0000BF H Delay interrupt output module × × #42 2A H FFFF54H Low

(Continued) : Available, EI 2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. With a stop request). : Available (The interrupt request flag is cleared by the interrupt clear signal.) : Available when any interrupt source sharing ICR is not used. × : Unavailable * : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS.

The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR).
If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “0” in the appropriate resource, and take measures by software polling.
Content of USB interruption factor USB interrupt factor Details USB function 1 End Point0-IN End Point0-OUT USB function 2 End Point1-5 USB function 3 VOFF VON SUSP SOF BRST WKUP CONF USB function 4 SPK USB Mini-HOST1 DIRQ CNNIRQ URIRQ RWKIRQ USB Mini-HOST2 SOFIRQ CMPIRQ

■ PERIPHERAL RESOURCES 1. I/O port The I/O ports are used as general-purpose input/outpu t ports (parallel I/O ports). MB90330 series model is provided with 12 ports (94 inputs) . The ports function as input/output pins for peripheral functions also. The port data register (PDR) can be used to send output data to the I/O pin and to receive the signal input to the I/O port. The port direction register (DDR) can be used to set the I/O direction of the I/O pin in bit units. The following table lists the I/O ports and the peripheral functions with which they share pins. Note : These pins also serve as the analog input pins for ports 7 and 8. T o use them as general-purpose ports, be sure to set the corresponding bits in the analog input enable register (ADER) to 0B. The ADER is initialized to FFH at a reset. Port Pin Name Pin Name (Peripheral) Peripheral Function that Shares Pin Port 0 P00 to P07 ⎯ (External bus) Port 1 P10 to P17 ⎯ (External bus) Port 2 P20 to P23 ⎯ (External bus) P24 to P27 PPG0 to PPG3 8/16-bit PPG timer 0, 1 (External bus) Port 3 P30 to P33 TIN1, TOT1, TIN2, TOT2 16-bit Reload timer 1, 2 (External bus) P34 to P37 ⎯ (External bus) Port 4 P40, P41 TIN0, TOT0 16-bit Reload timer 0 (External bus) P42 to P47 SIN0, SOT0, SCK0, SIN1, SOT1, SCK1 UART0, UART1 (External bus) Port 5 P50 to P57 ⎯ (External bus) Port 6 P60, P61 INT0, INT1 External interrupt P62 to P64 INT2 to INT4, SIN, SOT, SCK External interrupt, Serial I/O P65 INT5, PWC External interrupt, PWC P66, P67 INT6, INT7, SCL0, SDA0 External interrupt, I 2C 0 Port 7 P70 to P77 AN0 to AN7 8/10-bit A/D converter Port 8 P80 to P87 AN8 to AN15 8/10-bit A/D converter Port 9 P90 to P95 SIN2, SOT2, SCK2, SIN3, SOT3, SCK3 UART2, 3 P96 ADTG, FRCK 8/10-bit A/D converter, Free-run timer Port A PA0 to PA3 IN0 to IN3 Input capture 0, 1, 2, 3 PA4 to PA7 OUT0 to OUT3 Output compare 0, 1, 2, 3 Port B PB0 to PB3 SCL1, SDA1, SCL2, SDA2 I 2C 1, 2 PB4 ⎯⎯ PB5, PB6 PPG4, PPG5 PPG timer 2

Register list (port data register) * : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows :
Input mode Read : The level at the relevant pin is read. Write : Data is written to the output latch.
Output mode Read : The data register latch value is read. Write : Data is output to the relevant pin. PDR0 Initial Value Access Address : 000000H XXXXXXXXB R/W* PDR1 Address : 000001H XXXXXXXXB R/W* PDR2 Address : 000002H XXXXXXXXB R/W* PDR3 Address : 000003H XXXXXXXXB R/W* PDR4 Address : 000004H XXXXXXXXB R/W* PDR5 Address : 000005H XXXXXXXXB R/W* PDR6 Address : 000006H XXXXXXXXB R/W* PDR7 Address : 000007H XXXXXXXXB R/W* PDR8 Address : 000008H XXXXXXXXB R/W* PDR9 Address : 000009H - XXXXXXXB R/W* PDRA Address : 00000AH XXXXXXXXB R/W* PDRB Address : 00000CH - XXXXXXXB R/W* 76543210 P06P07 P05 P04 P03 P02 P01 P00 15 14 13 12 11 10 9 8 P16P17 P15 P14 P13 P12 P11 P10 76543210 P26P27 P25 P24 P23 P22 P21 P20 15 14 13 12 11 10 9 8 P36P37 P35 P34 P33 P32 P31 P30 76543210 P46P47 P45 P44 P43 P42 P41 P40 15 14 13 12 11 10 9 8 P56P57 P55 P54 P53 P52 P51 P50 76543210 P66 P65 P64 P63 P62 P61 P60P67 15 14 13 12 11 10 9 8 P76 P75 P74 P73 P72 P71 P70P77 76 5432 10 P84 P83 P82 P81 P80P87 P86 P85 15 14 13 12 11 10 9 8 P91 P90⎯ P96 P95 P94 P93 P92 76 5432 10 PA1 PA0PA7 PA6 PA5 PA4 PA3 PA2 76 5432 10 PB1 PB0⎯ PB6 PB5 PB4 PB3 PB2

Register list (port direction register) When each pin is serving as a port, the corresponding pin is controlled as follows : 0 : Input mode 1 : Output mode This bit becomes 0 after a reset. Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to current input values of the pins. When switching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output. DDR0 Initial Value Access Address : 000010 H 00000000B R/W DDR1 Address : 000011H 00000000B R/W DDR2 Address : 000012H 00000000B R/W DDR3 Address : 000013H 00000000B R/W DDR4 Address : 000014H 00000000B R/W DDR5 Address : 000015H 00000000B R/W DDR6 Address : 000016H 00000000B R/W DDR7 Address : 000017H 00000000B R/W DDR8 Address : 000018H 00000000B R/W DDR9 Address : 000019H -0000000B R/W DDRA Address : 00001AH 00000000B R/W DDRB Address : 00000DH -0000000B R/W 76 5432 10 D06D07 D05 D04 D03 D02 D01 D00 15 14 13 12 11 10 9 8 D16D17 D15 D14 D13 D12 D11 D10 76 5432 10 D26D27 D25 D24 D23 D22 D21 D20 15 14 13 12 11 10 9 8 D36D37 D35 D34 D33 D32 D31 D30 76 5432 10 D46D47 D45 D44 D43 D42 D41 D40 15 14 13 12 11 10 9 8 D56D57 D55 D54 D53 D52 D51 D50 76 5432 10 D66D67 D65 D64 D63 D62 D61 D60 15 14 13 12 11 10 9 8 D75 D74 D73 D72 D71 D70D76D77 76 5432 10 D84 D83 D82 D81 D80D87 D86 D85 15 14 13 12 11 10 9 8 D91 D90⎯ D96 D95 D94 D93 D92 76 5432 10 DA1 DA0DA7 DA6 DA5 DA4 DA3 DA2 15 14 13 12 11 10 9 8 DB1 DB0⎯ DB6 DB5 DB4 DB3 DB2

Register list (Analog input enable register) This register controls the port 7, 8 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. This bit becomes 1 after a reset.
Register list (Port pull-up resistance register) Controls the pull-up resistor in input mode. 0 : Without pull-up resistor in input mode. 1 : With pull-up resistor in input mode. Meaningless in output mode. (Without pull-up resistor)/The input/output mode is decided by the setting of the port direction register (DDR). Without pull-up resistor is used in stop mode (SPL = 1) . (High-Z) This function is disabled when the external bus is used. Do not attempt to write to this register.
Register list (Output pin register) Controls open-drain in output mode. 0 : Serves as a standard output port in output mode. 1 : Serves as an open-drain output port in output mode. Meaningless in input mode (output High-Z)./The input/output mode is decided by the setting of the port direction register (DDR). This function is disabled when the external bus is used. Do not attempt to write to this register. ADER0 Initial Value Access Address : 00001EH 11111111B R/W ADER1 Address : 00001FH 11111111B R/W 76 5432 10 ADE3 ADE2 ADE1 ADE0ADE7 ADE6 ADE5 ADE4 15 14 13 12 11 10 9 8 ADE11 ADE10 ADE9 ADE8ADE15 ADE14 ADE13 ADE12 RDR0 Initial Value Access Address : 00001CH 00000000B R/W RDR1 Address : 00001DH 00000000B R/W 76 5432 10 RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00 15 14 13 12 11 10 9 8 RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10 ODR4 Initial Value Access Address : 00001BH 00000000B R/W 76 5432 10 OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40

Block diagram of port 0 pin and port 1 pin
Block diagram of port 2 pin, port 3 pin, port 4 pin, port 5 pin, port 6 pin, port 9 pin, port A pin and port B pin Pull-up resistor setting register (RDRx) Port data register (PDRx) Port direction register (DDRx) I/O decision circuit Input buffer Output buffer Internal data bus PDRx read PDRx write Port pin Internal pull-up resistor Standby control (LPMCR : SPL = “1”) Port data register (PDRx) Port direction register (DDRx) I/O decision circuit Input buffer Output buffer Internal data bus PDRx read PDRx write Port pin Standby control (LPMCR : SPL = “1”) Resource output control signal Resource output Resource input

Block diagram of port 7 pin and port 8 pin Notes : • When using as an input port, set " 0 " in the corresponding bit of the port-7 and port-8 direction register (DDR7 and DDR8) and " 0 " in the related bit of the analog input enable register (ADER).
When using as an analog input pin, set " 0 " in the corresponding bit of the port-7 and port-8 direction register (DDR7 and DDR8) and " 1 " in the related bit of the analog input enable register (ADER). Analog input enable register (ADER) Port data register (PDRx) Port direction register (DDRx) I/O decision circuit Input buffer Output buffer Internal data bus PDRx read PDRx write Port pin A/D converter analog input signal Standby control (LPMCR : SPL = “1”)

Time-base timer The time-base timer is an 18-bit free-run counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock HCLK). Four different time intervals can be selected, for each of which an interrupt request can be generated. Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer.

Interval time of time-base timer Notes : • HCLK : Oscillation clock frequency
The parenthesized values assume an oscillator clock frequency of 6 MHz.
Clock cycles supplied from time-base timer Notes : • HCLK : Oscillation clock frequency
The parenthesized values assume an oscillator clock frequency of 6 MHz.
Register list Internal count clock cycle Interval time 2/HCLK (0.33 µs) 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Where to supply clock Clock cycle Main clock oscillation stabilization wait 213/HCLK (Approx. 1.36 ms) 215/HCLK (Approx. 5.46 ms) 217/HCLK (Approx. 21.84 ms) Watch dog timer 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Time-base timer control register (TBTC) Initial Value Address : 0000A9H 1 - - 00100B 15 14 13 12 11 10 9 8 ( R/W ) RESV ⎯ TBIE TBOF TBR TBC1 TBC0

Block Diagram Actual interrupt request number of time-base timer is as follows : Interrupt request number : #40 (28H) TBIE TBOF TBRRESV ⎯⎯ TBC1 TBC0 OF OF OF OF × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 To PPG timer Time-base timer counter Dividing HCLK by 2 To watchdog timer CKSCR : MCS = 1→0*1 CKSCR : SCS = 0→1*2 Counter clear control circuit Interval timer selector TBOF clear Time-base timer control register (TBTC) Time-base timer interrupt signal To clock controller oscillation stabilizing wait time selector TBOF set − : Unused OF : Overflow HCLK : Oscillation clock *1 : Switching the machine clock from main clock or subclock to PLL clock *2 : Switching the machine clock from subclock to main clock Power-on reset Stop mode start Hold state start

Watchdog timer The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time after start.

Interval time of watchdog timer Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.
The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or watch timer.
Interval time of watchdog timer is longer than the set time during the following conditions. - When clearing the timebase timer du ring operation on oscillation (HCLK) - When clearing the watch timer du ring operation on sub clock (SCLK)
Events that stop the watchdog timer Stop due to a power-on reset Watchdog reset
Clear factor of watchdog timer External reset input by RST pin Writing “0” to the software reset bit Writing “0” to the watchdog timer control bit (second and subsequent times) T ransition to sleep mode (clearing the watchdog timer to suspend counting) T ransition to time-base timer mode (clearing the watchdog timer to suspend counting) T ransition to stop mode (clearing the watchdog timer to suspend counting) HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 KHz) Min Max Clock cycle Approx. 2.39 ms Approx. 3.07 ms 2 14 ± 211/HCLK Approx. 9.56 ms Approx. 12.29 ms 2 16 ± 213/HCLK Approx. 38.23 ms Approx. 49.15 ms 2 18 ± 215/HCLK Approx. 305.83 ms Approx. 393.22 ms 2 21 ± 218/HCLK Approx. 0.448 s Approx. 0.576 s 2 12 ± 29/SCLK Approx. 3.584 s Approx. 4.608 s 2 15 ± 212/SCLK Approx. 7.168 s Approx. 9.216 s 2 16 ± 213/SCLK Approx. 14.336 s Approx. 18.432 s 2 17 ± 214/SCLK

Register list
Block Diagram Watchdog timer control register (WDTC) Initial Value Address : 0000A8H X-XXX111B 76543 2 10 ( R ) PONR WRST ERST SRST WTE WT1 WT0 ⎯ PONR ⎯ WRST ERST SRST WTE WT1 WT0 × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 × 21SCLK CLR CLR × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 Watchdog timer control register (WDTC) Watchdog timer Watch mode start Time-base timer mode start Sleep mode start Hold state start Counter clear control circuit Count clock selector 2-bit counter Watchdog timer reset generation circuit To internal reset generation circuit CLR and start (Time-base timer counter) Main clock (dividing HCLK by 2) HCLK: Oscillation clock SCLK: Sub clock Clear Stop mode start WDCS bit of WTC SCM bit of CKSCR

Watch timer The watch timer is a 15-bit timer using the subclock. It can generate interval interrupts. It can also be used as a clock source for the watchdog timer.

Register list
Block Diagram Watch timer control register (WTC) Initial Value Address : 0000AAH 10001000B 7654 3210 SCE ( R/W ) WDCS WTIE WTOF WTR WTC2 WTC1 WTC0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 210 211 212 213 214210 213 214 215 Sub clock Watch counter Interval selector Interrupt generation circuit Watch timer interrupt To watchdog timer Watch timer control register (WTC) Clear

16-bit reload timer The 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal clocks and the event count mode to decrement upon dete ction of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as an underflow. The timer therefore caus es an underflow when the count reac hes [reload register setting + 1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.

Register list
TMCSR (Timer control status register 0 to 2) Timer control status register (upper) (TMCSR0 to TMCSR2) Timer control status register (lower) (TMCSR0 to TMCSR2)
16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper) TMR0 to TMR2/TMRLR0 to TMRLR2 (lower) Address : 000063H 000067H 00006BH Initial Value XXXX0000B Address : 000062H 000066H 00006AH Initial Value 00000000B Address : 000065H 000069H 00006DH Initial Value XXXXXXXXB Address : 000064H 000068H 00006CH Initial Value XXXXXXXXB 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯⎯ ⎯ CSL1 CSL0 MOD2 MOD1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 OUTE ( R/W ) MOD0 OUTL RELD INTE UF CNTE TRG ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 D14 ( R/W ) D15 D13 D12 D11 D10 D09 D08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 D06 ( R/W ) D07 D05 D04 D03 D02 D01 D00

Block diagram TMRLR0∗1 TMRLR1∗2 TMRLR2∗3 TMR0∗1 TMR1∗2 TMR2∗3 CLK TIN0∗1 TIN1∗2 TIN2∗3 UF EN TOT0 ∗1 TOT1∗2 TOT2∗3 CLK 3 2 ⎯⎯⎯⎯ CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD UFINTE CNTE TRG Internal data bus 16-bit reload register 16-bit timer register Reload signal Reload control circuit Wait signal Output control circuit Output signal generation circuit Pin Valid clock decision circuit Clock selector Operating control circuit Select signal External clock Internal clock Input control circuit Pin Prescaler Count clock generation circuit Gate input Timer control status register (TMCSR0 to TMCSR2) Interrupt request output #23 (17H) *1, *4 #26 (1AH) *2, *4 #28 (1CH) *3, *4 Select function Clear Trigger Machine clock φ *1 : channel 0 *2 : channel 1 *3 : channel 2 *4 : Interrupt number *5 : Underflow

Multi function timer The multi-function timer enables the following based on the 16-bit free-run timer.

Output of independent waveform
Measurement of input pulse width
Measurement of external clock cycle
Configuration of a multi-functional timer
16-bit free-run timer : 1 channel The 16-bit free-run timer consists of a 16-bit up counte r (timer data register (TCDT)), compare clear register (CPCLR), timer control status register (TCCS), and prescaler. The counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input capture units. The count clock can be set, selected from among the following eight types. φ : Machine clock frequency During the following conditions, the interrupt should be output. - The counter value of 16-bit free run timer will be overflowed. - The counter value of 16-bit free run timer will be cleared after the counter value of 16-bit free run timer = the compare clear register value (CPCLR) (TCCS : ICRE = “1”, MODE = “1”) The counter value of 16-bit free run timer should be cleared to “0000 H” during the following conditions.
Reset
When setting the clear bit (SCLR) of timer control status register (TCCS) to “1”
When the counter value of the 16-bit free run timer = the compare clear register value (CPCLR) (TCCS : MODE = “1”)
When setting “0000H” to the timer data register (TCDT)
Output compare : 4 channels The output compare unit consists of compare registers (OCCP0 to OCCP3), compare control registers (OCS0 to OCS3), and a compare output latch. The output compare unit can invert the output level and output an interrupt when a compare register (OCCP0 to OCCP3) value matches the counter value of the 16-bit free-run timer. Output compare registers can operate as 4 independent channels. The compare registers (OCCP0 to OCCP3) of each channel have interrupt request flags of their respective output pins. Pin output can be inverted by using 2 channel s of compare registers (OCCP0 to OCCP3). If the counter value of 16-bit free run timer = the compare register (OCCP0 to OCCP3) (OCS0, OCS2 : IOP0 = “1”, IOP1 = “1”), the interrupt request should be generated. The initial value for pin output of each channel can be set.
Input capture : 4 channels The input capture unit consists of the input capture data registers (IPCP0 to IPCP3) corresponding to external input pins (IN0 to IN3) and input capture control registers (ICS01, ICS23). The input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data register (IPCP0 to IPCP3) to generated an interrupt request upon detection of the effective edge of the signal input through the external input. 16-bit free-run timer 16-bit Output Compare 16-bi t Input Capture 8/16-bit PPG timer 16-bit PWC timer 1 channel 4 channels 4 channels 8-bit × 6 channels (16-bit × 3 channels) 1 channel

The input capture unit in each channel can operate independently. The effective edge of the external signal can be selected (rising edge, falling edge, both edges). An interrupt request can be generated upon detection of the selected effective edge of the external sig- nal.(ICS01, ICS2 : ICE0 = “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”).

Register list (16-bit free-run timer) Compare clear register (CPCLR) Timer data register (TCDT) Timer control/status register (TCCS) Initial Value Address : 00008BH XXXXXXXXB Initial Value Address : 00008AH XXXXXXXXB Initial Value Address : 000087H 00000000B Initial Value Address : 000086H 00000000B Initial Value Address : 000089H 0--00000B Initial Value Address : 000088H 00000000B 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) CL14CL15 CL13 CL12 CL11 CL10 CL09 CL08 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) CL06CL07 CL05 CL04 CL03 CL02 CL01 CL00 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) T14T15 T13 T12 T11 T10 T09 T08 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) T06T07 T05 T04 T03 T02 T01 T00 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ⎯ECKE ⎯ MSI2 MSI1 MSI0 ICLR ICRE 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) IVFEIVF STOP MODE SCLR CLK2 CLK1 CLK0

Register list (output compare) Compare register (OCCP0 to OCCP3) Control register (OCS1/OCS3) Control register (OCS0/OCS2) Address : 007919H 00791BH 00791DH 00791FH Initial Value XXXXXXXXB Address : 007918H 00791AH 00791CH 00791EH Initial Value XXXXXXXXB Initial Value Address : 000055H 000057H ---00000B Initial Value Address : 000054H 000056H 0000--00B 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) C14C15 C13 C12 C11 C10 C09 C08 76 5 4 3 21 0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) C06C07 C05 C04 C03 C02 C01 C00 15 14 13 12 11 10 9 8 ⎯⎯⎯ CMOD OTE1 OTE0 OTD1 OTD0 76543210 ICP0ICP1 ICE1 ICE0 ⎯⎯ CST1 CST0

Register list (input capture) Input capture data register (IPCP0 to IPCP3) Input capture control status register (ICS23) Input capture control status register (ICS01) Address : 007911H 007913H 007915H 007917H Initial Value XXXXXXXXB Address : 007910H 007912H 007914H 007916H Initial Value XXXXXXXXB Initial Value Address : 000053H 00000000B Initial Value Address : 000052H 00000000B 15 14 13 12 11 10 9 8 CP14CP15 CP13 CP12 CP11 CP10 CP09 CP08 76543210 CP06CP07 CP05 CP04 CP03 CP02 CP01 CP00 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ICP2ICP3 ICE3 ICE2 EG31 EG30 EG21 EG20 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ICP0ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00

Block diagram of the 16-bit free-run timer, input capture units, and output compare units φ IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 ICLR ICP1 ICP0 IOE1 IOE0 ICP1 ICP3 ICP0 ICP2 ICE1 ICE3 ICE0 ICE2 EG11 EG31 EG10 EG30 EG01 EG21 EG00 EG20 IN0/IN2 IN1/IN3 CMOD TQ TQ ICREMSI2 to MSI0 OUT0/OUT2 OUT1/OUT3 OTE0 OTE1 To interrupt #36 (24H)* 16-bit free-run timer Divider Clock Compare circuit16-bit compare clear register Compare register 0/2 Compare circuit Compare register 1/3 Compare circuit To interrupt #36 (24H)* To interrupt #29 (1DH)* #31 (1FH)* Edge detection Edge detection To interrupt #25 (19H)* #27 (1BH)* Capture data register 0/2 Capture data register 1/3 Internal data bus * : Interrupt number φ : Machine clock frequency

8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels) 8/16-bit PPG timer consists of an 8-bit down counter (PCNT), PPG control register (PPGC0 to PPGC5), PPG output control register (PPG01, PPG23, PPG45) and PPG reload register (PRLL0 to PRLL5, PRLH0 to PRLH5). When used as an 8-/16-bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an arbitrary duty ratio at an arbitrary frequency. 8 - b i t P P G m o d e Each channel operates as an independent 8-bit PPG. 8-bit prescaler + 8-bit PPG mode Operates as an arbitrary-cycle 8-bit PPG with PPG0 (PPG2, PPG4) operating as an 8-bit prescaler and PPG1 (PPG3, PPG5) counted by the borrow output of PPG0 (PPG2, PPG4). 16-bit PPG mode Operates as a 16-bit PPG with PPG0 (PPG2, PPG4) and PPG1 (PPG3, PPG5) connected. PPG operation The PPG timer outputs pulses of an arbitrary duty ratio (the ratio betw een the High and Low level periods of pulse waveform) at an arbitrary frequency. This can also be used as a D/A converter by an external circuit.

Register list PPG operation mode control register (PPGC1/PPGC3/PPGC5) (PPGC0/PPGC2/PPGC4) PPG output control register (PPG01/PPG23/PPG45) PPG reload register (PRLH0 to PRLH5) (PRLL0 to PRLL5) Address : 000047 H 000049H 00004BH Initial Value 0X000001B Address : 000046H 000048H 00004AH Initial Value 0X000XX1B Address : 00004CH 00004EH 000050H Initial Value 000000XXB Address : 007901H 007903H 007905H 007907H 007909H 00790BH Initial Value XXXXXXXXB Address : 007900H 007902H 007904H 007906H 007908H 00790AH Initial Value XXXXXXXXB 15 14 13 12 11 10 9 8 ⎯PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved 76543210 ⎯PEN0 PE00 PIE0 PUF0 ⎯⎯ Reserved 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) PCS1PCS2 PCS0 PCM2 PCM1 PCM0 ReservedReserved 15 14 13 12 11 10 9 8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) D14D15 D13 D12 D11 D10 D09 D08 76543210 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) D06D07 D05 D04 D03 D02 D01 D00

8/16-bit PPG ch0/2/4 block diagram PPG0/PPG2/PPG4 PIE0 PEN0 PUF0 IRQ S RQ PRLL PRLBH PRLL Peripheral clock dividing by 16 Peripheral clock dividing by 8 Peripheral clock dividing by 4 Peripheral clock dividing by 2 Peripheral clock PPG0/PPG2/PPG4 output enable PPG0/PPG2/PPG4 output latch PCNT (down counter) L/H selector PPGC0 (operating mode control) L data bu s H data bus L/H select Count clock select Dividing by 512 of timebase counter output main clock A/D converteer ch1/3/5 borrow * : Interrupt number To interrupt #30 (1EH)* #32 (20H)* #34 (22H)*

8-bit PPG ch1/3/5 block diagram PPG1/PPG3/PPG5 PIE1 PEN1 PUF1 IRQ S RQ PRLL PRLBH PRLL Peripheral clock dividing by 16 Peripheral clock dividing by 8 Peripheral clock dividing by 4 Peripheral clock dividing by 2 Peripheral clock PPG1/PPG3/PPG5 output enable PPG1/PPG3/PPG5 output latch PCNT (down counter) L/H selector PPGC1 (operating mode control) L data bus H data bus L/H select Count clock select Dividing by 512 timebase counter output main clock * : Interrupt number To interrupt #30 (1EH)* #32 (20H)* #34 (22H)*

PWC timer The PWC timer is a 16-bit multi-function up-count timer capable of measuring the input signal pulse width.
Register list PWC control status register (PWCSR) PWC data buffer register (PWCR) Ratio of dividing frequency control register (DIVR) Address : 00005D H Initial Value 0000000XB Address : 00005CH Initial Value 00000000B Address : 00005FH Initial Value 00000000B Address : 00005EH Initial Value 00000000B Address : 000060H Initial Value 15 14 13 12 11 10 9 8 STOP ( R/W ) STRT EDIR EDIE OVIR OVIE ERR Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543 210 CKS0 ( R/W ) CKS1 PIS1 PIS0 S/C MOD2 MOD1 MOD0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 D14 ( R/W ) D15 D13 D12 D11 D10 D9 D8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 ( R/W ) D7 D5 D4 D3 D2 D1 D0 76543210 ( ⎯ )

Block Diagram ERR PWCR CKS1/CKS0 ERR CKS0/CKS1 PIS0/PIS1 PWCSR DIVR PWC PWCR read Error detection Reload Data transfer Overflow 16-bit up count timer Clock Internal clock (machine clock/4) Clock divider Control circuit Timer clear Count enable Divider clear Flag set etc... Control bit output Start edge selection Measurement termination edge End edge selection Edge detection Divider ON/OFF Measurement starting edge Overflow interrupt request Divide ratio select 8-bit divider F2MC-16 bus Measurement termination interrupt request Input waveform comparator

UART UART is a general purpose serial communication interfac e for synchronous or asynchronous (start-stop syn- chronization) communications with external devices. It supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). An interrupt can be generated upon completion of reception, detection of a reception error, or completion of transmission. EI2OS is supported.

UART functions UART , or a generic serial data communication interface that sends and receives serial data to and from other CPU and peripherals, has the functions listed in following. Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.
UART operation modes ⎯ : Setting disabled *1 : + 1 is an address/data setting bit (A/D) which is used for communication control. *2 : Only one bit can be detected as a stop bit at reception. Operation mode Data length Synchronization Stop bit length Without parity With parity

0 Normal mode 7-bit or 8-bit Asynchronous

1-bit or 2-bit *2

1 Multi processor mode 8-bit + 1*1 ⎯ Asynchronous

2 Normal mode 1 to 8-bit ⎯ Synchronous No

Data buffer Full-duplex double-buffered Transmission mode Clock synchronous (without start/stop bit) Clock asynchronous (start-stop synchronous) Baud rate Special-purpose baud-rate generator It is optional from 8 kinds. Baud rate by external clock (SCK 0/SCK1/SCK2/SCK3 terminal input) Data length 8-bit or 7-bit (in the asynchronous normal mode only) 1-bit to 8-bit (synchronous mode only) Signal system Non Return to Zero (NRZ) system Reception error detection Framing error Overrun error Parity error (Not supported in operation mode 1) Interrupt request Receive interrupt (reception co mpleted, reception error detected) T ransmission interrupt (transmission completed) Both the transmission and reception support EI2OS. Master/slave type communication function (multi processor mode) Capable of 1 (master) to many (slaves) communication (available just as master)

Register list Serial mode register (SMR0 to SMR3) Serial control register (SCR0 to SCR3) Serial input/output data register (SIDR0 to SIDR3 / SODR0 to SODR3) Serial status register (SSR0 to SSR3) UART prescaler reload register (UTRLR0 to UTRLR3) UART prescaler control register (UTCR0 to UTCR3) Initial Value Address : 000020 H 000026H 00002CH 000032H 00100000B Initial Value Address : 000021 H 000027H 00002DH 000033H 00000100B Initial Value Address : 000022 H 000028H 00002EH 000034H XXXXXXXXB Initial Value Address : 000023 H 000029H 00002FH 000035H 00001000B Initial Value Address : 000024 H 00002AH 000030H 000036H 00000000B Initial Value Address : 000025 H 00002BH 000031H 000037H 0000-000B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 MD0 ( R/W ) MD1 SCKL M2L2 M2L1 SCKE SOE M2L0 15 14 13 12 11 10 9 8 P ( R/W ) PEN SBL CL A/D REC RXE TXE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 ( R/W ) D7 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 ORE ( R ) PE FRE RDRF TDRE BDS RIE TIE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 ( R/W ) D7 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 SRST ( R/W ) MD CKS ⎯ D10 D9 D8Reserved

Block Diagram MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE PEN P SBL CL A/D REC RXE TXE PE ORE FRE RDRF TDRE BDS RIE TIE SIDR0 to SIDR3 SCK0 to SCK3 SOT0 to SOT3 SIN0 to SIN3 SODR0 to SODR3 Control bus Special-purpose baud-rate generator (UART prescaler control register UTCR0 to UTCR3) (UART prescaler reload UTRLR0 to UTRLR3) Clock selector Receive status decision circuit Reception error occurrence signal for EI2OS • µDMAC (to CPU) Reception clock Reception control circuit Start bit detection circuit Reception bit counter Reception parity counter Shift register for reception Reception complete Internal data bus Transmission clock Reception interrupt signal #39 (27 H)* #35 (23H)* Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter Shift register for transmission Start transmission SMR0 to SMR3 * : Interrupt number SCR0 to SCR3 SSR0 to SSR3 Send interrupt signal #37 (25 H)* #33 (21H)* Pin Pin Pin

Extended I/O serial interface The extended I/O serial interface is a serial I/O interface in an 8-bit, single-channel, capable of clock synchronous data transfer. LSB-first or MSB-first transfer mode can be selected for data transfer. There are 2 serial I/O operation modes available: Internal shift clock mode: T ransfer data in synchronization with the internal clock. External shift clock mode: T ransfer data in synchronization with the clock supplied via the external pin (SCK). By manipulating the general-purpose port sharing the ex ternal pin (SCK) in this mode, data can also be transferred by a CPU instruction.

Register list Serial mode control status register (SMCS) Serial data register (SDR) Communication prescaler control register (SDCR) Initial Value Address : 000059H 00000010B Initial Value Address : 000058H XXXX0000B Initial Value Address : 00005AH XXXXXXXXB Initial Value Address : 00005BH 0XXX0000B 15 14 13 12 11 10 9 8 SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )( R/W )( R/W )( R/W ) 7654 3210 ⎯⎯⎯ ⎯ MODE BDS SOE SCOE 76 543 21 0 D6D7 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )( R/W )( R/W ) 15 14 13 12 11 10 9 8 ( R/W ) MD ⎯⎯ DIV3 DIV2 DIV1 DIV0

Block Diagram SIN SOT SCK SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS 21 0 SOE SCOE (MSB fast) D0 to D7 D7 to D0 (LSB fast) SDR (serial data register) Internal clock Internal data bus Transfer direction selection Read Write Control circuit Shift clock counter Interrupt request Internal data bus Initial value

I 2C Interface The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C bus and has the following features. Master/slave sending and receiving Arbitration function Clock synchronization function Slave address and general ca ll address detection function Detecting transmitting direction function Start condition repeated generation and detection function Bus error detection function

Register list I 2C bus status register (IBSR0 to IBSR2) I2C bus control register (IBCR0 to IBCR2) I2C bus clock selection register (ICCR0 to ICCR2) I2C bus address register (IADR0 to IADR2) I2C bus data register (IDAR0 to IDAR2) Address : 000070H 000076H 00007CH Initial Value 00000000B Address : 000071H 000077H 00007DH Initial Value 00000000B Address : 000072H 000078H 00007EH Initial Value XX0XXXXXB Address : 000073H 000079H 00007FH Initial Value XXXXXXXXB Address : 000074H 00007AH 000080H Initial Value XXXXXXXXB 76543210 RSC ( R ) BB AL LRB TRX AAS GCA FBT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 BEIE ( R/W ) BER SCC MSS ACK GCAA INTE INT 76543210 ( ⎯ ) ⎯ EN CS4 CS3 CS2 CS1 CS0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯ A5 A4 A3 A2 A1 A0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 ( R/W ) D7 D5 D4 D3 D2 D1 D0

Block Diagram ICCRx EN ICCRx IBSRx BB RSC LRB Last Bit TRX FBT AL IBCRx BER BEIE INTE INT IBCRx SCC MSS ACK GCAA IBSRx IDAR IADR AAS GCA CS4 CS3 CS2 CS1 CS0 2 4 8 16 128 25632 64 56 78 Sync First Byte IRQ SCLx SDAx I2C enable Clock divide 2 Clock selector 2 Bus busy Repeat start Send/receive Start stop condition generation Arbitration lost detection Interrupt request Start Master ACK enable GC-ACK enable Slave Global call Slave address compare End Error Shift clock edge change timing Start stop condition detection Generating shift clock F2MC-16 bus Clock divide 1 Clock selector 1 Peripheral clock

USB Function The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.

Feature of USB function Conform to USB2.0 Full Speed Full speed (12 Mbps) is supported. The device status is auto-answer. Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16 T oggle check by data synchronization bit Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these 3 commands can be processed the same way as the class vendor commands). The class vendor commands can be receiv ed as data and responded via firmware. Supports up to 6 EndPoints (EndPoin t0 is fixed to control transfer) 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0) Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0) Capable of detection of connection and discon nection by monitoring the USB bus power line
Register list (Continued) UDC control register (UDCC) EP0 control register (EP0C) EP1 control register (EP1C) Initial Value Address : 0000D0 H 10100000B Initial Value Address : 0000D2H X1000000B Initial Value Address : 0000D3H XXXX000XB Initial Value Address : 0000D4H 00000000B Initial Value Address : 0000D5H 01100001B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 54 321 0 RESUM ( R/W ) RST HCON USTP RFBK PWC Reserved Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 PKS0 ( R/W ) PKS0 PKS0 PKS0 PKS0 PKS0PKS0Reserved 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯⎯ ⎯ STALReserved Reserved Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 PKS1 ( R/W ) PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 TYPE ( R/W ) EPEN TYPE DIR DMAE NULE STAL PKS1

(Continued) EP2/3/4/5 control register (EP2C to EP5C) Time stamp register (TMSP) UDC status register (UDCS) UDC Interrupt enable register (UDCIE) EP0I status register (EP0IS) Address : 0000D6H 0000D8H 0000DAH 0000DCH Initial Value 01000000B Address : 0000D7H 0000D9H 0000DBH 0000DDH Initial Value 01100000B Initial Value Address : 0000DEH 00000000B Initial Value Address : 0000DFH 00000000B Initial Value Address : 0000E0H 00000000B Initial Value Address : 0000E1H 00000000B Initial Value Address : 0000E2H XXXXXXXXB Initial Value Address : 0000E3H 10XXX1XXB ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 765432 1 0 PKS2 to 5 ( R/W ) PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 TYPE ( R/W ) EPEN TYPE DIR DMAE NULE STAL Reserved 765432 10 TMSP ( R ) TMSP TMSP TMSP TMSP TMSP TMSPTMSP 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯⎯ ⎯ ⎯ TMSP TMSP TMSP ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 VON ( R/W ) VOFF SUSP SOF BRST WKUP SETP CONF 15 14 13 12 11 10 9 8 VONIE ( R/W ) VOFFIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE 76543 210 ( ⎯ ) 15 14 13 12 11 10 9 8 DRQIIE ( R/W )

(Continued) EP0O status register (EP0OS) EP1 status register (EP1S) EP2/3/4/5 status register (EP2S to EP5S) EP0/1/2/3/4/5 data register (EP0DT to EP5DT) Initial Value Address : 0000E4H XXXXXXXXB Initial Value Address : 0000E5H 100XX00XB Initial Value Address : 0000E6H XXXXXXXXB Initial Value Address : 0000E7H 1000000XB Address : 0000E8H 0000EAH 0000ECH 0000EEH Initial Value XXXXXXXXB Address : 0000E9H 0000EBH 0000EDH 0000EFH Initial Value 1000000XB Address : 0000F0H 0000F2H 0000F4H 0000F6H 0000F8H 0000FAH Initial Value XXXXXXXXB Address : 0000F1H 0000F3H 0000F5H 0000F7H 0000F9H 0000FBH Initial Value XXXXXXXXB 76543210 SIZE ( ⎯ ) ⎯ SIZE SIZE SIZE SIZE SIZE SIZE 15 14 13 12 11 10 9 8 DRQOIE ( R/W ) BFINI SPKIE ⎯⎯ DRQO SPK ⎯ ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 SIZE ( R/W ) SIZE SIZE SIZE SIZE SIZE SIZESIZE 15 14 13 12 11 10 9 8 DRQIE ( R/W ) BFINI SPKIE ⎯ BUSY DRQ SPK SIZE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 SIZE ( ⎯ ) ⎯ SIZE SIZE SIZE SIZE SIZE SIZE 15 14 13 12 11 10 9 8 DRQIE ( R/W ) BFINI SPKIE ⎯ BUSY DRQ SPK ⎯ ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 BFDT ( R/W ) BFDT BFDT BFDT BFDT BFDT BFDTBFDT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 BFDT ( R/W ) BFDT BFDT BFDT BFDT BFDT BFDT BFDT

USB Mini -HOST USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred to and from Device without PC intervention.

Feature of USB Mini-HOST Automatic detection of Low Speed/Full Speed transfer Low Speed/Full Speed transfer support Automatic detection of connection and cutting device Reset sending function support to USB-bus Support of IN/OUT/SETUP/SOF token In-token handshake packet automatic transmission (excluding ST ALL) Out-token handshake packet automatic detection Supports a maximum packet length of 256 bytes. Error (CRC error/toggle error/time-out) various supports Wake-Up function support
Differences between the USB HOST and USB Mini-HOST : Supported × : Not supported HOST Mini-HOST Hub support × Transfer Bulk transfer Control transfer Interrupt transfer ISO transfer × Transfer speed Low Speed Full Speed PRE packet support × SOF packet support Error CRC error Toggle error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection

Register list (Continued) USB host control register 0 (HCNT0) USB host control register 1 (HCNT1) USB host interruption register (HIRQ) USB host error status register (HERR) USB host state status register (HSTATE) USB SOF interruption FRAME comparison register (HFCOMP) Initial Value Address : 0000C0 H 00000000B Initial Value Address : 0000C1H 00000001B Initial Value Address : 0000C2H 00000000B Initial Value Address : 0000C3H 00000011B Initial Value Address : 0000C4H XX010010B Initial Value Address : 0000C5H 00000000B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 URIRE ( R/W ) RWKIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ( R/W ) SOFSTEP CANCEL RETRYReserved Reserved Reserved ReservedReserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 ( R/W ) TCAN RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQReserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 RERR ( R/W ) LSTSOF TOUT CRC TGERR STUFF HS HS 76543210 ( ⎯ ) ⎯ ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ( R/W ) FRAME COMP FRAME COMP FRAME COMP FRAME COMP FRAME COMP FRAME COMP FRAME COMP FRAME COMP

(Continued) USB retry timer setting register 0/1/2 (HRTIMER) USB host address register (HADR) USB EOF setting register 0/1 (HEOF) USB FRAME setting register (HFRAME) USB token end point register (HTOKEN) Initial Value Address : 0000C6H 00000000B Initial Value Address : 0000C7H 00000000B Initial Value Address : 0000C8H XXXXXX00B Initial Value Address : 0000C9H X0000000B Initial Value Address : 0000CAH 00000000B Initial Value Address : 0000CBH XX000000B Initial Value Address : 0000CCH 00000000B Initial Value Address : 0000CDH XXXXX000B Initial Value Address : 0000CEH 00000000B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 RTIMER0 ( R/W ) RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER 0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 RTIMER1 ( R/W ) RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 76543210 ( ⎯ ) ⎯⎯ ⎯ ⎯ ⎯ RTIMER2 RTIMER 2 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ADDRESS ( ⎯ ) ⎯ ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 EOF0 ( R/W ) EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯ EOF1 EOF1 EOF1 EOF1 EOF1 EOF1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 FRAME0 ( R/W ) FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 15 14 13 12 11 10 9 8 ( ⎯ ) ⎯⎯ ⎯ ⎯ FRAME1 FRAME1 FRAME1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 TKNEN ( R/W ) TGGL TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT

8/10-bit A/D converter The A/D converter converts analog input voltages into digital values and has the following features. RC sequential compare conversion me thod with sample and hold circuit Selectable 8-bit resolution or 10-bit resolution Analog input program-selectable from among 16 channels Single conversion mode : Convert 1 selected channel Scan conversion mode : Continuous plural channels (maximum 16 channels can be programmed) are converted. Continuous conversion mode : Repeatedly convert the specified channels. Stop conversion mode: Convert 1 channel then suspend conversion to remain on standby until the next activation. (Simultaneous conversion start available.) An interrupt request to the CPU can be generated upon completion of A/D conversion. Suitable for continuous processing as this interrupt activates µDMA to transfer the data resulting from A/D conversion to memory. The activation source can be select ed from among software, external trigger (falling edge), and timer (rising edge).

Register list AD control status register lower/upper (ADCS0/ADCS1) AD data register lower/upper (ADCR0/ADCR1) AD conversion channel selection register (ADMR) Initial Value Address : 000040 H 00 - - - - - 0B Initial Value Address : 000041H 00000000B Initial Value Address : 000042H XXXXXXXXB Initial Value Address : 000043H 00101XXXB Initial Value Address : 000045H 00000000B 76543 210 MD0 ( R/W ) 15 14 13 12 11 10 9 8 INT ( R/W ) BUSY INTE PAUS STS1 STS0 STRT Reserved 76543 2 10 ( R ) D7 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 ST1 ( R/W ) S10 ST0 CT1 CT0 ⎯ D9 D8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ANS2 ( R/W ) ANS3 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0

Block Diagram φ MP ADTG AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADCR0, ADCR1 ADCS0, ADCS1 AVCC AVRH AVSS ADMR Input circuit D/A converter Sequential comparison register Data register A/D control register upper A/D control register lower Prescaler Operating clock Trigger start Timer start Decoder Comparator Sample & hold circuit Timer (PPG1 output) Data bus Conversion channel selection

DTP/External interrupt circuit DTP (Data T ransfer Peripheral)/External interrupt circuit detects the interrupt reques t input from the external interrupt input terminal (INT7 to INT0) , and outputs the interrupt request.

DTP/External interrupt circuit function The DTP/External interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (INT7 to INT0). If CPU accepts the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS. And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (DTP function) performed by EI2OS.
Overview of DTP/External interrupt circuit External interrupt DTP function Input pin 8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK, P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0) Interrupt source The detection level or the type of the edge for each terminal can be set in the request level setting register (ELVR). Input of H level/L level/rising edge/falling edge. Interrupt number #18 (12 H), #20 (14H), #22 (16H), #24 (18H) Interrupt control Enabling/disabling the interrupt request output using the DTP/interrupt enable register (ENIR) Interrupt flag Holding the interrupt causes us ing the DTP/interrupt cause register (EIRR) Process setting Disable EI 2OS (ICR: ISE=“0”) Enable EI 2OS (ICR: ISE=“1”) Process Branched to the interrupt handling routine After an automatic data transfer by EI2OS, branched to the interrupt handling routine

Register list DTP/Interrupt enable register (ENIR) DTP/Interrupt source register (EIRR) Request level setting register (ELVR) Initial Value Address : 00003C H 00000000B Initial Value Address : 00003DH 00000000B Initial Value Address : 00003EH 00000000B Initial Value Address : 00003FH 00000000B 76 5432 10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0 76 5432 10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4

Block Diagram LB7 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 P60/INT0 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 P61/INT1 P62/INT2 SIN P63/INT3 SOT #18(12H)* #20(14H)* #22(16H)* #24(18H)* 22222222 P64/INT4 SCK P65/INT5 PWC P66/INT6 SCL0 P67/INT7 SDA0 Request level setting register (ELVR) Pin Pin Pin Pin Selector Selector Selector Selector Selector Selector Selector Selector Pin Pin Pin Pin Interrupt request signal Internal data bus DTP/interrupt source register (EIRR) DTP/interrupt enable register (ENIR) * : Interrupt number DTP/external interrupt input detection circuit

Interrupt controller The interrupt control register is located inside the interr upt controller; it exists for every I/O having an interrupt function. This register has the following functions. Setting of the interrupt le vels of relevant resources

Register list Note : Do not access interrupt control registers using any read modify write instruction because it causes a malfunction.
Block Diagram Interrupt control register (ICR01, ICR03, ICR05, ICR07, ICR09, ICR11, ICR13, ICR15) Interrupt control register (ICR00, ICR02, ICR04, ICR06, ICR08, ICR10, ICR12, ICR14) Initial Value Address : ICR01 : 0000B1 H ICR03 : 0000B3H ICR05 : 0000B5H ICR07 : 0000B7H ICR09 : 0000B9H ICR11 : 0000BBH ICR13 : 0000BDH ICR15 : 0000BFH 00000111B Initial Value Address : ICR00 : 0000B0 H ICR02 : 0000B2H ICR04 : 0000B4H ICR06 : 0000B6H ICR08 : 0000B8H ICR10 : 0000BAH ICR12 : 0000BCH ICR14 : 0000BEH 00000111B 15 14 13 12 11 10 9 8 ICS2 ( W ) ICS3 ICS1 ICS0 IL2 IL1 IL0 ISE 76543210 ICS2 ( W ) ICS3 ICS1 ICS0 IL2 IL1 IL0 ISE IL2 IL1 IL0 Determine priority of interrupt Interrupt request (peripheral resource) (CPU) Interrupt level F2MC-16LX bus

µDMAC µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features. Performs automatic data transfer between the peripheral resource (I/O) and memory The program execution of CPU stops in the DMA start-up Capable of selecting whether to increment the transfer source and destination addresses DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and descriptor. A STOP request is available for stopping DMA transfer from the resource. Upon completion of DMA transfer, the flag bit corres ponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller.

Register list (Continued) DMA enable register upper (DERH) DMA enable register lower (DERL) DMA stop status register (DSSR) DMA status register upper (DSRH) DMA status register lower (DSRL) DMA descriptor channel specification register (DCSR) * : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”. The DSSR is upper when the STP bit of DCSR in the DSSR is “1”. Initial Value Address : 0000AD H 00000000B Initial Value Address : 0000ACH 00000000B Initial Value Address : 0000A4H 00000000B Initial Value Address : 00009DH 00000000B Initial Value Address : 00009CH 00000000B Initial Value Address : 00009BH 00000000B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 EN14 ( R/W ) EN15 EN13 EN12 EN11 EN10 EN9 EN8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 EN6 ( R/W ) EN7 EN5 EN4 EN3 EN2 EN1 EN0 76543210 STP6 STP14 STP7 STP15 STP5 STP13 STP4 STP12 STP3 STP11 STP2 STP10 STP1 STP9 STP0 STP8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) 15 14 13 12 11 10 9 8 DTE14DTE15 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5432 10 DTE6 ( R/W ) DTE7 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ( R/W ) STP DCSR3 DCSR2 DCSR1 DCSR0Reserved Rese rved Reserved

(Continued) DMA buffer address pointer lower 8-bit (DBAPL) DMA buffer address pointer middle 8-bit (DBAPM) DMA buffer address pointer upper 8-bit (DBAPH) DMA control register (DMACS) DMA I/O register address pointer lower 8-bit (DIOAL) DMA I/O register address pointer upper 8-bit (DIOAH) DMA data counter lower 8-bit (DDCTL) DMA data counter upper 8-bit (DDCTH) Note : The above register is switched for each channel depending on the DCSR. Initial Value Address : 007920H XXXXXXXXB Initial Value Address : 007921H XXXXXXXXB Initial Value Address : 007922H XXXXXXXXB Initial Value Address : 007923H XXXXXXXXB Initial Value Address : 007924H XXXXXXXXB Initial Value Address : 007925H XXXXXXXXB Initial Value Address : 007926H XXXXXXXXB Initial Value Address : 007927H XXXXXXXXB ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 DBAPL ( R/W ) DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL 15 14 13 12 11 10 9 8 DBAPMDBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) 76543210 DBAPHDBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) 15 14 13 12 11 10 9 8 RDY1RDY2 BYTEL IF BW BF DIR SE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76543210 A06 ( R/W ) A07 A05 A04 A03 A02 A01 A00 15 14 13 12 11 10 9 8 A14A15 A13 A12 A11 A10 A09 A08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) 76543210 B06B07 B05 B04 B03 B02 B01 B00 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W ) 15 14 13 12 11 10 9 B14B15 B13 B12 B11 B10 B09 B08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

External bus pin control circuit The external bus pin control circuit controls external bus pins to extend the CPU address and data buses to externals.

Register list
Block Diagram
Automatic ready function selection register (ARSR)
External address output control register (HACR)
Bus control signal selection register (EPCR) Initial Value Address : 0000A5H 0011- - 00B Initial Value Initial Value Address : 0000A7H 1000*10 -B W :Write only :Unused :“1” or “0” 15 14 13 12 11 10 9 8 ICR0 (W) ICR1 HMR1 HMR0 ⎯⎯ LMR1 LMR0 (W) (W) (W) (W) (W) (W) (W) 76543210 E22 (W) E23 E21 E20 E19 E18 E17 E16 15 14 13 12 11 10 98 RYE (W) CKE HDE Reserved HMBS (W)RE LMBS ⎯ RB Access control Access control Address control Data control P0 direction P0 data

Address matching detection function When the address is equal to the value set in the address detection register, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01 H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By perf orming processing by the INT#9 interrupt routine, the program patch function is enabled. 2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code.

Register list
Program address detect register 0 to 2 (PADR0)
Program address detect register 3 to 5 (PADR1)
Program address detection control status register (PACSR) PADR0 (lower) Initial Value XXXXXXXXB Address : 001FF0H PADR0 (middle) Initial Value XXXXXXXXB Address : 001FF1H PADR0 (upper) Initial Value XXXXXXXXB Address : 001FF2H PADR1 (lower) Initial Value XXXXXXXXB Address : 001FF3H PADR1 (middle) Initial Value XXXXXXXXB Address : 001FF4H PADR1 (upper) Initial Value XXXXXXXXB Address : 001FF5H PACSR Initial Value 00000000B Address : 00009EH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76543210 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76543210 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76543210 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76543210 (R/W) ADIE ADDEReserved Reserved Reserved Reserved Reserved Reserved R/W : Readable and Writable X : Undefined

Delay interrupt generator module The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware interrupt can be generated by software.

Delay interrupt generator module function
Block Diagram Function and control Interrupt source
Setting the R0 bit in the delayed interrupt request generation/release register to 1 (DIRR: R0 = 1) generates a delayed interrupt request.
Setting the R0 bit in the delayed interrupt request generation/release register to 0 (DIRR: R0 = 0) cancels the delayed interrupt request. Interrupt control No setting of permission register is provided. Interrupt flag Set in bit R0 of the delayed interr upt request generation /clear register (DIRR : R0) EI2OS support Not ready for ext ended intelligent I/O service (EI2OS). Internal data bus Delay interrupt factor generation/release register(DIRR) S Interrupt request R latch ⎯ : Undefined Interrupt request signal

ROM mirror function selection module The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read by accessing bank 00.

ROM mirroring function selection module function
Block Diagram

Description

Mirror setting address FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in the 00 bank. Interrupt source None. EI2OS support Not ready for ext ended intelligent I/O service (EI2OS) . ROM Internal data bus ROM mirror function selection register (ROMM) 00 bankFF bank Address Data Address area Re- served

Low power consumption (standby) mode The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode.

CPU operation mode and functional description
Register list CPU operating clock Operation mode Description PLL clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of oscillator clock (HCLK) frequency. Sleep Only peripheral resources operate at the clock frequency obtained by PLL multiplica- tion of the oscillator clock (HCLK) . Time-base timer Only the time-base timer operates at the clock frequency obtained by PLL multiplica- tion of the oscillator clock (HCLK) frequency. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. Main clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by divid- ing the oscillator clock (HCLK) frequency by two. Sleep Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Time-base timer Only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. Sub clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by dividing the subclock (SCLK) frequency by four. Sleep Only peripheral resources operate at the clock frequency obtained by dividing the subclock (SCLK) frequency by four. Watch mode Only the watch timer operates at the clock frequency obtained by dividing the subclock (SCLK) frequency by four. Stop The CPU and peripheral resources ar e suspended with the subclock stopped. CPU intermittent operation mode Normal run The halved or PLL-multiplied oscillator clock (HCLK) frequency or the subclock (SCLK) frequency is used for operation while being decimated in a certain period. Low power consumption mode control register (LPMCR) Initial Value Address : 0000A0H 00011000B 76543210 SLP ( W ) STP SPL RST TMD CG1 CG0 Reserved

Clock The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation is referred to as PLL clock.

Register list Clock selection register (CKSCR) Initial Value Address : 0000A1H 11111100B 15 14 13 12 11 10 9 8 MCM ( R ) SCM WS1 WS0 SCS MCS CS1 CS0

3 Mbits flash memory The description that follows applies to the flash memory built in the MB90F334A; it is not applicable to evaluation ROM or masked ROM. The flash memory is located in bank FF in the CPU memory map.

Function to flash memory * : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

Memory capacity 3072 Kbits (384 KB) Memory configuration 384 Kwords × 8 bits/192 Kwords × 16 bits Sector configuration 64 KB × 5 + 32 KB + 8 KB × 2 + 16 KB Sector protect function Possibility that set up with a recommendation parallel writer Program algorithm Automatic program algorithm (E mbedded Algorithm* : Similar to MBM29LV400TC) Operation command

Compatibility with the JEDEC standard-type command
Built-in deletion pause/deletion resume function
Detection of programming/erasure completion using data polling and the toggle bit
Capable of erasing data sector by sector (in arbitrary combination of sectors) Program/Erase cycle At le ast 10,000 times guaranteed How to program and erase memory
Parallel programmer available for programming and erasure (Ando Denki : AF9708, AF9709, AF9709B)
Can be written and erased using a dedicated serial writer (Yokogawa Digital Computer Corporation : AF220/AF210/AF120/AF110)
Write/delete operation by program execution Interrupt source Programming/erasure completion sources EI2OS supports Not ready for expanded intelligent I/O service (EI 2OS).

Sector configuration of flash memory
Register list SA0 (64 KB) SA1 (64 KB) F80000H F8FFFFH F90000H F9FFFFH FA0000H FAFFFFH FB0000H FBFFFFH 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH SA2 (64 KB) FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H FF7FFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 77FFFH SA3 (64 KB) SA4 (64 KB) SA5 (32 KB) SA6 (8 KB) SA7 (8 KB) SA8 (16 KB) FF8000H FF9FFFH FFA000H FFBFFFH FFC000H FFFFFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH Flash Memory CPU address Writer address * * : The writer address is relative to the CPU address when data is programmed into flash memory by a parallel programmer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. Prohibited Prohibited Flash memory control register (FMCS) Initial Value Address : 0000AEH 000X0000B 76543210 RDYINT ( R/W ) INTE WE RDY LPM1 LPM0 ReservedReserved

Standard configuration for Fujitsu standard serial on-board writing The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Y okogawa Digital Computer Cor- poration is used for Fujitsu standard serial on-board writing. Note : Inquire of Y okogawa Digital Computer Corporation for details about the functions and operations of the AF220, AF210, AF120 and AF110 flash microcontroller programmer, general-purpose common cable for connection (AZ210) and connectors.
Pins Used for Fujitsu Standard Serial On-board Programming Pin Function Description MD2, MD1, MD0 Mode input pin The device enters the serial program mode by setting MD2=1, MD1=1 and MD0 =0. X0, X1 Oscillation pin Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. P60, P61 Programming program start pins Input a Low level to P60 and a High level to P61. RST Reset input pin ⎯ SIN0 Serial data input pin. UART0 is used as CLK synchronous mode. In program mode, the pins used for the UART0 CLK synchronous mode are SIN0, SOT0 and SCK0. SOT0 Serial data output pin SCK0 Serial clock input pin VCC Power source input pin When supplying the write voltage (MB90F334A : 3.3 V ± 0.3 V) from the user system, connection with the flash microcontroller programmer is not necessary. When connecting, do not short-circuit with the user power supply. V SS GND Pin Share GND with the flash microcontroller programmer. Host interface cable (AZ201) General-purpose common cable (AZ210) CLK synchronous serial MB90F334A user system RS232C Can operate stand alone Flash microcontroller programmer Memory card

The control circuit shown in the figure is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the user system. Isolate the user circuit during serial on-board writing, with the TICS signal of the flash microcontroller programmer. Control circuit The MB90F334A serial clock frequency that can be input is determined by the following expression: Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used. Inputable serial clock frequency = 0.125 × oscillation clock frequency.

Maximum serial clock frequency
System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa Digital Computer Corporation) Contact to : Yokogawa Digital Computer Corporation TEL : 81-423-33-6224 Note : The AF200 flash microcontroller programmer is a retired product, but it can be supported using control module FF201. Oscillation clock frequency Maximum serial clock frequency acceptable to the microcontroller Maximum serial clock frequency that can be set with the AF220, AF210, AF120 or AF110 Maximum serial clock frequency that can be set with the AF200 At 6 MHz 750 kHz 500 kHz 500 kHz Part number Function Unit AF220/AC4P Model with internal Ethernet interface /100 V to 220 V power adapter AF210/AC4P Standard model /100 V to 220 V power adapter AF120/AC4P Single key internal Ethernet in terface mode /100 V to 220 V power adapter AF110/AC4P Single key model / 100 V to 220 V power adapter AZ221 PC/AT RS232C cable for writer AZ210 Standard target probe (a) length : 1 m FF201 Control module for Fujitsu F 2MC-16LX flash microcontroller control module AZ290 Remote controller /P4 4 MB PC Card (option) Flash me mory capacity to 512 KB correspondence 10 kΩ AF220/AF210/AF120/AF110 program control pin AF220/AF210/AF120/AF110/ TICS pin MB90F334A program control pin User

■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings *1 : The parameter is based on VSS = AVSS = 0.0 V . *2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on. *3 : Be careful not to let AVRH exceed AVcc. *4 : VI and VO must not exceed Vcc + 0.3 V . However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *5 : Applicable to pins : P60 to P67, P96, P A0 to P A7, PB0 to PB4, VBUS *6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P 27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, P90 to P95, PB5, PB6

Use within recommended operating conditions.
Use at DC voltage (current)
The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1 VCC VSS − 0.3 V SS + 4.0 V AVCC VSS − 0.3 V SS + 4.0 V V CC ≥ AVCC*2 AVRH V SS − 0.3 V SS + 4.0 V AV CC ≥ AVR ≥ 0 V*3 Input voltage*1 VI VSS − 0.3 V SS + 4.0 V *4 VSS − 0.3 V SS + 6.0 V Nch open-drain (Withstand voltage of

5 V I/O)*

− 0.5 V SS + 4.5 V USB I/O Output voltage*1 VO VSS − 0.3 V SS + 4.0 V *4 − 0.5 V SS + 4.5 V USB I/O Maximum clamp current I CLAMP − 2.0 +2.0 mA *6 Total maximum clamp current Σ⏐ICLAMP⏐⎯ 20 mA *6 “L” level maximum output current IOL1 ⎯ 10 mA Other than USB I/O* 7 IOL2 ⎯ 43 mA USB I/O* 7 “L” level average output current I OLAV ⎯ 3m A * 8 “L” level maximum total output current ΣIOL ⎯ 60 mA “L” level average total output current ΣIOLAV ⎯ 30 mA *9 “H” level maximum output current IOH1 ⎯− 10 mA Other than USB I/O* 7 IOH2 ⎯− 43 mA USB I/O* 7 “H” level average output current I OHAV ⎯− 3m A * 8 “H” level maximum total output current ΣIOH ⎯− 60 mA “H” level average total output current ΣIOHAV ⎯− 30 mA *9 Power consumption Pd ⎯ 340 mW Operating temperature T A − 40 + 85 °C Storage temperature Tstg − 55 + 150 °C − 55 + 125 °C USB I/O

The value of the limiting resistanc e should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/outpu t pins other than P60 to P67, P96, P A0 to P A7, PB0 to PB4, DVP , DVM, HVP , HVM, VBUS, HCON
Sample recommended circuits: *7 : A peak value of an applicable one pin is specified as a maximum output current. *8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Pch Nch VCC R Input/output equivalent circuits +B input (0 V to 16 V) Limiting resistance Protective diode

Recommended Operating Conditions (VSS = AVSS = 0.0 V) * : Applicable to pins : P60 to P67, P96, P A0 to P A7, PB0 to PB4, VBUS WARNING: The recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Remarks Min Max Power supply voltage V CC 3.0 3.6 V At normal operation (when using USB) 2.7 3.6 V At normal operation (when not using USB) 1.8 3.6 V Hold state of stop operation Input “H” voltage VIH 0.7 VCC VCC + 0.3 V CMOS input pin VIHS1 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHS2 0.8 VCC VSS + 5.3 V Nch open-drain (Withstand voltage of 5 V I/O)* VIHM VCC − 0.3 V CC + 0.3 V MD pin input VIHUSB 2.0 V CC + 0.3 V USB pin input Input “L” voltage VIL VSS − 0.3 0.3 V CC V CMOS input pin VILS VSS − 0.3 0.2 V CC V CMOS hysteresis input pin VILM VSS − 0.3 V SS + 0.3 V MD pin input VILUSB VSS 0.8 V USB pin input Differential input sensitivity VDI 0.2 ⎯ V USB pin input Differential common mode input voltage range VCM 0.8 2.5 V USB pin input Series resistance R S 25 30 Ω Recommended value = 27 Ω at using USB Operating temperature TA − 40 + 85 °C When not using USB 0 + 70 °C When using USB

DC Characteristics (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) (Continued) Parameter Sym bol Pin name Conditions Value Unit RemarksMin Typ Max Output “H” voltage VOH Output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, HVP, HVM, DVP, DVM I OH = − 4.0 mA VCC − 0.5 ⎯ Vcc V HVP, HVM, DVP, DVM RL = 15 kΩ ± 5% 2.8 ⎯ 3.6 V Output “L” voltage VOL Output pins other than HVP, HVM, DVP, DVM IOL = 4.0 mA Vss ⎯ Vss + 0.4 V HVP, HVM, DVP, DVM RL = 1.5 kΩ ± 5% 0 ⎯ 0.3 V Input leak current IIL Output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, HVP, HVM, DVP, DVM V CC = 3.3 V, Vss < VI < VCC − 10 ⎯+ 10 µA HVP, HVM, DVP, DVM ⎯− 5 ⎯+ 5 µA Pull-up resistance RPULL P00 to P07, P10 to P17 VCC = 3.3 V, TA = + 25 °C 25 50 100 k Ω Open drain output current I LIOD P60 to P67, P96, PA0 to PA7, PB0 to PB4, ⎯⎯ 0.1 10 µA Power supply current I CC VCC VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At USB operating (USTP = 0) ⎯ 75 85 mA MB90F334A ⎯ 65 75 mA MB90333A V CC = 3.3 V, Internal frequency 24 MHz, At normal operating At non-operating USB (USTP = 1) ⎯ 70 80 mA MB90F334A ⎯ 60 70 mA MB90333A I CCS VCC = 3.3 V, Internal frequency 24 MHz, At sleep mode ⎯ 27 40 mA I CTS VCC = 3.3 V, Internal frequency 24 MHz, At timer mode ⎯ 3.5 10 mA V CC = 3.3 V, Internal frequency 3 MHz, At timer mode ⎯ 12 m A I CCL VCC = 3.3 V, Internal frequency 8 kHz, At subclock operation, A = +25 °C) ⎯ 25 150 µA

(Continued) (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Note : P60 to P67, P96, P A0 to P A7, and PB0 to PB4 are Nch open-drain pins usually used as CMOS. Parameter Sym- bol Pin name Conditions Value Unit RemarksMin Typ Max Power supply current I CCLs VCC VCC = 3.3 V, Internal frequency 8 kHz, At sub clock, At sleep operating, A = + 25 °C) ⎯ 10 50 µA ICCT VCC = 3.3 V, Internal frequency 8 kHz, Watch mode, A = + 25 °C) ⎯ 1.5 40 µA ICCH TA = + 25 °C, At stop ⎯ 14 0 µA Input capacitance CIN Other than AVcc, AVss, Vcc, Vss ⎯⎯ 51 5 p F Pull-up resistor Rup RST ⎯ 25 50 100 k Ω

AC Characteristics (1)Clock input timing (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- bol Pin name Value Unit RemarksMin Typ Max Clock frequency fCH X0, X1 ⎯ 6 ⎯ MHz External crystal oscillation 6 ⎯ 24 MHz External clock input fCL X0A, X1A ⎯ 32.768 ⎯ kHz Clock cycle time tHCYL X0, X1 ⎯ 166.7 ⎯ ns External crystal oscillation 166.7 ⎯ 41.7 ns External clock input tLCYL X0A, X1A ⎯ 30.5 ⎯ s Input clock pulse width PWH PWL X0 10 ⎯⎯ ns A reference duty ratio is 30% to 70%. PWHL PWLL X0A ⎯ 15.2 ⎯ s Input clock rise time and fall time tcr tcf X0 ⎯⎯ 5 ns At external clock Internal operating clock frequency fCP ⎯ 3 ⎯ 24 MHz When main clock is used fCPL ⎯⎯ 8.192 ⎯ kHz When sub clock is used Internal operating clock cycle time tCP ⎯ 42 ⎯ 333 ns When main clock is used tCPL ⎯⎯ 122.1 ⎯ s When sub clock is used

0.8 VCC

0.2 VCC

Clock Timing

3.6 3.0 2.7 3 6 12 24

PLL operation guarantee range PLL operation guarantee range Normal Operation Assurance Range Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V. Relation between internal operation clock frequency and power supply voltage Internal clock FCP (MHz) Power voltage VCC (V) 6 24 Relation between oscillation frequency and internal operation clock frequency Multiplied by 4 Multiplied by 2 Multiplied by 1 Oscillation clock Fc (MHz) External clock Internal clock FCP (MHz)

The AC standards assume the following measurement reference voltages. 2.4 V 0.8 V

0.7 VCC

0.3 VCC

Input signal waveform Hysteresis input pin Hysteresis input/other than MD input pin
Output signal waveform Output pin

(2)Clock output timing (VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Note : t CP : See “ (1) Clock input timing”. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Cycle time t CYC CLK ⎯ tCP ⎯ ns CLK↑→CLK↓ tCHCL CLK V CC = 3.0 V to 3.6 V tCP/2 − 15 t CP/2 + 15 ns At f cp = 24 MHz tCP/2 − 20 t CP/2 + 20 ns At f cp = 12 MHz tCP/2 − 64 t CP/2 + 64 ns At f cp = 6 MHz CLK tCYC 2.4 V 2.4 V 0.8 V tCHCL

(3) Reset (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) * : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a FAR/ceramic oscillator, and 0 milliseconds on an external clock. Parameter Sym- bol Pin name Condi- tions Value Unit Remarks Min Max Reset input time t RSTL RST ⎯ 500 ⎯ ns At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode Oscillation time of oscillator* + 500 ns ⎯µ s At stop mode, At sub clock mode, At sub sleep mode, At watch mode RST RST 500 ns tRSTL 0.2 Vcc 0.2 Vcc tRSTL 0.2 Vcc 0.2 Vcc

During stop mode, subclock mode, sub-sleep mode and watch mode Internal operation clock Internal reset Oscillation time of oscillator Oscillation stabilization wait time Execute instruction 90% of amplitude
During normal operation, time-base timer mode, main sleep mode and PLL sleep mode

(4) Power-on reset (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to +85 °C) Notes : • VCC must be lower than 0.2 V before the power supply is turned on.

The above standard is a value for performing a power-on reset.
In the device, there are internal registers which is initialized only by a power-on reset. When the initialization of these items is expected, turn on the power supply according to the standards. Parameter Symbol Pin name Condi- tions Value Unit Remarks Min Max Power supply rising time t R VCC ⎯ 30 ms Power supply shutdown time tOFF VCC 1 ⎯ ms For repeated operation VCC VCC 3.0 V VSS tR 0.2 V0.2 V 2.7 V tOFF 0.2 V Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation. RAM data hold The rising edge should be 50 mV/ms or less.

(5) UART0, 1, 2, 3 I/O extended serial timing (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Notes : • Above rating is the case of CLK synchronous mode.

CL is a load capacitance value on pins for testing.
tCP : See “ (1) Clock input timing”. Parameter Sym bol Pin name Conditions Value Unit Remarks Min Max Serial clock cycle time t SCYC SCKx Internal shift clock mode output pin is : CL = 80 pF + 1TTL 8 tCP ⎯ ns SCK↓→SOT delay time t SLOV SCKx, SOTx − 80 + 80 ns Valid SIN→SCK↑ tIVSH SCKx, SINx 100 ⎯ ns SCK↑→valid SIN hold time t SHIX SCKx, SINx 60 ⎯ ns Serial clock H pulse width t SHSL SCKx, SINx External shift clock mode output pin is : CL = 80 pF + 1TTL 4 tCP ⎯ ns Serial clock L pulse width t SLSH SCKx, SINx 4 tCP ⎯ ns SCK↓→SOT delay time t SLOV SCKx, SOTx ⎯ 150 ns Valid SIN→SCK↑ tIVSH SCKx, SINx 60 ⎯ ns SCK↑→valid SIN hold time t SHIX SCKx, SINx 60 ⎯ ns

Internal shift clock mode
External shift clock mode SCK SOT SIN tSCYC tSLOV tIVSH tSHIX 0.8 V 0.8 V 2.4 V 2.4 V 0.8 V

0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC 2.4 V 0.8 V

(6) I2C timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : fCP is internal operating clock frequency. See “ (1) Clock input timing”. *2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance. *3 : The maximum tHDDA T only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. Parameter Symbol Conditions Value UnitMin Max SCL clock frequency t SCL Power-supply voltage of external pull-up resistor at 5.0 V. R = 1.2 kΩ, C = 50 pF* Power-supply voltage of external pull-up resistor at 3.6 V. R = 1.0 kΩ, C = 50 pF* 0 100 kHz (Repeat) [start] condition hold time SDA ↓ → SCL ↓ t HDSTA 4.0 ⎯µ s SCL clock “L” width t LOW 4.7 ⎯µ s SCL clock “H” width t HIGH 4.0 ⎯µ s Repeat [start] condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 ⎯µ s Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 03 . 4 5 * 3 µs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT Power-supply voltage of external pull-up resistor at 5.0 V. f CP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. f CP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 250 ⎯ nsPower-supply voltage of external pull-up resistor at 5.0 V. f CP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. f CP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2 200 ⎯ [Stop] condition setup time SCL ↑ → SDA ↑ tSUSTO Power-supply voltage of external pull-up resistor at 5.0 V. R = 1.2 kΩ, C = 50 pF* Power-supply voltage of external pull-up resistor at 3.6 V. R = 1.0 kΩ, C = 50 pF* 4.0 ⎯µ s Bus free time between [stop] condition and [start] condition tBUS 4.7 ⎯µ s SDA SCL tLOW tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO tHDSTA tHIGH tBUS

(7) Timer input timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Note : tCP : See “ (1) Clock input timing”. (8) Timer output timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) (9) Trigger input timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) Note : tCP : See “ (1) Clock input timing”. Parameter Symbol Pin name Condi- tions Value Unit Remarks Min Max Input pulse width tTIWH tTIWL FRCK, INx, TINx PWC ⎯ 4 tCP ⎯ ns Parameter Sym- bol Pin name Condi- tions Value Unit Remarks Min Max CLK↑→TOUT change time PPG0 to PPG5 change time OUT0 to OUT3 change time t TO TOTx, PPGx, OUTx ⎯ 30 ⎯ ns Parameter Symbol Pin name Condi- tions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL INTx, ADTG ⎯ 5 tCP ⎯ ns At normal operating 1 ⎯µ s In Stop mode 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWH tTIWL PWC TINx INx FRCK CLK PPGx OUTx 2.4 V tTO 2.4 V 0.8 V 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTRGH tTRGL INTx ADTGx

(10) Bus read timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Note : tCP : See “ (1) Clock input timing”. Parameter Sym bol Pin name Condi- tions Value Unit Remarks Min Max ALE pulse width t LHLL ALE ⎯ tCP/2 − 15 ⎯ ns At f cp = 24 MHz tCP/2 − 20 ⎯ ns At f cp = 12 MHz tCP/2 − 35 ⎯ ns At f cp = 6 MHz Valid address→ALE↓time t AVLL Address, ALE ⎯ tCP/2 − 17 ⎯ ns tCP/2 − 40 ⎯ ns At f cp = 6 MHz ALE↓→Address valid time t LLAX ALE, Address ⎯ tCP/2 − 12 ⎯ ns Valid address→RD↓time t AVRL RD, Address ⎯ tCP − 25 ⎯ ns Valid address→valid data input tAVDV Address/ data ⎯ ⎯ 5 tCP/2 − 55 ns ⎯ 5 tCP/2 − 80 ns At f cp = 6 MHz RD pulse width t RLRH RD ⎯ 3 tCP/2 − 25 ⎯ ns At f cp = 24 MHz 3 tCP/2 − 20 ⎯ ns At f cp = 12 MHz RD↓→valid data input t RLDV RD, Data ⎯ ⎯ 3 tCP/2 − 55 ns ⎯ 3 tCP/2 − 80 ns At f cp = 6 MHz RD↓→data hold time t RHDX RD, Data ⎯ 0 ⎯ ns RD↑→ALE↑time t RHLH RD, ALE ⎯ tCP/2 − 15 ⎯ ns RD↑→address valid time t RHAX Address, RD ⎯ tCP/2 − 10 ⎯ ns Valid address→CLK↑time t AVCH Address, CLK ⎯ tCP/2 − 17 ⎯ ns RD↓→CLK↑time t RLCH RD, CLK ⎯ tCP/2 − 17 ⎯ ns ALE↓→RD↓time t LLRL RD, ALE ⎯ tCP/2 − 15 ⎯ ns

0.8 V 0.8 V 2.4 V2.4 V 2.4 V 2.4 V 0.8 V 2.4 V 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 2.4 V tAVCH tLHLL tRHLH tAVLL tAVRL tRLDV tRLRH tRHAX tRHDX tLLAX tLLRL tRLCH tAVDV 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V Address Read data Read data In multiplex mode In non-multiplex mode

(11) Bus write timing (VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Note : tCP : See “ (1) Clock input timing”. Parameter Sym- bol Pin name Condi- tions Value Unit Remarks Min Max Valid address→WR↓time t AVWL Address, WR ⎯ tCP − 15 ⎯ ns WR pulse width t WLWH WRL, WRH ⎯ 3 tCP/2 − 25 ⎯ ns At f cp = 24 MHz ⎯ 3 tCP/2 − 20 ⎯ ns At f cp = 12 MHz Valid data output→WR↑time t DVWH Data, WR ⎯ 3 tCP/2 − 15 ⎯ ns WR↑→data hold time t WHDX WR, Data ⎯ 10 ⎯ ns At f cp = 24 MHz ⎯ 20 ⎯ ns At f cp = 12 MHz ⎯ 30 ⎯ ns At f cp = 6 MHz WR↑→address valid time t WHAX WR, Address ⎯ tCP/2 − 10 ⎯ ns WR↑→ALE↑time t WHLH WR, ALE ⎯ tCP/2 − 15 ⎯ ns WR↓→CLK↑time t WLCH WR, CLK ⎯ tCP/2 − 17 ⎯ ns WR (WRL, WRH) 0.8 V 0.8 V 2.4 V 2.4 V 2.4 V 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V CLK ALE A23 to A16 AD15 to AD00 tWHLH tAVWL tDVWH tDVWH tWLWH tWHAX tWHDX tWLCH 0.8 V 2.4 V 0.8 V 2.4 V A23 to A00 D15 to D00 tWHAX tWHDX 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V Address Write data Write data In multiplex mode In non-multiplex mode

(12) Ready input timing (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Notes : • If the RDY set-up time is insufficient, use the auto-ready function.

For input from the RDY pin, be careful as failure to satisfy AC standards may cause the chip to run out of control. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max RDY set-up time t RYHS RDY ⎯ 35 ⎯ ns ⎯ 70 ⎯ ns f cp = 6 MHz RDY hold time t RYHH ⎯ 0 ⎯ ns tRYHH 2.4 V 2.4 V 0.2 VCC0.2 VCC 0.8 VCC 0.8 VCC CLK ALE RD/WR tRYHS tRYHS RDY wait applies (1cycle) RDY wait not applied

(13) Hold timing (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Notes : • It takes one cycle or more for HAK to change after the HRQ pin is captured.

tCP : See “ (1) Clock input timing”. Parameter Symbol Pin name Condi- tions Value Unit Remarks Min Max Pin floating→HAK↓time t XHAL HAK 30 t CP ns HAK↓→pin valid time t HAHV HAK tCP 2 tCP ns HAK tXHAL tHAHV 2.4 V 0.8 V 2.4 V 2.4 V 0.8 V 0.8 V Each pin High-Z

Electrical Characteristics for the A/D Converter (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : tCP : See “ (1) Clock input timing”. *2 : The current when the CPU is in stop mode and the A/D converter is not operating (For VCC = AVCC = AVRH = 3.3 V). Parameter Sym bol Pin name Value Unit Remarks Min Typ Max Resolution ⎯⎯ ⎯ ⎯ 10 bit Total error ⎯⎯ ⎯ ⎯ ± 3.0 LSB Nonlinear error ⎯⎯ ⎯ ⎯ ± 2.5 LSB Differential linear error ⎯⎯ ⎯ ⎯ ± 1.9 LSB Zero transition voltage V OT AN0 to AN15 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV

1 LSB = AVRH/1024

voltage VFST AN0 to AN15 AVRH −

3.5 LSB

AVRH −

1.5 LSB

0.5 LSB mV

Conversion time ⎯⎯ ⎯ 176 tCP*1 ⎯ ns Sampling time ⎯⎯ ⎯ 64 tCP*1 ⎯ ns Analog port input current IAIN AN0 to AN15 ⎯⎯ 10 µA Analog input voltage V AIN AN0 to AN15 0 ⎯ AVRH V Reference voltage ⎯ AVRH 2.7 ⎯ AVCC V Power supply current IA AVCC ⎯ 1.4 3.5 mA IAH AVCC ⎯⎯ 5 µA* 2 Reference voltage supplying current IR AVRH ⎯ 95 170 µA IRH AVRH ⎯⎯ 5 µA* 2 Interchannel disparity ⎯ AN0 to AN15 ⎯⎯ 4L S B

Notes :

About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion presicion.
To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
About errors As |AVRH| becomes smaller, values of relative errors grow larger. R C Analog input Comparator
Analog input circuit model During sampling : ON Note : The values are reference values. MB90333A MB90F334A MB90V330A R 1.9 kΩ (Max) 1.9 kΩ (Max) 1.9 kΩ (Max) C 32.3 pF (Max) 25.0 pF (Max) 32.3 pF (Max) 100 0 5 10 15 20 25 30 3 MB90333A/ MB90V330A MB90F334A 20 0123456 MB90F333A/ MB90V330A MB90F334A (External impedance = 0 kΩ to 100 kΩ) External impedance [kΩ] Minimum sampling time [µs] (External impedance = 0 kΩ to 20 kΩ) External impedance [kΩ] Minimum sampling time [µs]
The relationship between the external impedance and minimum sampling time

USB characteristics (VCC = AVCC = 3.3 V ± 0.3 V , VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)

Data signal timing (Full Speed)
Data signal timing (Low Speed) Parameter Sym bol Value Unit Remarks Min Max Input characteristics Input High level voltage V IH 2.0 ⎯ V Input Low level voltage V IL ⎯ 0.8 V Differential input sensitivity V DI 0.2 ⎯ V Differential common mode range V CM 0.8 2.5 V Output characteristics Output High level voltage V OH 2.8 3.6 V I OH = − 200 µA Output Low level voltage V OL 0.0 0.3 V I OL = 2 mA Cross over voltage V CRS 1.3 2.0 V Rise time tFR 4 20 ns Full Speed tLR 75 300 ns Low Speed Fall time tFF 4 20 ns Full Speed tLF 75 300 ns Low Speed Rising/falling time matching tRFM 90 111.11 % (TFR/TFF) tRLM 80 125 % (TLR/TLF) Output resistance Z DRV 28 44 Ω Including Rs = 27 Ω DVP/HVP DVM/HVM 90% tFR 10% 90% 10% tFF Vcrs Rise time Fall time HVP HVM 90% tLR 10% 90% 10% tLF Vcrs Rise time Fall time

Load condition (Full Speed)
Load condition (Low Speed) DVP/HVP RS = 27 Ω C = 50 pF DVM/HVM RS = 27 Ω C = 50 pF Testing point Testing point HVP RS = 27 Ω C = 50 pF to 150 pF HVM RS = 27 Ω C = 50 pF to 150 pF Testing point Testing point

Flash memory write/erase characteristics * : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) Parameter Condition Value Unit Remarks Min Typ Max Sector erase time TA = + 25 °C VCC = 3.0 V ⎯ 11 5 s Excludes 00H programming prior to erasure. Chip erase time ⎯ 9 ⎯ s Excludes 00H programming prior to erasure. Word (16-bit width) programming time ⎯ 16 3,600 µs Except for over head time of system level Programming/erase cycle ⎯ 10,000 ⎯⎯ cycle Flash memory data retaining period Average TA = + 85 °C 20 ⎯⎯ year *

■ ORDERING INFORMATION Part number Package Remarks MB90F334APFF MB90333APFF 120-pin Plastic LQFP (FPT-120P-M05) MB90F334APMC MB90333APMC 120-pin Plastic LQFP (FPT-120P-M21) MB90V330A 299-pin Ceramic PGA (PGA-299C-A01) For evaluation

■ PACKAGE DIMENSIONS (Continued) 120-pin Plastic LQFP (FPT-120P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2003 FUJITSU LIMITED F120006S-c-4-5 0.07(.003) M INDEX 13 0 6091 120 6190 LEAD No. (Stand off) 0.10±0.10 (.004±.004) 0.25(.010) (.024±.006) 0.60±0.15 (.020±.008) 0.50±0.20 (Mounting height) 0~8˚ Details of "A" part 1.50 +0.20 –0.10 +.008 –.004.059 "A" (.006±.001) 0.145±0.055 (.006±.002) 0.08(.003)

(Continued) 120-pin Plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.26 (.010) MAX (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2002 FUJITSU LIMITED F120033S-c-4-4 1 30 90 61 120 SQ (.009±.002) M0.08(.003) INDEX .006 –.001 +.002 –0.03 +0.05 0.145 "A" 0.08(.003) LEAD No. .059 –.004 +.008 –0.10 +0.20 1.50 Details of "A" part (Mounting height) 0.60±0.15 (.024±.006) 0.25(.010) (.004±.002) 0.10±0.05 (Stand off) 0~8˚ * .630 –.004 +.016 –0.10 +0.40 16.00

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0411 © 2004 FUJITSU LIMITED Printed in Japan

Summary

16-bit Proprietary Microcontroller

Description

16-bit Proprietary Microcontroller

Source title MB90333A Datasheet(PDF) - fujitsu semiconductor

Read MB90333A online.

MB90330 FUJITSU | Alldatasheet

Document overview

Technical content

24 MHz and at operating V

24 MHz)

0 Normal mode 7-bit or 8-bit Asynchronous

1 Multi processor mode 8-bit + 1*1 ⎯ Asynchronous

2 Normal mode 1 to 8-bit ⎯ Synchronous No

Description

5 V I/O)*

0.8 VCC

0.2 VCC

0.7 VCC

0.3 VCC

1 LSB = AVRH/1024

3.5 LSB

1.5 LSB

0.5 LSB mV

MB90333A specifications and overview.

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