MB89181

MB89180 FUJITSU | Alldatasheet

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DS07-12404-2EFUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89180 Series MB89181/182/183/P185/PV180 ■ DESCRIPTION The MB89180 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, a remote control transmission output, external interrupts, an LCD controller/driver, and a watch prescaler. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES

• F 2MC-8L family CPU core
• Dual-clock control system
• High speed operation at low voltage
• Minimum execution time: 0.95 µs/2.7 V, 1.33 µs/2.2 V
• I/O ports: max. 64 channels
• 21-bit time-base timer
• 8/16-bit timer/counter: 1 channel (8 bits × 2 channels)
• 8-bit serial I/O: 1 channel
• LCD controller/driver: max. 32 segments outputs × 4 commons (Continued) ■ PACKAGE (FPT -64P-M06) (FPT -64P-M09) (MQP-64C-P01) 64-pin Plastic QFP 64-pin Plastic QFP 64-pin Ceramic MQFP (FPT -64P-M03) 64-pin Plastic SQFP

(Continued)

• Remote control transmission output
• Buzzer output
• Watch prescaler (15 bits)
• External interrupts (wake-up function) Four independent channels with edge detection function plus eight “L” level-interrupt channels ■ PRODUCT LINEUP (Continued) MB89182 MB89183 MB89P185 MB89PV180 Classification Mass production products (mask ROM products) One-time PROM product Piggyback/ evaluation product (for evaluation and development) ROM size 4 K × 8 bits (internal mask ROM)

6 K × 8 bits

(internal mask ROM)

8 K × 8 bits

(internal mask ROM) 16K × 8 bits (internal PROM, programming with general- purpose EPROM programmer)

32 K × 8 bits

(external ROM) RAM size 128 × 8 bits 256 × 8 bits 512 × 8 bits CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.95 µs/4.2 MHz Interrupt processing time: 8.57 µs/4.2 MHz Ports I/O ports (N-ch open drain): 8 (6 ports also serve as peripherals, and 3 ports are a heavy-current drive type.) Output ports (N-ch open drain): 18 (16 ports also serve as segment pins* 1, and 2 ports serve as booster capacitor connection pins.) I/O ports (CMOS): 16 (12 ports also serve as an external interrupt, and 8 ports also serve as segment pins*1.) Output port (CMOS): 1 (also serves as a remote control pin.) T otal: 43 (max.) 8/16-bit timer/ counter 8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel 8-bit serial I/O 8 bits LSB first/MSB first selectability LDC controller/driver Common output: 4 (COM2 and COM3 also serve as output ports.) Segment output: 32 (max.)* 1 Bias power supply pins: 3 LCD display RAM size: 32 × 4 bits Dividing resistor for LCD driving (external resistor selectability) External interrupt (wake-up function) 4 channels (edge selection, also serve as segment pins.)*1 8 channels (only for a level interrupt) MB89181 Part number Parameter

(Continued) *1: Selected by the mask option. See section “■ Mask Options.” *2: Varies with conditions such as the operating frequency and the connected ICE. (See section “■ Electrical Characteristics.”) *3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED. MB89182 MB89183 MB89P185 MB89PV180 Buzzer output 1 (7 frequency types are selectable by software.) Remote control transmission output 1 (pulse width and cycle are selectable by software.) Standby mode Sleep mode, stop mode, and watch mode Process CMOS Operating voltage*2 2.2 V*3 to 6.0 V 2.7 V to 6.0 V EPROM for use  MBM27C256A-20TV (LCC package) MB89181 Part number Parameter

■ PACKAGE AND CORRESPONDING PRODUCTS : Available × : Not available Note: For more information about each package, see section “■ Package Dimensions.” ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. T ake particular care on the following points:

• On the MB89181, addresses 0140H and later of the register bank cannot be used. On the MB89182, MB89183, and MB89P185 microcontrollers, addresses 0180H and later of the register bank cannot be used.
• On the MB89P185, addresses BFF0H to BFF5H comprise the option setting area, option settings can be read by reading these addresses.
• The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption
• In the case of the MB89PV180, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “■ Electrical Characteristics.” ) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” T ake particular care on the following point:
• Options are fixed on the MB89PV180 except the segment output selection. Package MB89181 MB89182 MB89183 MB89P185 MB89PV180 FPT -64P-M06 × FPT -64P-M09 × FPT -64P-M03 ×× MQP-64C-P01 ××

■ PIN ASSIGNMENT SEG4 SEG5 SEG6 SEG7 SEG8/P40 SEG9/P41 SEG10/P42 SEG11/P43 SEG12/P44 SEG13/P45 SEG14/P46 SEG15/P47 SEG16/P50 SEG17/P51 SEG18/P52 SEG19/P53 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 RST X0A X1A MODA P20/EC P21 * P22/TO P23/SI P24/SO SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2/P31 COM3/P32 V CC P30/RCO P00/INT20 P01/INT21 P02/INT22

1 SEG20/P54

*1 SEG21/P55 *1 SEG22/P56 *1 SEG23/P57 *1 SEG24/INT10/P10 *1 SEG25/INT11/P11 *1 SEG26/INT12/P12 VSS *1 SEG27/INT13/P13 *1 SEG28/P14 *1 SEG29/P15 *1 SEG30/P16 *1 SEG31/P17 *2 BUZ/P27 *2 P26 SCK/P25 (FPT-64P-M03) (Top view) *1: Selected using the mask option (in units of 4 pins). *2: N-ch open drain heavy-current drive type

P21 * P22/TO P23/SI P24/SO SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2/P31 COM3/P32 V CC P30/RCO P00/INT20 P01/INT21 P02/INT22 *1 SEG21/P55 *1 SEG22/P56 *1 SEG23/P57 *1 SEG24/INT10/P10 *1 SEG25/INT11/P11 *1 SEG26/INT12/P12 VSS *1 SEG27/INT13/P13 *1 SEG28/P14 *1 SEG29/P15 *1 SEG30/P16 *1 SEG31/P17 *2 BUZ/P27 *2 P26 SCK/P25 (FPT-64P-M09) *1: Selected using the mask option (in units of 4 pins). *2: N-ch open drain heavy-current drive type (Top view)

P21* P22/TO P23/SI P24/SO P25/SCK SEG2 SEG1 SEG0 COM0 COM1 COM2/P31 COM3/P32 V CC P30/RCO P00/INT20

1 SEG22/P56

*1 SEG23/P57 *1 SEG24/INT10/P10 *1 SEG25/INT11/P11 *1 SEG26/INT12/P12 VSS *1 SEG27/INT13/P13 *1 SEG28/P14 *1 SEG29/P15 *1 SEG30/P16 *1 SEG31/P17 *2 BUZ/P27 *2 P26 (FPT-64P-M06) (Top view) *1: Selected using the mask option (in units of 4 pins). *2: N-ch open drain heavy-current drive type

• Pin assignment on package top (MB89PV180 only) N.C.: Internally connected. Do not use. Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 65 N.C. 73 A2 81 N.C. 89 OE 66 V PP 74 A1 82 O4 90 N.C. 6 7 A 1 2 7 5A 08 3O 59 1 A 1 1 68 A7 76 N.C. 84 O6 92 A9

69 A6 77 O1 85 O7 93 A8

70 A5 78 O2 86 O8 94 A13

71 A4 79 O3 87 CE

95 A14

72 A3 80 V SS 88 A10 96 V CC

P21* P22/TO P23/SI P24/SO P25/SCK SEG2 SEG1 SEG0 COM0 COM1 COM2/P31 COM3/P32 V CC P30/RCO P00/INT20 *1 SEG23/P57 *1 SEG24/INT10/P10 *1 SEG25/INT11/P11 *1 SEG26/INT12/P12 VSS *1 SEG27/INT13/P13 *1 SEG28/P14 *1 SEG29/P15 *1 SEG30/P16 *1 SEG31/P17 *2 BUZ/P27 *2 P26 (Top view) (MQP-64C-P01) *1: Selected using the mask option (in units of 4 pins). *2: N-ch open drain heavy-current drive type

■ PIN DESCRIPTION (Continued)*1: FPT -64P-M09 *2: FPT -64P-M06 *3: FPT -64P-M03 *4: MQP-64C-P01 Pin no. Pin name Circuit type Function QFP SQFP *3 QFP *2 MQFP *4 39 40 X0 A Main clock crystal oscillator pins CR oscillation selectability (only for the mask ROM products) 38 39 X1 40 41 MODA C Operating mode selection pin Connect directly to VSS. 43 44 RST D Reset I/O pin This pin is an N-ch open drain output type with a pull- up resistor, and hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 44 to 51 45 to 52 P07/INT27 to P00/INT20 E General-purpose I/O ports Also serve as external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. 21 to 23 22 to 24 P10/INT10/ SEG24 to P12/INT12/ SEG26 E/K General-purpose I/O ports Also serve as external interrupt 1 input. The interrupt 1 input is a hysteresis type. Also serve as LCD controller/driver segment output. Switching is done by the mask option.25 26 P13/INT13/ SEG27 26 to 29 27 to 30 P14/SEG28 to P17/SEG31 F/K General-purpose I/O ports Also serve as LCD controller/driver segment output. Switching is done by the mask option. 37 38 P20/EC H General-purpose N-ch open-drain I/O port Also serves as the external clock input for the 8-bit timer counter. The resource is a hysteresis input type. 36 37 P21 I General-purpose N-ch open-drain I/O port 35 36 P22/TO I General-purpose N-ch open-drain I/O port Also serves as the 8-bit timer/counter output 34 35 P23/SI H General-purpose N-ch open-drain I/O port Also serves as the data input for the 8-bit serial I/O. The resource is a hysteresis input type. 33 34 P24/SO I General-purpose N-ch open-drain I/O port Also serves as the data output for the 8-bit serial I/O. 32 33 P25/SCK H General-purpose N-ch open-drain I/O port Also serves as the clock I/O for the 8-bit serial I/O. The resource is a hysteresis input type.

(Continued) *1: FPT -64P-M09 *2: FPT -64P-M06 *3: FPT -64P-M03 *4: MQP-64C-P01 Pin no. Pin name Circuit type Function QFP SQFP *3 QFP *2 MQFP *4 31 32 P26 I General-purpose N-ch open-drain I/O port 30 31 P27/BUZ I General-purpose N-ch open-drain I/O port Also serves as a buzzer output. 52 53 P30/RCO G General-purpose output-only port Also serves as a remote control transmission output pin. 13 to 20 14 to 21 P50/SEG16 to P57/SEG23 J/K N-ch open-drain type general-purpose output ports Also serve as LCD controller/driver segment output pins. Switching is done by the mask option. 5 to 12 6 to 13 P40/SEG8 to P47/SEG15 J/K 61 to 64, 1 to 4 62 to 64, 1 to 5 SEG7 to SEG0 K LCD controller/driver segment output-only pins 57, 58, COM3/P32, COM2/P31 L N-ch open-drain type general-purpose output ports Also serve as LCD controller/driver common output pins. 59, 60, COM1, COM0 K LCD controller/driver common output-only pins 53, 54, 54, 55, V1, V2, — LCD driving power supply pins 42 43 X0A B Subclock crystal oscillator pins (32.768 kHz) 41 42 X1A 56 57 V CC  Power supply pin 24 25 V SS  Power supply (GND) pin

• External EPROM pins (MB89PV180 only) Pin no. Pin name I/O Function

66 V PP O “H” level output pin

SS O Power supply (GND) pin I Data input pins 87 CE O ROM chip enable pin Outputs “H” during standby.

88 A10 O Address output pin

Outputs “L” at all times. A11 O Address output pins

94 A13 O

95 A14 O

96 V CC O EPROM power supply pin

N.C. — Internally connected pins Be sure to leave them open.

■ I/O CIRCUIT TYPE (Continued) Type Circuit Remarks A • Crystal or ceramic oscillation type (main clock) At an oscillation feedback resistor of approximately 1 MΩ /5.0 V

• CR oscillation type (main clock) (Selectable only for the MB89181/182/183) B • Crystal or ceramic oscillation type (subclock)
• At an oscillation feedback resistor of approximately 4.5 MΩ /5.0 V C D • Output pull-up resistor
• P-ch of approximately 50 KΩ /5.0 V
• Hysteresis input E • CMOS I/O The resource is a hysteresis input type.
• Pull-up resistor optional (MB89181/182/183/P185) F • CMOS I/O
• Pull-up resistor optional (MB89181/182/183/P185) Standby control signal Standby control signal X1A X0A Standby control signal R P-ch N-ch P-ch N-ch Port Resource R P-ch P-ch N-ch R P-ch

(Continued) Type Circuit Remarks G • CMOS output

• The P-ch output is a heavy-current drive type. H • N-ch open-drain I/O
• CMOS input
• The resource is a hysteresis input type.
• Pull-up resistor optional (MB89181/182/183) I • N-ch open-drain I/O
• CMOS input
• P21, P26, and P27 are a heavy-current drive type.
• Pull-up resistor optional (MB89181/182/183) J • N-ch open-drain output
• Pull-up resistor optional (MB89181/182/183) K • LCD controller/driver segment output L • N-ch open-drain output
• Common output P-ch N-ch Port N-ch Resource R P-ch N-ch R P-ch N-ch R P-ch P-ch N-ch P-ch N-ch N-ch P-ch N-ch P-ch N-ch

■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS . When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC ) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.

■ PROGRAMMING TO THE EPROM ON THE MB89P875 The MB89P185 is an OTPROM version of the MB89180 series. 1. Features

• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in the EPROM mode is diagrammed below. 3FF0H 4000H Option area Program area (EPROM) 16 KB Vacancy (Read value undefined) 7FFF H I/O RAM Not available Not available ROM 16 KB 0000H 0080H 0180H 8000H C000 H FFFF H Normal operating mode EPROM mode (Corresponding address on the EPROM programmer) 0000H 3FF6H Vacancy (Read value undefined)

1. Programming to the EPROM In EPROM mode, the MB89P185 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter.

• Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH in operating mode assign to 4000H to 7FFFH in EPROM mode). Program to 4000H to 7FFFH with the EPROM programmer. (3) Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see “7. PROM Option Bit Map.”) Program to 3FF0H to 3FF5H with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. Package Compatible socket adapter FPT-64P-M09 ROM-64QF2-28DP-8L2 FPT-64P-M06 ROM-64QF-28DP-8L3 Program, verify Aging +150°C, 48 Hrs. Data verification Assembly

1. PROM Option Bit Map The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: Notes:• Set each bit to 1 to erase.

• Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it.
• Address 3FF6H cannot be read and should not be accessed. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FF0H Vacancy Readable Vacancy Readable Oscillation stabilization delay timeVacancy Readable Reset pin output 1: Y es 0: No Clock mode selection 1: Dual clock 0: Single clock Power-on reset 1: Y es 0: No 3FF1 H P07 Pull-up 1: No 0: Y es P06 Pull-up 1: No 0: Y es P05 Pull-up 1: No 0: Y es P04 Pull-up 1: No 0: Y es P03 Pull-up 1: No 0: Y es P02 Pull-up 1: No 0: Y es P01 Pull-up 1: No 0: Y es P00 Pull-up 1: No 0: Y es 3FF2H P17 Pull-up 1: No 0: Y es P16 Pull-up 1: No 0: Y es P15 Pull-up 1: No 0: Y es P14 Pull-up 1: No 0: Y es P13 Pull-up 1: No 0: Y es P12 Pull-up 1: No 0: Y es P11 Pull-up 1: No 0: Y es P10 Pull-up 1: No 0: Y es 3FF3 H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable 3FF4H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable 3FF5H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable WTM1 WTM0 See “■ Mask Options”

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter T o program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 3. Memory Space Memory space in each mode is diagrammed below. 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH . (3) Program to 4000H to 7FFFH with the EPROM programmer. Package Adapter socket part number LCC-32(Rectangle) ROM-32LC-28DP-YG LCC-32(Square) ROM-32LC-28DP-S 0000H 4000H Not available EPROM 16KB 7FFF H I/O RAM Not available Not available PROM 16KB 0000H 0080H 0180H 8000H C000 H FFFF H Normal operating mode Corresponding address in ROM programmer

■ BLOCK DIAGRAM Main clock oscillator Clock controller Subclock oscillator (32.768 kHz) 21-bit time-base timer External interrupt 2 (wake-up function) CMOS I/O port N-ch open-drain output port (Only P30 for CMOS output port) Port 0 F 2MC-8L RAM (256 × 8 bits max.) MODA V CC V SS Other pins X0A X1A RST P00/INT20 to P07/INT27 ROM (8 K × 8 bits max.) 8-bit timer/counter 8-bit serial I/O Buzzer output N-ch open-drain I/O port P26 *2 P21 *2 P25/SCK P24/SO P23/SI P27 * 2 /BUZ P14 to P17 Internal bus Remote control transmission output Reset circuit CPU 8-bit timer/counter CMOS I/O port External interrupt 1 (wake-up function) N-ch open-drain output port 8 8 P22/TO P20/EC P10/INT10 to P13/INT13 SEG28 to SEG31 *1 (Also serve as P14 to P17.) SEG24 to SEG27 *1 (Also serve as P10 to P13.) SEG0 to SEG7 COM0, COM1 COM2 (Also serves as P31.) COM3 (Also serves as P32.) V1 to V3 P57/SEG23 * to P54/SEG20 *1 P53/SEG19 *1 to P50/SEG16 *1 P47/SEG15 *1 to P44/SEG12 *1 P43/SEG11 *1 to P40/SEG8 *1 LCD controller/driver P30/RCO P31/COM2 P32/COM3 MODA V CC V SS *1: The segment or port function is selected by the mask option. *2: N-ch open-drain heavy-current drive type 32 × 4 bits VRAM Port 3 Port 2Port 1Port 4 and port 5

■ CPU CORE 1. Memory Space The microcontrollers of the MB89180 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89180 series is structured as illustrated below. Memory Space 0000H 0080H 0100H 0200H 0280H 8000H MB89PV180 I/O RAM 512 B Register Unused External ROM 32 KB 0000H 0080H 0100H 0140H F000H FFFF H MB89181 I/O RAM 128 B Register ROM 4 KB 0000H 0080H 0100H 0180H E800H FFFF H MB89182 I/O Register ROM 6KB 0000H 0080H 0100H 0180H E000H FFFF H MB89183 I/O RAM 256 B RAM 256 B Register ROM 8 KB 0000H 0080H 0100H 0180H C000 H FFFF H MB89P185 I/O RAM 256 B Register ROM 16 KB FFFF H Unused Unused Unused Unused Unused 00C0 H

1. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. T emporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) PC A T IX EP SP PS 16 bits : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFD H Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. Initial value Structure of the Program Status Register Vacancy Vacancy Vacancy H I IL1, 0 N Z VC RPPS 1 0 9876 321015 14 13 12 11 RP CCR

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. IL1 IL0 Interrupt level High-low High Low = no interrupt 10 2 11 3 Rule for Conversion of Actual Addresses of the General-purpose Register Area “0” A15 “0” A14 “0” A13 “0” A12 “0” A11 “0” A10 “0” “1” RP Generated addresses Lower OP codes

The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 8 banks can be used on the MB89181 (RAM 128 × 8 bits) and a total of 16 banks can be used on the MB89182/183 (RAM 256 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 This address = 0100H + 8 × (RP) Memory area 8 banks (MB89181) 16 banks (MB89182/183)

■ I/O MAP (Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) DDR2 Port 2 data direction register 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0C H (R/W) PDR3 Port 3 data register 0D H Vacancy 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) PDR5 Port 5 data register 10H (R/W) BZCR Buzzer register 11H Vacancy 12H Vacancy 13H Vacancy 14H (R/W) RCR1 Remote control transmission control register 1 15H (R/W) RCR2 Remote control transmission control register 2 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR1 Serial mode register 1D H (R/W) SDR1 Serial mode register 1EH to 2FH Vacancy

(Continued) Note: Do not use vacancies. Address Read/write Register name Register description 30H (R/W) EIE1 External interrupt 1 enable register 31H (R/W) EIF1 External interrupt 1 flag register 32H (R/W) EIE2 External interrupt 2 enable register 33H (R/W) EIF2 External interrupt 2 flag register 34H to 5FH Vacancy 60H to 6FH (R/W) VRAM Display data RAM 70H to 71H Vacancy 72H (R/W) LCR1 LCD controller/driver control register 1 73H to 7BH Vacancy 7C H (W) ILR1 Interrupt level setting register 1 7D H (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy

■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) (Continued) Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC VSS – 0.3 V SS + 7.0 V LCD power supply voltage V1 to V3 V SS – 0.3 V SS + 7.0 V V1 to V3 must not exceed VCC . Input voltage VI1 VSS – 0.3 V CC + 0.3 V VI1 must not exceed Vss + 7.0 V. Except P20 to P27 without a pull- up resistor VI2 VSS – 0.3 V SS + 7.0 V P20 to P27 without a pull-up resistor Output voltage VO1 VSS – 0.3 V CC + 0.3 V VO1 must not exceed Vss + 7.0 V. Except P20 to P27, P40 to P47, and P50 to P57 without a pull-up resistor V O2 VSS – 0.3 V SS + 7.0 V P20 to P27, P40 to P47, and P50 to P57 without a pull-up resistor “L” level output current IOL1  10 mA Except P21, P26, P27, and power supply pins IOL2  20 mA P21, P26, and P27 “L” level average output current IOLAV1  4m A Average value (operating current × operating rate) Except P21, P26, P27, and power supply pins I OLAV2  8m A Average value (operating current × operating rate) P21, P26, and P27 “L” level total output current∑ IOL  80 mA “L” level total average output current ∑ IOLAV  40 mA Average value (operating current × operating rate) “H” level output current IOH1  –5 mA Except P30 and power supply pins IOH2  –10 mA P30

(Continued) (VSS = 0.0 V) Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Recommended Operating Conditions (VSS = 0.0 V) *1: The minimum operating power supply voltage varies with the operating frequency and execution time (instruction cycle). *2: The liquid-crystal power supply range and optimum value vary depending on the characteristics of the liquid- crystal display element used. Parameter Symbol Value Unit Remarks Min. Max. “H” level average output current IOHAV1  –2 mA Average value (operating current × operating rate) Except P30 and power supply pins IOHAV2  –4 mA Average value (operating current × operating rate) P30 “H” level total output current∑ IOH  –20 mA “H” level total average output current ∑ IOHAV  –10 mA Average value (operating current × operating rate) Power consumption P D  300 mW Operating temperature T A –40 +85 °C Storage temperature Tstg –55 +150 °C Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC 2.2*1 6.0 V Guaranteed normal operation range, applicable to the mask ROM products 2.7*1 6.0 V MB89P185/PV180 1.5 6.0 V RAM data holding assurance range in stop mode Power supply voltage for LCD V1 to V3 V SS VCC *2 V V1 to V3 pins Operating temperature T A –40 +85 °C

Figure 1 Operating Voltage vs. Main Clock Operating Frequency 23 4 4.0 2.0 0.8 10 5 1.0 Operation assurance range Operating voltage (V) Main clock operating frequency (MHz) Note: The shaded area is assured only for the MB89181/182/183. Minimum execution time (instruction cycle) (µs)

1. DC Characteristics (VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) (Continued) Parameter Symbol Pin Condition Value Unit RemarksMin. Typ. Max. “H” level input voltage VIH P00 to P07, P10 to P17, P20 to P27 0.7 V CC — VCC +

0.3 V CMOS

RST , MODA, EC, SI, SCK, INT10 to INT13, INT20 to INT27

0.8 VCC — VCC +

0.3 V Hysteresis

“L” level input voltage VIL P00 to P07, P10 to P17, P20 to P27 V SS – 0.3 — 0.3 V CC V CMOS input VILS RST , MODA, EC, SI, SCK, INT10 to INT13, INT20 to INT27 V SS – 0.3 — 0.2 V CC V Hysteresis input Open-drain output pin application voltage VD P20 to P27, P40 to P47, P50 to P57 V SS – 0.3 — VSS +

6.0 V Without pull-

“H” level output voltage VOH1 P00 to P07, P10 to P17 IOH = –2.0 mA 2.4 — — V VOH2 P30 I OH = –6.0 mA 4.0 — — V “L” level output voltage VOL P00 to P07, P10 to P17, P20, P22 to P25, P30 to P32, P40 to P47, P50 to P57 IOL = +1.8 mA — — 0.4 V VOL2 P21, P26, P27 IOL = +8.0 mA — — 0.4 V VOL3 RST IOL = +4.0 mA — — 0.4 V Input leakage current (Hi-z output leakagecurrent) ILI1 MODA, P00to P07, P10 to P17, P30 to P32

0.0 V < V

I < VCC —— ±5 µA Without pull- up resistor ILI2 P20 to P27, P40 to P47, P50 to P57 I < 6 V — — ±1 µA Without pull- up resistor Pull-up resistance R PULL P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, RST VI = 0.0 V 25 50 100 k Ω Without pull- up resistor Common output impedance RVCOM COM0 to COM3 V1 to V3 = 5.0 V —— 2 . 5 k Ω Segment output impedance RVSEG SEG0 to SEG31 V1 to V3 = 5.0 V — — 15 k Ω

(Continued) (VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) *1: The measurement conditions of power supply current are as follows: the external clock, open output pins, and the external LCD dividing resistor. In the case of the MB89PV180, the current consumed by the connected EPROM and ICE is not included. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note: For pins which serve as the segment (SEG8 to SEG31) and ports (P10 to P17, P40 to P47, and P50 to P57), see the port parameter when these pins are used as ports and the segment parameter when they are used as segment pins. Parameter Symbol Pin Condition Value Unit RemarksMin. Typ. Max. LCD divided resistor valueR LCD — Between VCC and VSS 300 500 750 k Ω LCD controller/ driver leakage current I LCDL V1 to V3, COM0 to COM3, SEG0 to SEG31 —— — ±1 µA Power supply current*2 ICC1 VCC FCH = 4.2 MHz VCC = 5.0 V tinst*2 = 0.95 µs

• Main clock operation mode — 3.0 4.5 mA MB89181/ 182/183/ PV180 — 3.8 6.0 mA MB89P185 I CC2 FCH = 4.2 MHz VCC = 3.0 V tinst*2 = 15.2 µs
• Main clock operation mode — 0.25 0.4 mA MB89181/ 182/183/ PV180 — 0.85 1.4 mA MB89P185 I CCL FCL = 32.768 kHz VCC = 3.0 V tinst*2 = 61 µs
• Subclock operation mode — 0.05 0.1 mA MB89181/ 182/183/ PV180 — 0.65 1.1 mA MB89P185 ICCS1 FCH = 4.2 MHz VCC = 5.0 V tinst*2 = 0.95 µs
• Main clock sleep mode — 0.8 1.2 mA ICCS2 FCH = 4.2 MHz VCC = 3.0 V tinst*2 = 15.2 µs
• Main clock sleep mode — 0.2 0.3 mA ICCSL FCL = 32.768 kHz VCC = 3.0 V tinst*2 = 61 µs
• Subclock mode —2 55 0 µA ICCT FCL = 32.768 kHz VCC = 3.0 V
• Watch mode —1 01 5 µA ICCH TA = +25°C VCC = 5.0 V
• Stop mode —0 . 1 1 µA MB89181/ —0 . 11 0 µA MB89PV18 0/P185 Input capacitanceC IN Other VCC and VSS f = 1 MHz — 10 — pF

1. AC Characteristics (1) Reset Timing (VSS = 0.0 V , TA = –40°C to +85°C) (2) Power-on Reset (VSS = 0.0 V , TA = –40°C to +85°C) Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. Parameter Symbol Condition Value Unit Remarks Min. Max. RST “L” pulse width t ZLZH — 48 t HCYL —n s Parameter Symbol Condition Value Unit Remarks Min. Max. Power supply rising time tR — 50 ms Power-on reset function only Power supply cut-off time tOFF 1 — ms Due to repeated operations 0.2 VCC 0.2 VCC RST tZLZH 0.2 V 0.2 V 2.0 V 0.2 V tR VCC tOFF

(3) Clock Timing (VSS = 0.0 V , TA = –40°C to +85°C) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. Clock frequency FCH X0, X1 1 — 4.2 MHz Main clock FCL X0A, X1A — 32.768 — kHz Subclock Clock cycle time tHCYL X0, X1 238 — 1000 ns Main clock tLCYL X0A, X1A — 30.5 — µs Subclock Input clock pulse width PWH PWL X0 20 — — ns External clockPWHL PWLL X0A — 15.2 — µs Input clock pulse rising/ falling time tCR tCF X0, X0A — — 10 ns X0 X1 X0 X1 C 1 C 2 FCH Open X0 X1 C FCH R 1 When crystal or ceramic resonator is used When an external clock is used When CR oscillation option is used tCF FCH tHCYL

0.8 VCC

0.2 VCC

X0 and X1 Timing and Conditions Main clock Conditions

(4) Instruction Cycle Parameter Symbol Value (typical) Unit Remarks Instruction cycle (minimum execution time)tinst 4/FCH , 8/FCH , 16/FCH , 64/FCH µs (4/FCH ) tinst = 0.95 µs when operating at FCH = 4.2 MHz 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz X0A X1A C 1 C 2 FCL Open X0A X1A When crystal or ceramic resonator is used When single-clock option is used R 2 X0A X1A FCL Open When an external clock is used tCF tLCYL X0A and X1A Timing and Conditions Subclock Conditions

(5) Serial I/O Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Condition Value Unit Remarks Min. Max. Serial clock cycle time t SCYC SCK Internal shift clock mode 2 tinst*— µs SCK ↓ → SO time t SLOV SCK, SO –200 200 ns Valid SI → SCK ↑ tIVSH SI, SCK 0.5 t inst*— µs SCK ↑ → valid SI hold time tSHIX SCK, SI 0.5 t inst*— µs Serial clock “H” pulse width tSHSL SCK External shift clock mode 1 tinst*— µs Serial clock “L” pulse width tSLSH SCK 1 t inst*— µs SCK ↓ → SO time t SLOV SCK, SO 0 200 ns Valid SI → SCK ↑ tIVSH SI, SCK 0.5 t inst*— µs SCK ↑ → valid SI hold time tSHIX SCK, SI 0.5 t inst*— µs Internal Shift Clock Mode External Shift Clock Mode tSCYC tSLOV

0.2 V cc

0.8 V cc

SI 0.2 V cc 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V tSLSH tSLOV SI 0.2 VCC 0.8 V 2.4 V

(6) Peripheral Input Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Value Unit Remarks Min. Max. Peripheral input “H” pulse width 1 tILIH1 INT10 to INT13, EC 1 t inst*— µs Peripheral input “L” pulse width 1 tIHIL1 INT10 to INT13, EC 1 t inst*— µs Peripheral input “H” pulse width 2 tILIH2 INT20 to INT27 2 t inst*— µs Peripheral input “L” pulse width 2 tIHIL2 INT20 to INT27 2 t inst*— µs INT10 to INT13, EC 0.2 VCC tILIH1

■ EXAMPLE CHARACTERISTICS 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 V IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC vs. VOH2 vs. IOH VCC vs. VOH2 (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 V IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC vs.VOH1 vs. IOH VCC vs. VOH1 (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 4 8 12 16 20 VCC = 2.0 V IOL (mA) VCC = 2.5 VVCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 2 6 10 14 18 TA = +25°C VOL2 vs.IOL VOL2 (V) (1) “L” level Output Voltage (2) “H” level Output Voltage 0.6 0.5 0.4 0.3 0.2 0.1 I OL (mA) 2468 1 0 VCC = 2.0 V V CC = 3.0 V 13579 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V TA = +25°C VOL1 (V) VOL1 vs. IOL

(Continued) (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) (5) Power Supply Current (External Clock) 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V CC (V) TA = +25°C VIN vs. VCC VIN (V) 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VIHS VILS VCC (V) TA = +25°C VIN vs. VCC VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 01234567 V CC (V) ICC1 vs. VCC (Mask ROM products) FCH = 3 MHz FCH = 4.2 MHz FCH = 1 MHz TA = +25°C ICC1 (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 01234567 V CC (V) ICC2 vs. VCC (Mask ROM products) FCH = 3 MHz FCH = 4.2 MHz FCH = 1 MHz TA = +25°C ICC2 (mA) VIHS: Threshold when input voltage in hysteresis VILS: Threshold when input voltage in hysteresis characteristics is set to “H” level characteristics is set to “L” level

(Continued) (Continued) 1.2 0 1234567 VCC (V) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ICCS1 vs. VCC TA = +25°C ICCS1 (mA) FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1234567 V CC (V) ICCS2 vs. VCC FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz TA = +25°C ICCS2 (mA) 200 180 160 140 120 100 0 1234567 V CC (V) ICCL vs. VCC (Mask ROM units) FCL = 32.768 kHz TA = +25°C ICCL (µA) 1234567 V CC (V) ICCT vs. VCC FCL = 32.768 kHz TA = +25°C ICCT (µA)

(Continued) (6) Pull-up Resistance Value 200 180 160 140 120 100 0 1234567 V CC (V) ICCSL vs. VCC FCL = 32.768 kHz TA = +25°C ICCSL (µA) 1234567 1,000 VCC (V) 500 100 TA = +25°C TA = +85°C TA = –40°C R PULL (kΩ ) R PULL vs. VCC

■ INSTRUCTIONS Execution instructions can be divided into the following four groups:

• T ransfer
• Arithmetic operation
• Branch
• Others T able 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols (Continued) Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T T emporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits)

(Continued) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: “–” indicates no change.

• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction is executed.
• 00 becomes 00. N, Z, V , C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F . Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ( × ) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Table 2 Transfer Instructions (48 instructions) Notes:• During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 48 to 4F 08 to 0F 88 to 8F A8 to AF A0 to A7

Table 3 Arithmetic Operation Instructions (62 instructions) (Continued) Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) dL dH dH dH dH dH dH dH dH + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + – – – – – – – – – + + – – + + + – – – – – – – – – + + – – – – – – – – – – + + R – + + R – + + R – + + + + + + + + + + – + + + – + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – 28 to 2F 38 to 3F C8 to CF D8 to DF 18 to 1F 58 to 5F A C AC

(Continued) Table 4 Branch Instructions (17 instructions) Table 5 Other Instructions (9 instructions) Mnemonic ~ # Operation TL TH AH N Z V C OP code AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + + + + + + + + + + + + + + + – – – – – – – – 68 to 6F 78 to 7F 98 to 9F Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call Return from subrountine Return form interrupt dH – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + – – – + – – – – – – – – – – – – – – – – – – – – – – – – – – Restore FD FC FB FA FF FE B0 to B7 B8 to BF E8 to EF Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI dH – – – – – – – – – – – – – – – – – – – – – – – R – – – S – – – – – – – –

■ INSTRUCTION MAP 0123456789A B C D EF

0 NOP SWAP RET RETI PUSHW

A POPW A MOV A,ext MOVW A,PS CLRI SETI CLRB dir: 0 BBC dir: 0,rel INCW A DECW A JMP MOVW A,PC 1M U L U A DIVU A JMP addr16 CALL addr16 PUSHW IX POPW IX MOV ext,A MOVW PS,A CLRC SETC CLRB dir: 1 BBC dir: 1,rel INCW SP DECW SP MOVW SP,A MOVW A,SP

2 ROLC

A CMP A ADDC A SUBC A XCH A, T XOR A AND A OR A MOV @A,T MOV A,@A CLRB dir: 2 BBC dir: 2,rel INCW IX DECW IX MOVW IX,A MOVW A,IX

3 RORC

A CMPW A ADDCW A SUBCW A XCHW A, T XORW A ANDW A ORW A MOVW @A,T MOVW A,@A CLRB dir: 3 BBC dir: 3,rel INCW EP DECW EP MOVW EP,A MOVW A,EP 4M O V A,#d8 CMP A,#d8 ADDC A,#d8 SUBC A,#d8 XOR A,#d8 AND A,#d8 OR A,#d8 DAA DAS CLRB dir: 4 BBC dir: 4,rel MOVW A,ext MOVW ext,A MOVW A,#d16 XCHW A,PC 5M O V A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#d8 CMP dir,#d8 CLRB dir: 5 BBC dir: 5,rel MOVW A,dir MOVW dir,A MOVW SP,#d16 XCHW A,SP

6 MOV

A,@IX +d CMP A,@IX +d ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A XOR A,@IX +d AND A,@IX +d OR A,@IX +d MOV @IX +d,#d8 CMP @IX +d,#d8 CLRB dir: 6 BBC dir: 6,rel MOVW A,@IX +d MOVW @IX +d,A MOVW IX,#d16 XCHW A,IX 7M O V A,@EP CMP A,@EP ADDC A,@EP SUBC A,@EP MOV @EP,A XOR A,@EP AND A,@EP OR A,@EP MOV @EP,#d8 CMP @EP,#d8 CLRB dir: 7 BBC dir: 7,rel MOVW A,@EP MOVW @EP,A MOVW EP,#d16 XCHW A,EP 8M O V A,R0 CMP A,R0 ADDC A,R0 SUBC A,R0 MOV R0,A XOR A,R0 AND A,R0 OR A,R0 MOV R0,#d8 CMP R0,#d8 SETB dir: 0 BBS dir: 0,rel INC DEC CALLV BNC rel 9M O V A,R1 CMP A,R1 ADDC A,R1 SUBC A,R1 MOV R1,A XOR A,R1 AND A,R1 OR A,R1 MOV R1,#d8 CMP R1,#d8 SETB dir: 1 BBS dir: 1,rel INC DEC CALLV BC rel AM O V A,R2 CMP A,R2 ADDC A,R2 SUBC A,R2 MOV R2,A XOR A,R2 AND A,R2 OR A,R2 MOV R2,#d8 CMP R2,#d8 SETB dir: 2 BBS dir: 2,rel INC DEC CALLV BP rel BM O V A,R3 CMP A,R3 ADDC A,R3 SUBC A,R3 MOV R3,A XOR A,R3 AND A,R3 OR A,R3 MOV R3,#d8 CMP R3,#d8 SETB dir: 3 BBS dir: 3,rel INC DEC CALLV BN rel CM O V A,R4 CMP A,R4 ADDC A,R4 SUBC A,R4 MOV R4,A XOR A,R4 AND A,R4 OR A,R4 MOV R4,#d8 CMP R4,#d8 SETB dir: 4 BBS dir: 4,rel INC DEC CALLV BNZ rel D MOV A A,R5 CMP A,R5 ADDC A,R5 SUBC A,R5 MOV R5,A XOR A,R5 AND A,R5 OR A,R5 MOV R5,#d8 CMP R5,#d8 SETB dir: 5 BBS dir: 5,rel INC DEC CALLV BZ rel EM O V A,R6 CMP A,R6 ADDC A,R6 SUBC A,R6 MOV R6,A XOR A,R6 AND A,R6 OR A,R6 MOV R6,#d8 CMP R6,#d8 SETB dir: 6 BBS dir: 6,rel INC DEC CALLV BGE rel FM O V A,R7 CMP A,R7 ADDC A,R7 SUBC A,R7 MOV R7,A XOR A,R7 AND A,R7 OR A,R7 MOV R7,#d8 CMP R7,#d8 SETB dir: 7 BBS dir: 7,rel INC DEC CALLV BLT rel

■ MASK OPTIONS No. Part number MB89181/182/183 MB89P185 MB89PV180 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible

1 Pull-up resistors

P00 to P07, P10 to P17 Can be set per pin (P10 to P17 are available only when segment output is not selected.) Can be set per pin (P10 to P17 are available only when segment output is not selected.) Fixed to without pull- up resistor

2 Pull-up resistors

P40 to P47, P50 to P57 Can be set per pin (Available only when segment output is not selected.) Fixed to without pull- up resistor

3 Pull-up resistors

P20 to P27 Can be set per pin Fixed to without pull- up resistor Power-on reset With power-on reset Without power-on reset Selectable Selectable Fixed to with power- on reset Selection of oscillation stabilization delay time The initial value of the main clock oscillation stabilization time is selectable by bit value of WTM1 and WTM0. Selectable WTM1 WTM0 00 : 2 2/FCH 01 : 2 12/FCH 10 : 2 16/FCH 11 : 2 18/FCH Selectable WTM1 WTM0 00 : 2 2/FCH 01 : 2 12/FCH 10 : 2 16/FCH 11 : 2 18/FCH Fixed to oscillation stabilization time of 216/FCH Main clock oscillation type Crystal or ceramic oscillator CR Selectable Crystal or ceramic oscillator Crystal or ceramic oscillator Reset pin output With reset output Without reset output Selectable Selectable With reset output Clock mode selection Dual-clock mode Single-clock mode Selectable Selectable Fixed to dual-clock mode Segment output selection 32 segments:No port selection 28 segments:Selection of P17 to P14 24 segments: Selection of P17 to P10 20 segments:Selection of P17 to P10,and P57 to P54 16 segments:Selection of P17 to P10,and P57 to P50 12 segments:Selection of P17 to P10,P57 to P50, and P47 to P44 8 segments: Selection of P17 to P10,P57 to P50, and P47 to P40 Selectable Selects the number of segments. -101: 32 segments -102: 28 segments -103: 24 segments -104: 20 segments -105: 16 segments -106: 12 segments -107: 8 segments

■ ORDERING INFORMATION Part number Package Remarks MB89181PF MB89182PF MB89183PF MB89P185PF-101 MB89P185PF-102 MB89P185PF-103 MB89P185PF-104 MB89P185PF-105 MB89P185PF-106 MB89P185PF-107 64-pin Plastic QFP (FPT-64P-M06) MB89181FM MB89182FM MB89183FM MB89P185PFM-101 MB89P185PFM-102 MB89P185PFM-103 MB89P185PFM-104 MB89P185PFM-105 MB89P185PFM-106 MB89P185PFM-107 64-pin Plastic QFP (FPT-64P-M09) MB89181PFV MB89182PFV MB89183PFV 64-pin Plastic SQFP (FPT-64P-M03) MB89PV180CF-101 MB89PV180CF-102 MB89PV180CF-103 MB89PV180CF-104 MB89PV180CF-105 MB89PV180CF-106 MB89PV180CF-107 64-pin Ceramic MQFP (MQP-64C-P01)

+0.20 –0.10 +.008 –.004 +0.05 –0.02 +.002 –.001 LEAD No. (STAND OFF) 48 33 161 NOM (.512) REF (.384) 13.009.75 (.012±.004) (.020±.008) (.004±.004) 0.10±0.10 0.50±0.20 0 10° Details of "A" part "A" 1.50 .059 0.127 .005

1 PIN INDEX

0.10(.004) M0.13(.005) Dimensions in mm (inches). n PACKAGE DIMENSIONS 64 pin, Plastic QFP (FPT -64P-M09) "A" LEAD No. 52 32 0.25(.010) 0.30(.012) 51 33 1 19 INDEX TYP (.016±.004) 18.00(.709)REF (STAND OFF) 0.05(.002)MIN 3.35(.132)MAX (.551±.008) 14.00±0.20 (.642±.016) 16.30±0.40 REF 12.00(.472) (.736±.016) 18.70±0.40 (.047±.008) Details of "B" part 1.20±0.20 0 10° Details of "A" part 0.18(.007)MAX 0.63(.025)MAX 0.10(.004) "B" M0.20(.008)

1994 FUJITSU LIMITED F64013S-3C-2C

(Mounting height) 64-pin Plastic QFP (FPT -64P-M06) Dimensions in mm (inches)

C 1995 FUJITSU LIMITED F64009S-2C-5 0.10(.004) .005−.001 +.002 −0.02 +0.05 0.127 .059−.004 +.008 −0.10 +0.20 1.50 "A" 0.50±0.20 (.020±.008) Details of "A" part 0 10˚ 161 INDEX LEAD No. (STAND OFF) 0.50±0.08 +.003 −0.03 +0.08 0.18 11.007.50 (.295) REF (.433) NOM 0.10±0.10 (.004±.004) (Mounting Height) (Continued) 64 pin, PlasticLQFP (FPT -64P-M03) 64-pin Ceramic MQFP (MQP-64C-P01) +0.40 –0.20 +.016 –.008 +0.40 –0.20 +.016 –.008 1.20 .047 12.00(.472)TYP (.039±.010) 1.00±0.25 TYP 18.00(.709) (.039±.010) 1.00±0.25 (.016±.004) 0.40±0.10 1.20 .047(.016±.004) 0.40±0.10 MAX 10.82(.426) (.006±.002) 0.15±0.05 0.50(.020)TYP 11.68(.460)TYP 9.48(.373)TYP 7.62(.300)TYP 0.30(.012)TYP (.050±.005) 1.27±0.13 (.713±.008) 18.12±0.20 TYP 14.22(.560) TYP 12.02(.473) TYP 10.16(.400) TYP 24.70(.972) (.878±.013) 22.30±0.33 (.050±.005) 1.27±0.13 TYP 0.30(.012) INDEX AREA 18.70(.736)TYP (.642±.013) 16.30±0.33 (.613±.008) 15.58±0.20

1994 FUJITSU LIMITED M64004SC-1-3C

Dimensions in mm (inches). Dimensions in mm (inches)

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9703 ª FUJITSU LIMITED Printed in Japan