MB89170

MB89170 FUJITSU | Alldatasheet

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DS07-12518-8EFUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89170/170A/170L Series MB89173/P173/174A/P175A/PV170A MB89173L/174L n DESCRIPTION The MB89170/170A/170L series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such as timers, a serial interface, a DTMF generator, and external interrupts, making it suitable for circuit control such as required in telephones. *: F2MC stands for FUJITSU Flexible Microcontroller. n FEATURES

F 2MC-8L family CPU core
Maximum memory space: 64 Kbytes
Minimum execution time/interrupt processing time MB89170 series: 1.1 ms/10 ms (at 3.58 MHz oscillation) MB89170A/170L series: 0.6 ms/5.4 ms (at 7.16 MHz oscillation)
Dual-clock control system (MB89170/170A series only)
I/O ports: max. 37 ports
21-bit timebase counter
Watch prescaler (MB89170/170A series only)
Watchdog timer
8/16-bit timer/counter: 1 channel (Continued) n PACKAGE 48-pin Plastic QFP (FPT -48P-M16) 48-pin Ceramic MQFP (MQP-48C-P01)

(Continued)

8-bit serial I/O: 1 channel
DTMF generator (MB89170/170A series only) Selectable oscillation frequency (MB89170A series only)
External interrupt 1: 3 channels Three channels are independent and capable of using for wake-up from low-power consumption modes (with an edge detection function).
External interrupt 2 (wake-up): 8 channels Eight channels are independent and capable of using for wake-up from low-power consumption modes (with an “L” level detection function).
Low-power consumption modes(stop mode, sleep mode, watch mode, and subclock mode)
CMOS technology

: Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See “n Electrical Characteristics.”) MB89P173 MB89174A MB89P175A MB89PV170A Classification Mass-produced product (mask ROM product) One-time PROM product (EPROM product) Mass-produced product (mask ROM product) One-time PROM product (EPROM product) Piggyback/ evaluation product (for evaluation and development) ROM size 8 K · 8 bits (internal mask ROM)

8 K · 8 bits

(internal PROM, to be programmed with general- purpose EPROM programmer)

12 K · 8 bits

(internal mask ROM)

16 K · 8 bits

(internal PROM, to be programmed with general- purpose EPROM programmer)

32 K · 8 bits

(external ROM) RAM size 384 · 8 bits 512 · 8 bits 1 K · 8 bits CPU functions The number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 1.1 to 17.6 ms at 3.58 MHz, 61 ms at 32.768 kHz Interrupt processing time: 10 to 160 ms at 3.58 MHz, 562.5 ms at 32.768 kHz Minimum instruction execution time: 0.6 to 9.6 ms at 7.16 MHz, 61 ms at 32.768 kHz Interrupt processing time: Ports Output ports (N-ch open-drain): 5 Output ports (CMOS): 8 I/O ports (CMOS): 24 (16 ports also serve as peripherals.) To t a l : 3 7 8/16-bit timer/ counter 8 bits · 2 ch or 16 bits · 1 ch, capable of rectangular wave output One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 2.2 ms, 35.2 ms, 563.2 ms; when operating at 3.58 MHz) 8-bit serial I/O 8 bits LSB/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 2.2 ms, 8.8 ms, 35.2 ms; when operating at 3.58 MHz) DTMF generator All ITU-T (the old name: CCITT) tones selectable as output Fixed to oscillation frequency(3.58 MHz) All ITU-T (the old name: CCITT) tones selectable as output Selectable oscillation frequency(3.58 MHz or 7.16 MHz) External interrupt 1 3 independent channels (selectable edge, interrupt vector, source flag) Rising/falling/both edges selectable Used also for wake-up from the watch/stop/sleep mode. (Edge detection is also permitted in the watch/stop mode.) External interrupt 2 (wake-up) 8 independent channels (“L” level interrupt) Used also for wake-up from the watch/stop/sleep mode. (Edge detection is also permitted in the watch/stop mode.) Standby mode Sleep mode, stop mode, watch mode, and subclock mode Process CMOS EPROM for use MBM27C256A -20TVM MB89173Item Part number

: Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See “n ELECTRICAL CHARACTERISTICS.”) MB89P174L Classification Mass-produced product (mask ROM product) ROM size 8 K · 8 bits (internal mask ROM)

(internal mask ROM) RAM size 384 · 8 bits 512 · 8 bits CPU functions The number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum instruction execution time: 0.6 to 9.6 ms at 7.16 MHz, Interrupt processing time: 5.4 to 86.4 ms at 7.16 MHz, Ports Output ports (N-ch open-drain): 5 Output ports (CMOS): 8 I/O ports (CMOS): 24 (16 ports also serve as peripherals.) To t a l : 3 7 8/16-bit timer/ counter 8 bits · 2 ch or 16 bits · 1 ch, capable of rectangular wave output One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 2.2 ms, 35.2 ms, 563.2 ms; when operating at 3.58 MHz) 8-bit serial I/O 8 bits LSB/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 2.2 ms, 8.8 ms, 35.2 ms; when operating at 3.58 MHz) DTMF generator ¾ External interrupt 1 3 independent channels (selectable edge, interrupt vector, source flag) Rising/falling/both edges selectable Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in the stop mode.) External interrupt 2 (wake-up) 8 independent channels (“L” level interrupt) Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in the stop mode.) Standby mode Sleep mode, stop mode Process CMOS Operating voltage* 2.2 V to 6.0 V EPROM for use MB89173LItem Part number

n PACKAGE AND CORRESPONDING PRODUCTS : Available · : Not available Note: For more information about each package, see “n Package Dimensions.” n DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. 2. Current Consumption In the case of the MB89PV170A, added is the current consumed by the EPROM which is connected to the top socket. 3. Mask Options Functions that can be selected as options and how to designate these options vary with the product. Before using options, check “n Mask Options.” Take particular care on the following points:

Pull-up resistor option cannot be set for P40 to P44 on the MB89P175A.
Each option is fixed on the MB89PV170A. Package MB89173 MB89P173 MB89174A MB89P175A MB89173L MB89174L MB89PV170A FPT-48P-M16 · MQP-48C-P01 ·

N.C. RST MOD0 MOD1 V CC N.C. N.C. P27 P26 P25 P36/INT2 P37/BZ P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10 P11 P40 P41 P42 P43 P44 V SS P30/SCK P31/SO P32/SI P33/EC P34/TO/INT0 P35/INT1 P24 P23 P22 P21 P20 P17 V SS P16 P15 P14 P13 P12 (TOP VIEW) (FPT-48P-M16) DTMF RST MOD0 MOD1 V CC X0A X1A P27 P26 P25 P36/INT2 P37/BZ P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10 P11 P40 P41 P42 P43 P44 V SS P30/SCK P31/SO P32/SI P33/EC P34/TO/INT0 P35/INT1 P24 P23 P22 P21 P20 P17 V SS P16 P15 P14 P13 P12 (Top view) (FPT-48P-M16) MB89170/170A series MB89170L series

Pin assignment on package top (MB89PV170A only) N.C.: Internally connected. Do not use. Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 49 V PP 57 N.C. 65 O4 73 OE 5 0 A 1 2 5 8A 26 6O 57 4 N . C .

51 A7 59 A1 67 O6 75 A11

52 A6 60 A0 68 O7 76 A9

53 A5 61 O1 69 O8 77 A8

54 A4 62 O2 70 CE

78 A13

55 A3 63 O3 71 A10 79 A14

56 N.C. 64 V SS 72 N.C. 80 V CC DTMF RST MOD0 MOD1 V CC X0A X1A P27 P26 P25 P36/INT2 P37/BZ P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10 P11 P40 P41 P42 P43 P44 V SS P30/SCK P31/SO P32/SI P33/EC P34/TO/INT0 P35/INT1 P24 P23 P22 P21 P20 P17 V SS P16 P15 P14 P13 P12 (Top view) (MQP-48C-P01 )

(Continued)*1: FPT -48P-M16 *2: MQP-48C-P01 Please connect them with GND. Pin no. Pin name Circuit type Function QFP *1 MQFP *2

5 X0 A Main clock crystal oscillator pins

8 X0A B Subclock oscillation pins (32.768 kHz) 9X 1 A

3 MOD0 C Operation mode selecting pins

CC or VSS .4M O D 1 2R S T D Reset I/O pin This pin is of an N-ch open-drain output type with pull-up resistor and of hysteresis input type. “L” is output from this pin by an internal reset source (optional function). The internal circuit is initialized by the input of “L”. 34 to 27 P00/INT20 to P07/INT27 E General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt input is a hysteresis input. 26 to 20, 18 P10 to P17 F General-purpose I/O ports 17 to 10 P20 to P27 H General-purpose output ports

42 P30/SCK G General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O. This port is of hysteresis input type.

41 P31/SO G General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O. This port is of hysteresis input type.

40 P32/SI G General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O. This port is of hysteresis input type.

39 P33/EC G General-purpose I/O port

Also serves as an external clock input for a 8-bit timer/ counter. This port is of hysteresis input type.

38 P34/TO/INT0 G General-purpose I/O port

Also serves as the overflow output for the 8-bit timer/counter and an external interrupt 1 input. This port is of hysteresis input type. 36, P36/INT2, P35/INT1 G General-purpose I/O ports Also serve as an external interrupt 1 input. These ports are of hysteresis input type.

(Continued) *1: FPT -48P-M16 *2: MQP-48C-P01 Pin no. Pin name Circuit type Function QFP *1 MQFP *2

35 P37/BZ G General-purpose I/O port

Also serves as a buzzer output. This port is of hysteresis input type. 48 to 44 P40 to P44 I N-ch open-drain output ports

1 DTMF J DTMF signal output pin

7V CC — Power supply pin 19, 43 V SS — Power supply (GND) pin

External EPROM pins (the MB89PV170A only) * : MQP-48C-P01 Pin no. Pin name I/O Function MQFP *

49 V PP O “H” level output pin

SS O Power supply (GND) pin I Data input pins 70 CE O ROM chip enable pin Outputs “H” during standby.

71 A10 O Address output pin

Outputs “L” at all times. A11 A13 A14 O Address output pins 80 V CC O EPROM power supply pin N.C. — Internally connected pin Be sure to leave them open.

(Continued) Type Circuit Remarks A Main clock

Oscillation feedback resistor of approximately

1 MW /5 V

Oscillation feedback resistor of approximately

4.5 MW /5 V

When single clock mode is selected, the switch is open. C D • Output pull-up resistor (P-ch) of approximately 50 kW /5 V
Hysteresis input E • CMOS output
CMOS input
Hysteresis input
Pull-up resistor optional Standby control signal X1A X0A Standby control signal R P-ch N-ch P-ch N-ch Port Resource P-ch R

(Continued) Type Circuit Remarks F • CMOS output

CMOS input
Pull-up resistor optional G • CMOS output
Hysteresis input
Pull-up resistor optional H • CMOS output I • N-ch open-drain output
Pull-up resistor optional J • DTMF analog output P-ch N-ch P-ch R N-ch P-ch P-ch R P-ch N-ch N-ch P-ch R OPAMP

Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “n Electrical Characteristics” is applied between VCC to VSS . When latchup occurs, power supply current increases rapidly and might thermally damaged elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down registor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although operating is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 6. Turning on the supply voltage (only for the MB89P175A) Power on sharply up to the option enabling voltage (2 V) within 13 clock cycles after starting of oscillation.

n PROGRAMMING TO THE EPROM ON THE MB89P173 AND MB89P175A The MB89P173 is an OTPROM (one-time PROM) versions of the MB89170/170L series, and the MB89P175A is of the MB89170A/170L series. 1. Features

8-Kbyte (MB89P173), 16-Kbyte (MB89P175A) PROM on chip
Options can be set using the EPROM programmer (MB89P175A only).
Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 8-Kbyte PROM,16-Kbyte PROM and option area is diagrammed below. PROM 8 KB FFFF H 8000 H E000 H Not available 0200 H 0080 H 0000 H Not available RAM I/O 7FFF H 0000 H

6000 H PROM

(Corresponding addresses on the EPROM programmer) MB89P175A Single chip EPROM mode (Corresponding addresses on the EPROM programmer) Vacancy (Read value FF H) Vacancy (Read value FF H) Vacancy (Read value FF H) EPROM 8 KB EPROM 16 KB Address Address

Programming to the EPROM In EPROM mode, the MB89P173 and MB89P175A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter.

Programming procedure (MB89P173) (1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to 0FFFFH while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode). (3) Program the data to the EPROM with the EPROM programmer.
Programming procedure (MB89P175A) (1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to 0FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF6H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options (MB89P175A Only).”) (3) Program the data to the EPROM with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. 5. Programming Yield Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Part number Package Compatible socket adapter Sun Hayato Co., Ltd. MB89P175A QFP-48P ROM-48QF-28DP-8L Program, verify Aging + 150°C, 48 Hrs. Data verification Assembly

Setting OTPROM Options (MB89P175A Only) The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map:

OTPROM option bit map Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is selected. Addre ss Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FF0H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Clock mode select 1: 1 clock 0: 2 clocks Reset pin output 1: Y es 0: No Power-on reset 1: Y es 0: No Oscillation stabilization time 00 2 3/FCH 10 2 16/FCH 01 212/FCH 11 2 18/FCH 3FF1H P07 Pull-up 1: Y es 0: No P06 Pull-up 1: Y es 0: No P05 Pull-up 1: Y es 0: No P04 Pull-up 1: Y es 0: No P03 Pull-up 1: Y es 0: No P02 Pull-up 1: Y es 0: No P01 Pull-up 1: Y es 0: No P00 Pull-up 1: Y es 0: No 3FF2H P17 Pull-up 1: Y es 0: No P16 Pull-up 1: Y es 0: No P15 Pull-up 1: Y es 0: No P14 Pull-up 1: Y es 0: No P13 Pull-up 1: Y es 0: No P12 Pull-up 1: Y es 0: No P11 Pull-up 1: Y es 0: No P10 Pull-up 1: Y es 0: No 3FF3 H P37 Pull-up 1: Y es 0: No P36 Pull-up 1: Y es 0: No P35 Pull-up 1: Y es 0: No P34 Pull-up 1: Y es 0: No P33 Pull-up 1: Y es 0: No P32 Pull-up 1: Y es 0: No P31 Pull-up 1: Y es 0: No P30 Pull-up 1: Y es 0: No 3FF4 H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 3FF5H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 3FF6H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable

n PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter T o program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 3. Memory Space Memory space in each mode, such as 32-Kbyte EPROM, is diagrammed below. 4. Programming to the EPROM (1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH . (3) Program with the EPROM programmer. Package Socket adapter part number LCC-32(Square) ROM-32LC-28DP-S PROM 32 KB FFFF H 8000 H 0480 H 0080 H 0000 H Not available RAM I/O EPROM 32 KB 7FFF H 0000 H Single chip Corresponding address on the EPROM programmerAddress

MB89170/170A series Main clock oscillator Subclock oscillator Timebase timer External interrupt 2 (wake-up) CMOS I/O ports CMOS output port Port 0 and Port 1 F2MC-8L RAM MOD1, MOD0, V CC , VSS · 2 The other pins RST P00/INT20 to P07/INT27 ROM 8-bit serial I/O Buzzer output N-ch open-drain output port P30/SCK P34/TO/INT0 Internal bus Reset circuit CPU 8-bit timer/counter CMOS I/O port P20 to P27 DTMF generator P10 to P17 Port 3 Watch prescalar

8 External interrupt 1

MB89170L series Main clock oscillator Timebase timer External interrupt 2 (wake-up) CMOS I/O ports CMOS output port Port 0 and Port 1 F2MC-8L RAM MOD1, MOD0, V CC , VSS · 2, N.C. · 2 The other pins RST P00/INT20 to P07/INT27 ROM 8-bit serial I/O Buzzer output N-ch open-drain output port P30/SCK P34/TO/INT0 Internal bus CPU 8-bit timer/counter CMOS I/O port P20 to P27 P10 to P17 Port 3 Reset circuit (Watch dog timer)

Memory Space The microcontrollers of the MB89170/170A/170L series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the program area. The memory space of the MB89170/170A/170L series is structured as illustrated below. External ROM 32 KB RAM 1 KB I/O 0000 H FFFF H Register Not available 0080 H 0100 H 0200 H 0480 H 8000 H ROM 16 KB RAM 512 B I/O 0000 H FFFF H Register 0080 H 0100 H 0200 H C000 H ROM 12 KB RAM 512 B I/O 0000 H FFFF H Register Not available 0080 H 0100 H 0200 H 0280 H D000 H ROM 8 KB RAM 384 B I/O 0000 H FFFF H Register Not available 0080 H 0100 H 0200 H E000 H 0280 H MB89PV170A MB89P175A MB89174A MB89174L MB89P173 MB89173L MB89173 Not available Memory Space

Registers The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose memory registers. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating the instruction storage positions Accumulator (A): A 16-bit temporary register for arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. T emporary accumulator (T): A 16-bit register which is used for arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit pointer for indicating a stack area Progam status (PS) : A 16-bit register for storing a register pointer, a condition code The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) PC A T IX EP SP PS 16 bits : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFD H Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. Initial value Structure of the Program Status Register Vacancy H I IL1, 0 N Z VC RPPS 1 0 9876 321015 14 13 12 11 RP CCR Vacancy Vacancy

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise. Z-flag: Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. IL1 IL0 Interrupt level High-low High Low 10 2 11 3 Rule for Conversion of Actual Addresses of the General-purpose Register Area “0” ﬂ A15 “0” ﬂ A14 “0” ﬂ A13 “0” ﬂ A12 “0” ﬂ A11 “0” ﬂ A10 “0” ﬂ “1” ﬂ ﬂ ﬂ ﬂ ﬂ ﬂ ﬂ ﬂ ﬂ Lower OP codesRP Generated addresses

The following general-purpose registers are provided: General-purpose register: An 8-bit register for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89170/170A/170L series . The bank currently in use is indicated by the register bank pointer(RP). Register Bank Configuraiton R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 This address = 0100 H + 8 · (RP) Memor y area 32 banks}

MB89170/170A series (Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog control register 0AH (R/W) TBTC Timebase timer control register 0BH (R/W) WPCR Watch prescaler control register 0C H (R/W) PDR3 Port 3 data register 0D H (R/W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H Vacancy 11H Vacancy 12H Vacancy 13H Vacancy 14H Vacancy 15H Vacancy 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR Serial mode register 1D H (R/W) SDR Serial data register 1EH Vacancy 1FH Vacancy

(Continued) * R/W: Readable and writable R: Read only W: Write only Note: Do not use vacancies. Address Read/write * Register name Register description H (R/W) DTMC DTMF control register 21H (R/W) DTMD DTMF data register 22H Vacancy 23H (R/W) EIC1 External interrupt control register 1 24H (R/W) EIC2 External interrupt control register 2 25H to 31H Vacancy 32H (R/W) EIE2 External interrupt 2 enable register 33H (R/W) EIF2 External interrupt 2 flag register 34H to 7BH Vacancy 7C H (W) ILR1 Interrupt level setting register 1 7D H (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy

MB89170L series (Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog control register 0AH (R/W) TBTC Timebase timer control register 0BH Vacancy 0C H (R/W) PDR3 Port 3 data register 0D H (R/W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H Vacancy 11H Vacancy 12H Vacancy 13H Vacancy 14H Vacancy 15H Vacancy 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR Serial mode register 1D H (R/W) SDR Serial data register 1EH Vacancy 1FH Vacancy

(Continued) * R/W: Readable and writable R: Read only W: Write only Note: Do not use vacancies. As for MB89170L series, WPCR register(0B H ), DTMC register(20H ) and DTMD register(21H ) become Vacancy. Address Read/write * Register name Register description 20H Vacancy 21H Vacancy 22H Vacancy 23H (R/W) EIC1 External interrupt control register 1 24H (R/W) EIC2 External interrupt control register 2 25H to 31H Vacancy 32H (R/W) EIE2 External interrupt 2 enable register 33H (R/W) EIF2 External interrupt 2 flag register 34H to 7BH Vacancy 7C H (W) ILR1 Interrupt level setting register 1 7D H (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy

n ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC VSS – 0.3 V SS + 7.0 V Input voltage VI VSS – 0.3 V CC + 0.3 V Except P40 to P44 VI2 VSS – 0.3 V CC + 0.3 V P40 to P44 (with pull-up option) VSS – 0.3 V SS + 7.0 V P40 to P44 (without pull-up option) Output voltage VO VSS – 0.3 V CC + 0.3 V Except P40 to P44 VO2 VSS – 0.3 V CC + 0.3 V P40 to P44 (with pull-up option) VSS – 0.3 V SS + 7.0 V P40 to P44 (without pull-up option) “L” level maximum output current IOL ¾ 10 mA “L” level average output current IOLAV ¾ 4m A Average value (operating current · operating rate) “L” level total maximum output current SIOL ¾ 100 mA “L” level total average output current SIOLAV ¾ 20 mA Average value (operating current · operating rate) “H” level maximum output current IOH ¾ –10 mA “H” level average output current IOHAV ¾ –2 mA Average value (operating current · operating rate) “H” level total maximum output current SIOH ¾ –25 mA “H” level total average output current SIOHAV ¾ –10 mA Average value (operating current · operating rate) Power consumption P D ¾ 200 mW Operating temperature T A –40 +85 °C Storage temperature Tstg –55 +150 °C

Recommended Operating Conditions (VSS = 0.0 V) * : These values vary with the operating frequency, instruction cycle, and the assurance range for the DTMF gen- erator. See Figure 1 and “(7) Electrical Characteristics of DTMF Generator” in “4. AC characteristics.” Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC 2.2* 6.0* V Normal operation assurance range* MB89174A/173/174L/173L 2.7* 6.0* V Normal operation assurance range* MB89PV170A/P175A/P173 1.5 6.0 V Retains the RAM state in the stop mode Operating temperature T A –40 +85 °C Assurance range for DTMF generator Operating assurance range Operating voltage (V) Main clock operating frequency (at an instruction cycle of 4/FCH ) (MHz) Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89170A series. Figure 1 Operating Voltage vs. Main Clock Operating Frequency(MB89170/170A series)

DC Characteristics (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) (Continued) Parameter Sym- bol Pin name Condition Value Unit RemarksMin. Typ. Max. “H” level input voltage VIH P00 to P07, P10 to P17

0.7 VCC ¾ VCC +

0.3 V VIHS RST , MOD0, MOD1, P30 to P37, INT20 to INT27

0.8 VCC ¾ VCC +

0.3 V “L” level input voltage VIL P00 to P07, PI0 to PI7 VSS - 0.3 ¾ 0.3 VCC V VILS RST , MOD0, MOD1, P30 to P37, INT20 to INT27 VSS - 0.3 ¾ 0.2 VCC V Open-drain output pin applied voltageVD P40 to P44 VSS - 0.3 ¾ VSS + 6.0 V “H” level output voltage VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 I OH = –2.0 mA 2.4 ¾¾ V “L” level output voltage VOL1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44 I OL = 1.8 mA ¾¾ 0.4 V VOL2 RST IOL = 4.0 mA ¾¾ 0.6 V Input leakage current (Hi-z output leakage current) I LI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44, MOD0, MOD1

0.0 V < V

I < VCC ¾¾– 5 mA Without pull- up resistor Pull-up resistance RPULL P00 to P07, P10 to P17, P30 to P37, P40 to P44, RST VI = 0.0 V 25 50 100 k W With pull-up resistor

(Continued) (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) * : The power supply current is measured at the external clock. Parameter Symbol Pin name Condition Value Unit Remarks Min. Typ. Max. Power supply voltage* ICC VCC (when DTMF is not operating) VCC = 5.0 V FCH = 3.58 MHz

Main clock operation mode
Highest gear speed —3 . 5 8 m A MB89173/ 174A/173L/ 174L —6 . 51 0 m A MB89P173/ P175A I CCS1 VCC = 5.0 V FCH = 3.58 MHz
Main clock sleep mode
Highest gear speed —2 5 m A ICCS2 VCC = 3.0 V FCL = 32.768 kHz
Subclock sleep mode —2 55 0 mA I CCH TA = +25°C
Subclock stop mode
Main clock stop mode in single clock system —— 1 mA I CSB VCC = 3.0 V FCL = 32.768 kHz
Subclock operation mode — 50 100 mA MB89173/ 174A —1 3 m A MB89P173/ P175A I CCT VCC = 3.0 V
Watch mode ——1 5 mA ID VCC (when DTMF is operating) VCC = 5.0 V FCH = 3.58 MHz
Main clock operation mode
Highest gear speed —5 . 51 0 m A MB89173/ 174A —8 . 51 3 m A MB89P173/ P175A Input capacitance C IN Other than VCC , VSS f = 1 MHz — 10 — pF

AC Characteristics (1) Reset Timing (VCC = 5.0 V–10%, VSS = 0.0 V, TA = –40°C to +85°C) (2) Power-on Reset (VSS = 0.0 V, TA = –40°C to +85°C) Note: Make sure that power supply rises within the oscillation stabilization time selected. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. Parameter Symbol Condition Value Unit Remarks Min. Max. RST “L” pulse width t ZLZH — 48 t HCYL —n s Parameter Symbol Condition Value Unit Remarks Min. Max. Power supply rising time tR — 50 ms Power-on reset function only Power supply cut-off time tOFF 1 — ms Due to repeated operations 0.2 VCC 0.2 VCC RST tZLZH 0.2 V 0.2 V 2.0 V VCC 0.2 V tR tOFF

(3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition Value Unit Remarks Min. Typ. Max. Clock frequency FCH X0, X1 1 — 3.58 MHz MB89173/ P173 1 — 7.16 MHz MB89174A/ P175A/ PV170A/ 173L/174L FCL X0A, X1A — 32.768 — kHz Subclock Clock cycle time tHCYL X0, X1 280 — 1000 ns MB89173/ P173 140 — 1000 ns MB89174A/ P175A/ PV170A/ 173L/174L t LCYL X0A, X1A — 30.5 — ms Subclock Input clock pulse width PWH PWL X0 20 — — ns External clock PWHL PWLL X0A — 15.2 — ms External clock Input clock rising/ falling time tCR tCF X0, X0A — — 10 ns External clock When a crystal or ceramic resonator is used When an external clock is used X0 X1 Open X0 X1 tCR

0.8 VCC

0.2 VCC

0.2 VCC 0.2 VCC

Main Clock Timing Condition
Main Clock Configurations

(4) Instruction Cycle Parameter Symbol Value (typical) Unit Remarks Instruction cycle (minimum execution time)tinst 4/FCH , 8/FCH , 16/FCH , 64/FCH ms (4/FC ) tinst = 1.1 ms when operating at FC = 3.58 MHz 2/FCL ms tinst = 61.036 ms when operating at FCL = 32.768 kHz (MB89170/170A series only) X0A tCR 0.2 VCC 0.2 VCC Open X0A X1A When an external clock is used X0A X1A When a crystal or ceramic resonator is used X0A X1A When a single clock option is used

Subclock Timing Condition
Subclock Configurations

(5) Recommend Resonator Manufacturers (6) Serial I/O Timing (VCC = +5.0 V–10%, VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Condition Value Unit Remarks Min. Max. Serial clock cycle time t SCYC SCK Internal shift clock mode 2 tinst*— ms SCK ﬂ ﬁ SO time t SLOV SCK, SO –200 200 ns Valid SI ﬁ SCK tIVSH SI, SCK 0.5 t inst*— ms SCK › ﬁ valid SI hold time tSHIX SCK, SI 0.5 t inst*— ms Serial clock “H” pulse width tSHSL SCK External shift clock mode 1 tinst*— ms Serial clock “L” pulse width tSLSH 1 tinst*— ms SCK ﬂ ﬁ SO time t SLOV SCK, SO 0 200 ns Valid SI ﬁ SCK › tIVSH SI, SCK 0.5 t inst*— ms SCK › ﬁ valid SI hold time tSHIX SCK, SI 0.5 t inst*— ms

Sample Application of Piezoelectric Resonator (FAR Family) X0 X1 FAR *1 C1 *2 C2 *2 *1: Fujitsu Acoustic Resonator Inquiry: FUJITSU LIMITED FAR part number (built-in capacitor type) Frequency (MHz) Initial deviation of FAR frequency (TA = +25°C) Temperature characteristics of FAR frequency (TA = –20°C+60 °C) Loading capacitors*2 FAR-C4 A-03580- 01 3.58 ±0.5% ±0.5% Built-in (MB89170 series only)

0.8 V 2.4 V tSCYC 2.4 V tSLOV 0.8 V 0.8 V tIVSH 2.4 V tSLOV 0.8 V tIVSH

Internal Shift Clock Mode
External Shift Clock Mode

(7) Peripheral Input Timing (VCC = +5.0 V–10%, VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” (8) Electrical Characteristics of DTMF Generator (VSS = 0.0 V, FCH = 3.579545 MHz, TA = –30°C to + 60°C) Parameter Symbol Pin name Value Unit Remarks Min. Max. Peripheral input “H” pulse width 1 tILIH1 EC, INT0 to INT2, INT20 to INT27 2 tinst*— ms Peripheral input “L” pulse width 1 tIHIL1 2 tinst*— ms Parameter Symbol Condition Value Unit Remarks Min. Typ. Max. Operating voltage range —— 3.0 — 6.0 V MB89P173 2.4 — 6.0 V MB89173/174A 2.7 — 6.0 V MB89P175A Output load requirements R O VCC = 4.5 V to 6.0 V 30 — — k W Defined when the DTMF pin is connected to a pull- down resistor for the MB89P173.VCC = 3.0 V to 4.5 V 200 — — k W VCC = 2.4 V to 6 V 30 — — k W Defined when the DTMF pin is connected to a pull- down resistor for the MB89173/174A V CC = 2.7 V to 6 V MB89P175A DTMF output offset voltage (at signal output) VMOF VCC = 5.0 V —2 . 4— V When the DTMF pin is open for MB89P173. —0 . 6— V When the DTMF pin is open for the MB89173/ 174A/P175A. DTMF output amplitude (COL single tone) VMFOC VCC = 5.0 V 450 530 600 mV P-P When DTMF pin is open.DTMF output amplitude (ROW single tone) VMFOR VCC = 5.0 V 350 420 480 mV P-P Difference between COL and ROW levelsR MF — 1.6 2.0 2.4 dB

0.00 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V IN (V) VCC (V) TA = +25°C VIHS : VILS : Threshold when input voltage in hysteresis characteristics is set to “H” level Threshold when input voltage in hysteresis characteristics is set to “L” level VIN vs. VCC 0.00 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V IN (V) VCC (V) TA = +25°C VIN vs. VCC (1) “L” Level Output Voltage (2) “H” Level Output Voltage (3) “H” Level Input Voltage/“L”ow Level Input (4) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) Voltage (Hysteresis Input) VOL (V) VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V IOL (mA ) 0123456789 1 0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.1 VCC = 2.5 V VCC = 2.2 V VCC = 3.0 V TA = +25°C VOL vs. IOL VCC – VOH (V) VCC = 6.0 V VCC = 5.0 V VCC = 4.0 V IOH (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.1 VCC = 2.5 VVCC = 2.2 V 0.0 VCC = 3.0 V TA = +25°C VCC – VOH vs. IOH

(5) Power Supply Current (6) Pull-up Resistance I CC (mA) I CC vs. V CC 1234567 V CC (V) Divide-by-8 F CH = 3.58 MHz T A = +25°C Divide-by-16 Divide-by-64 Divide-by-4 (I CC) I D (mA) I D vs. V CC 1234567 V CC (V) Divide-by-4 (I D)F CH = 3.58 MHz T A = +25°C Divide-by-8 Divide-by-16 Divide-by-64 1234567 1000 R PULL (kW ) VCC (V) 300 100 TA = +25°C R PULL vs. VCC

n INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups:

T ransfer
Arithmetic operation
Branch
O t h e r s T able 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T T emporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very · is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ( · ) Indicates that the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( · )) The address indicated by the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: “–” indicates no change.

dH is the 8 upper bits of operation description data.
AL and AH must become the contents of AL and AH prior to the instruction executed.
00 becomes 00. N, Z, V , C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ‹ This indicates 48, 49, ... 4F .

Table 2 Transfer Instructions (48 instructions) Notes:• During byte transfer to A, T ‹ A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC (dir) ‹ (A) ( (IX) +off ) ‹ (A) (ext) ‹ (A) ( (EP) ) ‹ (A) (Ri) ‹ (A) (A) ‹ d8 (A) ‹ (dir) (A) ‹ ( (IX) +off) (A) ‹ (ext) (A) ‹ ( (A) ) (A) ‹ ( (EP) ) (A) ‹ (Ri) (dir) ‹ d8 ( (IX) +off ) ‹ d8 ( (EP) ) ‹ d8 (Ri) ‹ d8 (dir) ‹ (AH),(dir + 1) ‹ (AL) ( (IX) +off) ‹ (AH), ( (IX) +off + 1) ‹ (AL) (ext) ‹ (AH), (ext + 1) ‹ (AL) (EP) ‹ (A) (A) ‹ d16 (AH) ‹ (dir), (AL) ‹ (dir + 1) (AH) ‹ ( (IX) +off), (AL) ‹ ( (IX) +off + 1) (AH) ‹ (ext), (AL) ‹ (ext + 1) (A) ‹ (EP) (EP) ‹ d16 (IX) ‹ (A) (A) ‹ (IX) (SP) ‹ (A) (A) ‹ (SP) ( (A) ) ‹ (T) (IX) ‹ d16 (A) ‹ (PS) (PS) ‹ (A) (SP) ‹ d16 (AH) « (AL) (dir): b ‹ 1 (dir): b ‹ 0 (AL) « (TL) (A) « (T) (A) « (EP) (A) « (IX) (A) « (SP) (A) ‹ (PC) AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 48 to 4F 08 to 0F 88 to 8F A8 to AF A0 to A7

Table 3 Arithmetic Operation Instructions (62 instructions) (Continued) Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir (A) ‹ (A) + (Ri) + C (A) ‹ (A) + d8 + C (A) ‹ (A) + (dir) + C (A) ‹ (A) + ( (IX) +off) + C (AL) ‹ (AL) + (TL) + C (A) ‹ (A) - (Ri) - C (A) ‹ (A) - d8 - C (A) ‹ (A) - (dir) - C (A) ‹ (A) - ( (IX) +off) - C (AL) ‹ (TL) - (AL) - C (Ri) ‹ (Ri) + 1 (EP) ‹ (EP) + 1 (IX) ‹ (IX) + 1 (A) ‹ (A) + 1 (Ri) ‹ (Ri) - 1 (EP) ‹ (EP) - 1 (IX) ‹ (IX) - 1 (A) ‹ (A) - 1 (A) ‹ (AL) · (TL) (A) ‹ (T) / (AL),MOD ﬁ (T) (A) ‹ (A) Ù (T) (A) ‹ (A) Ú (T) (A) ‹ (A) " (T) (TL) - (AL) (T) - (A) (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ‹ (AL) " (TL) (A) ‹ (AL) " d8 (A) ‹ (AL) " (dir) (A) ‹ (AL) " ( (IX) +off) (A) ‹ (AL) " (Ri) (A) ‹ (AL) Ù (TL) (A) ‹ (AL) Ù d8 (A) ‹ (AL) Ù (dir) dL dH dH dH dH dH dH dH dH + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + – – – – – – – – – + + – – + + + – – – – – – – – – + + – – – – – – – – – – + + R – + + R – + + R – + + + + + + + + + + – + + + – + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – 28 to 2F 38 to 3F C8 to CF D8 to DF 18 to 1F 58 to 5F A C ﬁﬁ AC

(Continued) Table 4 Branch Instructions (17 instructions) Table 5 Other Instructions (9 instructions) Mnemonic ~ # Operation TL TH AH N Z V C OP code AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP (A) ‹ (AL) Ù ( (EP) ) (A) ‹ (AL) Ù ( (IX) +off) (A) ‹ (AL) Ù (Ri) (A) ‹ (AL) Ú (TL) (A) ‹ (AL) Ú d8 (A) ‹ (AL) Ú (dir) (A) ‹ (AL) Ú ( (EP) ) (A) ‹ (AL) Ú ( (IX) +off) (A) ‹ (AL) Ú (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ‹ (SP) + 1 (SP) ‹ (SP) – 1 + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + + + + + + + + + + + + + + + – – – – – – – – 68 to 6F 78 to 7F 98 to 9F Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI If Z = 1 then PC ‹ PC + rel If Z = 0 then PC ‹ PC + rel If C = 1 then PC ‹ PC + rel If C = 0 then PC ‹ PC + rel If N = 1 then PC ‹ PC + rel If N = 0 then PC ‹ PC + rel If V " N = 1 then PC ‹ PC + rel If V " N = 0 then PC ‹ PC + reI If (dir: b) = 0 then PC ‹ PC + rel If (dir: b) = 1 then PC ‹ PC + rel (PC) ‹ (A) (PC) ‹ ext Vector call Subroutine call Return from subrountine Return form interrupt dH – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + – – – + – – – – – – – – – – – – – – – – – – – – – – – – – – Restore FD FC FB FA FF FE B0 to B7 B8 to BF E8 to EF Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI dH – – – – – – – – – – – – – – – – – – – – – – – R – – – S – – – – – – – –

H L 0123456789 ABCDEF

0 NOP SWAP RET RETI PUSHW

A POPW A MOV A,ext MOVW A,PS CLRI SETI CLRB dir: 0 BBC dir: 0,rel INCW A DECW A JMP MOVW A,PC

1 MULU

A DIVU A JMP addr16 CALL addr16 PUSHW IX POPW IX MOV ext,A MOVW PS,A CLRC SETC CLRB dir: 1 BBC dir: 1,rel INCW SP DECW SP MOVW SP ,A MOVW A,SP

2 ROLC

A CMP A ADDC A SUBC A XCH A, T XOR A AND A OR A MOV @A,T MOV A,@A CLRB dir: 2 BBC dir: 2,rel INCW IX DECW IX MOVW IX,A MOVW A,IX

3 RORC

A CMPW A ADDCW A SUBCW A XCHW A, T XORW A ANDW A ORW A MOVW @A,T MOVW A,@A CLRB dir: 3 BBC dir: 3,rel INCW EP DECW EP MOVW EP ,A MOVW A,EP

4 MOV

A,#d8 CMP A,#d8 ADDC A,#d8 SUBC A,#d8 XOR A,#d8 AND A,#d8 OR A,#d8 DAA DAS CLRB dir: 4 BBC dir: 4,rel MOVW A,ext MOVW ext,A MOVW A,#d16 XCHW A,PC

5 MOV

A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#d8 CMP dir,#d8 CLRB dir: 5 BBC dir: 5,rel MOVW A,dir MOVW dir,A MOVW SP ,#d16 XCHW A,SP

6 MOV

A,@IX +d CMP A,@IX +d ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A XOR A,@IX +d AND A,@IX +d OR A,@IX +d MOV @IX +d,#d8 CMP @IX +d,#d8 CLRB dir: 6 BBC dir: 6,rel MOVW A,@IX +d MOVW @IX +d,A MOVW IX,#d16 XCHW A,IX

7 MOV

A,@EP CMP A,@EP ADDC A,@EP SUBC A,@EP MOV @EP ,A XOR A,@EP AND A,@EP OR A,@EP MOV @EP ,#d8 CMP @EP ,#d8 CLRB dir: 7 BBC dir: 7,rel MOVW A,@EP MOVW @EP ,A MOVW EP ,#d16 XCHW A,EP

8 MOV

A,R0 CMP A,R0 ADDC A,R0 SUBC A,R0 MOV R0,A XOR A,R0 AND A,R0 OR A,R0 MOV R0,#d8 CMP R0,#d8 SETB dir: 0 BBS dir: 0,rel INC DEC CALLV BNC rel

9 MOV

A,R1 CMP A,R1 ADDC A,R1 SUBC A,R1 MOV R1,A XOR A,R1 AND A,R1 OR A,R1 MOV R1,#d8 CMP R1,#d8 SETB dir: 1 BBS dir: 1,rel INC DEC CALLV BC rel A MOV A,R2 CMP A,R2 ADDC A,R2 SUBC A,R2 MOV R2,A XOR A,R2 AND A,R2 OR A,R2 MOV R2,#d8 CMP R2,#d8 SETB dir: 2 BBS dir: 2,rel INC DEC CALLV BP rel B MOV A,R3 CMP A,R3 ADDC A,R3 SUBC A,R3 MOV R3,A XOR A,R3 AND A,R3 OR A,R3 MOV R3,#d8 CMP R3,#d8 SETB dir: 3 BBS dir: 3,rel INC DEC CALLV BN rel C MOV A,R4 CMP A,R4 ADDC A,R4 SUBC A,R4 MOV R4,A XOR A,R4 AND A,R4 OR A,R4 MOV R4,#d8 CMP R4,#d8 SETB dir: 4 BBS dir: 4,rel INC DEC CALLV BNZ rel D MOV A,R5 CMP A,R5 ADDC A,R5 SUBC A,R5 MOV R5,A XOR A,R5 AND A,R5 OR A,R5 MOV R5,#d8 CMP R5,#d8 SETB dir: 5 BBS dir: 5,rel INC DEC CALLV BZ rel E MOV A,R6 CMP A,R6 ADDC A,R6 SUBC A,R6 MOV R6,A XOR A,R6 AND A,R6 OR A,R6 MOV R6,#d8 CMP R6,#d8 SETB dir: 6 BBS dir: 6,rel INC DEC CALLV BGE rel F MOV A,R7 CMP A,R7 ADDC A,R7 SUBC A,R7 MOV R7,A XOR A,R7 AND A,R7 OR A,R7 MOV R7,#d8 CMP R7,#d8 SETB dir: 7 BBS dir: 7,rel INC DEC CALLV BLT rel

Note: Reset is input asynchronized with the internal clock whether power-on reset is provided or not. n ORDERING INFORMATION No. Part number MB89173L MB89174L MB89P173 MB89173 MB89174A MB89P173-201 MB89P175A MB89PV170A Specifying procedure Specify when ordering masking Specify when ordering masking Standard option product Set with EPROM programmer Setting not possible Pull-up resistors

P00 to P07, P10 to P17
P30 to P37, P40 to P44 Can be selected per pin Can be selected per pin All ports Fixed to no pull- up resistor Can be set per pin (However, P40 to P44 are available only for no pull-up resistor.) All ports Fixed to no pull-up resistor option Power-on reset
Power-on reset provided
No power-on reset Selectable Selectable Fixed to no power-on reset option Setting possible Fixed to power-on reset option Selection of oscillation stabilization time initial value (when operating at F CH = 3.58 MHz) 3: 218/FCH (approx. 73.2 ms) 2: 216/FCH (approx. 18.3 ms) 1: 212/FCH (approx. 1.1 ms) 0: 23/FCH (approx. 0 ms) Selectable Selectable Fixed to 216/FCH Setting possible Fixed to 218/ FCH Reset pin output
Reset output enabled
Reset output disabled Selectable Selectable Fixed to reset output option Setting possible Fixed to reset output option Clock mode selection
Dual-clock mode
Single-clock mode Fixed to single-clock mode Selectable Fixed to dual- clock mode Setting possible Fixed to dual- clock mode Part number Package Remarks MB89173PF MB89174APF MB89P173PF MB89P175APF MB89173LPF MB89174LPF 48-pin Plastic QFP (FPT-48P-M16) MB89PV170ACF 48-pin Ceramic MQFP (MQP-48C-P01)

C 1994 FUJITSU LIMITED F48026S-1C-1 Details of "A" part 17.20±0.40 0.30±0.06 13.60±0.408.80 (.535±.016)(.346) REF 0.15(.006) INDEX Details of "B" part 121 2536 37 24 1348 0.80(.0315)TYP LEAD No. (.677±.016) SQ SQ "A" 0.15(.006) 0.20(.008) 0.50(.020)MAX 0.15(.006)MAX 0~10° 1.80±0.30 (.071±.012) "B" (STAND OFF) 0.05(.002)MIN .472–.004 +.012 –0.10 +0.30 12.00 .006–.0004 +.002 –0.01 +0.05 0.15 2.70(.106)MAX (Mounting height) Dimensions in mm (inches) 48-pin Plastic QFP (FPT-48P-M16)

C 1994 FUJITSU LIMITED M48001SC-4-2 14.82±0.35 (.583±.014) 15.00±0.25 (.591±.010) 17.20(.677)TYP PIN No.1 INDEX .430–0 +.005 –0.0 +0.13 10.92 1.02±0.13 (.040±.005) TYPTYP 0.30(.012)TYP 4.50(.177)TYP PAD No.1 INDEX 0.15±0.05 (.006±.002) 8.50(.335)MAX 0.60(.024)TYP1.10 +0.45 –0.25 +.018 –.010 .043 0.40±0.08 (.016±.003) 0.80±0.22 (.0315±.0087) 8.80(.346)REF 1.00(.040)TYP 1.50(.059)TYP PIN No.1 INDEX Dimensions in mm (inches) 48-pin Ceramic MQFP (MQP-48C-P01)

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9910 ª FUJITSU LIMITED Printed in Japan

Summary

8-bit Proprietary Microcontroller

Description