MB89161-PF

MB89161 FUJITSU | Alldatasheet

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DS07-12405-2EFUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89160/160A Series MB89161/163/165/P165/PV160/W165 MB89161A/163A/165A n DESCRIPTION The MB89160 series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver, an A/D converter, timers, a serial interface, PWM timers, and external interrupts. n FEATURES

• F 2MC-8L family CPU core
• Dual-clock control system
• Maximum memory size: 16-Kbyte ROM, 512-byte RAM (max.)
• Minimum execution time: 0.95 ms/4.2 MHz
• I/O ports: max. 54 channels
• 21-bit time-base counter
• 8/16-bit timer/counter: 2 or 1 channels
• 8-bit serial I/O: 1 channel
• External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels
• 8-bit A/D converter: 8 channels
• 8-bit PWM timers: 2 channels
• Watch prescaler (15 bits)
• LCD controller/driver: 24 segments · 4 commons (max. 96 pixels)
• LCD driving reference voltage generator and booster (option)
• Remote control transmission output
• Buzzer output
• Power-on reset function (option)
• Low-power consumption modes (stop, sleep, and watch mode)
• C M O S t e c h n o l o g y

(FTP-80P-M05) (FPT-80C-A02) (MQP-80C-P01) 80-pin Ceramic MQFP 80-pin Plastic SQFP 80-pin Ceramic QFP (FTP-80P-M06) (FTP-80P-M11) 80-pin Plastic QFP 80-pin Plastic QFP

(Continued) MB89161/ MB89161A *1 MB89163/ MB89163A *1 MB89165/ MB89165A *1 MB89P165 MB89W165 MB89PV160 Classification Mass production products (mask ROM products) One-time PROM product EPROM product Piggyback/ evaluation product (for development) ROM size 4 K · 8 bits (internal mask ROM)

8 K · 8 bits

(internal mask ROM)

16 K · 8 bits

(internal mask ROM) (internal PROM, programming with general-purpose EPROM programmer)

32 K · 8 bits

(external ROM) RAM size 128 · 8 bits 256 · 8 bits 512 · 8 bits CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8,16 bits Minimum execution time: 0.95 ms/4.2 MHz Interrupt processing time: 9 ms/4.2 MHz Ports I/O port (N-ch open-drain): 8 (6 ports also serve as peripherals, 3 ports are a heavy-current drive type.) Output ports (N-ch open-drain): 28 (16 ports also serve as segment pins, 2 ports serve as booster capacitor connection pins, 2 ports serve as common pins.) (8 ports also serve as an A/D input) I/O ports (CMOS): 16 (12 ports also serve as an external interrupt) Output ports (CMOS): 2 (Also serve as peripherals) T otal: 54 (max.) Timer/counter 8-bit timer operation (toggled output capable, operating clock cycle 1.9 ms to 486 ms) 16-bit timer operation (toggled output capable, operating clock cycle 1.9 ms to 486 ms) Serial I/O 8 bits LSB first/MSB first selectability One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 1.9 ms, 7.6 ms, 30.4 ms) LCD controller/ driver Common output: 4 (max.) Segment output: 24 (max.) Bias power supply pins: 4 LCD display RAM size: 24 · 4 bits Booster for LCD driving: Built-in (product with a booster)*3 Dividing resistor for LCD driving: Built-in (an external resistor selectability) Without a booster for LCD driving A/D converter 8-bit resolution · 8 channels A/D conversion mode (conversion time 43 ms/4.2 MHz (44 instruction cycles)) Sense mode (conversion time 11.9 ms/4.2 MHz) Continuous activation by an internal timer capable Reference voltage input Part number Parameter

(Continued) *1: Products with an internal booster. *2: Varies with conditions such as the operating frequency. (The operating voltage of the A/D converter is assured separately. See section “n Electrical Characteristics.”) *3: See section “n Mask Options.” n PACKAGE AND CORRESPONDING PRODUCTS : Available · : Not available Note: For more information about each package, see section “n Package Dimensions.” MB89161/ MB89161A *1 MB89163/ MB89163A *1 MB89165/ MB89165A *1 MB89P165 MB89W165 MB89PV160 PWM timer 1, PWM timer 2 8 bits · 2 channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.95 ms to 124 ms) 8-bit resolution PWM operation (conversion cycle: 243 ms to 32 s) External interrupt 1 (wake-up function) 4 independent channels (edge selectability) Rising edge/falling edge selectability Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) External interrupt 2 “L” level interrupts · 8 channels Buzzer output 1 (7 frequencies are selectable by the software.) Remote control transmission output 1 (Pulse width and cycle are software selectable.) Standby modes Subclock mode, sleep mode, stop mode, and watch mode Process CMOS Operating voltage*2 2.2 V to 6.0 V (single clock)/ 2.2 V to 4.0 V (dual clock) 2.7 V to 6.0 V EPROM for use — MBM27C256A- 20TV MB89161A MB89163 MB89163A MB89165 MB89165A MB89PW165 MB89W165 MB89PV160 FPT -80P-M05 ·· FPT -80P-M06 ·· FPT -80P-M11 ·· Part number Parameter

n DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points:

• On the MB89161/A and MB89163/A, the upper half of each register bank cannot be used.
• The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption
• In the case of the MB89PV160, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in the sleep/stop modes is the same. (For more information, see section “n Electrical Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “n Mask Options.” Take particular care on the following points:
• A pull-up resistor cannot be set for P20 to P27 on the MB89P165.
• A pull-up resistor is not selectable for P40 to P47 and P60 to P67 if they are used as LCD pins.
• Options are fixed on the MB89PV160.

P46/SEG22* P47/SEG23*7 AV SS AVR AV CC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 V SS P57/AN7 MOD1 MOD0 RST P00/INT20 SEG1 SEG0 P71/COM3* P70/COM2* 8 COM1 COM0 V CC P33* 2/C0*1 P32*2/C1*1 P31/PWM1 P30/RCO/BUZ X1A X0A P27/PWM2* P26*3 P25/SCK P45/SEG21* P44/SEG20*7 P43/SEG19*6 P42/SEG18*6 P41/SEG17*6 P40/SEG16*6 P67/SEG15*5 P66/SEG14*5 P65/SEG13*5 P64/SEG12*5 P63/SEG11*4 P62/SEG10*4 P61/SEG9*4 P60/SEG8*4 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21 P22/TO P23/SI P24/SO (Top view) (FPT-80P-M11) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain heavy-current drive type *4 to *7: Selected using the mask option (in units of 4 pins) *8: Selected using the mask option (in units of 2 pins) Note: For more information on mask option combinations of *4 to *8, see section n Mask Options."

P44/SEG20* P45/SEG21*7 P46/SEG22*7 P47/SEG23*7 AV SS AVR AV CC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 V SS P57/AN7 MOD1 MOD0 RST P00/INT20 P01/INT21 P02/INT22 SEG3 SEG2 SEG1 SEG0 P71/COM3* P70/COM2* 8 COM1 COM0 V CC P33* 2/C0*1 P32*2/C1*1 P31/PWM1 P30/RCO/BUZ X1A X0A P27/PWM2* P26*3 P25/SCK P24/SO P23/SI P43/SEG19* P42/SEG18*6 P41/SEG17*6 P40/SEG16*6 P67/SEG15*5 P66/SEG14*5 P65/SEG13*5 P64/SEG12*5 P63/SEG11*4 P62/SEG10*4 P61/SEG9*4 P60/SEG8*4 SEG7 SEG6 SEG5 SEG4 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21* P22/TO (Top view) (FPT-80P-M06) (FPT-80C-A02) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain heavy-current drive type *4 to *7: Selected using the mask option (in units of 4 pins) *8: Selected using the mask option (in units of 2 pins) Note: For more information on mask option combinations of *4 to *8, see section “n Mask Options.”

P46/SEG22* P47/SEG23*7 AV SS AVR AV CC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 V SS P57/AN7 MOD1 MOD0 RST P00/INT20 SEG1 SEG0 P71/COM3* P70/COM2* 8 COM1 COM0 V CC P33* 2/C0*1 P32*2/C1*1 P31/PWM1 P30/RCO/BUZ X1A X0A P27/PWM2* P26*3 P25/SCK P45/SEG21* P44/SEG20*7 P43/SEG19*6 P42/SEG18*6 P41/SEG17*6 P40/SEG16*6 P67/SEG15*5 P66/SEG14*5 P65/SEG13*5 P64/SEG12*5 P63/SEG11*4 P62/SEG10*4 P61/SEG9*4 P60/SEG8*4 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21* P22/TO P23/SI P24/SO (Top view) (FPT-80P-M05) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain heavy-current drive type *4 to *7: Selected using the mask option (in units of 4 pins) *8: Selected using the mask option (in units of 2 pins) Note: For more information on mask option combinations of *4 to *8, see section “n Mask Options.”

• Pin assignment on package top (MB89PV160 only) N.C.: Internally connected. Do not use. Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE 82 V PP 90 A1 98 O4 106 N.C.

83 A12 91 A0 99 O5 107 A11

84 A7 92 N.C. 100 O6 108 A9

85 A6 93 O1 101 O7 109 A8

86 A5 94 O2 102 O8 110 A13

87 A4 95 O3 103 CE

111 A14

88 A3 96 V SS 104 A10 112 V CC

P44/SEG20* P45/SEG21*7 P46/SEG22*7 P47/SEG23*7 AV SS AVR AV CC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 V SS P57/AN7 MOD1 MOD0 RST P00/INT20 P01/INT21 P02/INT22 SEG3 SEG2 SEG1 SEG0 P71/COM3* P70/COM2* 8 COM1 COM0 V CC P33* 2/C0*1 P32*2/C1*1 P31/PWM1 P30/RCO/BUZ X1A X0A P27/PWM2* P26*3 P25/SCK P24/SO P23/SI P43/SEG19* P42/SEG18*6 P41/SEG17*6 P40/SEG16*6 P67/SEG15*5 P66/SEG14*5 P65/SEG13*5 P64/SEG12*5 P63/SEG11*4 P62/SEG10*4 P61/SEG9*4 P60/SEG8*4 SEG7 SEG6 SEG5 SEG4 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21* P22/TO (Top view) 101 102 103 104 105 106 107 108 109 100 110 111 112 (MQP-80C-P01) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain heavy-current drive type *4 to *7: Selected using the mask option (in units of 4 pins) *8: Selected using the mask option (in units of 2 pins) Note: For more information on mask option combinations of *4 to *8, see section “n Mask Options.”

(Continued)*1: FPT -80P-M05 *2: FPT -80P-M11 *3: MQP-80C-P01 *4: FPT -80P-M06 Pin no. Pin name Circuit type Function SQFP QFP *2 MQFP *3 QFP *4 16 18 X0 A Main clock crystal oscillator pins CR oscillation selectability (mask products only)15 17 X1 18 20 MOD0 C Operating mode selection pins Connect directly to VSS .17 19 MOD1 19 21 RST D Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 20 to 27 22 to 29 P00/INT20 to P07/INT27 E General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. 28 to 31 30 to 33 P10/INT10 to P13/INT13 E General-purpose I/O ports Also serve as an external interrupt 1 input. External interrupt 1 input is hysteresis input. 32 to 35 34 to 37 P14 to P17 F General-purpose I/O ports 36 38 P20/EC H N-ch open-drain general-purpose I/O port Also serves as the external clock input for the timer. The peripheral is a hysteresis input type. 37 39 P21 I N-ch open-drain general-purpose I/O port 38 40 P22/TO I N-ch open-drain general-purpose I/O port Also serves as a timer output. 39 41 P23/SI H N-ch open-drain general-purpose I/O port Also serves as the data input for the serial I/O. The peripheral is a hysteresis input type. 40 42 P24/SO I N-ch open-drain general-purpose I/O port Also serves as the data output for the serial I/O. 41 43 P25/SCK H N-ch open-drain general-purpose I/O port Also serves as the clock I/O for the serial I/O. The peripheral is a hysteresis input type. 42 44 P26 I N-ch open-drain general-purpose I/O port 43 45 P27/PWM2 I N-ch open-drain general-purpose I/O port Also serves as the square wave or PWM wave output for the 8-bit PWM timer 2. 49 51 P33 J Functions as an N-ch open-drain general-purpose output port only in the products without a booster. C0 — Functions as a capacitor connection pin in the products with a booster.

(Continued) *1: FPT -80P-M05 *2: FPT -80P-M11 *3: MQP-80C-P01 *4: FPT -80P-M06 Pin no. Pin name Circuit type Function SQFP QFP *2 MQFP *3 QFP *4 48 50 P32 J Functions as an N-ch open-drain general-purpose output port only in the products without a booster. C1 — Functions as a capacitor connection pin in the products with a booster. 47 49 P31/PWM1 G General-purpose output-only port Also serves as the square wave or PWM wave output for the 8-bit PWM timer 1. 46 48 P30/RCO/BUZ G General-purpose output-only port Also serves as a buzzer output and a remote control transmission frequency output. 14, 12 to 6 16, 14 to 8 P57/AN7 to P50/AN0 L N-ch open-drain general-purpose output ports Also serve as an analog input. 2, 1, 80 to 75 4 to 1 80 to 77 P47/SEG23 to P40/SEG16 J/K N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. Switching between port and segment output is done by the mask option. 74 to 67 76 to 69 P67/SEG15 to P60/SEG8 J/K 66 to 59 68 to 61 SEG7 to SEG0 K LCD controller/driver segment output pins 58, 60, P71/COM3, P70/COM2 J/K N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver common output. Switching between port and common output is done by the mask option. 56, 58, COM1, COM0 K LCD controller/driver common output-only pins 54, 52 to 50 56, 54 to 52 V3, V2 to V0 — LCD driving power supply pins 44 46 X0A B Subclock crystal oscillator pins (32.768 KHz) 45 47 X1A 53 55 V CC — Power supply pin 13 15 V SS — Power supply (GND) pin

57 A V SS — A/D converter power supply pin

Use this pin at the same voltage as VCC . 4 6 AVR — A/D converter reference voltage input pin

35 A V

SS — A/D converter power supply pin Use this pin at the same voltage as VSS .

• External EPROM pins (MB89PV160 only) Pin no. Pin name I/O Function

82 V PP O “H” level output pin

SS O Power supply (GND) pin 100 101 102 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby.

104 A10 O Address output pin

Outputs “L” at all times. 107 108 109 A11 O Address output pins

110 A13 O

111 A14 O

CC O EPROM power supply pin 106 N.C. — Internally connected pins Be sure to leave them open.

(Continued) Type Circuit Remarks A Main clock

• At an oscillation feedback resistor of approximately 1 MW /5.0 V
• CR oscillation is selectable (MB8916X/A only). B Subclock
• At an oscillation feedback resistor of approximately 4.5 MW /5.0 V C D • At an output pull-up resistor of approximately 50 kW /5.0 V
• Hysteresis input E • CMOS I/O
• The peripheral is a hysteresis input type.
• Pull-up resistor optional (Not available on the MB89PV160.) Standby control signal X1A X0A Standby control signal R P-ch N-ch P-ch N-ch Port Peripheral P-ch R

(Continued) (Continued) Type Circuit Remarks F• C M O S I / O

• Pull-up resistor optional (Not available on the MB89PV160) G • CMOS output
• P-ch output is a heavy-current drive type. H • N-ch open-drain I/O
• CMOS input
• The peripheral is a hysteresis input type.
• P21, P26, and P27 are a heavy-current drive type.
• Pull-up resistor optional (Not available on the MB89P165/A, MB89W165/A and MB89PV160) I • N-ch open-drain output
• CMOS input
• Pull-up resistor optional (Not available on the MB89P165/A, MB89W165/A and MB89PV160) J • N-ch open-drain output
• Pull-up resistor optional (Not available on the MB89P165/A, MB89W165/A and MB89PV160)
• P32 and P33 are not provided with a pull-up resistor. P-ch N-ch P-ch R P-ch N-ch Port N-ch Port Peripheral P-ch R Port N-ch P-ch R N-ch P-ch R

(Continued) Type Circuit Remarks K • LCD controller/driver segment output L • N-ch open-drain output

• Analog input
• Pull-up resistor optional (Not available on the MB89PV160) P-ch N-ch P-ch N-ch N-ch P-ch Analog input R P-ch

1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum Ratings” in section “n Electrical Characteristics” is applied between VCC to VSS . When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC ) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pin Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.

n PROGRAMMING TO THE EPROM ON THE MB89P165 The MB89P165 is an OTPROM version of the MB89160 series. 1. Features

• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below. 3. Programming to the EPROM In EPROM mode, the MB89P165 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating area for a single chip is 16 Kbyte (C000H to FFFFH ) the PROM can be programmed as follows:
• Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program into the EPROM programmer at 4000H to 7FFFH . (Note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode.) Load option data into address 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see “8. Setting OTPROM Options.”) (3) Program with the EPROM programmer. 0000H FFFF H I/O RAM Not available PROM 16 KB 3FF6H 7FFF H Not available EPROM 16 KB Single-chip EPROM mode (Corresponding addresses on the EPROM programmer) 0080H 0280H Not available Not available Not available 3FF0H C000 H 4000H Option areaNot available 0000H8000H Address

1. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Adapter Socket 7. Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000 mW/cm 2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000Å. Although erasure time will be much longer than with UV source at 2537Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. Package Compatible adapter socket FPT -80P-M05 ROM-80SQF-28DP-8L FPT -80P-M06 ROM-80QF-28DP-8L3 FPT -80P-M11 ROM-80QF2-28DP-8L2 Program, verify Aging +150°C, 48 Hrs. Data verification Assembly

1. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming value at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map:

• OTPROM option bit map Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FF0H Vacancy Readable Vacancy Readable Vacancy Readable Reset pin output 1: Y es 0: No Clock mode selection 1: Dual clock 0: Single clock Power-on reset 1: Y es 0: No WTM1 WTM0 See section “n Mask Option.” 3FF1H P07 Pull-up 1: No 0: Y es P06 Pull-up 1: No 0: Y es P05 Pull-up 1: No 0: Y es P04 Pull-up 1: No 0: Y es P03 Pull-up 1: No 0: Y es P02 Pull-up 1: No 0: Y es P01 Pull-up 1: No 0: Y es P00 Pull-up 1: No 0: Y es 3FF2H P17 Pull-up 1: No 0: Y es P16 Pull-up 1: No 0: Y es P15 Pull-up 1: No 0: Y es P14 Pull-up 1: No 0: Y es P13 Pull-up 1: No 0: Y es P12 Pull-up 1: No 0: Y es P11 Pull-up 1: No 0: Y es P10 Pull-up 1: No 0: Y es 3FF3H P57 Pull-up 1: No 0: Y es P56 Pull-up 1: No 0: Y es P55 Pull-up 1: No 0: Y es P54 Pull-up 1: No 0: Y es P53 Pull-up 1: No 0: Y es P52 Pull-up 1: No 0: Y es P51 Pull-up 1: No 0: Y es P50 Pull-up 1: No 0: Y es 3FF4H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable 3FF5H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Oscillation stabilization time

n PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter T o program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below. 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH . (3) Program to 0000H to 7FFFH with the EPROM programmer. Package Adapter socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG FFFF H PROM 32 KB 7FFF H EPROM 32 KB Single chip Corresponding addresses on the EPROM programmer 0000H 0080H I/O Not available 8000H 0000H RAM 0280H Address

(32.768 KHz) Time-base timer External interrupt 2 (Wake-up) CMOS I/O port Port 0 F 2MC-8L CPU RAM X0A X1A RST P00/INT20 to P07/INT27 ROM Port 2 8-bit serial Buzzer output N-ch open-drain I/O port P21*4, P26*4 P27/PWM2* 4 P25/SCK P24/SO P23/SI Reset circuit (WDT) 8-bit timer/counter N-ch open-drain output port N-ch open-drain I/O port (P30 and P31 are a CMOS output type.) 8 4 P22/TO P20/EC SEG0 to SEG7 V0 to V3 P40/SEG16*3 to P43/SEG19 P60/SEG8*3 to P63/SEG11 P64/SEG12*3 to P67/SEG15 P33/C0*2 LCD controller/driver Watch prescaler timer 8-bit A/D converter N-ch open-drain output port P10/INT10 to P13/INT13 8 8 AV CC AVR AV SS 8-bit PWM timer 2 8-bit timer/counter Reference voltage generator and booster*1 Remote control output 8-bit PWM timer 1 P44/SEG20*3 to P47/SEG23 P70/COM2* 3, P71/COM3 COM0, COM124 · 4 bits VRAM P32/C1*2 P31/PWM1 P30/RCO/BUZ P50/AN0 to P57/AN7 P14 to P17 Port 1 External interrupt 1 (Wake-up) CMOS I/O port Internal bus Port 4Port 6 and port 7 Port 5 *1: Selected by mask option *2: Used as ports without a reference voltage generator and booster *3: Functions selected by mask option. (For information on selecting procedure, see section “n Mask Options.”) *4: Heavy-current drive type Other pins MOD0, MOD1, V CC , VSS

1. Memory Space The microcontrollers of the MB89160 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89160 series is structured as illustrated below. Memory Space MB89PV160 MB89161/A MB89163/A MB89165/A MB89P165 FFFF H 8000H 0280H 0100H 0080H I/O RAM 256 B Not available External ROM 32 KB 0000H FFFF H F000H 0140H 00C0 H 0080H I/O RAM 128 B Register Not available ROM 4 KB 0000H 0100H FFFF H E000H 0180H 0080H I/O RAM 256 B Register Not available ROM 8 KB 0000H 0100H FFFF H C000 H 0280H 0100H 0080H I/O RAM 512 B Register Not available ROM 16 KB 0000H 0200H Not available Register 0200H

1. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. T emporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 18-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code The PS can further be divide into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) PC A T IX EP SP PS 16 bits : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFD H Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. Initial value Structure of the Program Status Register Vacancy H I IL1, 0 N Z VC RPPS 1 0 9876 321015 14 13 12 11 RP CCR VacancyVacancy

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set the shift-out value in the case of a shift instruction. IL1 IL0 Interrupt level High-low High Low = no interrupt 10 2 11 3 Rule for Conversion of Actual Addresses of the General-purpose Register Area “0” fl A15 “0” fl A14 “0” fl A13 “0” fl A12 “0” fl A11 “0” fl A10 “0” fl “1” fl fl fl fl fl fl fl fl fl Lower OP codesRP Generated addresses

The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 16 banks can be used on the MB89163 (RAM 256 · 8 bits), and a total of 32 banks can be used on the MB89165 (RAM 256 · 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuraiton This address = 0100H + 8 · (RP) Memory area 16 banks (MB89163) 32 banks (MB89165) R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7

(Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) DDR2 Port 2 data direction register 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTE Watchdog timer control register 0AH (R/W) TBTC Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0C H (R/W) PDR3 Port 3 data register 0D H Vacancy 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) PDR5 Port 5 data register 10H (R/W) BUZR Buzzer register 11H Vacancy 12H (R/W) PDR6 Port 6 data register 13H (R/W) PDR7 Port 7 data register 14H (R/W) RCR1 Remote control transmission register 1 15H (R/W) RCR2 Remote control transmission register 2 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR Serial mode register 1D H (R/W) SDR Serial data register 1EH (R/W) CNTR1 PWM 1 control register 1FH (W) COMP1 PWM 1 compare register

(Continued) Note: Do not use vacancies. Address Read/write Register name Register description 20H (R/W) CNTR2 PWM 2 control register 21H (W) COMP2 PWM 2 compare register 22H to 2CH Vacancy 2D H (R/W) ADC1 A/D converter control register 1 2EH (R/W) ADC2 A/D converter control register 2 2FH (R/W) ADCD A/D converter data register 30H (R/W) EIE1 External interrupt 1 enable register 1 31H (R/W) EIF1 External interrupt 1 flag register 1 32H (R/W) EIE2 External interrupt 2 enable register 2 33H (R/W) EIF2 External interrupt 2 flag register 2 34H to 5FH Vacancy 60H to 6BH (R/W) VRAM Display data RAM 6C H to 71H Vacancy 72H (R/W) LCDR LCD controller/driver control register 1 73H to 7BH Vacancy 7C H (W) ILR1 Interrupt level setting register 1 7D H (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Access prohibited ITR Interrupt test register

n ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) (Continued) Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage VCC VSS – 0.3 V SS + 7.0 V AV CC VSS – 0.3 V SS + 7.0 V AV CC must not exceed VCC + 0.3 V. AVR V SS – 0.3 V SS + 7.0 V AVR must not exceed AV CC + 0.3 V. LCD power supply voltage V0 to V3 V SS – 0.3 V SS + 7.0 V V0 to V3 on the product without booster must not exceed VCC . Input voltage VI1 VSS – 0.3 V CC + 0.3 V VI1 must not exceed VSS + 7.0 V. All pins except P20 to P27 without a pull-up resistor VI2 VSS – 0.3 V SS + 7.0 V P20 to P27 without a pull-up resistor Output voltage VO1 VSS – 0.3 V CC + 0.3 V VO1 must not exceed VSS + 7.0 V . All pins except P20 to P27, P32, P33, P40 to P47, and P60 to P67 without a pull-up resistor V O2 VSS – 0.3 V SS + 7.0 V P20 to P27, P32, P33, P40 to P47, and P60 to P67 without a pull-up resistor “L” level maximum output current IOL1 ¾ 10 mA All pins except P21, P26, and P27 IOL2 ¾ 20 mA P21, P26, and P27 “L” level average output current IOLAV1 ¾ 4m A All pins except P21, P26, P27, and power supply pins Average value (operating current · operating rate) IOLAV2 ¾ 8m A P21, P26, and P27 Average value (operating current · operating rate) “L” level total maximum output currentSIOL ¾ 100 mA Peak value “L” level total average output currentSIOLAV ¾ 40 mA Average value (operating current · operating rate) “H” level maximum output current IOH1 ¾ –5 mA All pins except P30, P31, and power supply pins IOH2 ¾ –10 mA P30 and P31

(Continued) (AVSS = VSS = 0.0 V) Precautions: Parmanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) *1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for the operating frequency. A/D converter assurance accuracy varies with the operating power supply voltage. *2: P32 and P33 are applicable only for procucts of the MB89160 series (without “A” suffix). P40 to P47 and P60 to P67 are applicable when selected as ports. Parameter Symbol Value Unit Remarks Min. Max. “H” level average output current IOHAV1 —– 2 m A All pins except P30, P31, and power supply pins Average value (operating current · operating rate) IOHAV2 —– 4 m A P30 and P31 Average value (operating current · operating rate) “H” level total maximum output currentSIOH — –50 mA Peak value “H” level total average output currentSIOHAV —– 1 0 m A Average value (operating current · operating rate) Power consumption P D —3 0 0 m W Operating temperature T A –40 +85 °C Storage temperature Tstg –55 +150 °C Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage VCC AV CC 2.2*1 6.0*1 V Normal operation assurance range*1 2.2*1 4.0 V Dual-clock mask ROM products 2.7 6.0 V Normal operation assurance range for MB89P165/A and MB89W165/A 1.5 6.0 V Retains the RAM state in stop mode AVR 2.0 AV CC V Normal operation assurance range LCD power supply voltage V0 to V3 V SS VCC V V0 to V3 pins on the products without a booster LCD power supply range (The optimum value dependent on the LCD element in use.) EPROM program power supply voltage V PP —V SS + 13.0 V MOD1 pin of the MB89P165 Operating temperature T A –40 +85 °C

Figure 1 Operating Voltage vs. Main Clock Operating Frequency (Single-clock MB8916X/A and MB89P165/PV160) Operation assurance range 1234 4.0 2.0 1.0 Main clock operating frequency Analog accurancy assured in the AVCC = VCC = 3.5 V to 6.0 V range Minimum execution time (instruction cycle) Note: The shaded area is assured only for the MB8916X/A. (MHz) (ms) Operating voltage (V)

Figure 2 Operating Voltage vs. Main Clock Operating Frequency (Dual-clock MB8916X/A) Figures 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH . Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 1234 4.0 2.0 1.0 Main clock operating frequency Minimum execution time (instruction cycle) Analog accurancy assured in the AV CC = VCC = 3.5 V to 6.0 V range Operation assurance range Operating voltage (V) (MHz) (ms)

1. DC Characteristics (1) Pin DC characteristics (VCC = +5.0 V) (VSS = 0.0 V, TA = –40°C to +85°C) (Continued) Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. “H” level input voltage VIH P00 to P07, P10 to P17, P20 to P27 0.7 VCC ¾ VCC + 0.3 V VIHS RST , MOD0, MOD1, EC, SI, SCK, INT10 to INT13, INT20 to INT27 0.8 V CC ¾ VCC + 0.3 V “L” level input voltage VIL P00 to P07, P10 to P17, P20 to P27 VSS - 0.3 ¾ 0.3 VCC V VILS RST , MOD0, MOD1, EC, SI, SCK, INT10 to INT13, INT20 to INT27 VSS - 0.3 ¾ 0.2 VCC V Open-drain output pin application voltage V P20 to P27, P33, P32, P40 to P47, P60 to P67 VSS - 0.3 ¾ VSS + 6.0*2 V P20 to P27, P40 to P47, and P60 to P67 without pull- up resistor only VD2 P50 to P57 VSS - 0.3 ¾ VCC + 0.3 V “H” level output voltage VOH1 P00 to P07, P10 to P17 IOH = –2.0 mA 2.4 ¾¾ V VOH2 P30, P31 I OH = –6.0 mA 4.0 ¾¾ V “L” level output voltage VOL P00 to P07, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P71 I OL = 1.8 mA ¾¾ 0.4 V VOL2 P21, P26, P27 IOL = 8.0 mA ¾¾ 0.4 V VOL3 RST IOL = 4.0 mA ¾¾ 0.6 V Input leakage current (Hi-z output leakage current) ILI1 P00 to P07, P10 to P17, MOD0, MOD1, P30, P31

0.45 V < VI < VCC ¾¾ – 5 mA Without pull-

(Continued) (VSS = 0.0 V , TA = –40°C to +85°C) Note: For pins which serve as the segment (SEG8 to SEG24) and ports (P40 to P47, P50 to P57, and P60 to P67), see the port parameter when these pins are used as ports and the segment parameter when they are used as segments. P32 and P33 are applicable only for products of the MB89160 series (without “A” suffix). Applicable as external capacitor connection pins for products of the MB89160A series (with “A” suffix). Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. Open-drain output leakage current I LO1 P20 to P27, P32, P33, P40 to P47, P60 to P67, P70, P71 0.45 V < VI < 6.0 V —— –1 mA Without pull- up resistor ILO2 P50 to P57 0.45 V < V I < VCC —— –1 mA Without pull- up resistor Pull-up resistance R PULL P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, P60 to P67, RST VI = 0.0 V 25 50 100 k W With pull-up resistor Common output impedance RVCOM COM0 to COM3 V1 to V3 = +5.0 V ——2 . 5 k W Segment output impedance RVSEG SEG0 to SEG24 — — 15 k W LCD divided resistance R LCD — Between VCC and V0 300 500 750 k W Products without a booster only LCD controller/driver leakage current ILCDL V0 to V3, COM0 to COM3, SEG0 to SEG23 —— — –1 mA Booster for LCD driving output voltage VOV3 V3 V1 = 1.5 V 4.3 4.5 4.7 V Products with a booster only VOV2 V2 2.9 3.0 3.1 V Reference output voltage for LCD driving VOV1 V1 I IN = 0 mA 1.27 1.5 1.73 V Reference voltage input impedance R RIN V1 — 600 1000 1400 k W Procucts with a booster only Input capacitance CIN Other than VCC , VSS f = 1 MHz — 10 — pF

(2) Pin DC Characteristics (VCC = +3.0 V) (VCC = 3.0 V , VSS = 0.0 V , TA = –40°C to +85°C) Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. “H” level output voltage VOH1 P00 to P07, P10 to P17 IOH = –1.0 mA 2.4 — — V VOH2 P30, P31 I OH = –3.0 mA 2.4 — — V “L” level output voltage VOL P00 to P07, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P71 I OL = 1.8 mA — — 0.4 V VOL2 RST IOL = 1.8 mA — — 0.4 V VOL3 P21, P26, P27 IOL = 3.6 mA — — 0.4 V Pull-up resistance R PULL P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, P60 to P67, RST VI = 0.0 V 50 100 150 k W With pull-up resistor

(3) Power Supply Current Characteristics (MB8916X) (VSS = 0.0 V , TA = –40°C to +85°C) *1: The power supply current is measured at the external clock, open output pins, and the external LCD dividing resistor (or external input for the reference voltage). In the case of the MB89PV160, the current consumed by the connected EPROM and ICE is not included. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. Power supply current*1 ICC1 VCC FCH = 4.2 MHz, VCC = 5.0 V tinst*2 = 4/FCH Main clock operation mode — 5.0 10.0 mA MB8916X/A, MB89PV160 — 8.0 15.0 mA MB89PV165 ICC2 FCH = 4.2 MHz, VCC = 3.0 V tinst*2 = 64/FCH Main clock operation mode —1 . 5 2 . 0 m A MB8916X/A, MB89PV160 — 2.4 2.8 mA MB89P165 ICCL FCL = 32.768 kHz, VCC = 3.0 V tinst*2 = 2/FCL Subclock operation mode —0 . 0 5 0 . 1 m A MB8916X/A, MB89PV160 — 1.0 3.0 mA MB89PV165 ICCS1 FCH = 4.2 MHz, VCC = 5.0 V tinst*2 = 4/FCH Main clock sleep mode —2 . 5 5 . 0 m A MB8916X/A, MB89PV160, MB89PV165 ICCS2 FCH = 4.2 MHz, VCC = 3.0 V tinst*2 = 64/FCH Main clock sleep mode —1 . 0 1 . 5 m A ICCSL FCL = 32.768 kHz, VCC = 3.0 V tinst*2 = 2/FCL Subclock sleep mode —2 55 0 mA ICCT FCL = 32.768 kHz, VCC = 3.0 V Watch mode —1 01 5 mA MB8916X, MB89P165-1XX, MB89PV160 ICCT2 FCL = 32.768 kHz, VCC = 3.0 V

• W a t c h m o d e
• During reference voltage generator and booster operation —2 5 0 4 0 0 mA MB8916XA, MB89P165-2XX ICCH TA = +25°C, VCC = 5.0 V Stop mode —0 . 1 1 . 0 mA MB8916X —0 . 11 0 mA MB89PV160, MB89P165-1XX IA AV CC FCH = 4.2 MHz, VCC = 5.0 V — 1.0 3.0 mA When A/D conversion is activated

1. AC Characteristics (1) Reset Timing (VCC = +5.0 V –10 %, VSS = 0.0 V, TA = –40°C to +85°C) (2) Power-on Reset (VSS = 0.0 V , TA = –40°C to +85°C) Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. Parameter Symbol Condition Value Unit Remarks Min. Max. RST “L” pulse width t ZLZH 48 tXCYL —n s RST “H” pulse width t ZHZL 24 tXCYL —n s Parameter Symbol Condition Value Unit Remarks Min. Max. Power supply rising time tR —— 5 0 m s Power-on reset function only Power supply cut-off time tOFF —1 — m s Due to repeated operations 0.2 VCC 0.2 VCC0.2 VCC

0.8 VCC

0.2 V 0.2 V 2.0 V 0.2 V tR VCC tOFF

(3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. Clock frequency FCH X0, X1 1 — 4.2 MHz Main clock FCL X0A, X1A — 32.768 — kHz Subclock Clock cycle time tHCYL X0, X1 238 — 1000 ns Main clock tLCYL X0A, X1A — 30.5 — ms Subclock Input clock pulse widthPWH PWL X0 20 — — ns External clock Input clock rising/falling time tCR tCF X0 — — 24 ns ceramic resonator is used When an external clock is used When the CR oscillation option is used tHCYL

0.2 VCC

C FCH R X0 X1 FCH Main Clock Timing and Conditions Main Clock Conditions

(4) Instruction Cycle Parameter Symbol Value (typical) Unit Remarks Instruction cycle (minimum execution time) tinst 4/FCH , 8/FCH , 16/FCH , 64/FCH ms( 4 / FCH ) tinst = 1.0 ms at FCH = 4 MHz 2/FCL mst inst = 62 ms at FCL = 32.768 kHz ceramic oscillator is used When the single-clock option is used tLCYL X0A X0A X1A FCL Subclock Timing and Conditions Subclock Conditions

(5) Serial I/O Timing (VCC = +5.0 V –10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Condition Value Unit Remarks Min. Max. Serial clock cycle time t SCYC SCK Internal clock operation 2 tinst*— ms SCK fl fi SO time t SLOV SCK, SO –200 200 ns Valid SI fi SCK › tIVSH SI, SCK 1/2 t inst*— ms SCK › fi valid SI hold time tSHIX SCK, SI 1/2 t inst*— ms Serial clock “H” pulse width tSHSL SCK External clock operation 1 tinst*— ms Serial clock “L” pulse width tSLSH 1 tinst*— ms SCK fl fi SO time t SLOV SCK, SO 0 200 ns Valid SI fi SCK › tIVSH SI, SCK 1/2 t inst*— ms SCK › fi valid SI hold time tSHIX SCK, SI 1/2 t inst*— ms 2.4 V 0.8 V 0.8 V 2.4 V tSCYC 2.4 V 0.8 V 0.8 V tIVSH

(6) Peripheral Input Timing (VCC = +5.0 V –10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Value Unit Remarks Min. Max. Peripheral input “H” pulse width 1 tILIH1 INT10 to INT13, EC 1 tinst*— ms Peripheral input “L” pulse width 1 tIHIL1 1 tinst*— ms Peripheral input “H” pulse width 2 tILIH2 INT20 to INT27 2 tinst*— ms Peripheral input “L” pulse width 2 tIHIL2 2 tinst*— ms INT10 to 13, EC

1. A/D Converter Electrical Characteristics (3 MHz, AVCC = VCC = +3.5 V to +6.0 V , AVSS = VSS = 0.0 V , TA = –40°C to +85°C) (1) A/D Glossary

• Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28=256.
• Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” « “0000 0001”) with the full-scale transition point (“1111 1111” « “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• T otal error (unit: LSB) The difference between theoretical and actual conversion values Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. Resolution ——— 8 b i t T otal error AVR = AVCC —— –1.5 LSB Linearity error — — –1.0 LSB Differential linearity error —— –0.9 LSB Zero transition voltageVOT AV SS – 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSBmV Full-scale transition voltage VFST AVR – 3.0 LSB AVR – 1.5 LSB AVR mV Interchannel disparity —— 0 . 5 L S B A/D mode conversion time —4 4 t inst — ms Sense mode conversion time —1 2 t inst — ms Analog port input currentIAI AN0 to AN7 ——1 0 mA Analog input voltage — 0.0 — AVR V Reference voltage — AVR 2.0 — AV CC V Reference voltage supply current IR AVR = 5.0 V , when A/D conversion is activated — 100 — mA IRH AVR = 5.0 V , when A/D conversion is stopped —— 1 mA

(2) Precautions

• Input impedance of analog input pins The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kW ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 mF for the analog input pin.
• E r r o r The smaller the |AVR – AVSS |, the greater the error would become relatively. VOT Analog input Linearity error = Actual conversion value 1 LSB = 256 Digital output AVR Theoretical conversion value (1 LSB · N + VOT ) VNT VFSTV(N + 1)T - 1

1 LSB

VNT - (1 LSB · N + VOT ) Defferential linearity error = V(N+1)T - VNT Total error = VNT - (1 LSB · N + 1 LSB) Linearity error 1111 1111 1111 1110 0000 0010 0000 0001 0000 0000 Analog input pin Sample hold circuit C = 33 pF If the analog input impedance is higher than 10 kW , it is recommended to connect an external capacitor of approx. 0.1 mF. Comparator R = 6 kW Analog channel selector Close for 8 instruction cycles after activating A/D conversion. Analog Input Equivalent Circuit

1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 V IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC – VOH1 vs. IOH VCC – VOH1 (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 V IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC – VOH2 vs. IOH VCC – VOH2 (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 4 8 12 16 20 VCC = 2.0 V IOL (mA) VCC = 2.5 VVCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 2 6 10 14 18 TA = +25°C VOL2 vs. IOL VOL2 (V) (1) “L” Level Output Voltage (2) “H” Level Output Voltage 0.6 0.5 0.4 0.3 0.2 0.1 I OL (mA) 2468 1 0 VCC = 2.0 V V CC = 3.0 V 13579 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V TA = +25°C VOL1 vs. IOL VOL1 (V)

(Continued) (3) “H” Level Input Voltage/“L” level Input Voltage (4) Power Supply Current (External Clock) 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V CC (V) 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VIHS VILS VCC (V) TA = +25°C TA = +25°C CMOS input CMOS hysteresis input VIN (V)VIN (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 0 1234567 VCC (V) ICC1 vs. VCC (Mask ROM products) ICC1 (mA) TA = +25°C FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz 0 1234567 VCC (V) ICC2 vs. VCC (Mask ROM products) ICC2 (mA) 1.0 2.0 TA = +25°C FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz

(Continued) 0 1234567 VCC (V) ICC1S vs.VCC (Mask ROM products) ICC1S (mA) 1.0 2.0 TA = +25°C3.0 FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz 0 1234567 VCC (V) ICC2S vs. VCC (Mask ROM products) ICC2S (mA) 1.0 2.0 TA = +25°C FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz 200 180 160 140 120 100 0 1234567 V CC (V) ICCL vs. VCC (Mask ROM products) FCL = 32.768 kHz TA = +25°C ICCL (mA) 1234567 V CC (V) ICCT vs. VCC FCL = 32.768 kHz TA = +25°C ICCT (mA)

(Continued) IR (mA) AVR (V) 1.5 2 100 120 140 160 180 200 IR vs. AVR TA = +25°C IA (mA) AV CC (V) 1.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IA vs. AVCC TA = +25°C FCH = 4 MHz 1234567 1,000 VCC (V) 500 100 TA = +25°C TA = +85°C TA = –40°C R PULL (kW ) R PULL vs. VCC (5) Pull-up Resistance 200 180 160 140 120 100 0 1234567 V CC (V) ICCSL vs. VCC FCL = 32.768 kHz TA = +25°C ICCSL (mA) 1,000 900 800 700 600 500 400 300 200 100 1234567 VCC (V) ICCT2 vs. VCC FCL = 32.768 kHz TA = +25°C ICCT2 (mA)

Execution instructions can be divided into the following four groups:

• T ransfer
• Arithmetic operation
• Branch
• O t h e r s T able 1 lists symbols used for notation for instructions. Table 1 Instruction Symbols (Continued) Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T T emporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits)

(Continued) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: “–” indicates no change.

• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction is executed.
• 00 becomes 00. N, Z, V , C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ‹ This indicates 48, 49, ... 4F . Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7)
• Indicates that the very · is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ( · ) Indicates that the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( · )) The address indicated by the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Table 2 Transfer Instructions (48 instructions) Notes:• During byte transfer to A, T ‹ A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC (dir) ‹ (A) ( (IX) +off ) ‹ (A) (ext) ‹ (A) ( (EP) ) ‹ (A) (Ri) ‹ (A) (A) ‹ d8 (A) ‹ (dir) (A) ‹ ( (IX) +off) (A) ‹ (ext) (A) ‹ ( (A) ) (A) ‹ ( (EP) ) (A) ‹ (Ri) (dir) ‹ d8 ( (IX) +off ) ‹ d8 ( (EP) ) ‹ d8 (Ri) ‹ d8 (dir) ‹ (AH),(dir + 1) ‹ (AL) ( (IX) +off) ‹ (AH), ( (IX) +off + 1) ‹ (AL) (ext) ‹ (AH), (ext + 1) ‹ (AL) (EP) ‹ (A) (A) ‹ d16 (AH) ‹ (dir), (AL) ‹ (dir + 1) (AH) ‹ ( (IX) +off), (AL) ‹ ( (IX) +off + 1) (AH) ‹ (ext), (AL) ‹ (ext + 1) (A) ‹ (EP) (EP) ‹ d16 (IX) ‹ (A) (A) ‹ (IX) (SP) ‹ (A) (A) ‹ (SP) ( (A) ) ‹ (T) (IX) ‹ d16 (A) ‹ (PS) (PS) ‹ (A) (SP) ‹ d16 (AH) « (AL) (dir): b ‹ 1 (dir): b ‹ 0 (AL) « (TL) (A) « (T) (A) « (EP) (A) « (IX) (A) « (SP) (A) ‹ (PC) AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 48 to 4F 08 to 0F 88 to 8F A8 to AF A0 to A7

Table 3 Arithmetic Operation Instructions (62 instructions) (Continued) Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir (A) ‹ (A) + (Ri) + C (A) ‹ (A) + d8 + C (A) ‹ (A) + (dir) + C (A) ‹ (A) + ( (IX) +off) + C (AL) ‹ (AL) + (TL) + C (A) ‹ (A) - (Ri) - C (A) ‹ (A) - d8 - C (A) ‹ (A) - (dir) - C (A) ‹ (A) - ( (IX) +off) - C (AL) ‹ (TL) - (AL) - C (Ri) ‹ (Ri) + 1 (EP) ‹ (EP) + 1 (IX) ‹ (IX) + 1 (A) ‹ (A) + 1 (Ri) ‹ (Ri) - 1 (EP) ‹ (EP) - 1 (IX) ‹ (IX) - 1 (A) ‹ (A) - 1 (A) ‹ (AL) · (TL) (A) ‹ (T) / (AL),MOD fi (T) (A) ‹ (A) Ù (T) (A) ‹ (A) Ú (T) (A) ‹ (A) " (T) (TL) - (AL) (T) - (A) (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ‹ (AL) " (TL) (A) ‹ (AL) " d8 (A) ‹ (AL) " (dir) (A) ‹ (AL) " ( (IX) +off) (A) ‹ (AL) " (Ri) (A) ‹ (AL) Ù (TL) (A) ‹ (AL) Ù d8 (A) ‹ (AL) Ù (dir) dL dH dH dH dH dH dH dH dH + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + – – – – – – – – – + + – – + + + – – – – – – – – – + + – – – – – – – – – – + + R – + + R – + + R – + + + + + + + + + + – + + + – + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – 28 to 2F 38 to 3F C8 to CF D8 to DF 18 to 1F 58 to 5F A C fifi AC

(Continued) Table 4 Branch Instructions (17 instructions) Table 5 Other Instructions (9 instructions) Mnemonic ~ # Operation TL TH AH N Z V C OP code AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP (A) ‹ (AL) Ù ( (EP) ) (A) ‹ (AL) Ù ( (IX) +off) (A) ‹ (AL) Ù (Ri) (A) ‹ (AL) Ú (TL) (A) ‹ (AL) Ú d8 (A) ‹ (AL) Ú (dir) (A) ‹ (AL) Ú ( (EP) ) (A) ‹ (AL) Ú ( (IX) +off) (A) ‹ (AL) Ú (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ‹ (SP) + 1 (SP) ‹ (SP) – 1 + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + + + + + + + + + + + + + + + – – – – – – – – 68 to 6F 78 to 7F 98 to 9F Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI If Z = 1 then PC ‹ PC + rel If Z = 0 then PC ‹ PC + rel If C = 1 then PC ‹ PC + rel If C = 0 then PC ‹ PC + rel If N = 1 then PC ‹ PC + rel If N = 0 then PC ‹ PC + rel If V " N = 1 then PC ‹ PC + rel If V " N = 0 then PC ‹ PC + reI If (dir: b) = 0 then PC ‹ PC + rel If (dir: b) = 1 then PC ‹ PC + rel (PC) ‹ (A) (PC) ‹ ext Vector call Subroutine call Return from subrountine Return form interrupt dH – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + – – – + – – – – – – – – – – – – – – – – – – – – – – – – – – Restore FD FC FB FA FF FE B0 to B7 B8 to BF E8 to EF Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI dH – – – – – – – – – – – – – – – – – – – – – – – R – – – S – – – – – – – –

0 NOP SWAP RET RETI PUSHW

A POPW A MOV A,ext MOVW A,PS CLRI SETI CLRB dir: 0 BBC dir: 0,rel INCW A DECW A JMP MOVW A,PC

1 MULU

A DIVU A JMP addr16 CALL addr16 PUSHW IX POPW IX MOV ext,A MOVW PS,A CLRC SETC CLRB dir: 1 BBC dir: 1,rel INCW SP DECW SP MOVW SP ,A MOVW A,SP

2 ROLC

A CMP A ADDC A SUBC A XCH A, T XOR A AND A OR A MOV @A,T MOV A,@A CLRB dir: 2 BBC dir: 2,rel INCW IX DECW IX MOVW IX,A MOVW A,IX

3 RORC

A CMPW A ADDCW A SUBCW A XCHW A, T XORW A ANDW A ORW A MOVW @A,T MOVW A,@A CLRB dir: 3 BBC dir: 3,rel INCW EP DECW EP MOVW EP ,A MOVW A,EP

4 MOV

A,#d8 CMP A,#d8 ADDC A,#d8 SUBC A,#d8 XOR A,#d8 AND A,#d8 OR A,#d8 DAA DAS CLRB dir: 4 BBC dir: 4,rel MOVW A,ext MOVW ext,A MOVW A,#d16 XCHW A,PC

5 MOV

A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#d8 CMP dir,#d8 CLRB dir: 5 BBC dir: 5,rel MOVW A,dir MOVW dir,A MOVW SP ,#d16 XCHW A,SP

6 MOV

A,@IX +d CMP A,@IX +d ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A XOR A,@IX +d AND A,@IX +d OR A,@IX +d MOV @IX +d,#d8 CMP @IX +d,#d8 CLRB dir: 6 BBC dir: 6,rel MOVW A,@IX +d MOVW @IX +d,A MOVW IX,#d16 XCHW A,IX

7 MOV

A,@EP CMP A,@EP ADDC A,@EP SUBC A,@EP MOV @EP ,A XOR A,@EP AND A,@EP OR A,@EP MOV @EP ,#d8 CMP @EP ,#d8 CLRB dir: 7 BBC dir: 7,rel MOVW A,@EP MOVW @EP ,A MOVW EP ,#d1 XCHW A,EP

8 MOV

A,R0 CMP A,R0 ADDC A,R0 SUBC A,R0 MOV R0,A XOR A,R0 AND A,R0 OR A,R0 MOV R0,#d8 CMP R0,#d8 SETB dir: 0 BBS dir: 0,rel INC DEC CALLV BNC rel

9 MOV

A,R1 CMP A,R1 ADDC A,R1 SUBC A,R1 MOV R1,A XOR A,R1 AND A,R1 OR A,R1 MOV R1,#d8 CMP R1,#d8 SETB dir: 1 BBS dir: 1,rel INC DEC CALLV BC rel A MOV A,R2 CMP A,R2 ADDC A,R2 SUBC A,R2 MOV R2,A XOR A,R2 AND A,R2 OR A,R2 MOV R2,#d8 CMP R2,#d8 SETB dir: 2 BBS dir: 2,rel INC DEC CALLV BP rel B MOV A,R3 CMP A,R3 ADDC A,R3 SUBC A,R3 MOV R3,A XOR A,R3 AND A,R3 OR A,R3 MOV R3,#d8 CMP R3,#d8 SETB dir: 3 BBS dir: 3,rel INC DEC CALLV BN rel C MOV A,R4 CMP A,R4 ADDC A,R4 SUBC A,R4 MOV R4,A XOR A,R4 AND A,R4 OR A,R4 MOV R4,#d8 CMP R4,#d8 SETB dir: 4 BBS dir: 4,rel INC DEC CALLV BNZ rel D MOV A,R5 CMP A,R5 ADDC A,R5 SUBC A,R5 MOV R5,A XOR A,R5 AND A,R5 OR A,R5 MOV R5,#d8 CMP R5,#d8 SETB dir: 5 BBS dir: 5,rel INC DEC CALLV BZ rel E MOV A,R6 CMP A,R6 ADDC A,R6 SUBC A,R6 MOV R6,A XOR A,R6 AND A,R6 OR A,R6 MOV R6,#d8 CMP R6,#d8 SETB dir: 6 BBS dir: 6,rel INC DEC CALLV BGE rel F MOV A,R7 CMP A,R7 ADDC A,R7 SUBC A,R7 MOV R7,A XOR A,R7 AND A,R7 OR A,R7 MOV R7,#d8 CMP R7,#d8 SETB dir: 7 BBS dir: 7,rel INC DEC CALLV BLT rel L H

Part number MB89161/3/5 MB89P165 MB89PV160 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible Pull-up resistors (SEG) P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, P60 to P67 Slectable per pin (The pull-up resistors for P40 to P47 and P60 to P67 are only selectable when these pins are not set as segment outputs. When the A/D is used, P50 to P57 are must not selected.) Can be set per pin (P20 to P27, P40 to P47, and P60 to P67 are available only for without a pull-up resistor.) Fixed to without pull-up resistor Power-on reset (POR) With power-on reset Without power-on reset Selectable Selectable Fixed to with power-on reset Selection of oscillation stabilization time (OSC)

• The initial value of the oscillation stabilization time for the main clock can be set by selecting the values of the WTM1 and WTM0 bits on the right. Selectable OSC 0 : 2 2/FCH 1 : 2 12/FCH 2 : 2 16/FCH 3 : 2 18/FCH Selectable WTM1 WTM0 0 0 : 2 2/FCH 0 1 : 2 12/FCH 1 0 : 2 16/FCH 1 1 : 2 18/FCH Fixed to oscillation stabilization time of 216/FCH Main clock oscillation type (XSL) Crystal or ceramic resonator CR Selectable Crystal or ceramic onlyFixed to crystal or ceramic Reset pin output (RST) With reset output Without reset output Selectable Selectable Fixed to with reset output Clock mode selection (CLK) Dual-clock mode Single-clock mode Selectable Selectable Fixed to dual-clock mode

• Segment Options n VERSIONS No. Part number MB89161/3/5 MB89P165 MB89PV160 Specifying procedure Specify when ordering masking Select by version number Select by version number

7 LCD output pin configuration

SEG = 4: P40 to P47 segment output P60 to P67 segment output P70, P71 common output Specify as SEG = 4 –101 : SEG 24 pins –201 COM 4 pins –101 : SEG 24 pins COM 4 pins SEG = 3: P40 to P43 segment output P44 to P47 port output P60 to P67 segment output P70, P71 common output Specify as SEG = 3 –102 : SEG 20 pins –202 COM 4 pins –102 : SEG 20 pins COM 4 pins SEG = 2: P40 to P47 port output P60 to P67 segment output P70, P71 common output Specify as SEG = 2 –103 : SEG 16 pins –203 COM 4 pins –103 : SEG 16 pins COM 4 pins SEG = 1: P40 to P47 port output P60 to P63 segment output P64 to P67 port output P70, P71 port output Specify as SEG = 1 –104 : SEG 12 pins COM 2 pins –104 : SEG 12 pins COM 2 pins SEG = 0: P40 to P47 port output P60 to P67 port output P70, P71 port output Specify as SEG = 0 –105 : SEG 8 pins COM 2 pins –105 : SEG 8 pins COM 2 pins Version Features Mass production product One-time PROM product Piggyback/evaluation product Number of segment pins Booster MB89160A series MB89P165-201 -202 -203 24 (4 commons) 20 (4 commons) 16 (4 commons) Yes MB89160 series MB89P165-101 -102 -103 -104 -105 MB89PV160-101 -102 -103 -104 -105 24 (4 commons) 20 (4 commons) 16 (4 commons) 12 (2 commons) 8 (2 commons) No

Note: For information on ··· , see section “n Versions.” Part number Package Remarks MB89161-PFV MB89161A-PFV MB89163-PFV MB89163A-PFV MB89165-PFV MB89165A-PFV MB89P165- ··· -PFV 80-pin Plastic SQFP (FPT-80P-M05) MB89161-PF MB89161A-PF MB89163-PF MB89163A-PF MB89165-PF MB89165A-PF MB89P165- ··· -PF 80-pin Plastic QFP (FPT-80P-M06) MB89161-PFS MB89161A-PFS MB89163-PFS MB89163A-PFS MB89165-PFS MB89165A-PFS MB89P165- ··· -PFS 80-pin Plastic QFP (FPT-80P-M11) MB89W165- ··· -PF 80-pin Ceramic QFP (FPT-80C-A02) MB89PV160- ··· -PF 80-pin Ceramic MQFP (MQP-80C-P01)

C 1995 FUJITSU LIMITED F80008S-2C-5 0.10(.004) 0.10±0.10 (.004±.004) Details of "A" part 0 10° 9.50 13.00 (.374) REF (.512) NOM 0.50±0.08 +.003 –0.03 +0.08 0.18 .005–.001 +.002 –0.02 +0.05 0.127 .059–.004 +.008 –0.10 +0.20 1.50 "A" 12 0 4160 61 40 INDEX (STAND OFF) LEAD No. (Mounting height) Dimensions in mm (inches). 80-pin plastic LQFP (FPT -80P-M05) C 1994 FUJITSU LIMITED F80010S-3C-2 "B" 0.10(.004) 0.58(.023)MAX 0.18(.007)MAX Details of "A" part 0 10° Details of "B" part 12.00(.472) REF 16.30±0.40 (.642±.016) 0.05(.002)MIN (STAND OFF) INDEX 18.40(.724)REF 1 24 4164 0.25(.010) 0.30(.012) 0.80±0.20 (.031±.008) LEAD No. "A" 3.35(.132)MAX (Mounting height) Dimensions in mm (inches). 80-pin plastic QFP (FPT -80P-M06)

C 1995 FUJITSU LIMITED F80016S-1C-3 0.13(.005)M 0.10(.004)

1 PIN INDEX

.059–.004 +.008 –0.10 +0.20 1.50 "A" Details of "A" part 0 10° 0.50±0.20 0.10±0.10 (.004±.004) (.020±.008) (STAND OFF) (.012±.004) 0.127 +0.05 –0.02 +.002 –.001 .005 12.35 15.00 (.486) REF (.591) NOM 4160 LEAD No. (Mounting height) Dimensions in mm (inches). 80-pin plastic LQFP (FPT -80P-M11) C 1994 FUJITSU LIMITED F80014SC-1-2 INDEX AREA 14.00±0.25 17.91(.705) TYP (.551±.010) 16.00(.630) TYP 16.31(.642) TYP 12.00(.472) REF 0.51(.020) TYP 4.45(.175)MAX 0.15±0.05 (.006±.002) 23.90(.941) TYP 20.00±0.25 (.787±.010) 18.40(.725) REF (.0315±.0040) 0.80±0.10 (.014±.003) 1.60(.063) TYP 22.00(.866) TYP 8.50(.335)TYP 0.35 +0.08 –0.07 (.0315±.0040) 0.80±0.10 Dimensions in mm (inches). 80-pin ceramic QFP (FPT -80C-A02)

(Continued) C 1994 FUJITSU LIMITED M80001SC-4-2 15.58±0.20 (.613±.008) 16.30±0.33 (.642±.013) 18.70(.736)TYP INDEX AREA 0.30(.012) TYP 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 10.16(.400) TYP 12.02(.473) TYP 14.22(.560) TYP 18.12±0.20 (.713±.008) 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.15±0.05 (.006±.002) 8.70(.343) MAX 0.40±0.10 +.016 –0.20 +0.40 1.20 0.40±0.10 (.016±.004) 18.40(.724) REF 0.80±0.25 (.0315±.010) 12.00(.472)TYP .047–.008 +.016 –0.20 +0.40 1.20 0.80±0.25 (.0315±.010) 1.50(.059) TYP 1.00(.040) TYP 1.00(.040)TYP 1.50(.059)TYP INDEX AREA 6.00(.236) TYP 4.50(.177) TYP INDEX Dimensions in mm (inches). 80-pin ceramic MQFP (MQP-80C-P01)

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