MB89151APFM

MB89151 FUJITSU | Alldatasheet

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DS07-12506-4EFUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89150/150A Series MB89151/151A/152/152A/153/153A/154/154A/155/155A MB89P155/PV150 ■ DESCRIPTION The MB89150/A series has been developed as general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the MB89150 series microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, a remote control transmission output, external interrupts, an LCD controller/driver, an LCD booster, and a watch prescaler. *: F 2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES

• F 2MC-8L family CPU core
• Dual-clock system
• High-speed processing at low voltage
• Minimum execution time: 0.95 µs/2.7 V, 1.33 µs/2.2 V
• I/O ports: max. 43 channels
• 21-bit time-base timer
• 8/16-bit timer/counter: 1 channel (8 bits × 2 channels)
• 8-bit serial I/O: 1 channel
• LCD controller/driver: Max. 36 segments × 4 commons (built-in booster)
• Remote control transmission output (Continued) ■ PACKAGE 80-pin Plastic QFP 80-pin Plastic LQFP 80-pin Ceramic MQFP80-pin Plastic LQFP (FPT -80P-M06) (FPT -80P-M11) (FPT -80P-M05) (MQP-80C-P01)

(Continued)

• Buzzer output
• Watch prescaler (15 bits)
• External interrupts (wake-up function) Four independent channels with edge detection function plus eight level-interrupt channels ■ PRODUCT LINEUP (Continued) MB89152/A MB89153/A MB89154/A MB89155/A MB89P155 MB89 PV150 Classification Mass production products (mask ROM products) One-time PROM product Piggyback/ evaluation product (for evaluation and development) ROM size 4 K × 8 bits (internal mask ROM)

6 K × 8 bits

(internal mask ROM)

8 K × 8 bits

(internal mask ROM)

12 K × 8 bits

(internal mask ROM)

16 K × 8 bits

(internal mask ROM) (internal PROM, programming with general- purpose EPROM programmer)

32 K × 8 bits

(external ROM) RAM size 128 × 8 bits 256 × 8 bits 512 × 8 bits CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.95 µs/4.2 MHz Interrupt processing time: 8.57 µs/4.2 MHz Ports I/O port (N-ch open-drain): 8 (6 ports also serve as peripherals, 3 ports are a high-current drive type.) Output port (N-ch open-drain): 18 (16 ports also serve as segment pins, 2 ports serve as boost capacitor connection pins.) I/O port (CMOS): 16 (12 ports also serve as an external interrupt.) Output port (CMOS): 1 (Also serves as a remote control.) Total: 43 (max.) Timer/counter 8-bit timer counter × 2 channel or 16-bit event counter × 1 channel 8-bit serial I/O 8 bits LSB first/MSB first selectability LCD controller/ driver Common output: 4 Segment output: 32 (max.) Bias power supply pins: 4 LCD display RAM size: 36 × 4 bits Booster for LCD driving: Built-in *1 Dividing resistor for LCD driving: Built-in (an external resistor selectability) No reference voltage generator and booster for LCD driving External interrupts (wake-up function) 4 (edge selectability) 8 (level interrupt only) Buzzer output 1 (7 frequencies are selectable by the software.) MB89151/A Part number Parameter

(Continued) *1: Selected by the mask option. See section “■ Mask Options.” *2: Varies with conditions such as the operating frequency and the connected ICE. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS : Available × : Not available Note: For more information about each package, see section “■ Package Dimensions.” MB89152/A MB89153/A MB89154/A MB89155/A MB89P155 MB89 PV150 Remote control transmission output 1 (Pulse width and cycle are software selectable.) Standby modes Sleep mode, stop mode, and watch mode Process CMOS EPROM for use MBM27C256A -20TV (LCC package) Package MB89151/A MB89152/A MB89153/A MB89154/A MB89155/A MB89P155 MB89PV150 FPT -80P-M06 × FPT -80P-M11 × FPT -80P-M05 × MQP-80C-P01 ×× MB89151/A Part number Parameter

■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points:

• On the MB89151/A, addresses 0140H and later of the register bank cannot be used. On the MB89152/A, 153/A, 154/A, 155/A, and MB89P155, addresses 0180H and later of each register bank cannot be used.
• On the MB89P155, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read by reading these addresses.
• The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption
• In the case of the MB89PV150, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following point:
• On the MB89PV150, options are fixed, except for the segment output selection.

■ PIN ASSIGNMENT P43/SEG23* P44/SEG24*4 P45/SEG25*4 P46/SEG26*4 P47/SEG27*4 P50/SEG28*4 P51/SEG29*4 P52/SEG30*4 P53/SEG31*4 P54/SEG32*4 P55/SEG33*4 P56/SEG34*4 VSS P57/SEG35*4 MOD1 MOD0 RST P00/INT20 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V CC P32* 2/C0*1 P31*2/C1*1 P30/RCO X1A X0A P27/BUZ* P26*3 P25/SCK P42/SEG22* P41/SEG21*4 P40/SEG20*4 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 (Top view) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain high-current drive type *4: Selected using the mask option (in units of 4 pins) (FPT-80P-M05) P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21*3 P22/TO P23/SI P24/SO

P43/SEG23* P44/SEG24*4 P45/SEG25*4 P46/SEG26*4 P47/SEG27*4 P50/SEG28*4 P51/SEG29*4 P52/SEG30*4 P53/SEG31*4 P54/SEG32*4 P55/SEG33*4 P56/SEG34*4 VSS P57/SEG35*4 MOD1 MOD0 RST P00/INT20 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V CC P32* 2/C0*1 P31*2/C*1 P30/RCO X1A X0A P27/BUZ* P26*3 P25/SCK P42/SEG22* P41/SEG21*4 P40/SEG20*4 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 (Top view) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain high-current drive type *4: Selected using the mask option (in units of 4 pins) (FPT-80P-M11) P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 P20/EC P21*3 P22/TO P23/SI P24/SO

P41/SEG21* P42/SEG22*4 P43/SEG23*4 P44/SEG24*4 P45/SEG25*4 P46/SEG26*4 P47/SEG27*4 P50/SEG28*4 P51/SEG29*4 P52/SEG30*4 P53/SEG31*4 P54/SEG32*4 P55/SEG33*4 P56/SEG34*4 VSS P57/SEG35*4 MOD1 MOD0 RST P00/INT20 P01/INT21 P02/INT22 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V CC P32* 2/C0*1 P31*2/C1*1 P30/RCO X1A X0A P27/BUZ* P26*3 P25/SCK P24/SO P23/SI P40/SEG20* SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 (Top view) *1: For products with a booster circuit *2: For products without a booster circuit *3: N-ch open-drain high-current drive type *4: Selected using the mask option (in units of 4 pins) (FPT-80P-M06) P20/EC P21*3 P22/TO

• Pin assignment on package top N.C.: Internally connected. Do not use. Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE 82 V PP 90 A1 98 O4 106 N.C.

83 A12 91 A0 99 O5 107 A11

84 A7 92 N.C. 100 O6 108 A9

85 A6 93 O1 101 O7 109 A8

86 A5 94 O2 102 O8 110 A13

87 A4 95 O3 103 CE

111 A14

88 A3 96 V SS 104 A10 112 V CC

P41/SEG21* P42/SEG22*2 P43/SEG23*2 P44/SEG24*2 P45/SEG25*2 P46/SEG26*2 P47/SEG27*2 P50/SEG28*2 P51/SEG29*2 P52/SEG30*2 P53/SEG31*2 P54/SEG32*2 P55/SEG33*2 P56/SEG34*2 VSS P57/SEG35*2 MOD1 MOD0 RST P00/INT20 P01/INT21 P02/INT22 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V CC P32 P31 P30/RCO X1A X0A P27/BUZ* P26*1 P25/SCK P24/SO P23/SI P40/SEG20* SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14 P15 P16 P17 (Top view) 101 102 103 104 105 106 107 108 109 100 110 111 112 *1: N-ch open-drain high-current drive type *2: Selected using the mask option (in units of 4 pins). (MQP-80C-P01) P20/EC P21*1 P22/TO

■ PIN DESCRIPTION (Continued)*1: FPT -80P-M11 *2: FPT -80P-M06 *3: FPT -80P-M05 *4: MQP-80C-P01 Pin no. Pin name Circuit type Function LQFP *1*3 MQFP *4 QFP *2 16 18 X0 A Main clock oscillator pins 15 17 X1 18 20 MOD0 C Operating mode selection pins Connect directly to V SS .17 19 MOD1 19 21 RST D Reset I/O pin This pin is an N-ch open-drain output type with a pull- up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 20 to 27 22 to 29 P00/INT20 to P07/INT27 E General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. 28 to 31 30 to 33 P10/INT10 to P13/INT13 E General-purpose I/O ports Also serve as external interrupt 1 input. External interrupt 1 input is hysteresis input. 32 to 35 34 to 37 P14 to P17 F General-purpose I/O ports 36 38 P20/EC H N-ch open-drain general-purpose I/O port Also serves as the external clock input for the timer. The peripheral is a hysteresis input type. 37 39 P21 I N-ch open-drain general-purpose I/O port 38 40 P22/TO I N-ch open-drain general-purpose I/O port Also serves as a timer output. 39 41 P23/SI H N-ch open-drain general-purpose I/O port Also serves as the data input for the 8-bit serial I/O. The peripheral is a hysteresis input type. 40 42 P24/SO I N-ch open-drain general-purpose I/O port Also serves as the data output for the 8-bit serial I/O. 41 43 P25/SCK H N-ch open-drain general-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O. The peripheral is a hysteresis input type. 42 44 P26 I N-ch open-drain general-purpose I/O port 43 45 P27/BUZ I N-ch open-drain general-purpose I/O port Also serves as a buzzer output.

(Continued) *1: FPT -80P-M11 *2: FPT -80P-M06 *3: FPT -80P-M05 *4: MQP-80C-P01 Pin no. Pin name Circuit type Function LQFP *1*3 MQFP *4 QFP *2 48 50 P32 J Functions as an N-ch open-drain general-purpose output port only in the products without a booster. C0 — Functions as a capacitor connection pin in the products with a booster. 47 49 P31 J Functions as an N-ch open-drain general-purpose output port only in the products without a booster. C1 — Functions as a capacitor connection pin in the products with a booster. 46 48 P30/RCO G General-purpose output-only port Also serves as a remote control transmission output. 14 16 P57/SEG35 J/K N-ch open-drain general-purpose output ports Also serve as LCD controller/driver segment output. Switching between port and common output is done by the mask option. 12 to 6 14 to 8 P56/SEG34 to P50/SEG28 5 to 1 7 to 3 P47/SEG27 to P43/SEG23 J/K 80, 79, P42/SEG22, P41/SEG21, P40/SEG20 77 to 58 79 to 60 SEG19 to SEG0 K LCD controller/driver segment output-only pins 57 to 54 59 to 56 COM3 to COM0 K LCD controller/driver common output-only pins 52 to 49 54 to 51 V3 to V0 — LCD driving power supply pins 44 46 X0A B Subclock crystal oscillator pins (32.768 kHz) 45 47 X1A 53 55 V CC — Power supply pin 13 15 V SS — Power supply (GND) pin

• External EPROM pins (MB89PV150 only) Pin no. Pin name I/O Function

82 V PP O “H” level output pin

SS O Power supply (GND) pin 100 101 102 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby.

104 A10 O Address output pin

105 OE O ROM output enable pin

Outputs “L” at all times. 107 108 109 A11 O Address output pins

110 A13 O

111 A14 O

CC O EPROM power supply pin 106 N.C. — Internally connected pins Be sure to leave them open.

■ I/O CIRCUIT TYPE (Continued) Type Circuit Remarks A Crystal or ceramic oscillation type (main clock)

• At an oscillation feedback resistor of approximately 1 MΩ /5.0 V CR oscillation type (main clock) (except MB89PV150/P155) B Crystal oscillation type (subclock)
• At an oscillation feedback resistor of approximately 4.5 MΩ /3.0 V C D • At output pull-up resistor (P-ch) of approximately 50 kΩ /5.0 V
• Hysteresis input E • CMOS I/O
• The peripheral is a hysteresis input type.
• Pull-up resistor optional (except MB89PV150) Standby control signal Standby control signal X1A X0A Standby control signal R P-ch N-ch P-ch N-ch Port Peripheral P-chR

(Continued) Type Circuit Remarks F • CMOS I/O

• Pull-up resistor optional (except MB89PV150) G • CMOS output
• P-ch output is a high-current drive type. H • N-ch open-drain I/O
• CMOS input
• The peripheral is a hysteresis input type.
• Pull-up resistor optional (except MB89PV150/P155) I • N-ch open-drain I/O
• CMOS input
• P21, P26, and P27 are a high-current drive type.
• Pull-up resistor optional (except MB89PV150/P155) J • N-ch open-drain output
• Pull-up resistor optional (except MB89PV150/P155)
• P31 and P32 are not provided with a pull-up resistor. K • LCD controller/driver segment output P-ch N-ch P-ch R P-ch N-ch N-ch Port Peripheral P-ch R N-ch P-ch R N-ch P-chR P-ch N-ch P-ch N-ch

■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS . When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC ) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that V CC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.

■ PROGRAMMING TO THE EPROM ON THE MB89P155 The MB89P155 is an OTPROM version of the MB89150/A series. 1. Features

• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in the EPROM mode is diagrammed below. PROM FFFF H 0000 H 8000 H 0180 H Not available Normal operating mode I/O RAM C000 H Not available 7FFF H 0000 H 4000 H Program area (EPROM) Option area Address EPROM mode (Corresponding addresses on the EPROM programmer) Vacancy (Read value FFH ) Vacancy (Read value FFH ) 3FF0 H 3FF6 H 0080 H

1. Programming to the EPROM In EPROM mode, the MB89P155 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter.

• Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a normal operating mode assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options.”) (3) Program with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Package Compatible socket adapter FPT-80P-M05 ROM-80SQF-28DP-8L FPT-80P-M06 ROM-80QF-28DP-8L3 FPT-80P-M11 ROM-80QF2-28DP-8L2 Program, verify Aging +150°C, 48 Hrs. Data verification Assembly

1. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map:

• OTPROM option bit map Notes:• Set each bit to 1 to erase.
• Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FF0H Vacancy Readable Vacancy Readable Oscillation stabilization time WTM1 WTM0 See section “■ Mask Options.” Vacancy Readable Reset pin output 1: Y es 0: No Clock mode selection 1: Dual clock 0: Single clock Power-on reset 1: Y es 0: No 3FF1H P07 Pull-up 1: No 0: Y es P06 Pull-up 1: No 0: Y es P05 Pull-up 1: No 0: Y es P04 Pull-up 1: No 0: Y es P03 Pull-up 1: No 0: Y es P02 Pull-up 1: No 0: Y es P01 Pull-up 1: No 0: Y es P00 Pull-up 1: No 0: Y es 3FF2 H P17 Pull-up 1: No 0: Y es P16 Pull-up 1: No 0: Y es P15 Pull-up 1: No 0: Y es P14 Pull-up 1: No 0: Y es P13 Pull-up 1: No 0: Y es P12 Pull-up 1: No 0: Y es P11 Pull-up 1: No 0: Y es P10 Pull-up 1: No 0: Y es 3FF3H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable 3FF4H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable 3FF5H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 3. Memory Space Memory space in each mode is diagrammed below. 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH . (3) Program to 0000H to 7FFFH with the EPROM programmer. Package Adapter socket part number LCC-32(Rectangle) ROM-32LC-28DP-YG LCC-32(Square) ROM-32LC-28DP-S PROM 32 KB FFFF H 0000 H 8000 H 0080 H 0280 H Normal operating mode I/O RAM Not available 7FFF H 0000 H EPROM 32 KB Address Corresponding addresses on the EPROM programmer

■ BLOCK DIAGRAM Main clock oscillator Clock controller Subclock oscillator (32.768 kHz) 21-bit time-base timer External interrupt 2 (wake-up function) CMOS I/O port CMOS I/O port F 2MC-8L CPU RAM (Max. 256 × 8bits) MOD0, MOD1, V CC , V SS X0A X1A RST P00/INT20 to P07/INT27 ROM (Max. 16 K × 8 bits) 8-bit serial I/O N-ch open-drain I/O port P21*4,P26*4 P27/BUZ*4 P25/SCK P24/SO P23/SI Reset circuit (WDT) 8-bit timer/counter N-ch open-drain output port (Only P30 is a CMOS output type.) 16 4 P22/TO P20/EC SEG0 to SEG19 V0 to V3 P54/SEG32*3 to P57/SEG35*3 P44/SEG24*3 to P47/SEG27*3 P40/SEG20*3 to P43/SEG23*3 P32/C0*2 LCD controller/ driver External interrupt 1 (wake-up function) P10/INT10 to P13/INT13 Buzzer output 8-bit timer/counter Remote control output Reference voltage generator and booster* P50/SEG28*3 to P53/SEG31*3 COM0 to COM3 P31/C1*2 P30/RCO P14 to P17 N-ch open-drain output port Port 0 *1: Selected by mask option *2: Used as ports without a reference voltage generator and booster *3: Functions selected by mask option *4: N-ch open-drain high-current drive type Port 1 Internal bus Port 2Port 4 and port 5Port 3 36 × 4 bits VRAM Other pins

■ CPU CORE 1. Memory Space The microcontrollers of the MB89150/A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89150/A series is structured as illustrated below. Memory Space 0000H 0080H 0100H 0200H 0280H 8000H MB89PV150 I/O RAM 512 B Register Not available External ROM 32 KB 0000H 0080H 0100H 0140H F000H FFFF H MB89151/A I/O RAM 128 B Register ROM 4 KB 0000H 0080H 0100H 0180H E800H FFFF H MB89152/A I/O RAM 256 B Register ROM 6 KB 0000H 0080H 0100H 0180H E000H FFFF H MB89153/A I/O RAM 256 B Register ROM 8 KB 0000H 0080H 0100H 0180H D000 H FFFF H MB89154/A I/O RAM 256 B Register ROM 12 KB FFFF H 00C0 H 0000H 0080H 0100H 0180H C000 H FFFF H MB89155/A MB89P155 I/O RAM 256 B Register ROM 16 KB Not available Not available Not available Not available Not available Not available

1. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) PC A T IX EP SP PS 16 bits : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFD H Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. Initial value Structure of the Program Status Register Vacancy H I IL1, 0 N Z VC RPPS 1 0 9876 321015 14 13 12 11 RP CCR Vacancy Vacancy

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. IL1 IL0 Interrupt level High-low High Low = no interrupt 10 2 11 3 Rule for Conversion of Actual Addresses of the General-purpose Register Area “0” A15 “0” A14 “0” A13 “0” A12 “0” A11 “0” A10 “0” “1” RP Generated addresses Lower OP codes

The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 8 banks can be used on the MB89151 (RAM 128 × 8 bits), and a total of 16 banks can be used on the MB89152/3/4/5 (RAM 256 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration R 1 R 2 R 3 R 4 R 5 R 6 R 7 This address = 0100H + 8 × (RP) Memory area 8 banks (MB89151) 16 banks (MB89152/3/4/5) R 0

■ I/O MAP (Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) DDR2 Port 2 data direction register 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0C H (R/W) PDR3 Port 3 data register 0D H Vacancy 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) PDR5 Port 5 data register 10H (R/W) BZCR Buzzer register 11H Vacancy 12H Vacancy 13H Vacancy 14H (R/W) RCR1 Remote control transmission register 1 15H (R/W) RCR2 Remote control transmission register 2 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR1 Serial mode register 1D H (R/W) SDR1 Serial data register 1EH to 2FH Vacancy

(Continued) Note: Do not use vacancies. Address Read/write Register name Register description 30H (R/W) EIE1 External interrupt 1 enable register 31H (R/W) EIF1 External interrupt 1 flag register 32H (R/W) EIE2 External interrupt 2 enable register 33H (R/W) EIF2 External interrupt 2 flag register 34H to 5FH Vacancy 60H to 71H (R/W) VRAM Display data RAM 72H (R/W) LCR1 LCD controller/driver control register 1 73H to 7BH Vacancy 7C H (W) ILR1 Interrupt level setting register 1 7D H (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy

■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings ( VSS = 0.0 V) (Continued) Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC VSS – 0.3 V SS + 7.0 V LCD power supply voltage V0 to V3 VSS – 0.3 V SS + 7.0 V V0 to V3 pins on the product with booster VSS – 0.3 V CC + 0.3 V V0 to V3 pins on the product without booster Input voltage VI1 VSS – 0.3 V CC + 0.3 V VI1 must not exceed VSS +7.0 V. All pins except P20 to P27 without a pull-up resistor VI2 VSS – 0.3 V SS + 7.0 V P20 to P27 without a pull-up resistor Output voltage VO1 VSS – 0.3 V CC + 0.3 V VO1 must not exceed VSS +7.0 V. All pins except P20 to P27, P31, P32, P40 to P47, P50 to P57 without a pull-up resistor V O2 VSS – 0.3 V SS + 7.0 V P20 to P27, P31, P32, P40 to P47, and P50 to P57, without a pull-up resistor “L” level maximum output current IOL1 —1 0 m A All pins except P21, P26, P27, and power supply pins IOL2 — 20 mA P21, P26, and P27 “L” level average output current IOLAV1 —4 m A Average value (operating current × operating rate) All pins except P21, P26, P27, and power supply pins. IOLAV2 —8 m A Average value (operating current × operating rate) P21, P26, and P27 “L” level total maximum output current ∑ IOL —8 0 m A “L” level total average output current ∑ IOLAV —4 0 m A Average value (operating current × operating rate) “H” level maximum output current IOH1 —– 5 m A All pins except P30 and power supply pins IOH2 — –10 mA P30

(Continued) (VSS = 0.0 V) Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Recommended Operating Conditions (VSS = 0.0 V) *1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for the operating frequency. *2: The LCD power supply voltage range and optimum value vary depending on the characteristics of the liquid- crystal display element. Parameter Symbol Value Unit Remarks Min. Max. “H” level average output current IOHAV1 —– 2 m A Average value (operating current × operating rate) All pins except P30 and power supply pins. IOHAV2 —– 4 m A Average value (operating current × operating rate) P30 “H” level total output current∑ IOH — –20 mA “H” level total average output current ∑ IOHAV — –10 mA Average value (operating current × operating rate) Power consumption P D — 300 mW Operating temperature T A –40 +85 °C Storage temperature Tstg –55 +150 °C Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC 2.2*1 6.0 V Normal operation assurance range Single clock system of the mask ROM product. 2.2*1 4.0 V Normal operation assurance range Dual-clock system of the mask ROM product. 2.7*1 6.0 V MB89P155/PV150 1.5 6.0 V Retains the RAM state in stop mode LCD power supply voltage V0 to V3 V SS VCC *2 V V0 to V3 pins LCD reference power supply input voltage VIR 1.3 2.2 V V1 pin on the products with a booster Reference power external input Operating temperature T A –40 +85 °C

1. DC Characteristics (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) (Continued) Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. “H” level input voltage VIH P00 to P07, P10 to P17, P20 to P27 0.7 V CC  VCC + 0.3 V CMOS input VIHS RST , MOD0, MOD1, EC, SI, SCK, INT10 to INT13, INT20 to INT27 0.8 VCC  VSS + 0.3 V Hysteresis input “L” level input voltage VIL P00 to P07, P10 to P17, P20 to P27 VSS − 0.3  0.3 VCC V CMOS input VILS RST , MOD0, MOD1, EC, SI, SCK, INT10 to INT13, INT20 to INT27 VSS − 0.3  0.2 VCC V Hysteresis input Open-drain output pin application voltage V D P20 to P27, P31, P32, P40 to P47, P50 to P57 VSS − 0.3  VSS + 6.0*1 V Without pull-up resistor “H” level output voltage VOH1 P00 to P07, P10 to P17IOH = –2.0 mA 2.4  V VOH2 P30 I OH = –6.0 mA 4.0 — — V “L” level output voltage VOL1 P00 to P07, P10 to P17, P20, P22 to P25, P30 to P32, P40 to P47, P50 to P57 IOL = 1.8 mA —  0.4 V VOL2 P21, P26, P27 I OL = 8.0 mA — — 0.4 V VOL3 RST IOL = 4.0 mA — — 0.4 V Input leakage current (Hi-z output leakage current) ILI1 MOD0, MOD1, P30, P00 to P07, P10 to P170.0 V < VI < VCC — ± 5 µA Without pull-up resistor ILI2 P20 to P27, P31, P32, P40 to P47, P50 to P570.0 V < VI < 6.0 V —— ±1 µA Without pull-up resistor Pull-up resistance RPULL P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, RST VI = 0.0 V 25 50 100 k Ω With pull-up resistor Common output impedance RVCOM COM0 to COM3 V1 to V3 = 5.0 V—— 2 . 5 k Ω Segment output impedance RVSEG SEG0 to SEG35 V1 to V3 = 5.0 V— — 15 k Ω LCD divided resistance R LCD — Between VCC and V0 300 500 750 k Ω Products without a booster only LCD leakage current I LCDL V0 to V3, COM0 to COM3, SEG0 to SEG35 —— — ±1 µA

(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) (Continued) Parameter Symbol Pin Condition Value Unit RemarksMin. Typ. Max. Booster for LCD driving output voltage VOV3 V3 V1 = 1.5 V 4.3 4.5 4.7 V Products with a booster only VOV2 V2 2.9 3.0 3.1 V Reference output voltage for LCD driving V OV1 V1 I IN = 0 µA 1.3 1.5 1.7 V Power supply current*2 ICC1 VCC FCH = 4.2 MHz, VCC = 5.0 V tinst*3 = 0.95 µs Main clock operation — 3.0 4.5 mA MB89151/A, 152/A, 153/A, 154/A, 155/A, MB89PV150- 101 to 105 — 3.8 6.0 mA MB89P155-101 to 105/201 to 205 ICC2 FCH = 4.2 MHz, VCC = 3.0 V tinst*3 = 15.2 µs Main clock operation — 0.25 0.4 mA MB89151/A, 152/A,153/A, 154/A, 155/A, MB89PV150- 101 to 105 — 0.85 1.4 mA MB89P155-101 to 105/201 to 205 ICCL FCL = 32.768 kHz, VCC = 3.0 V tinst*3 = 61 µs Subclock operation — 0.05 0.1 mA MB89151/A, 152/A, 153/A, 154/A, 155/A, MB89PV150- 101 to 105 — 0.65 1.1 mA MB89P155-101 to 105/201 to 205 ICCS1 FCH = 4.2 MHz, VCC = 5.0 V tinst*3 = 0.95 µs Main clock sleep mode — 0.8 1.2 mA I CCS2 FCH = 4.2 MHz, VCC = 3.0 V tinst*3 = 15.2 µs Main clock sleep mode — 0.2 0.3 mA I CCSL FCL = 32.768 kHz, VCC = 3.0 V tinst*3 = 61 µs Subclock sleep mode —2 55 0 µA

(Continued) (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) *1: P31 and P32 are applicable only for products of the MB89150 series (without the “A” suffix). P40 to P47 and P50 to P57 are applicable when selected as ports. *2: The power supply current is measured at the external clock, open output pins, and the external LCD dividing resistor (or external input for the reference voltage). In the case of the MB89PV150, the current consumed by the connected EPROM and ICE is not included. *3: For information on t inst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note: For pins which serves as the segment (SEG20 to SEG35) and ports (P40 to P47, P50 to P57), see the port parameter when these pins are used as ports and the segment parameter when they are used as segments. P31 and P32 are applicable only for products without a booster (applicable as external capacitor connection pins for products with a booster). Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. Power supply current*2 ICCT VCC FCL = 32.768 kHz, VCC = 3.0 V Watch mode —1 01 5 µA MB89151/2/3/4/5, MB89P155-101 to 105, MB89PV150-101 to 105 ICCT2 FCL = 32.768 kHz, VCC = 3.0 V

• Watch mode
• D u r i n g reference voltage generator and booster operation — 250 400 µA MB89151A/2A/ 3A/4A/5A, MB89P155-201 to 205 ICCH TA = +25°C, VCC = 5.0 V Stop mode —0 . 1 1 µA MB89151/2/3/4/5 —0 . 11 0 µA MB89PV150-101 to 105, MB89P155-101 to 105 Input capacitance CIN Other than VCC , VSS f = 1 MHz — 10  pF

1. AC Characteristics (1) Reset Timing (VSS = 0.0 V, TA = –40°C to +85°C) (2) Power-on Reset (VSS = 0.0 V, TA = –40°C to +85°C) Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. Parameter Symbol Condition Value Unit Remarks Min. Max. RST “L” pulse width t ZLZH —4 8 t HCYL —n s Parameter Symbol Condition Value Unit Remarks Min. Max. Power supply rising time tR — 50 ms Power-on reset function only Power supply cut-off time tOFF 1 — ms Due to repeated operations

0.2 VCC

0.2 V 0.2 V 2.0 V 0.2 V tR VCC tOFF

(3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. Clock frequency FCH X0, X1 1 — 4.2 MHz Main clock FCL X0A, X1A — 32.768 — kHz Subclock Clock cycle time tHCYL X0, X1 238 — 1000 ns Main clock tLCYL X0A, X1A — 30.5 — µs Subclock Input clock pulse width PWH PWL X0 20 — — ns External clockPWHL PWLL X 0 A —1 5 . 2— µs Input clock pulse rising/falling time tCR tCF X0, X0A — — 10 ns

0.8 VCC

C FCH R X0 X1 FCH X0 and X1 Timing and Conditions Main Clock Conditions

(4) Instruction Cycle Parameter Symbol Value Unit Remarks Instruction cycle (minimum execution time)tinst 4/FCH , 8/FCH , 16/FCH , 64/FCH µs (4/FCH ) tinst = 0.95 µs when operating at FCH = 4.2 MHz 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz R X0A X1A FCL Open X0A and X1A Timing and Conditions Subclock Conditions

(5) Serial I/O Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Condition Value Unit Remarks Min. Max. Serial clock cycle time t SCYC SCK Internal shift clock mode 2 tinst*— µs SCK ↓ → SO time t SLOV SCK, SO –200 200 ns Valid SI → SCK ↑ tIVSH SI, SCK 0.5 t inst*— µs SCK ↑ → valid SI hold time tSHIX SCK, SI 0.5 t inst*— µs Serial clock “H” pulse width tSHSL SCK External shift clock mode 1 tinst*— µs Serial clock “L” pulse width tSLSH SCK 1 t inst*— µs SCK ↓ → SO time t SLOV SCK, SO 0 200 ns Valid SI → SCK ↑ tIVSH SI, SCK 0.5 t inst*— µs SCK ↑ → valid SI hold time tSHIX SCK, SI 0.5 t inst*— µs tSCYC tSLOV tSLOV tSHIXtIVSH SCK 2.4 V 0.8 V 0.8 V 2.4 V 0.8 V SCK 0.8 VCC 2.4 V 0.8 V

(6) Peripheral Input Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) * : For information on tinst, see “(4) Instruction Cycle.” Parameter Symbol Pin Value Unit Remarks Min. Max. Peripheral input “H” pulse width 1 tILIH1 INT10 to INT13, EC 1 tinst*— µs Peripheral input “L” pulse width 1 tIHIL1 1 tinst*— µs Peripheral input “H” pulse width 2 tILIH2 INT20 to INT27 2 tinst*— µs Peripheral input “L” pulse width 2 tIHIL2 2 tinst*— µs INT10 to 13, EC INT20 to 27 tIHIL1

■ EXAMPLE CHARACTERISTICS (Continued) (1) “L” Level Output Voltage (2) “H” Level Output Voltage 0.6 0.5 0.4 0.3 0.2 0.1 V OL1 (V) IOL (mA) 2468 1 0 VCC = 2.0 V VCC = 3.0 V 13579 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V TA = +25°C VOL1 vs. IOL 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 4 8 12 16 20 VCC = 2.0 VVOL2 (V) IOL (mA ) VCC = 2.5 VVCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 2 6 10 14 18 TA = +25°C VOL2 vs. IOL 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 VVCC – VOH1 (V) IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC – VOH1 vs. IOH 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 2.0 VVCC – VOH2 (V) IOH (mA) VCC = 2.5 V VCC = 4.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V TA = +25°C VCC – VOH2 vs. IOH

(Continued) ICC2 (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 V CC (V) ICC2 vs. VCC (Mask ROM product) FCH = 3 MHz FCH = 4.2 MHz FCH = 1 MHz TA = +25°C 1234567 ICC1 (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 01234567 V CC (V) ICC1 vs. VCC (Mask ROM product) FCH = 3 MHz FCH = 4.2 MHz FCH = 1 MHz TA = +25°C 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V CC (V) V IN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VIHS VILS VCC (V) V IN (V) TA = +25°C TA = +25°C VIN vs. VCC V IN vs. VCC 1234567 (3) “H” Level Input Voltage/“L” level Input Voltage (4) Power Supply Current (External Clock) VIHS: Threshold when input voltage in hysteresis VILS: Threshold when input voltage in hysteresis characteristics is set to “H” level characteristics is set to “L” level (CMOS input) (Hysteresis input)

(Continued) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 I CCS1 (mA) ICCS1 vs. VCC TA = +25°C FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz VCC (V) 1234567 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ICCS2 (mA) ICCS2 vs. VCC FCH = 4.2 MHz FCH = 3 MHz FCH = 1 MHz TA = +25°C VCC (V) 1234567 200 180 160 140 120 100 ICCL (µA) ICCL vs. VCC (Mask ROM product) FCL = 32.768 kHz TA = +25°C 1234567 VCC (V) I CCT (µA) ICCT vs. VCC FCL = 32.768 kHz TA = +25°C 1234567 VCC (V)

(Continued) (5) Pull-up Resistance 200 180 160 140 120 100 ICCSL (µA) ICCSL vs. VCC FCL = 32.768 kHz TA = +25°C 1234567 VCC (V) 1,000 900 800 700 600 500 400 300 200 100 ICCT2 (µA) ICCT2 vs. VCC FCL = 32.768 kHz TA = +25°C 1234567 VCC (V) 1234567 1,000 R PULL (kΩ ) VCC (V) 500 100 TA = +25°C TA = +85°C TA = –40°C

■ INSTRUCTIONS Execution instructions can be divided into the following four groups:

• Transfer
• Arithmetic operation
• Branch
• Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols (Continued) Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits)

(Continued) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: “–” indicates no change.

• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction is executed.
• 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F . Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ( × ) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Table 2 Transfer Instructions (48 instructions) Notes:• During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 48 to 4F 08 to 0F 88 to 8F A8 to AF A0 to A7

Table 3 Arithmetic Operation Instructions (62 instructions) (Continued) Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) dL dH dH dH dH dH dH dH dH + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + – – – – – – – – – + + – – + + + – – – – – – – – – + + – – – – – – – – – – + + R – + + R – + + R – + + + + + + + + + + – + + + – + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – 28 to 2F 38 to 3F C8 to CF D8 to DF 18 to 1F 58 to 5F A C AC

(Continued) Table 4 Branch Instructions (17 instructions) Table 5 Other Instructions (9 instructions) Mnemonic ~ # Operation TL TH AH N Z V C OP code AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + + + + + + + + + + + + + + + – – – – – – – – 68 to 6F 78 to 7F 98 to 9F Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call Return from subrountine Return form interrupt dH – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + – – – + – – – – – – – – – – – – – – – – – – – – – – – – – – Restore FD FC FB FA FF FE B0 to B7 B8 to BF E8 to EF Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI dH – – – – – – – – – – – – – – – – – – – – – – – R – – – S – – – – – – – –

■ INSTRUCTION MAP0123456789A B C D EF

0 NOP SWAP RET RETI PUSHW

A POPW A MOV A,ext MOVW A,PS CLRI SETI CLRB dir: 0 BBC dir: 0,rel INCW A DECW A JMP MOVW A,PC

1 MULU

A DIVU A JMP addr16 CALL addr16 PUSHW IX POPW IX MOV ext,A MOVW PS,A CLRC SETC CLRB dir: 1 BBC dir: 1,rel INCW SP DECW SP MOVW SP ,A MOVW A,SP

2 ROLC

A CMP A ADDC A SUBC A XCH A, T XOR A AND A OR A MOV @A,T MOV A,@A CLRB dir: 2 BBC dir: 2,rel INCW IX DECW IX MOVW IX,A MOVW A,IX

3 RORC

A CMPW A ADDCW A SUBCW A XCHW A, T XORW A ANDW A ORW A MOVW @A,T MOVW A,@A CLRB dir: 3 BBC dir: 3,rel INCW EP DECW EP MOVW EP ,A MOVW A,EP

4 MOV

A,#d8 CMP A,#d8 ADDC A,#d8 SUBC A,#d8 XOR A,#d8 AND A,#d8 OR A,#d8 DAA DAS CLRB dir: 4 BBC dir: 4,rel MOVW A,ext MOVW ext,A MOVW A,#d16 XCHW A,PC

5 MOV

A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#d8 CMP dir,#d8 CLRB dir: 5 BBC dir: 5,rel MOVW A,dir MOVW dir,A MOVW SP ,#d16 XCHW A,SP

6 MOV

A,@IX +d CMP A,@IX +d ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A XOR A@,IX +d AND A,@IX +d OR A,@IX +d MOV @IX +d,#d8 CMP @IX +d,#d8 CLRB dir: 6 BBC dir: 6,rel MOVW A,@IX +d MOVW @IX +d,A MOVW IX,#d16 XCHW A,IX

7 MOV

A,@EP CMP A,@EP ADDC A,@EP SUBC A,@EP MOV @EP ,A XOR A,@EP AND A,@EP OR A,@EP MOV @EP ,#d8 CMP @EP ,#d8 CLRB dir: 7 BBC dir: 7,rel MOVW A,@EP MOVW @EP ,A MOVW EP ,#d16 XCHW A,EP

8 MOV

A,R0 CMP A,R0 ADDC A,R0 SUBC A,R0 MOV R0,A XOR A,R0 AND A,R0 OR A,R0 MOV R0,#d8 CMP R0,#d8 SETB dir: 0 BBS dir: 0,rel INC DEC CALLV BNC rel

9 MOV

A,R1 CMP A,R1 ADDC A,R1 SUBC A,R1 MOV R1,A XOR A,R1 AND A,R1 OR A,R1 MOV R1,#d8 CMP R1,#d8 SETB dir: 1 BBS dir: 1,rel INC DEC CALLV BC rel A MOV A,R2 CMP A,R2 ADDC A,R2 SUBC A,R2 MOV R2,A XOR A,R2 AND A,R2 OR A,R2 MOV R2,#d8 CMP R2,#d8 SETB dir: 2 BBS dir: 2,rel INC DEC CALLV BP rel B MOV A,R3 CMP A,R3 ADDC A,R3 SUBC A,R3 MOV R3,A XOR A,R3 AND A,R3 OR A,R3 MOV R3,#d8 CMP R3,#d8 SETB dir: 3 BBS dir: 3,rel INC DEC CALLV BN rel C MOV A,R4 CMP A,R4 ADDC A,R4 SUBC A,R4 MOV R4,A XOR A,R4 AND A,R4 OR A,R4 MOV R4,#d8 CMP R4,#d8 SETB dir: 4 BBS dir: 4,rel INC DEC CALLV BNZ rel D MOV A,R5 CMP A,R5 ADDC A,R5 SUBC A,R5 MOV R5,A XOR A,R5 AND A,R5 OR A,R5 MOV R5,#d8 CMP R5,#d8 SETB dir: 5 BBS dir: 5,rel INC DEC CALLV BZ rel E MOV A,R6 CMP A,R6 ADDC A,R6 SUBC A,R6 MOV R6,A XOR A,R6 AND A,R6 OR A,R6 MOV R6,#d8 CMP R6,#d8 SETB dir: 6 BBS dir: 6,rel INC DEC CALLV BGE rel F MOV A,R7 CMP A,R7 ADDC A,R7 SUBC A,R7 MOV R7,A XOR A,R7 AND A,R7 OR A,R7 MOV R7,#d8 CMP R7,#d8 SETB dir: 7 BBS dir: 7,rel INC DEC CALLV BLT rel L H

■ MASK OPTIONS No. Part number MB89151/1A, 2/2A, 3/3A, 4/4A, 5/5A MB89P155 MB89PV150 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible

1 Pull-up resistors

P00 to P07, P10 to P17 Selectable per pin Can be set per pin Fixed to without a pull-up resistor2 Pull-up resistors P40 to P47, P50 to P57 Selectable per pin (Only when segment output is not selected.) Fixed to without a pull-up resistor

3 Pull-up resistors

P20 to P27 Selectable by pin Fixed to without a pull-up resistor Power-on reset With power-on reset Without power-on reset Selectable Selectable Fixed to with power-on reset Selection of oscillation stabilization time

• The initial value of the oscillation stabilization time for the main clock can be set by selecting the values of the WTM1 and WTM0 bits on the right. Selectable WTM1 WTM0 00 : 2 2/FCH 01 : 2 12/FCH 10 : 2 16/FCH 11 : 2 18/FCH Selectable WTM1WTM0 00 : 2 2/FCH 01 : 2 12/FCH 10 : 2 16/FCH 11 : 2 18/FCH Fixed to oscillation stabilization time of 216/FCH Main clock oscillation type Crystal or ceramic resonator CR Selectable Fixed to crystal or ceramic only Fixed to crystal or ceramic Reset pin output With reset output Without reset output Selectable Selectable Fixed to with reset output Clock mode selection Dual-clock mode Single-clock mode Selectable Selectable Fixed to dual-clock mode Segment output selection 36: No ports selection 32: Selection of P57 to P54 28: Selection of P57 to P50 24: Selection of P57 to P50, and P47 to P44. 20: Selection of P57 to P50, and P47 to P40. Selectable Selection of the number of segments. -101/201: 36 segments -102/202: 32 segments -103/203: 28 segments -104/204: 24 segments -105/205: 20 segments -101: 36 segments -102: 32 segments -103: 28 segments -104: 24 segments -105: 20 segments

10 Selection of a built-in booster

Without booster: MB89151/2/3/4/5 With booster: MB89151A/2A/3A/4A/5A Without booster: -101 to 105 With booster: -201 to 205 Fixed to without booster (-100 to 105 only)

• Versions ■ ORDERING INFORMATION (Continued) Version Features Mass production product One-time PROM product Piggyback/evaluation product Number of segment pins Booster MB8915151A 152A 153A 154A 155A MB89P155-201 -202 -203 -204 -205 Yes MB8915151 152 153 154 155 MB89P155-101 -102 -103 -104 -105 MB89PV150-101 -102 -103 -104 -105 No Part number Package Remarks MB89151PF MB89152PF MB89153PF MB89154PF MB89155PF MB89P155PF-101 MB89P155PF-102 MB89P155PF-103 MB89P155PF-104 MB89P155PF-105 80-pin Plastic QFP (FPT-80P-M06) Without booster MB89151APF MB89152APF MB89153APF MB89154APF MB89155APF MB89P155PF-201 MB89P155PF-202 MB89P155PF-203 MB89P155PF-204 MB89P155PF-205 With booster

(Continued) Part number Package Remarks MB89151PFM MB89152PFM MB89153PFM MB89154PFM MB89155PFM MB89P155PFM-101 MB89P155PFM-102 MB89P155PFM-103 MB89P155PFM-104 MB89P155PFM-105 80-pin Plastic LQFP (FPT-80P-M11) Without booster MB89151APFM MB89152APFM MB89153APFM MB89154APFM MB89155APFM MB89P155PFM-201 MB89P155PFM-202 MB89P155PFM-203 MB89P155PFM-204 MB89P155PFM-205 With booster MB89151PFV MB89152PFV MB89153PFV MB89154PFV MB89155PFV MB89P155PFV-101 MB89P155PFV-102 MB89P155PFV-103 MB89P155PFV-104 MB89P155PFV-105 80-pin Plastic LQFP (FPT-80P-M05) Without booster MB89151APFV MB89152APFV MB89153APFV MB89154APFV MB89155APFV MB89P155PFV-201 MB89P155PFV-202 MB89P155PFV-203 MB89P155PFV-204 MB89P155PFV-205 With booster MB89PV150CF-101 MB89PV150CF-102 MB89PV150CF-103 MB89PV150CF-104 MB89PV150CF-105 80-pin Ceramic MQFP (MQP-80C-P01) Without booster

C 1995 FUJITSU LIMITED F80016S-1C-3 0.13(.005)M 0.10(.004)

1 PIN INDEX

.059−.004 +.008 −0.10 +0.20 1.50 "A" Details of "A" part 0 10˚ 0.50±0.20 0.10±0.10 (.004±.004) (.020±.008) (STAND OFF) (.012±.004) 0.127 +0.05 −0.02 +.002 −.001.005 12.35 15.00 (.486) REF (.591) NOM 4160 LEAD No. ■ PACKAGE DIMENSIONS "A" LEAD No. (.031±.008) 0.80±0.20 0.30(.012) 0.25(.010) 64 41 241 18.40(.724)REF INDEX (STAND OFF) 0.05(.002)MIN 3.35(.132)MAX (.642±.016) 16.30±0.40 REF 12.00(.472) Details of "B" part 0 10° Details of "A" part 0.18(.007)MAX 0.58(.023)MAX 0.10(.004) "B"

1994 FUJITSU LIMITED F80010S-3C-2C

Dimensions in mm (inches) 80-pin Plastic QFP (FPT -80P-M06) Dimensions in mm (inches) 80-pin Plastic LQFP (FPT -80P-M11) (Mounting height)

C 1995 FUJITSU LIMITED F80008S-2C-5 0.10(.004) 0.10±0.10 (.004±.004) Details of "A" part 0 10˚ 9.50 13.00 (.374) REF (.512) NOM 0.50±0.08 +.003 −0.03 +0.08 0.18 .005−.001 +.002 −0.02 +0.05 0.127 .059−.004 +.008 −0.10 +0.20 1.50 "A" 1 20 4160 61 40 INDEX (STAND OFF) LEAD No. Dimensions in mm (inches) 80-pin Plastic LQFP (FPT -80P-M05) +0.40 –0.20 +.016 –.008 +0.40 –0.20 +.016 –.008 INDEX TYP 4.50(.177) TYP 6.00(.236) INDEX AREA 1.50(.059)TYP 1.00(.040)TYP TYP 1.00(.040) TYP 1.50(.059) (.0315±.010) 0.80±0.25 1.20 .047 12.00(.472)TYP (.0315±.010) 0.80±0.25 REF 18.40(.724) (.016±.004) 0.40±0.10 1.20 .047(.016±.004) 0.40±0.10 MAX 8.70(.343) (.006±.002) 0.15±0.05 11.68(.460)TYP 9.48(.373)TYP 7.62(.300)TYP 0.30(.012)TYP (.050±.005) 1.27±0.13 (.713±.008) 18.12±0.20 TYP 14.22(.560) TYP 12.02(.473) TYP 10.16(.400) TYP 24.70(.972) (.878±.013) 22.30±0.33 (.050±.005) 1.27±0.13 TYP 0.30(.012) INDEX AREA 18.70(.736)TYP (.642±.013) 16.30±0.33 (.613±.008) 15.58±0.20

1994 FUJITSU LIMITED M80001SC-4-2C Dimensions in mm (inches)

(MQP-80C-P01) (Mounting height)

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