MB89120

MB89121 FUJITSU | Alldatasheet

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DS07-12509-6EFUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89120/120A Series MB89121/P131/123A/P133A/125A/P135A/ MB89PV130A nnnn DESCRIPTION The MB89120 series is a line of single-chip microcontrollers containing a compact instruction set and a great variety of peripheral functions such as a timer, serial interface, and external interrupt. The MB89120A series is an extended variant of the MB89120, with a remote control transmission function and wake-up interrupt channels. nnnn FEATURES

• F 2MC-8L family CPU core
• Low-voltage operation
• Low current consumption (allowing for dual clock)
• Minimum execution time : 0.95 ms at 4.2 MHz
• 21-bit timebase counter
• I/O ports : Max. 36 ports
• External interrupts : 3 channels
• External interrupts (wake-up function) : 8 channels (only in the MB89120A series)
• 8-bit serial I/O : 1 channel
• 8-/16-bit timer/counter : 1 channel
• Built-in remote-control transmitting frequency generator (only in the MB89120A series)
• Low-power consumption modes (stop mode, sleep mode, watch mode)
• Package : QFP-48
• CMOS technology nnnn PACKAGE 48-pin plastic QFP (FPT-48P-M13)

• : Varies with conditions such as operating frequencies. (See “n ELECTRICAL CHARACTERISTICS”.) (Continued) Part number MB89121 MB89123A MB89125A MB89P133A MB89P131 Item Classification Mass-produced products (Mask ROM products) One-time products ROM size

4 K · 8 bits

(internal mask ROM)

8 K · 8 bits

(internal mask ROM)

16 K · 8 bits

(internal mask ROM) (Internal PROM to be programmed with a general- purpose EPROM programmer) (Internal PROM to be programmed with a general- purpose EPROM programmer) RAM size 128 · 8 bits 256 · 8 bits 128 · 8 bits CPU functions The number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.95 ms at 4.2 MHz : 8.57 ms at 4.2 MHz Ports Output ports (N-ch open-drain) Output ports (CMOS) I/O ports (CMOS) Total : 4 (All also serves as peripherals.) : 8 : 24 (8 ports also serve as peripherals.) : 36 Timer/counter 8-bit timer/counter · 2 channels or 16-bit event counter · 1 channel Serial I/O 8 bits LSB/MSB first selectable External interrupt 1

3 Independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge/both edges selectable Also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode) External interrupt 2 (wake-up function) ¾ 8 channels (only for level detection) ¾ Remote control transmitting frequen- cy generator 1 channel (pulse width and frequency selectable by program) Standby mode Sleep mode, stop mode, watch mode Process CMOS Operating voltage* 2.2 V to 4.0 V (with the dual clock option) 2.2 V to 6.0 V (with the single clock option) 2.7 V to 6.0 V EPROM for use ¾

(Continued) Part number MB89P135A MB89PV130A Item Classification One-time PROM products Piggyback/evaluation product ROM size (internal PROM, to be programmed with general-purpose EPROM programmer)

32 K · 8 bits

(external ROM) RAM size 512 · 8 bits 1 K · 8 bits CPU functions The number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.95 ms/4.2 MHz : 8.57 ms/4.2 MHz Ports Output ports (N-ch open-drain ports) Output ports (CMOS) I/O ports (CMOS) Total : 4 (All also serve as peripherals.) : 8 : 24 (8 ports also serve as peripherals.) : 36 Timer/counter 8-bit timer/counter · 2 channels or 16-bit event counter · 1 channel Serial I/O 8 bits LSB/MSB first selectable External interrupt 1 3 independent channels (edge selection, interrupt vector, source flag) Rising/falling/both edges selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) External interrupt 2 (wake-up function) 8 channels (only for level detection) Remote control transmitting fre- quency generator 1 channel (Pulse width and cycle selectable by program) Standby mode Sleep mode, stop mode, and clock mode Process CMOS Operating voltage 2.7 V to 6.0 V 2.7 V to 6.0 V EPROM for use ¾ MBM27C256A-20TVM

nnnn PACKAGE AND CORRESPONDING PRODUCTS : Available, : Not available Note : Package details of OTPROM products and piggyback/evaluation products are common to those of MB89130/ 130A series. Refer to the MB89130/130A series data sheet for details. nnnn DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the one-time ROM product, verify its difference from the product that will actually be used. T ake particular care on the following points :

• The number of register banks available is different between the MB89121 and the MB89123A/125A/P135A/ PV130A.
• The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption
• When operated at low speed, a product with an OTPROM (EPROM) will consume more current than a product with a mask ROM. However, the same is current consumption in the sleep/stop mode is the same. (For more information, see “n ELECTRICAL CHARACTERISTICS”.)
• In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the top socket. 3. Mask Options Functions that can be selected as options and how to designate these options vary with product. Before using options, check “n MASK OPTIONS”. T ake particular care on the following point :
• Pull-up resistor can’t be set for P40 to P43 on the MB89P135A.
• Options are fixed on the MB89PV130A. FPT-48P-M13 MQP-48C-P01 FPT-48P-M13 MQP-48C-P01

V CC X0A X1A P27 P26 P25 P36/INT2 P37/BZ/(RCO) P00/(INT20) P01/(INT21) P02/(INT22) P03/(INT23) P04/(INT24) P05/(INT25) P06/(INT26) P07/(INT27) P10 P11 P40 P41 P42 P43 AVR AV SS P30/SCK P31/SO P32/SI P33/EC/SCO P34/TO/INT0 P35/INT1 P24 P23 P22 P21 P20 P17 V SS P16 P15 P14 P13 P12 (TOP VIEW) (FPT-48P-M13) Note : Parenthesized function is available only for the MB89120A series.

(Continued) Pin no. Pin name Circuit type Function 5X 0 A Main clock crystal oscillator pins (max. 4.2 MHz) 6X 1 8X 0 A B Subclock crystal oscillator pins (for 32.768 kHz) 9X 1 A 3M O D 0 C Operation mode select pins Connect these pins directly to VSS .4M O D 1 2R S T D Reset I/O pin This port is of N-ch open-drain output type with pull-up re- sistor and a hysteresis input type. The internal circuit is ini- tialized by the input of “L”. “L” is output from this pin by an internal reset source as optional setting. 27 to 34 P07/ (INT27 ) to P00/ (INT20) I General-purpose I/O ports On the MB89120A series, these pins also serve as exter- nal interrupt input. External interrupt input is hysteresis input. 18, 20 to 26 P17 to P10 E General-purpose I/O ports 10 to 17 P27 to P20 G General-purpose output-only ports

42 P30/SCK F

Also serves as clock I/O for the 8-bit serial I/O interface. This port is of hysteresis input type.

41 P31/SO F

Also serves as a serial I/O data output. This port is of hys- teresis input type.

40 P32/SI F

Also serves as a serial I/O data input. This port is of hys- teresis input type.

39 P33/EC/SCO F

Also serves as the external clock input for the 8-bit timer/ counter. This port is of hysteresis input type. System clock output is optional.

38 P34/TO/INT0 F

Also serves as the overflow output and external interrupt input for the 8-bit timer/counter. This port is of hysteresis input type. 36, P36/INT2, P35/INT1 F General-purpose I/O ports Also serve as an external interrupt input. These ports are of hysteresis input type.

35 P37/BZ/ (RCO) F

Also serves as a buzzer output. This port is of hysteresis input type. On the MB89120A series, the pin also serves as a remote control output.

(Continued) Pin no. Pin name Circuit type Function 45 to 48 P43 to P40 H N-ch open-drain output ports 7V CC — Power supply pin

19 V SS — Power supply (GND) pin

1A V CC — Power supply (GND) pin Use this pin at the same voltage as VCC .

44 AVR — Reference voltage input pin

43 AV SS — Power supply (GND) pin

Use this pin at the same voltage as VSS .

(Continued) Type Circuit Remarks A

• Crystal and ceramic oscillation type (main clock)
• Cricuit for the MB89P133A/P131/P135A/PV130A
• External clock input select versions of MB89121/ 123A/125A At an oscillation feedback resistor of approximately

1 MW / 5 V

• Crystal and ceramic oscillation type (main clock)
• Crystal or ceramic oscillator select versions of MB89121/123A/125A At an oscillation feedback resistor of approximately

B

• Crystal and ceramic oscillation type (sub clock) Circuit for the MB89121/123A/125A At an oscillation feedback resistor of approximately

4.5 MW / 5 V

• Crystal and ceramic oscillation type (sub clock) Circuit for the MB89P131/P133A/P135A/PV130A At an oscillation feedback resistor of approximately

C D

• Output pull-up resistor (P-ch) of approximately 50 kW / 5 V
• Hysteresis input Standby control signal Standby control signal X1A X0A Standby control signal X1A X0A Standby control signal R P-ch N-ch

(Continued) Type Circuit Remarks E

• C M O S o u t p u t
• CMOS input
• Pull-up resistor optional F
• C M O S o u t p u t
• Hysteresis input
• Pull-up resistor optional G
• C M O S o u t p u t H
• N-ch open-drain output
• Pull-up resistor optional I
• C M O S o u t p u t
• CMOS input
• The interrupt input is a hysteresis input (available only on the MB89120A series) .
• Pull-up resistor optional P-ch N-ch R P-ch P-ch N-ch P-chR P-ch N-ch N-ch P-ch R P-ch P-ch N-ch Interrupt input R Only for the MB89120A series P-ch

1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high- voltage pins, or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “n ELECTRICAL CHARACTERISTICS” is applied between V CC and VSS . When latchup occurs, power supply current increases rapidly, and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC ) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that V CC ripple fluctu- ations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and release from stop mode. 6. Turning on the supply voltage (only for the MB89P135A) When the power supply is turned on if MB89P135A is used, power on sharply up to 2.0 V within 13 clock cycles after starting of oscillation. Further, various option may be set, if power supply up to keep this condition.

nnnn PROGRAMMING TO THE EPROM ON THE MB89P131 The MB89P131 is a one-time PROM version of the MB89121. 1. Features

• 4-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below : 3. Programming to the EPROM In EPROM mode the MB89P131 functions equivalent to the MBM27C256A. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, how- ever, that the electronic signature mode cannot be used.
• Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 7000 H to 7FFFH (note that addresses F000H to FFFF H while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode) . (3) Program with the EPROM programmer. 0000H F000H FFFF H I/O RAM Not available PROM 4 KB 7000H 7FFF H Not available EPROM 32 KB 0000H Address EPROM mode (Corresponding addresses in the EPROM programmer) Not available Single chip

nnnn PROGRAMMING TO THE EPROM ON THE MB89P133A The MB89P133A is a one-time PROM version of the MP89123A. 1. Features

• 8-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below : 3. Programming to the EPROM In EPROM mode the MB89P133A functions equivalent to the MBM27C256A, This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, how- ever, that the MB89P133A cannot use the electronic signature mode.
• Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 6000 H to 7FFFH (note that addresses E000H to FFFF H while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode) . (3) Program with the EPROM programmer. 0000H E000H FFFF H I/O RAM Not available PROM 8 KB 6000H 7FFF H Not available EPROM 32 KB 0000H Address EPROM mode (Corresponding addresses in the EPROM programmer) Single chip

nnnn PROGRAMMING TO THE EPROM ON THE MB89P135A The MB89P135A is an OTPROM version of the MB89123A/125A. 1. Features

• 16-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. 3. Programming to the EPROM In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter.
• Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000 H to 7FFFH (note that addresses C000H to FFFF H while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode) . (3) Load option data into the EPROM programmer at 3FF0H to 3FF6H . (4) Program with the EPROM programmer. 0000H 0080H BFF6 H BFF0 H C000 H FFFF H I/O RAM Not available Not available Not available Not available PROM 16 KB EPROM mode (Corresponding addresses on the EPROM programmer) Single chipAddress 0280H 8000H Vacancy (Read value FFH ) Vacancy (Read value FFH ) Option area EPROM 16 KB 0000H 3FF6H 7FFF H 3FF0H 4000H

1. Setting OTPROM Options (MB89P135A Only) The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map :

• OTPROM option bit map Note : Each bit is set to “1” as the initialized value, therefore the pull-up option is not selected. Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FF0 H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Clock mode selection 1 : Single clock 0 : Dual clock Reset pin output 1 : Yes 0 : No Power-on reset 1 : Yes 0 : No Oscillation stabilization time 00 : 2 2/FCH 01 : 212/FCH 10 : 216/FCH 11 : 218/FCH 3FF1H P07 Pull-up 1 : Yes 0 : No P06 Pull-up 1 : Yes 0 : No P05 Pull-up 1 : Yes 0 : No P04 Pull-up 1 : Yes 0 : No P03 Pull-up 1 : Yes 0 : No P02 Pull-up 1 : Yes 0 : No P01 Pull-up 1 : Yes 0 : No P00 Pull-up 1 : Yes 0 : No 3FF2 H P17 Pull-up 1 : Yes 0 : No P16 Pull-up 1 : Yes 0 : No P15 Pull-up 1 : Yes 0 : No P14 Pull-up 1 : Yes 0 : No P13 Pull-up 1 : Yes 0 : No P12 Pull-up 1 : Yes 0 : No P11 Pull-up 1 : Yes 0 : No P10 Pull-up 1 : Yes 0 : No 3FF3 H P37 Pull-up 1 : Yes 0 : No P36 Pull-up 1 : Yes 0 : No P35 Pull-up 1 : Yes 0 : No P34 Pull-up 1 : Yes 0 : No P33 Pull-up 1 : Yes 0 : No P32 Pull-up 1 : Yes 0 : No P31 Pull-up 1 : Yes 0 : No P30 Pull-up 1 : Yes 0 : No 3FF4 H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 3FF5 H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 3FF6 H Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable

nnnn HANDLING MB89P131/P133A/P135A 1. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. 2. Programming Yield Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming yeild of 100% cannot be assured at all times. 3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Inquiry : Sun Hayato Co., Ltd. : TEL : (81) -3-3986-0403 Minato Electronics Inc. : TEL : USA (1) -916-348-6066 JAP AN (81) -45-591-5611 Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name Minato Electronics Inc. 1890A MB89P131PF QFP-48 ROM-48QF2-28DP-8L Recommended MB89P133APFM ¾ Program, verify Aging +150 °C, 48 h Data verification Assembly

nnnn PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter T o program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato Co., Ltd.) listed below : Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403 FAX (81) -3-5396-9106 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM is diagrammed below. 4. Programming to the EPROM Package Adapter socket part number LCC-32 (Square) ROM-32LC-28DP-S (1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH . (3) Program with the EPROM programmer. PROM 32 KB FFFF H 0000 H 8000 H 0080 H 0480 H Single chip I/O RAM Not available 7FFF H 0000 H EPROM 32 KB Corresponding addresses on the EPROM programmerAddress

Main clock oscillator Timebase timer External interrupt* (Wake-up) CMOS I/O port CMOS output port F 2MC-8L RAM MOD0, MOD1, V CC , VSS AV CC , AVR, AVSS The other pins RST P00/(INT20) to P07/(INT27) ROM Buzzer output N-ch open-drain output port P30/SCK P34/TO/INT0 CPU CMOS I/O port P10 to P17 Reset circuit (WDT) External interrupt 8-bit timer/counter P33/EC/SCO P32/SI P31/SO P35/INT1 P36/INT2 P37/BZ/(RCO) P40 to P43 Subclock oscillator (32.768 kHz)

8 Remote control

frequency generator* Clock controller P20 to P27 X0A X1A Port 0/1Port 2 Internal bus 8-bit timer/counter 8-bit serial I/O Port 3Port 4 * : Only the MB89120A series has wake-up interrupt inputs and remote control transmission. Note : Parenthesized pins are available only with the MB89120A series.

1. Memory Space The microcontrollers of the MB89120/A series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address with the program area. The memory space of the MB89120/A series is structured as illustrated below : ROM FFFF H 007F H 0000 H I/O MB89121 MB89P131 EFFF H 00BF H 00C0 H ROM I/O RAM Register RAM Register 013F H Not available 0100 H FFFF H 0000 H 017F H 0180 H 0100 H DFFF H MB89123A MB89P133A Not available Not available ROM I/O RAM Register Not available FFFF H 0000 H BFFF H MB89125A F000 H 0140 H 0080 H E000 H 007F H 0080 H 007F H 0080 H 017F H 0100 H C000 H BFFF H C000 H ROM 16 KB I/O RAM 512 B Register Vacancy FFFF H 0000 H 01FF H 0200 H 0100 H 00FF H 00FF H 027F H MB89P135A External ROM 32 KB I/O RAM 1 KB Register Vacancy FFFF H 0000 H 7FFF H MB89PV130A 0280 H 007F H 0080 H 007F H 0080 H 01FF H 0100 H 8000 H 047F H 0480 H 0180 H 0200 H Memory Space

1. Registers The F2MC-8L family has two types of registers; dedicated hardware registers and general-purpose memory registers. The following dedicated registers are provided : The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) (see the diagram below) . Program counter (PC) : A 16-bit-long register for indicating the instruction storage positions Accumulator (A) : A 16-bit-long temporary register for arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit-long register which is used for arithmetic operations with the accumu- lator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit-long register for index modification Extra pointer (EP) : A 16-bit-long pointer for indicating a memory address Stack pointer (SP) : A 16-bit-long pointer for indicating a stack area Program status (PS) : A 16-bit-long register for storing a register pointer, a condition code PC A T IX EP SP PS 16 bits : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFD H Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are Indeterminate. Initial value Vacancy H I IL1, 0 N Z VC RPPS 1 0 9876 321015 14 13 12 11 RP CCR Vacancy Vacancy Structure of the Program Status Register

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared “0” otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”. Cleared to “0” at the reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level High-low High Low 10 2 11 3 N-flag : Set to “1” if the MSB becomes “1” as the result of an arithmetic operation. Cleared to “0” otherwise. Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise. V-flag : Set to “1” if the complement on “2” overflows as a result of an arithmetic operation. Cleared to “0” if the overflow does not occur. C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. "0" fl A15 "0" fl A14 "0" fl A13 "0" fl A12 "0" fl A11 "0" fl A10 "0" fl "1" fl fl fl fl fl fl fl fl fl Lower OP codesRP Generated addresses Rule for Conversion of Actual Addresses of the General-purpose Register Area

The following general-purpose registers are provided : General-purpose registers : An 8-bit-long register for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 8 banks can be used on the MB89121/P131, and a total of 16 banks can be used on the MB89123A/125A/P133A and a total of 32 banks can be used on the MB89P135A/PV130A. The bank currently in use is indicated by the register bank pointer (RP) . This address = 0100H + 8 · (RP) Memory area 8 banks (MB89121/P131) 16 banks (MB89123A/125A/133A) 32 banks (MB89P135A/PV130A) R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 Register Bank Configuration

(Continued) Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog control register 0AH (R/W) TBTC Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0C H (R/W) PDR3 Port 3 data register 0D H (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H Vacancy 11H Vacancy 12H (R/W) SCGC Peripheral control clock register 13H Vacancy 14H (R/W) RCR1 Remote control transmission control register 1* 15H (R/W) RCR2 Remote control transmission control register 2* 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1C H (R/W) SMR1 Serial mode register 1D H (R/W) SDR1 Serial data register 1EH Vacancy 1FH Vacancy

(Continued) * : Only in the MB89120A series Note : Do not use vacancies. Address Read/write Register name Register description 20H Vacancy 21H Vacancy 22H Vacancy 23H (R/W) EIC1 External interrupt control register 1 24H (R/W) EIC2 External interrupt control register 2 25H Vacancy 26H to 31H Vacancy 32H (R/W) EIE2 External interrupt 2 enable register* 33H (R/W) EIF2 External interrupt 2 flag register* 34H to 7BH Vacancy 7C H (W) ILR1 Interrupt level register 1 7D H (W) ILR2 Interrupt level register 2 7EH (W) ILR3 Interrupt level register 3 7FH Vacancy

nnnn ELECTRICAL CARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage VCC AV CC AVR VSS - 0.3 V SS + 7.2 V Use VCC , AVCC , and AVR set to the same voltage. Program voltage V PP VSS - 0.6 V SS + 13.0 V MOD1 pin on the MB89P131/P133A/P135A Input voltage V I VSS - 0.3 V CC + 0.3 V Output voltage V O VSS - 0.3 V CC + 0.3 V “L” level maximum output current IOL ¾ 10 mA “L” level average output current IOLAV ¾ 4m A Avarage value (operating current · operating rate) “L” level total maximum output cur- rent SIOL ¾ 100 mA “L” level total average output current SIOLAV ¾ 20 mA Avarage value (operating current · operating rate) “H” level maximum output current IOH ¾- 10 mA “H” level average output current IOHAV ¾- 2m A Avarage value (operating current · operating rate) “H” level total maximum output cur- rent SIOH ¾- 30 mA “H” level total average output current SIOHAV ¾- 10 mA Avarage value (operating current · operating rate) Power consumption P D ¾ 200 mW Operating temperature T A -40 +85 °C Storage temperature Tstg -55 +150 °C

1. Recommended Operating Conditions (AVSS = VSS = 0.0 V) * : These values vary with the operating conditions. See “ Operating Voltage vs. Main Clock Operating Frequency.” WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Remarks Min. Max. Power supply voltage V CC 2.2* 6.0* V Normal operation assurance range Applied to “MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A*” 2.7* 6.0* V Normal operation assurance range Applied to “ Dual-clock MB89121/123A/125A*” 1.5 6.0 V Retains the RAM state in stop mode Operating temperature T A -40 +85 °C

• Operating Voltage vs. Main Clock Operating Frequency Operation assurance range 123 4 4.0 2.0 1.0 Main clock operating frequency (Instruction cycle time of 4/FCH ) (MHz) Minimum execution time (µs) Operating voltage (V) Dual-clock MB89121/123A/125A Operation assurance range 123 4 4.0 2.0 1.0 Main clock oprating frequency (Instruction cycle time of 4/FCH ) (MHz) Minimum execution time (µs) Operating voltage (V) Note : The shaded area is assured only for the MB89121/123A/125A (instruction cycle time of 4/FCH ) . MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A

1. DC Characteristics (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) (Continued) Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. “H” level input voltage VIH P00 to P07, P10 to P17 ¾ 0.7 VCC ¾ VCC + 0.3 V VIHS RST , P30 to P37, INT20 to INT27 ¾ 0.8 VCC ¾ VCC + 0.3 V INT20 to INT27 are available only in the MB89120A series. “L” level input voltage V IL P00 to P07, P10 to P17 ¾ VSS - 0.3 ¾ 0.3 VCC V VILS RST , P30 to P37, INT20 to INT27 ¾ VSS - 0.3 ¾ 0.2 VCC V INT20 to INT27 are available only in the MB89120A series. Open-drain output pin applied voltage V D P40 to P43 ¾ VSS - 0.3 ¾ VCC + 0.3 V “H” level output voltage VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 I OH = -2.0 mA 2.4 ¾¾ V “L” level output voltage VOL P00 to P07, P10 to P17 P20 to P27, P30 to P37, P40 to P43 I OL = 1.8 mA ¾¾ 0.4 V VOL2 RST IOL = 4.0 mA ¾¾ 0.6 V Input leakage current (Hi-z output leakage current) I LI P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P43, MOD0, MOD1

0.45 V < V

I < VCC ¾¾– 5 mA Without pull-up resistor Pull-up resistance R PULL P00 to P07, P10 to P17, P30 to P37, P40 to P43, RST VI = 0.0 V 25 50 100 k W

(Continued) (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) *1 : The measurement conditions of power supply current is external clock. (VCC = 5.0 V, VCC = 3.0 V) *2 : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.” Parameter Symbol Pin Condition Value Unit Remarks Min. Typ. Max. Power supply current*1 ICC1 VCC (External clock operation) V CC = 5.0 V FCH = 4.00 MHz tinst*2 = 1.0 ms ¾ 47 m A MB89121/ 123A/125A ¾ 61 0 m A MB89P131/ P133A/ P135A I CCS1 VCC = 5.0 V FCH = 4.00 MHz Main sleep mode t inst*2 = 1.0 ms ¾ 25 m A ICCL VCC = 3.0 V FCL = 32.768 kHz Subclock mode ¾ 50 100 mA MB89121/ 123A/125A ¾ 13 m A MB89P131/ P133A/ P135A I CCLS VCC = 3.0 V FCL = 32.768 kHz Subclock sleep mode ¾ 25 50 mA I CCT VCC = 3.0 V FCL = 32.768 kHz

• Watch mode
• Main clock stop mode at dual clock system ¾¾ 15 mA I CCH TA = +25 °C
• Subclock stop mode
• Main clock stop mode at single clock system ¾¾ 1 mA Input capacitance C IN Other than AV CC , AVSS , VCC , and VSS f = 1 MHz ¾ 10 ¾ pF

1. AC Characteristics (1) Reset Timing (VCC = +5.0 V –10% , AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) * : tHCYL is the oscillation cycle (1/FCH ) input to the X0. (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) Note : Make sure that power supply rises within the oscillation stabilization time selected. When the main clock is operating at FCH = 3 MHz and the oscillation stabilization time select option has been set to 212/FCH , for example, the oscillation settling time is 1.4 ms and accordingly the maximum value of power supply rising time is about 1.4 ms. Keep in mind that rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. Parameter Symbol Condition Value Unit Remarks Min. Max. RST “L” pulse width t ZLZH ¾ 48 tHCYL * ¾ ns Parameter Symbol Condition Value Unit Remarks Min. Max. Power supply rising time t R ¾ 50 ms Power-on reset function only Power supply cut-off time t OFF 1 ¾ ms Due to repeated operations tZLZH 0.2 VCC 0.2 VCC

0.8 VCC

0.2 V 0.2 V 2.0 V VCC 0.2 V tR tOFF

(3) Clock Timings (VSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. Clock frequency FCH X0, X1 1 ¾ 4.2 MHz Main clock FCL X0A, X1A ¾ 32.768 ¾ kHz Subclock Clock cycle time tHCYL X0, X1 238 ¾ 1000 ns Main clock tLCYL X0A, X1A ¾ 30.5 ¾m s Subclock Input clock pulse width PWH1 PWL1 X0 72 ¾¾ ns External clock Input clock rising/falling timetCR1 tCF1 X0 ¾¾ 24 ns External clock tCR1

0.2 VCC

When an external clock is used FCH X0, X1 Timings and Conditions of Applied Voltage Main Clock Conditions of Applied Voltage

(4) Instruction Cycles (VSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Symbol Value (typical) Unit Remarks Instruction cycle (minimum execution time) tinst 4/FCH , 8/FCH , 16/FCH , 64/FCH ms (4/FCH ) tinst = 1.0 ms when operating at FCH = 4 MHz 2/FCL ms tinst = 61.036 ms when operating at FCL = 32.768 kHz X0A Single-clock option is used Rd X0A, X1A Timings and Conditions of Applied Voltage Subclock Conditions of Applied Voltage

(5) Recommended Resonator Manufacturers X0 X1 C1 *2 C2 *2 FAR *1R Inquiry : FUJITSU MEDIA DEVICES LIMITED FAR part number (built-in capacitor type) Frequency (MHz) Dumping resistor Initial deviation of FAR frequency (TA = +25 °C) Temperature characteristics of FAR frequency (TA = -20 °C to +60 °C) Loading capacitors*2 FAR-C4CC-02000-L00 2.00 1000 –0.5%– 0.5% Built-in 510 FAR-C4 A-03580- 01 3.58 FAR-C4CB-04000-M00 4.00 Sample Application of Piezoelectric Resonator (FAR Series) for Main Clock Oscillation Circuit (Only in the MB89120A Series) *1 : FUJITSU MEDIA DEVICE LIMITED

R

• Mask ROM products Resonator manufacturer* Resonator Frequency (MHz) C1 (pF) C2 (pF) R (k W ) Kyocera Corporation KBR-4.0MKS 4.00 33 33 Not required Matsushita Electronic Compo- nents EFOV4004B 4.00 Built-in Built-in 1.5 Murata Mfg. Co. Ltd. CSBF1000J 1.00 100 100 6.8 CSTCS4.00MG800 4.00 Built-in Built-in Not required CSA4.00MG040 100 100 Not required CST4.00MGW040 Built-in Built-in Not required Inquiry : Kyocera Corporation
• AVX Corporation North American Sales Headquarters : TEL (803) 448-9411
• AVX Limited European Sales Headquarters : TEL (01252) 770000
• AVX/Kyocera H.K. Ltd. Asian Sales Headquarters : TEL 363-3303 Matsushita Electronic Components Co., Ltd.
• Ceramic Division : TEL 81-6-908-1101 Murata Mfg Co., Ltd.
• Murata Electronics North America, Inc. : TEL 1-404-436-1300
• Murata Europe Management GmbH : TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd. : TEL 65-758-4233 Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit

• Mask ROM product Resonator manufacturer* Resonator Frequency (kHz) C1 (pF) C2 (pF) Rd (k W ) SII DS-VT-200 32.768 24 24 680 Inquiry : SII Seiko Instruments Inc. (Japan) : Seiko Instruments U.S.A. Inc. : Seiko Instruments GmbH : TEL 81-43-211-1219 TEL 310-517-7770 TEL 49-6102-297-122 Sample Application of Crystal Resonator for Subclock Oscillation Circuit

(6) Serial I/O Timings (VCC = +5.0 V –10% , AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) * : For information on tinst, see “ (4) Instruction Cycles.” Parameter Symbol Pin Condition Value Unit Remarks Min. Max. Serial clock cycle time t SCYC SCK Internal clock operation 2 tinst* ¾m s SCK fl fi SO time t SLOV SCK, SO -200 200 ns Valid SI fi SCK › tIVSH SI, SCK 200 ¾ ns SCK › fi Valid SI hold time t SHIX SCK, SI 200 ¾ ns Serial clock “H” pulse width tSHSL SCK External clock operation tinst* ¾m s Serial clock “L” pulse width tSLSH tinst* ¾m s SCK fl fi SO time t SLOV SCK, SO 0 200 ns Valid SI fi SCK › tIVSH SI, SCK 200 ¾ ns SCK › fi Valid SI hold time t SHIX SCK, SI 200 ¾ ns tSLSH 2.4 V 0.8 V tIVSH 0.2 VCC0.2 VCC SO SI SCK tSLOV 0.8 V 2.4 V tSCYC 2.4 V 0.8 V 0.8 V tIVSH

(7) Peripheral Input Timings (VCC = +5.0 V –10% , AVSS = VSS = 0.0 V, TA = -40 °C to +85 °C) * : For information on tinst, see “ (4) Instruction Cycle.” Parameter Symbol Pin Value Unit Remarks Min. Max. Peripheral input “H” pulse width Peripheral input “L” pulse width tILIH EC, INT0 to INT2 2 tinst* ¾m s tIHIL 2 tinst* ¾m s

nnnn EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIHS : Threshold when input voltage in hysteresis characteristics is set to “H” level VILS : Threshold when input voltage in hysteresis characteristics is set to “L” level (5) Pull-up Resistance VOL (V) VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V IOL (mA) 0123456789 1 0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.1 VCC = 2.5 V VCC = 2.2 V VCC = 3.0 V TA = +25 °C VOL vs. IOL VCC - VOH (V) VCC = 6.0 V VCC = 5.0 V VCC = 4.0 V IOH (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.1 VCC = 2.5 VVCC = 2.2 V VCC = 3.0 V TA = +25 °C VCC - VOH vs. IOH .00 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V IN (V) VCC (V) TA = +25 °C VIN vs. VCC VIHS VILS .00 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V IN (V) VCC (V) TA = +25 °C VIN vs. VCC 0 234567 1000 R PULL (kW ) VCC (V) 300 100 TA = +25 °C R PULL vs. VCC

(6) Power Supply Current ICCL (µA) VCC (V) 1.5 2.0 100 120 140 160 180 200 ICCL vs. VCC TA = +25 °C 1.5 6.5 VCC (V) 5.0 ICC (mA) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 ICC1 vs. VCC Divide by 4 (ICC1 ) Divide by 64 FCH = 4.0 MHz TA = +25 °C 1.5 6.5 VCC (V) ICCS (mA) 0.0 ICCS1 vs. VCC Divide by 4 (ICCS1 ) Divide by 64 0.5 1.0 1.5 2.0 2.5 3.0 FCH = 4.0 MHz TA = +25 °C 1.5 6.5 VCC (V) ICCLS (µA) ICCLS vs. VC C TA = +25 °C 1.5 6.5 VCC (V) ICCT (µA) ICCT vs. VCC

30 TA = +25 °C

ICCH (µA) VCC (V) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

2.0 TA = +25 °C

ICCH vs. VCC

nnnn INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups:

• T ransfer
• Arithmetic operation
• Branch
• O t h e r s T able 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00. N, Z, V , C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ‹ This indicates 48, 49, ... 4F . Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T T emporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7)
• Indicates that the very · is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ( · ) Indicates that the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( · )) The address indicated by the contents of · is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Table 2 Transfer Instructions (48 instructions) Note: During byte transfer to A, T ‹ A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC (dir) ‹ (A) ( (IX) +off ) ‹ (A) (ext) ‹ (A) ( (EP) ) ‹ (A) (Ri) ‹ (A) (A) ‹ d8 (A) ‹ (dir) (A) ‹ ( (IX) +off) (A) ‹ (ext) (A) ‹ ( (A) ) (A) ‹ ( (EP) ) (A) ‹ (Ri) (dir) ‹ d8 ( (IX) +off ) ‹ d8 ( (EP) ) ‹ d8 (Ri) ‹ d8 (dir) ‹ (AH),(dir + 1) ‹ (AL) ( (IX) +off) ‹ (AH), ( (IX) +off + 1) ‹ (AL) (ext) ‹ (AH), (ext + 1) ‹ (AL) (EP) ‹ (A) (A) ‹ d16 (AH) ‹ (dir), (AL) ‹ (dir + 1) (AH) ‹ ( (IX) +off), (AL) ‹ ( (IX) +off + 1) (AH) ‹ (ext), (AL) ‹ (ext + 1) (A) ‹ (EP) (EP) ‹ d16 (IX) ‹ (A) (A) ‹ (IX) (SP) ‹ (A) (A) ‹ (SP) ( (A) ) ‹ (T) (IX) ‹ d16 (A) ‹ (PS) (PS) ‹ (A) (SP) ‹ d16 (AH) « (AL) (dir): b ‹ 1 (dir): b ‹ 0 (AL) « (TL) (A) « (T) (A) « (EP) (A) « (IX) (A) « (SP) (A) ‹ (PC) AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + – – + + – – + + – – + + – – + + – – + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + + + + – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 48 to 4F 08 to 0F 88 to 8F A8 to AF A0 to A7

Table 3 Arithmetic Operation Instructions (62 instructions) (Continued) Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir (A) ‹ (A) + (Ri) + C (A) ‹ (A) + d8 + C (A) ‹ (A) + (dir) + C (A) ‹ (A) + ( (IX) +off) + C (AL) ‹ (AL) + (TL) + C (A) ‹ (A) - (Ri) - C (A) ‹ (A) - d8 - C (A) ‹ (A) - (dir) - C (A) ‹ (A) - ( (IX) +off) - C (AL) ‹ (TL) - (AL) - C (Ri) ‹ (Ri) + 1 (EP) ‹ (EP) + 1 (IX) ‹ (IX) + 1 (A) ‹ (A) + 1 (Ri) ‹ (Ri) - 1 (EP) ‹ (EP) - 1 (IX) ‹ (IX) - 1 (A) ‹ (A) - 1 (A) ‹ (AL) · (TL) (A) ‹ (T) / (AL),MOD fi (T) (A) ‹ (A) Ù (T) (A) ‹ (A) Ú (T) (A) ‹ (A) " (T) (TL) - (AL) (T) - (A) (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ‹ (AL) " (TL) (A) ‹ (AL) " d8 (A) ‹ (AL) " (dir) (A) ‹ (AL) " ( (IX) +off) (A) ‹ (AL) " (Ri) (A) ‹ (AL) Ù (TL) (A) ‹ (AL) Ù d8 (A) ‹ (AL) Ù (dir) dL dH dH dH dH dH dH dH dH + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + – – – – – – – – – + + – – + + + – – – – – – – – – + + – – – – – – – – – – + + R – + + R – + + R – + + + + + + + + + + – + + + – + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – 28 to 2F 38 to 3F C8 to CF D8 to DF 18 to 1F 58 to 5F A C fifi AC

(Continued) Table 4 Branch Instructions (17 instructions) Table 5 Other Instructions (9 instructions) Mnemonic ~ # Operation TL TH AH N Z V C OP code AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP (A) ‹ (AL) Ù ( (EP) ) (A) ‹ (AL) Ù ( (IX) +off) (A) ‹ (AL) Ù (Ri) (A) ‹ (AL) Ú (TL) (A) ‹ (AL) Ú d8 (A) ‹ (AL) Ú (dir) (A) ‹ (AL) Ú ( (EP) ) (A) ‹ (AL) Ú ( (IX) +off) (A) ‹ (AL) Ú (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ‹ (SP) + 1 (SP) ‹ (SP) – 1 + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + R – + + + + + + + + + + + + + + + + – – – – – – – – 68 to 6F 78 to 7F 98 to 9F Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI If Z = 1 then PC ‹ PC + rel If Z = 0 then PC ‹ PC + rel If C = 1 then PC ‹ PC + rel If C = 0 then PC ‹ PC + rel If N = 1 then PC ‹ PC + rel If N = 0 then PC ‹ PC + rel If V " N = 1 then PC ‹ PC + rel If V " N = 0 then PC ‹ PC + reI If (dir: b) = 0 then PC ‹ PC + rel If (dir: b) = 1 then PC ‹ PC + rel (PC) ‹ (A) (PC) ‹ ext Vector call Subroutine call Return from subrountine Return form interrupt dH – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – + – – – + – – – – – – – – – – – – – – – – – – – – – – – – – – Restore FD FC FB FA FF FE B0 to B7 B8 to BF E8 to EF Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI dH – – – – – – – – – – – – – – – – – – – – – – – R – – – S – – – – – – – –

H L 0123456789A B C D EF

0 NOP SWAP RET RETI PUSHW

A POPW A MOV A,ext MOVW A,PS CLRI SETI CLRB dir: 0 BBC dir: 0,rel INCW A DECW A JMP MOVW A,PC

1 MULU

A DIVU A JMP addr16 CALL addr16 PUSHW IX POPW IX MOV ext,A MOVW PS,A CLRC SETC CLRB dir: 1 BBC dir: 1,rel INCW SP DECW SP MOVW SP ,A MOVW A,SP

2 ROLC

A CMP A ADDC A SUBC A XCH A, T XOR A AND A OR A MOV @A,T MOV A,@A CLRB dir: 2 BBC dir: 2,rel INCW IX DECW IX MOVW IX,A MOVW A,IX

3 RORC

A CMPW A ADDCW A SUBCW A XCHW A, T XORW A ANDW A ORW A MOVW @A,T MOVW A,@A CLRB dir: 3 BBC dir: 3,rel INCW EP DECW EP MOVW EP ,A MOVW A,EP

4 MOV

A,#d8 CMP A,#d8 ADDC A,#d8 SUBC A,#d8 XOR A,#d8 AND A,#d8 OR A,#d8 DAA DAS CLRB dir: 4 BBC dir: 4,rel MOVW A,ext MOVW ext,A MOVW A,#d16 XCHW A,PC

5 MOV

A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#d8 CMP dir,#d8 CLRB dir: 5 BBC dir: 5,rel MOVW A,dir MOVW dir,A MOVW SP ,#d16 XCHW A,SP

6 MOV

A,@IX +d CMP A,@IX +d ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A XOR A,@IX +d AND A,@IX +d OR A,@IX +d MOV @IX +d,#d8 CMP @IX +d,#d8 CLRB dir: 6 BBC dir: 6,rel MOVW A,@IX +d MOVW @IX +d,A MOVW IX,#d16 XCHW A,IX

7 MOV

A,@EP CMP A,@EP ADDC A,@EP SUBC A,@EP MOV @EP ,A XOR A,@EP AND A,@EP OR A,@EP MOV @EP ,#d8 CMP @EP ,#d8 CLRB dir: 7 BBC dir: 7,rel MOVW A,@EP MOVW @EP ,A MOVW EP ,#d16 XCHW A,EP

8 MOV

A,R0 CMP A,R0 ADDC A,R0 SUBC A,R0 MOV R0,A XOR A,R0 AND A,R0 OR A,R0 MOV R0,#d8 CMP R0,#d8 SETB dir: 0 BBS dir: 0,rel INC DEC CALLV BNC rel

9 MOV

A,R1 CMP A,R1 ADDC A,R1 SUBC A,R1 MOV R1,A XOR A,R1 AND A,R1 OR A,R1 MOV R1,#d8 CMP R1,#d8 SETB dir: 1 BBS dir: 1,rel INC DEC CALLV BC rel A MOV A,R2 CMP A,R2 ADDC A,R2 SUBC A,R2 MOV R2,A XOR A,R2 AND A,R2 OR A,R2 MOV R2,#d8 CMP R2,#d8 SETB dir: 2 BBS dir: 2,rel INC DEC CALLV BP rel B MOV A,R3 CMP A,R3 ADDC A,R3 SUBC A,R3 MOV R3,A XOR A,R3 AND A,R3 OR A,R3 MOV R3,#d8 CMP R3,#d8 SETB dir: 3 BBS dir: 3,rel INC DEC CALLV BN rel C MOV A,R4 CMP A,R4 ADDC A,R4 SUBC A,R4 MOV R4,A XOR A,R4 AND A,R4 OR A,R4 MOV R4,#d8 CMP R4,#d8 SETB dir: 4 BBS dir: 4,rel INC DEC CALLV BNZ rel D MOV A,R5 CMP A,R5 ADDC A,R5 SUBC A,R5 MOV R5,A XOR A,R5 AND A,R5 OR A,R5 MOV R5,#d8 CMP R5,#d8 SETB dir: 5 BBS dir: 5,rel INC DEC CALLV BZ rel E MOV A,R6 CMP A,R6 ADDC A,R6 SUBC A,R6 MOV R6,A XOR A,R6 AND A,R6 OR A,R6 MOV R6,#d8 CMP R6,#d8 SETB dir: 6 BBS dir: 6,rel INC DEC CALLV BGE rel F MOV A,R7 CMP A,R7 ADDC A,R7 SUBC A,R7 MOV R7,A XOR A,R7 AND A,R7 OR A,R7 MOV R7,#d8 CMP R7,#d8 SETB dir: 7 BBS dir: 7,rel INC DEC CALLV BLT rel

*1 : Both external clock and oscillation resonator is usable on the one-time product. *2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output. *3 : The peripheral control clock function can be used only by software. No. Part number MB89121 MB89123A MB89125A MB89P131 MB89P133A MB89P135A MB89PV130A Specifying procedure Specify when ordering masking Set with EPROM programmer Specification impossible Pull-up resistors

• P00 to P07, P10 to P17,
• P30 to P37, P40 to P43 Selectable by pin Selectable by pin (P40 to P43 must be set to without a pull-up resistor.) All pins fixed to no pull-up resis- tor optional Power-on reset Power-on reset provided No power-on reset Selectable Selectable Selectable With power-on reset Selection of oscillation stabiliza- tion wait time
• The oscillation stabilization wait time initial value is selectable from 4 types given below. 0 : Oscillation stabilization 2 2/FCH 1 : Oscillation stabilization 212/FCH 2 : Oscillation stabilization 216/FCH 3 : Oscillation stabilization 218/FCH Selectable Selectable Selectable Oscillation sta- bilization 18/FCH Reset pin output
• Reset output provided
• No reset output Selectable Selectable Selectable With reset out- put Clock mode selection
• Single-clock mode
• Dual-clock mode Selectable Selectable Selectable Dual-clock mode Main clock oscillation circuit type
• External clock input
• Oscillation resonator Selectable Not required* 1 Peripheral control clock output function*2
• Not used
• Used Selectable Not required* 3

nnnn MB89P131/P133A STANDARD OPTIONS nnnn ORDERING INFORMATION No. Product option MB89P131-101 MB89P133A-201

1 Pull-up resistor Not provided for any port Not provided for any port

2 Power-on reset Provided Provided

3 Selection of oscillation stabilization

time 2 : Oscillation stabilization 216/FCH 2 : Oscillation stabilization 216/FCH

4 Reset pin output Provided Provided

5 Clock mode selection Dual-clock mode Dual-clock mode

Part number Package Remarks MB89121PFM MB89123APFM MB89125APFM 48-pin Plastic QFP (FPT-48P-M13) MB89P131PFM-101 MB89P133APFM-201 MB89P135APFM MB89PV130ACF-ES 48-pin Ceramic MQFP (MQP-48C-P01)

(FPT-48P-M13) Dimensions in mm (inches) C 1994 FUJITSU LIMITED F48023S-1C-1 Details of "A" part 13.10±0.40 0.30±0.10 11.50±0.308.80 (.453±.012)(.346) REF 0.10(.004) INDEX Details of "B" part 121 2536 37 24 1348 0.80(.0315)TYP LEAD No. (.516±.016) SQ (.394±.008) 10.00±0.20 SQ "A" 0.15±0.05 (.006±.002) 0.15(.006) 0.20(.008) 0.53(.021)MAX 0.18(.007)MAX 0~10° 0.80±0.30 (.031±.012) "B" (STAND OFF) 0(0)MIN 2.35(.093)MAX (Mounting height)

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San Jose, CA 95134-1804, U.S.A. T el: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany T el: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New T ech Park, Singapore 556741 T el: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD.

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