MB88151APNF-G-200-JNERE1

MB88151A FUJITSU | Alldatasheet

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DS04-29127-1EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©2007 FUJITSU LIMITED All rights reserved ASSP Spread Spectrum Clock Generator MB88151A ■ DESCRIPTION MB88151A is a clock generator for EM I (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the o scillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates frequency in modulation off as Middle Centered and down spread which modulates so as not to exceed frequency in modulation off. ■ FEATURES

• Modulation rate : ± 0.5%, ± 1.5% (Center spread), − 1.0%, − 3.0% (Down spread)  Equipped with oscillation circuit : R ange of oscillation 8.3 MHz to 33.4 MHz  Modulation clock output Duty : 40 % to 60%  Low current consumption by CMOS proces s : 5 mA (24 MHz : Typ-sample, no load)  Power supply voltage : 3.3 V ± 0.3 V  Operating temperature : − 40 °C to + 85 °C  Package : SOP 8-pin MB88151A- (multiply-by-1) MB88151A- (multiply-by-2) MB88151A- (multiply-by-4) MB88151A- (multiply-by-1/2) MB88151A- (multiply-by-8) Input frequency/ Output frequency 16.6 MHz to 33.4 MHz/ 16.6 MHz to 33.4 MHz 16.6 MHz to 33.4 MHz/ 33.2 MHz to 66.8 MHz 16.6 MHz to 33.4 MHz/ 66.4 MHz to 133.6 MHz 16.6 MHz to 33.4 MHz/ 8.3 MHz to 16.7 MHz 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz Modulation clock cycle-cycle jitter Less than100 ps Less than 100 ps Less than 150 ps Less than 200 ps Less than 150 ps

■ PRODUCT LINEUP MB88151A has five kinds of multiplication type. ■ PIN ASSIGNMENT ■ PIN DESCRIPTION * : XPD = 800 kΩ pull-up resistor at “L” Product Input frequency range Multiplier ratio Output frequency range MB88151A-100/101 16.6 MHz to 33.4 MHz Multiply-by-1 16.6 MHz to 33.4 MHz MB88151A-200/201 Multiply-by-2 33.2 MHz to 66.8 MHz MB88151A-400/401 Multiply-by-4 66.4 MHz to 133.6 MHz MB88151A-500/501 Multiply-by-1/2 8.3 MHz to 16.7 MHz MB88151A-800/801 8.3 MHz to 16.7 MH z Multiply-by-8 66.4 MHz to 133.6 MHz Pin name I/O Pin no. Description XIN I 1 Resonator connection pin/clock input pin V SS ⎯ 2 GND pin SEL0 I 3 Modulation rate setting pin SEL1 I 4 Modulation rate setting pin CKOUT O 5 Modulated clock output pin ENS/XPD I 6 Modulation enable setting pin (with pull-up resistance)/ Power down pin (with pull-up resistor)* VDD ⎯ 7 Power supply voltage pin XOUT O 8 Resonator connection pin XIN V SS SEL0 SEL1 XOUT V DD ENS/XPD CKOUT MB88151A TOP VIEW FPT-8P-M02

■ I/O CIRCUIT TYPE Note : For XIN and XOUT pins, refer to “■OSCILLATION CIRCUIT”. Pin Circuit type Remarks SEL0, SEL1 CMOS hysteresis input ENS CMOS hysteresis input with 50 kΩ + 800 kΩ (Typ) pull-up resistors Note : If “L” is input to XPD when the XPD function is selected, 50 kΩ pull-up resistor is disconnected. CKOUT  CMOS output I OL = 4 mA 800 kΩ 50 kΩ

■ HANDLING DEVICES Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in parallel between VSS pin and VDD pin near the device, as a bypass capacitor. Oscillation circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground.

■ BLOCK DIAGRAM M N L IDAC ICO VDD CKOUT VSS Rf = 1 MΩ SEL1 XOUT XIN SEL0 ENS/XPD Modulation clock output Modulation rate setting Modulation rate setting Modulation enable setting/ Power down setting Reference clock PLL block Reference clock Phase compare V/I conversion Modulation logic Modulation rate setting/ Modulation enable setting Loop filter Modulation clock output MB88151A PLL block Charge pump A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI.

■ PIN SETTING When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock take the maximum value of “ ■ ELECTRICAL CHARACTERISTICS • AC Characteristics Lock-up time”. ENS modulation enable setting (MB88151A-100/200/400/500/800) Note : Spectrum does not spread when “L ” is set to ENS. The clock with low jitter can be obtained. Because of ENS has Pull-up resistance, spectrum spread when “H” is set to it or open the terminal. XPD Power down setting (MB88151A-101/201/401/501/801) Note : CKOUT of output pins are fixed to “L ” output during power down. SEL0, SEL1 Modulation rate setting Note : The modulation rate can be changed at the level of the terminal. ENS Modulation L No modulation H Modulation XPD Status L Power down Status H Operating status SEL1 SEL0 Modulation rate Modulation type LL ± 1.5% Center spread LH ± 0.5% Center spread HL − 1.0% Down spread HH − 3.0% Down spread

• Center spread Spectrum is spread (modulated) by centering on the frequency in modulation off.
• Down spread Spectrum is spread (modulated) below the frequency in modulation off. −1.5% +1.5% Radiation level Frequency Frequency in modulation off Center spread example of ± 1.5% modulation rate Modulation width 3.0% −3.0% Frequency in modulation off Frequency Radiation level Down spread example of − 3.0% modulation rate Modulation width 3.0%

■ ABSOLUTE MAXIMUM RATINGS * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Min Max Power supply voltage* V DD − 0.5 + 4.0 V Input voltage* V I VSS − 0.5 V DD + 0.5 V Output voltage* V O VSS − 0.5 V DD + 0.5 V Storage temperature T ST − 55 + 125 °C Operation junction temperature T J − 40 + 125 °C Output current I O − 14 + 14 mA Overshoot V IOVER ⎯ VDD + 1.0 (tOVER ≤ 50 ns) V Undershoot V IUNDER VSS−1.0 (tUNDER ≤ 50 ns) ⎯ V VDD VSSInput pin Overshoot/Undershoot tUNDER ≤ 50 ns tOVER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VIUNDER ≤ VSS − 1.0 V

■ RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) WARNING: The recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Pin Conditions Value Unit Min Typ Max Power supply voltage V DD VDD ⎯ 3.0 3.3 3.6 V “H” level input voltage V IH XIN, SEL0, SEL1, ENS ⎯ V DD × 0.8 ⎯ VDD + 0.3 V “L” level input voltage V IL ⎯ VSS ⎯ VDD × 0.2 V Input clock duty cycle tDCI XIN 8.3 MHz to

33.4 MHz 40 50 60 %

Operating temperature Ta ⎯⎯ − 40 ⎯ + 85 °C XIN ta tb 1.5 V Input clock duty cycle (tDCI = tb/ta)

■ ELECTRICAL CHARACTERISTICS

• DC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol Pin Conditions Value Unit Min Typ Max Power supply current I CC VDD No load capacitance at output 24 MHz MB88151A-100 ⎯ 5.0 7.0 mA At power down MB88151A-101 ⎯ 10 ⎯µ A Output voltage VOH CKOUT “H” level output, IOH = − 4 mA VDD − 0.5 ⎯ VDD V VOL “L” level output, IOL = 4 mA VSS ⎯ 0.4 V Output impedance Z O CKOUT 8.3 MHz to 133.6 MHz ⎯ 45 ⎯Ω Input capacitance C IN XIN, SEL0, SEL1, ENS Ta = + 25 °C, VDD = VI = 0.0 V, f = 1 MHz ⎯⎯ 16 pF Load capacitance C L CKOUT 8.3 MHz to 66.8 MHz ⎯⎯ 15 pF66.8 MHz to 100 MHz ⎯⎯ 10 100 MHz to 133.6 MHz ⎯⎯ 7 Input pull-up resistance RPUE ENS V IL = 0.0 V 25 50 200 kΩ RPUP XPD V IL = 0.0 V 500 800 1200

• AC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time, assign the maximum value for lock-up time. Parameter Symbol Pin Conditions Value Unit Min Typ Max Oscillation frequency f x XIN, XOUT Fundamental oscillation 8.3 ⎯ 33.4 MHz Input frequency f in XIN External clock input (multiply-by-1, 2, 4, divided by 2) 16.6 ⎯ 33.4 MHz External clock input (multiply-by-8) 8.3 ⎯ 16.7 Output frequency f OUT CKOUT MB88151A-100/101 (Multiply by 1) 16.6 ⎯ 33.4 MHz MB88151A-200/201 (Multiply by 2) 33.2 ⎯ 66.8 MB88151A-400/401 (Multiply by 4) 66.4 ⎯ 133.6 MB88151A-500/501 (2-frequency division) 8.3 ⎯ 16.7 MB88151A-800/801 (multiply-by-8) 66.4 ⎯ 133.6 Output slew rate SR CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 0.4 ⎯ 4.0 V/ns Output clock duty cycle t DCC CKOUT 1.5 V 40 ⎯ 60 % Modulation period (Number of input clocks per modulation) fMOD (nMOD) CKOUT MB88151A-100/101, MB88151A-200/201, MB88151A-400/401, MB88151A-500/501 fin/2200 (2200) fin/1900 (1900) fin/1600 (1600) kHz (clks) MB88151A-800/801 fin/880 (880) fin/760 (760) fin/640 (640) kHz (clks) Lock-up time t LK CKOUT

8.3 MHz to 80 MHz ⎯ 25

80 MHz to 133.6 MHz ⎯ 38 Cycle-cycle jitter t JC CKOUT MB88151A-100/101, MB88151A-200/201 No load capacitance, Ta = + 25 °C, V DD = 3.3 V ⎯⎯ 100 ps-rms MB88151A-400/401, MB88151A-800/801 No load capacitance, Ta = + 25 °C, V DD = 3.3 V ⎯⎯ 150 MB88151A-500/501 No load capacitance, Ta = + 25 °C, VDD = 3.3 V ⎯⎯ 200

<Definition of modulation frequency and number of input clocks per modulation> MB88151A contains the modulation period to realize the efficient EMI reduction. The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. t fMOD (Min) f MOD (Max) t Modulation waveform Clock time nMOD (Max) f (Output frequency) Clock time nMOD (Min)

■ OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta) ■ INPUT FREQUENCY (fin = 1/tin) ■ OUTPUT SLEW RATE (SR) ■ CYCLE-CYCLE JITTER (tJC = | tn − tn+1 |) CKOUT 1.5 V ta tb

0.8 VDD

2.4 V 0.4 V tftr CKOUT tn+1tn CKOUT Note : Cycle-cycle jitter is defined the differen ce between a certain cycle and immediately after (or, immediately before) .

■ MODULATION WAVEFORM fMOD − 1.5 % + 1.5 % fMOD − 1.0 % − 0.5 %

• ±1.5% modulation rate, Example of center spread
• −1.0% modulation rate, Example of down spread CKOUT Output frequency CKOUT Output frequency Frequency at modulation OFF Frequency at modulation OFF Time Time

■ LOCK-UP TIME If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. For modulation enable control using the ENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the ENS pin is determined. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle- cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time.

3.0 VVDD

SEL0, SEL1, ENS Internal clock stabilization wait time tLK (lock-up time ) VIL VIH XIN ENS CKOUT tLK (lock-up time ) tLK (lock-up time )

When the power down is controlled by XPD pin, the desired clock is obtained after the pin is set to H level until the maximum lock-up time tLK is elapsed. XPD XIN CKOUT Internal clock stabilization wait time tLK (lock-up time)

■ OSCILLATION CIRCUIT The figure below shows the connection example about general resonator. The oscillation circuit has the built-in resistance (1 MΩ) . The value of capacity (C1 and C2) is required adjusting to the most suitable value of individual resonator. The most suitable value is different by individual reso nator. Please refer to the resonator manufacturer which you use for the most suitable value. Input the clock to XIN pin, and do not connect anything with XOUT pin if you use the external clock (you do not use the resonator). Rf (1 MΩ) XIN Pin MB88151A LSI Internal MB88151A LSI External XOUT Pin

• When using the resonator
• When using an external clock OPEN Rf (1 MΩ) Note : Note that a jitter characteristic of an i nput clock may cause an affect a cycle-cycle jitter characteristic. MB88151A LSI Internal MB88151A LSI External XOUT PinXIN Pin External clock

■ INTERCONNECTION CIRCUIT EXAMPLE MB88151A C 1 C2 C4 C3 SEL0 SEL1 Xtal ENS C1, C2 : Oscillation stabilization capacitance (refer to “■OSCILLATION CIRCUIT”.) C3 : Capacitor of 10 µF or higher C4 : Capacitor about 0.01 µF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) R1 : Impedance matching resistor for board pattern

■ SPECTRUM EXAMPLE CHARACTERISTICS The condition of the examples of the characte ristic is shown as follows : Input frequency = 20 MHz (Output frequency = 20 MHz : Using MB88151A-100 (Multiply-by-1)), Power - supply voltage = 3.3 V, None load capacity, Modulation rate = ± 1.5% (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for − 6dB). CH B Spectrum 10 dB /REF 0 dBm Avg RBW# 1 kHZ VBW 1 kHZ ATT 6 dB CENTER 20 MHZ SWP 2.505 s SPAN 4 MH Z No modulation −6.54 dBm ±1.5% modulation −24.45 dBm

■ ORDERING INFORMATION Part number Input frequency range Multiplier ratio Output frequency range Package Remarks MB88151APNF-G-100-JNE1 MB88151APNF-G-101-JNE1

16.6 MHz to

33.4 MHz

by-1 16.6 MHz to 33.4 MHz 8-pin plastic SOP (FPT-8P-M02) MB88151APNF-G-200-JNE1 MB88151APNF-G-201-JNE1 Multiply- by-2 33.2 MHz to 66.8 MHz MB88151APNF-G-400-JNE1 MB88151APNF-G-401-JNE1 Multiply- by-4 66.4 MHz to 133.6 MHz MB88151APNF-G-500-JNE1 MB88151APNF-G-501-JNE1 Multiply- by-1/2 8.3 MHz to 16.7 MHz MB88151APNF-G-800-JNE1 MB88151APNF-G-801-JNE1

8.3 MHz to

16.7 MHz

by-8 66.4 MHz to 133.6 MHz MB88151APNF-G-100-JNEFE1 MB88151APNF-G-101-JNEFE1 by-1 16.6 MHz to 33.4 MHz Emboss taping (EF type) MB88151APNF-G-200-JNEFE1 MB88151APNF-G-201-JNEFE1 Multiply- by-2 33.2 MHz to 66.8 MHz MB88151APNF-G-400-JNEFE1 MB88151APNF-G-401-JNEFE1 Multiply- by-4 66.4 MHz to 133.6 MHz MB88151APNF-G-500-JNEFE1 MB88151APNF-G-501-JNEFE1 Multiply- by-1/2 8.3 MHz to 16.7 MHz MB88151APNF-G-800-JNEFE1 MB88151APNF-G-801-JNEFE1 by-8 66.4 MHz to 133.6 MHz MB88151APNF-G-100-JNERE1 MB88151APNF-G-101-JNERE1 by-1 16.6 MHz to 33.4 MHz Emboss taping (ER type) MB88151APNF-G-200-JNERE1 MB88151APNF-G-201-JNERE1 Multiply- by-2 33.2 MHz to 66.8 MHz MB88151APNF-G-400-JNERE1 MB88151APNF-G-401-JNERE1 Multiply- by-4 66.4 MHz to 133.6 MHz MB88151APNF-G-500-JNERE1 MB88151APNF-G-501-JNERE1 Multiply- by-1/2 8.3 MHz to 16.7 MHz MB88151APNF-G-800-JNERE1 MB88151APNF-G-801-JNERE1 by-8 66.4 MHz to 133.6 MHz

■ PACKAGE DIMENSION Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 8-pin plastic SOP Le ad pitch 1.27 mm Package width × package length 3.9 × 5.05 mm Lead shape G ullwing Sealing method Pl astic mold Mounting height 1.75 mm MAX Weight 0.06 g 8-pin plastic SOP (FPT -8P-M02) (FPT-8P-M02) C 2002 FUJITSU LIMITED F08004S-c-4-7 1.27(.050) .199 –.008 +.010 –0.20 +0.25 5.05 0.13(.005) M 0.10(.004) 0.44±0.08 (.017±.003) –0.07 +0.03 0.22 .009 +.001 –.003 45˚ 0.40(.016) "A" 0~8˚ 0.25(.010) (Mounting height) Details of "A" part 1.55±0.20 (.061±.008) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3)P i ns width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.