MB88141 FUJITSU | Alldatasheet

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DS04-13211-3EFUJITSU SEMICONDUCTOR DATA SHEET General Purpose Linear IC’s General Purpose Converters CMOS D/A Converter for Digital Tuning (With Built-in OP Amp and I/O Expander) MB88141 nnnn DESCRIPTION The FUJITSU MB88141 is a D/A converter with 12 built-in channels. The 12 analog output channels have built-in OP Amps, providing large current drive capability. Data input is compatible with I2C specifications, and is controlled by two control lines. The built-in I/O expander function allows the MB88141 to be controlled by devices incompatible with I2C bus specifications (provides conversion between I2C serial and 8- or 4-bit parallel I/O). Can be adapted for tuning by electronically variable or pre-fixed resistance, etc. nnnn FEATURES

  • Ultra-low power consumption (0.9 mW/channel T yp.)
  • Ultra-compact package
  • Built-in 12-channel R-2R type 8-bit D/A converter
  • Built-in analog output amplifier (maximum sink current 1.0 mA, maximum source current 1.0 mA)
  • Analog output range 0 V to V CC (Continued) nnnn PACKAGES 24-pin plastic DIP 24-pin plastic SOP 24-pin plastic SSOP (DIP-24P-M02) (FPT-24P-M01) (FPT-24P-M03) “Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.”

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  • 5 V single power supply
  • Power supply/GND for MCU interface and OP Amp is separate from power supply/GND for D/A converter
  • Power supply for D/A converter is divided into two systems for VDD1 /VSS1 (AO1 to AO4) and VDD2 /VSS2 (AO5 to AO 12), allowing separate level settings for each system
  • Compatible with serial data input, I2C specifications
  • Built-in I/O expander function (converts between I2C serial and 8- or 4-bit parallel)
  • CMOS process
  • Packages: DIP 24-pin, SOP 24-pin, SSOP 24-pin

(TOP VIEW) (DIP-24P-M02) (FPT-24P-M01) (FPT-24P-M03) AO1 AO2 AO3 AO4 D7/AO5 D6/AO6 D5/AO7 D4/AO8 D3/AO9 D2/AO10 D1/AO 11 D0/AO12 GND VSS1 VDD1 SDA SCL MOD CS2 CS1 CS0 VDD2 VSS2 VCC

*1: The MOD and CS0-CS2 pins should be used with fixed level input. *2: Use particular caution in handling the SDA and SCL pins. These pins have no transistor protection against VCC voltage and therefore have weaker anti-static characteristics than other pins. *3: When using the I/O expander function together with the D/A converter function, take care that D/A converter output precision is within a range that will not affect overall system operation. Pin no. Symbol I/O Description 21 SDA BUS I2C bus data input/output pin (hysteresis input). *2 Outputs the acknowledge signal. 20 SCL I I 2C bus shift clock input pin (hysteresis input). *2

19 MOD I

D/A converter and I/O expander mode switching pin. *1, *3 Input “L” to operate as a D/A converter, “H” to operate as I/O expander and D/A converter. CS0 CS1 CS2 I Lower 3 bits of the slave address setting pins. * This allows up to eight MB88141 chips to be used on the same bus line. AO1 AO2 AO3 AO4 O 8-bit D/A output with OP Amp. * D7/AO5 D6/AO6 D5/AO7 D4/AO8 D3/AO9 D2/AO10 D1/AO11 D0/AO12 I/O 8-bit D/A output with OP Amp. * In I/O expander operation, these pins function as parallel data input/output pins. 13 VCC ¾ Power supply pin for digital circuits and OP Amp. 24 GND ¾ GND pin for digital circuits and OP Amp. 22 VDD1 ¾ Reference power supply pin for D/A converter (H). AO1 to AO4. 23 VSS1 ¾ Reference power supply pin for D/A converter (L). AO1 to AO4. 15 VDD2 ¾ Reference power supply pin for D/A converter (H). AO5 to AO12. 14 VSS2 ¾ Reference power supply pin for D/A converter (L). AO5 to AO12.

D 0 D 7 D 0 D 7 D 0 D 7 D 0 12 ch 5 ch I2C Bus Interface D/A & I/O Control Logic 4 ch 1 ch 8-bit latch 8-bit latch 8-bit latch 8-bit latch R-2R ladder circuit R-2R ladder circuit R-2R ladder circuit R-2R ladder circuit D 7 -+ -+ -+

The MB88141 data configuration differs in each of the two operating modes (D/A converter (12-channel) and I/O expander plus D/A converter), selected by the MOD pin signal. 1. For D/A Converter (12-channel) Operation (MOD = “L”) (1) I2C Bus Format (2) Slave Address Comparison (7 bits) Address comparison: Operates only for devices whose own slave address (internally fixed CS6 to CS3 and externally set CS2 to CS0) matches the slave address input value. (3) R/W Selection (1 bit) Fixed at “0” (the D/A converter performs write operations only). Slave address input (7 bits) Internally fixed Externally set S6 S5 S4 S3 S2 S1 S0 CS6 CS5 CS4 CS3 CS2 CS1 CS0 1001000 = 1001000 1001001 = 1001001 1001010 = 1001010 1001011 = 1001011 1001100 = 1001100 1001101 = 1001101 1001110 = 1001110 1001111 = 1001111 P First A A A S6 S0 C0 R/W C7 D7 D0 Last S 0Slave address (7 bits) Channel selection (8 bits) D/A data (8 bits) : Sent from master device : Sent from MB88141 (slave device) S: “Start” condition P: “Stop” condition A: “Acknowledge” output

(4) Channel Selection (8 bit)

  • : Don’t care *1: The 1 byte of data following the channel selection is set on all channels (all channels set to the same data value). *2: The 12 bytes of data following the channel selection are set on all channels (all channels set to separate data values). Note: Setting will repeat, continuing in order from ch1, until the start and stop conditions are acknowledged. (5) D/A Data (8 bits) Note: VREF = VDD - VSS C7 C6 C5 C4 C3 C2 C1 C0 Channel select
  • ··· 0 0 0 0 All channels selected * 1
  • ··· 0001 A O 1 s e l e c t e d
  • ··· 1 1 0 0 AO12 selected
  • ··· 1101 D o n ’ t c a r e
  • ··· 1110 D o n ’ t c a r e
  • ··· 1 1 1 1 All channels selected * 2 D7 D6 D5 D4 D3 D2 D1 D0 Channel select 00000000 @ VSS 00000001 @ (VREF / 256) · 1 + VSS 00000010 @ (VREF / 256) · 2 + VSS 11111110 @ (VREF / 256) · 254 + VSS 11111111 @ (VREF / 256) · 255 + VSS A AA P0S Slave address (7 bits) XXXX0000 D/A data (8 bits) A AA A PS 0 • • •Slave address XXXX1111 AO1 data AO12 data : Sent from master device : Sent from MB88141 (slave device) S: “Start” condition P: “Stop” condition A: “Acknowledge” output
  1. For D/A Converter + I/O Expander Operation (MOD = “H”) (1) I2C Bus Format (2) Slave Address Comparison (7 bits) Slave address comparison is the same as for D/A converter (12-channel) operation (see “1. (2) “Slave Address Comparison”), with the exception that the CS2 setting determines the number of D/A converter channels and the number of I/O expander bits. When CS2 = “1” is selected, the upper 4 bits (D 7 to D4) of write operations (I2C bus to parallel interface) are ignored, and the upper 4 bits or read operations (parallel interface to I2C bus) are output at “0” (low). (3) R/W Selection (1 bit) CS2 D/A converter I/O expander 0 4 channels (AO1 to AO4) 8 bits (D7 to D0) 1 8 channels (AO1 to AO8) 4 bits (D3 to D0) R/W I/O expander operation D/A converter operation 0I 2C bus input fi parallel data output I 2C bus input fi analog output

1 Parallel data input fi I2C bus output ¾

First S6 S0 R/W D7 D0 Last LastD0D7C0C7R/WS0S6First S 1 A A A A A P PSlave address (7 bits) Digital data (8 bits) Slave address (7 bits) Channel selection (8 bits) Digital data (8 bits) : Sent from master device : Sent from MB88141 (slave device) S: “Start” condition P: “Stop” condition A: “Acknowledge” output

(4) Channel Selection (8 bits) ( ): When using D/A converter 8 channel, I/O expander 4 bit operation.

  • : Don’t care (5) D/A Data (8 bits) Same as “1. (5) D/A Data (8 bits).” (6) I/O Expander Continuous Operation I2C bus input fi parallel data output Note: In continuous operation, operation continues until start and stop conditions are acknowledged. Parallel data input fi I 2C bus output C7 C6 C5 C4 C3 C2 C1 C0 Channel select
  • ··· 0 0 0 0 I/O expander operation
  • ··· 0001 A O 1 s e l e c t e d
  • ··· 0100 A O 4 s e l e c t e d
  • ··· 0101 D o n ’ t c a r e ( A O 5 s e l e c t e d )
  • ··· 1000 D o n ’ t c a r e ( A O 8 s e l e c t e d )
  • ··· 1001 D o n ’ t c a r e
  • ··· 1110 D o n ’ t c a r e
  • ··· 1 1 1 1 I/O expander continuous operation AA A A P0S •••Slave address XXXX1111 Digital data Digital data AS 1 AAA P•••Slave address Digital data Digital data Digital data : Sent from master device : Sent from MB88141 (slave device) S: “Start” condition P: “Stop” condition A: “Acknowledge” output

nnnn TIMING CHART (I2C BUS SPECIFICATIONS) nnnn ANALOG OUTPUT VOLTAGE RANGE "Start" condition Analog output HiZ state Load data Load data Digital input HiZ input HiZ state "Acknowledge" response "Acknowledge" response "Acknowledge" response "Acknowledge" response "Stop" condition Delay Delay Data change 123 45 6789 10 DX D7 D6 D5 D6 D0 D0 D7 D7 11 12 17 18 19 20 26 27 S5 S4 S3 S2 S1 S0 R/W ACK ACK ACK C7 C6 C5 C0 D7 D6 D0SDA input SCL input AO1 to AO12 D0 to D7 output D0 to D7 input SDA output Note:

  • The SDA input acknowledge response (ACK) is an output signal from the MB88141.
  • The D0-D7 input and output timing represent the timing of switching to write and read operations respectively. Also, D0-D7 input remains in HiZ state between the end of a read operation and the acknowledgment of the next I/O write signal. GND ( = VSS1, VSS2) VCC ( = VDD1, VDD2)VDD1 & VDD2 Operating amp circuit Analog output range R-2R ladder circuit VSS1 & VSS2

nnnn ABSOLUTE MAXIMUM RATINGS *: VCC ‡ VDD1 ‡ VSS1 , VCC ‡ VDD2 ‡ VSS2 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Conditions Rating Unit Min. Max. Supply voltage V CC With reference to GND, at Ta = +25 °C -0.3 +7.0* V VDD -0.3 +7.0* V VSS -0.3 +7.0* V Input voltage V IN -0.3 V CC + 0.3 V Output voltage V OUT -0.3 V CC + 0.3 V Power consumption P D ¾¾ 250 mW Operating temperature Ta ¾- 20 +85 °C Storage temperature Tstg ¾- 55 +120 °C Parameter Symbol Conditions Value Unit Min. Typ. Max. Supply voltage 1 VCC ¾ 4.5 5.0 5.5 V GND ¾¾ 0 ¾ V Supply voltage 2 VDD1 VCC ‡ VDD1 > VSS1 VDD1 - VSS1 ‡ 2.0 V 2.0 ¾ VCC V VSS1 0 ¾ 3.5 V Supply voltage 3 VDD2 VCC ‡ VDD2 > VSS2 VDD2 - VSS2 ‡ 2.0 V 2.0 ¾ VCC V VSS2 0 ¾ 3.5 V Analog output current IAL Source current 0 ¾ 1.0 mA IAH Sink current 0 ¾ 1.0 mA Oscillator limit output capacitance COL ¾¾ ¾ 1.0 mF Digital data setting range ¾¾ #00 ¾ #FF ¾ Operating temperature Ta ¾- 20 ¾+ 85 °C

nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics (1) Digital Circuits (VCC = 5 V ± 10% , GND = 0 V , T a = -20 °C to +85 °C) (2) Analog Circuits 1 (VCC = 5 V – 10% , GND = 0 V , T a = -20 °C to +85 °C) Parameter Symbol Pin name Conditions Value Unit Min. Typ. Max. Supply voltage V CC VCC ¾ 4.5 5.0 5.5 V Supply current I CC SCL = 400 kHz, no load ¾ 1.0 3.7 mA Input leak current I ILK SDA, SCL, CS0, CS1, CS2, MOD, D0 to D7 VIN = 0 to VCC -10 ¾+ 10 mA “L” level input voltage V IL ¾ 0 ¾ 0.3 VCC V “H” level input voltage VIH ¾ 0.7 VCC ¾ VCC V Input hysteresis width V HYS SDA, SCL ¾ 0.05 VCC ¾¾ V “H” level output voltage VOH D0 to D7 IOH = -400 mAV CC - 0.4 ¾¾ V “L” level output voltage VOL1 IOL = 2.5 mA ¾¾ 0.4 V VOL2 SDA IOL = 3.0 mA ¾¾ 0.4 V VOL3 IOL = 6.0 mA ¾¾ 0.6 V Parameter Symbol Pin name Conditions Value Unit Min. Typ. Max. Current consumption I DD VDD1, VDD2 No load IDD = IDD1 + IDD2 ¾ 1.2 2.5 mA Analog voltage VDD VDD1 - VSS1 ‡ 2.0 V VDD2 - VSS2 ‡ 2.0 V 2.0 ¾ VCC V VSS VSS1, VSS2 GND ¾ 3.5 V Resolution Res AO1 to AO12 No load VDD1 , VDD2 £ VCC - 0.1 V VSS1 , VSS2 ‡ 0.1 V ¾ 8 ¾ bit Monotonic increase Rem ¾ 8 ¾ bit Non-linearity error LE -1.5 ¾+ 1.5 LSB Differential linearity error DLE -1.0 ¾+ 1.0 LSB

Non-linearity error: Error in the input/output curve with respect to a straight line connecting output voltage at “00” and output voltage at “FF” levels. Differential linearity error: Deviation from ideal voltage with respect to a 1-bit increase in digital value. (3) Analog Circuits 2 (VCC = VDD1 = VDD2 = 5.0 V , GND = VSS1 = VSS2 = 0.0 V , T a = -20 °C to +85 °C) Parameter Symbol Pin name Conditions Value Unit Min. Typ. Max. Output minimum voltage 1 VAOL1 AO1 to AO12 IAL = 0 mA Digital data “00” VSS ¾ VSS + 0.1 V Output minimum voltage 2 VAOL2 IAL = 500 mAV SS - 0.2 V SS VSS + 0.2 V Output minimum voltage 3 VAOL3 IAH = 500 mAV SS ¾ VSS + 0.2 V Output minimum voltage 4 VAOL4 IAL = 1.0 mA V SS - 0.3 V SS VSS + 0.3 V Output minimum voltage 5 VAOL5 IAH = 1.0 mA V SS ¾ VSS + 0.3 V Output maximum voltage 1 VAOH1 IAL = 0 mA Digital data “FF” VDD - 0.1 ¾ VDD V Output maximum voltage 2 VAOH2 IAL = 500 mAV DD - 0.2 ¾ VDD V Output maximum voltage 3 VAOH3 IAH = 500 mAV DD - 0.2 V DD VDD + 0.2 V Output maximum voltage 4 VAOH4 IAL = 1.0 mA V DD - 0.3 ¾ VDD V Output maximum voltage 5 VAOH5 IAH = 1.0 mA V DD - 0.3 V DD VDD + 0.3 V VAOH VAOL #00 Analog output #FF Ideal linearity Non-linearity error Digital setting Note: VAOH and VDD , as well as VAOL and VSS are not necessarily the same values.

  1. AC Characteristics *3: The I/O expander input open time value applies to read operation following an I/O write operation, or to an I/O write operation following a read operation. Parameter Symbol Con- dition Value UnitStandard mode High speed mode Min. Max. Min. Max. SCL clock frequency f SCL ¾ 0 100 0 400 kHz Bus free time between “stop” condition and “start” condition tBUF ¾ 4.7 ¾ 1.3 ¾m s Hold time (resend) “start” condition. The first clock pulse is generated after this interval. t HD ; STA ¾ 4.0 ¾ 0.6 ¾m s SCL clock low hold time t LOW ¾ 4.7 ¾ 1.3 ¾m s SCL clock high hold time t HIGH ¾ 4.0 ¾ 0.6 ¾m s Resend “start” condition setup time tSU ; STA ¾ 4.7 ¾ 0.6 ¾m s Data hold time t HD ; DAT ¾ 0 ¾ 00 . 9 ms Data setup time t SU ; DAT ¾ 250 ¾ 100 ¾ ns SDA and SCL signal fall time t R ¾¾ 1000 20 + 0.1 Cb 300 ns SDA and SCL signal rise time t F ¾¾ 300 20 + 0.1 Cb 300 ns “Stop” condition setup time t SU ; STO ¾ 4.0 ¾ 0.6 ¾m s Pulse width of spike suppressed by input filter tSP ¾¾ ¾ 05 0 n s Output fall time when bus capacitance is between 10 pF and 400 pF Sink current 3 mA t OF ¾¾ 250 20 + 0.1 Cb 250 ns Sink current 6 mA ¾¾ ¾ 20 + 0.1 Cb 250 ns I2C bus line capacitance load Cb ¾¾ 400 ¾ 400 pF D/A Analog output settling time t DL ; AO *1 ¾ 100 ¾ 100 ms I/O expander Digital output delay time tDL ; DO *2 ¾ 300 ¾ 300 ns Input open time t DZ ; DI *3 200 ¾ 200 ¾ ns Digital input setup time tSU ; DI ¾ 250 ¾ 100 ¾ ns Digital input hold time t HD ; DI ¾ 0.9 ¾ 0.9 ¾m s *1: Load condition 1 *2: Load condition 2 C AL = 50 pF Measurement point R AL = 10 kW DUT C AL = 50 pF Measurement point DUT
  • Input/output Timing P Digital input Digital outputDigital input Analog output Sr189 Acknowl edge Acknowl edge SP tSU; STO tHD; STAtSU; STAtSPtHD; DATtSU; DAT tHD; STAtBUF tHIGHtLOW tF tHD; DI tDL; DO tDL; AO tDZ; DI tSU; DItDZ; DI tR SDA SCL D0 to D7 D0 to D7 AO1 to AO12 90% 10%
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  • • Note: The discrimination levels are 70% and 30% of VCC .

Part number Package Remarks MB88141P 24-pin plastic DIP (DIP-24P-M02) MB88141PF 24-pin plastic SOP (FPT-24P-M01) MB88141PFV 24-pin plastic SSOP (FPT-24P-M03)

(Continued) 24-pin plastic DIP (DIP-24P-M02) Dimensions in mm (inches) C 1994 FUJITSU LIMITED D24015S-2C-3 0.45±0.08 (.018±.003) INDEX-2 2.54(.100) TYP –0.30 +0.20 30.20 15°MAX 0.51(.020)MIN (.010±.002) 0.25±0.05 1.50 +0.50 1.27(.050) MAX INDEX-1 +0.50 0.98 +.020 –0.039 1.189–.012 +.008 13.55±0.25 (.533±.010) 4.96(.195) 3.00(.118) .059–0 +.020 15.24(.600) TYP MAX MIN

(Continued) (Continued) 24-pin plastic SOP (FPT-24P-M01) Dimensions in mm (inches) C 2000 FUJITSU LIMITED F24007S-3C-5 Ø0.13(.005)M "A" 0.68(.027)MAX 0.18(.007)MAX 0.20(.008) 0.50(.020) Details of "A" part 0.45±0.10 0.05(.002)MIN 7.80±0.405.30±0.30 0.50±0.20 (.020±.008) (STAND OFF) (.018±.004) .600–.008 +.010 –0.20 +0.25 15.24 .006–.001 +.002 –0.02 +0.05 0.15 .268–.008 +.016 –0.20 +0.40 6.80INDEX TYP 1.27(.050) 13.97(.550)REF 2.25(.089)MAX (Mounting height) 0.10(.004)

(Continued) 24-pin plastic SSOP (FPT-24P-M03) Note) * marked dimensions do not include resin residues. Dimensions in mm (inches) C 2000 FUJITSU LIMITED F24018S-2C-3 0.50±0.20 (.020±.008) (STAND OFF) 0 10° Details of "A" part 7.15(.281)REF NOM 7.60±0.20 "A" .006–.001 +.002 –0.02 +0.05 0.15 .049–.004 +.008 –0.10 +0.20 1.25 .009–.002 +.004 –0.05 +0.10 0.22 INDEX (Mounting height) 0.10(.004)

For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, T okyo 163-0721, Japan T el: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A. T el: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany T el: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New T ech Park, Singapore 556741 T el: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280 Korea T el: +82-2-3484-7100 Fax: +82-2-3484-7111 F0101 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.