MB87073 | DigiCamel IC Datasheet

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MB87073 FUJITSU | Alldatasheet

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1-59-)'2 March 1990 eator3, FUJITSU ehh ooo DATA SHEET = CMOS PLL FREQUENCY SYNTHESIZER CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL) 28 | FREQUENOY SYNTHESIZER ‘The Fujitay MB67073, tabricoted in advanced CMOS technology, ts a serial Input PLL frequency synthesizer. The 887073 contains an lewerter for cscillstor, 8 programmable refersnoe : | divider, a divide factor of programmable reference divider contro! cfroult, a phase detector, a charge pump, a 10-bit shift regityr, @ 18-bit latch, a pro- 7 wammuble divider [a binary 7-bit swallow countar, a binary 11-bit program- mable counter], and a control generator for an external dual modulus prescaler. When supplemented with # loop filter and VCO, the MBS7073 contains the PLASTIC PACKAGE twotssary clroult to make up PLL frequency synthesizer. Typically, a dust Oonrenaned modubus prescaler such as the M8501 L can be odded, allowing Input frequency operation up to 1.1GHz. . © Sings power supply voltage: © Programmable 18-bit divider with Voo *2.7 to $.8¥ Input amelitier consisting of: © Wide teenper ature range: Binary 7-bit swallow counter Ta = 40 to 88°C Binary 11-bit programmable © 13MHz typical input capebillty counter BBV (fi, input) © 2 type of phase detector output © Onchip inverter for oxtillator On-chip charge pume output fuse monn © B divide factors for programmable Output for external charge pump referance divider Is telected by $, © Emsy Interface to Fujitsu dust S and S3 input (1/8, 1/16, 1/64, modubss prescalar 2s, 1/286, 10012, 1/1024, PIN ASSIGNMENT ABSOLUTE MAXIMUM RATING (Se9 NOTE) (Vs3 = OV) [patna [van ume] Thy [eer | veo | veraswvava |v | | sett! 7 wBwe = == lv | Ow l]3 “yy La [ewevaton | voor | va-steveoros |v | | “Uh | abe [owtowtcurent | tows | #10 ma wnt obs [opmvatain Ovout | Voor | Vee-05t0Vooea0 | v_| uce Bs [operate Tompwanre | Ta | ores | °c wet}? oPior [someones | toe | awe [ve | | Ct pm ee NOTE: Permanent davice damage may occur if ABSOLUTE maximum — | [he device coamns clsniey, fe Rees oe } he as detailed in the operations! sections a Sorrel pracewiions ; that, Exponure 1o abethute maximum rating condition: for extended | svelitedin, 01 bry, wees Se ace pariods may affect davice reliabitity, sircult 2-37

[e=[ew [el oe ee Clock signal input for 18-bit shift register. Each rising adge of the clock shifts one bit of the dats Into the shifter register, Serial data input for 18-bit shift register, ‘This data ts used for setting the divide fector of programmable divider. Load enabite input. ‘When this pin is high level (high active), the data stored In the 16-bit shift cogistor bs transferred to 16-bit latch. Input for programeable divider fram VCO or presealar output. Thit Input Involves bles cireult and amplifier. The connection with external ual modutus prescalar should be an AC connection. Control output for external dual modutus prescaler, ‘Tha connection to the prescaler should be OC connection. This output level is synchronized with falling edge of fin input signal (pin #5). Pulse Swallow Function: MBSO1L «= M-=Highs Preset modulus fector 64 or 128 Mm Low: Preset modulus fector 65 of 129 Output of phase detector. Jt Is high level whan f, and fy are equal, and then the loop ls locked, Othar- weiss It outputs negative pulte signal. ‘Threestate charge pump outgut of the phase detector, ‘The made of Do |s changed by the combination of programmable reference dhider output frequency f, and progammable divider output frequency f, as listed bebow: fe> ty | Orive mode {Dg = High level) fe" fp i Highr-impedance mode fe Sfp i Sink mode {Dg = Low level) Phase detector outputs for an extemal charge pump. ‘The mods of @R and OP are changed by the combination of programmable reference divider output frequency f, and programmable divider output fre- quency f, as listed below: oR OP te > ty Lows Low fe = tp: Low: Migh-lnpedanes fe < fps High: High-lnpedance “OP is 4 N-channel open drain output. 2-39

PIN DESCRIPTION (continued) (2) pe eee Control input for programmable reference divider. The combination of these inputs provides 8 kinds of divide factor for the programmable reference divider. Divide NARBRRREE pos felifofifols fos | | & [ofolifsfolfofs] +s | [= feofeofolfofifirfifi] [| o | SERS wna ‘Cutput of the inverting amplifier. This pin should ke open when an external osciliator Is used. Input to the inverting amplifier that forms part of the oscillator, This pin receives the oscillator signal #s AC coupled when an external orcillstor Is wed. For largo amplitude signals (standard CMOS levels) DC coupling may slo be und. 2-40

DIVIDE FACTOR OF PROGRAMMABLE DIVIDER Garlal date of binary code Is input to Data pin, These data are loaded into the 18-Dit shift register from MSB. When bosd enable ‘signal LE is high, tha data stored in the 18-bit shift register is transferred to the 18-bit latch. ‘The data (@) to @) set # divide factor of the binary 7-bit swallow counter and date(®) to GB) set « Pivide factor of binary T1-bit programmable counter. in other words, serial data Is equevslent to the divide factor of programmable divider. Fig. 2 = BLOCK OIAGRAM OF PROGRAMMABLE DIVIDER a Cl a GGG CG Groans REGISTER| FFT FE-4-4 1444444444 5-4 LTTE Ee | Ses ee H }OFVIDER | (rennet 2-41

—_Reaaaweeoeoooooeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee aaa... FUJITSU MICROELECTRONICS SLE D EM 3749762 OOL6964 4 BMFMI T-50-17 MB87073 bh Ee] Binary 7-bit Swallow Counter Data Input @|O|© ae Factor A ofofolfofo o}of}o}o]o o}o}]ofo}jo o|o}]o]o}jo of o}]o}oj]4 rpauptarjparsya Note: Davide factor A: 0 to 127 Depending upon the divide factor set input (SW) of external prescaler, the input data should be as follows. Example MB5O1L SW=H (64/65); Bit 7 of shift register (7) should be zero. . Binary 11-bit Programmable Counter Data Input Factor N 0 5 t) 6 o 7 1 2047 Note: Divide factor less than 5 is prohibited, Divide factor N: 5 to 2047 PULSE SWALLOW FUNCTION fyco = (NX M) +A} xf, (A<N) fyco + Output frequency of external voltage controlled oscillator (VCO) N Preset divide factor of binary 11-bit programmable counter (5 to 2047) M1 Preset modulus factor of external dual modulus prescaler (e.g. 64 in 64/65 mode, 128 in 128/129 mode of an MBEO1L proscaler) A + Preset divide factor of binary 7-bit swallow counter (0 to 127) fe 1 Output frequency of the programmable reference divider 2-42

FUJITSU MICROELECTRONICS 31E D 3749762 OOL69bS & MFNI T-50-17 MB87073 ety ta > tas ty 2 Ons Date Sia MBB { sr ) Si6 ses, aX =X 3-188 out PLLA a lt Le Clock: Clock signal Input for the 18-bit shift register. Each rising edge of the clock shifts one bit of data into the shift register. Data : Serial data for the 18-bit shift register is input. LE : Load enable input. When LE is high (high active), the data stored in the 18-bit shift register is transferred to the 18-bit latch, ‘The 18-bit data is used for setting ¢ divide factor of the programmable divider. RECOMMENDED OPERATING CONDITIONS \\ [Vss = 0) : eT a Lonenistenmnne [te [|| =» |e _| 2-43

FUJITSU MICROELECTRONICS SLE D EM 3749762 OO16%9bb 8 BEFMI T-50~17 MB87073 ee

ELECTRICAL CHARACTERISTICS

FUJITSU MICROELECTRONICS 3LE D KE 3749762 0016967? T MMFMI T-50-17 | MB87073 srs ELECTRICAL CHARACTERISTICS (continued) (Vo = 5.0V, Vss = OV, Ta = —40 to 85°C) Parameter Symbol [sim [te [mm | and v plitude in AC and BA a a [ie [tm | vwnvowveo [| so | | Input Current BA ar and v OSCour and Lento Output arent | O8tour vorew | ol |_| N-channel Open Drain Cut . Off Current [or | tor | vo-veorso | | | | HA Max. Operating Frequency of Programmable Reference Divider Max. Operating Frequency of Programmable Divider Note: *1 fin = 5.OMHz, 12.8MHz Crystal Is connected between OSCiy and OSCoyr. Inputs are connected to ground except for fin and OSCour. Outputs are open. 2-45

FUJITSU MICROELECTRONICS 32E D EM 3749762 OOLL9b8 1 EAFNI . T-50-17 MB87073 Fig. 3 — TYPICAL APPLICATION EXAMPLE cy Vextien.8v1 16 18 14131211 10 9 © outeuT weerers Geek —| | pKa : I fo | g3ese top: §SSSES 0008: tity Veco 12 3 4 CI] Xt: 12aMHe Xt 100086: I Vex: 8V Max. ito ——— Joa 2-46 :

[FUJITSU MICROELECTRONICS 3LE D MM 3749762 0016969 3 EMFMI 7-50-17 MB87073 PACKAGE DIMENSIONS 16-LEAD PLASTIC DUAL IN-LINE PACKAGE 628] (CASE No.: DIP-16P-M04) 770%: 808119.584 8.29) \\ wont + ection

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“FUJITSU MICROELECTRONICS SLE D MM 3749762 0016970 T MFNI 7 1-50-17 mpe7o7s PACKAGE DIMENSIONS (Continued) 46-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-16P-M02) ‘| 2021005) o bea “eee | TT Sa | ‘ .. : 260/089) ner —} : eaten | 2-48 i

Product Information

MB87073 specifications and overview.

Summary

CMOS PLL FREQUENCY SYNTHESIZER

Description

CMOS PLL FREQUENCY SYNTHESIZER

Source title MB87073 Datasheet(PDF) - fujitsu semiconductor

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