MB86961A FUJITSU | Alldatasheet
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UNIVERSAL INTER FACE FOR 10 BASE -T FE ATURES
- Full-duplex capability
- Combines Manchester encoder/decoder and twisted pair transceiver functions
- Direct interface to all popular Ethernet controllers
- Direct interface to A UI and 10B ASE-T outputs
- Manual or automatic A UI /10B ASE-T selection
- Integrated pulse shaper and Tx/Rx filters
- Selectable 100 Ω /150 Ω termination permits opera- tion with shielded or unshielded twisted pair cable
- R everse-polarity detection for receiver with auto- matic correction
- On-chip jabber logic, SQE test and link test with enable/disable option
- Remote signaling of link down and jabber condi- tions
- Programmable receive threshold for extended range
- Output drivers for receive, transmit, collision and link test pass LED indicators
- TP loopback enable/disable for external loopback testing
- Power down mode for minimum power dissipation
- Automatic shut-down of unused port to reduce power consumption
- Low power CMOS technology, single 5 volt power supply
- 44-pin PLCC and 48-pin PQFP packages GENERAL DESCRIPTION The MB86961A Un iversal Interface for 10B ASE-T (Twisted-Pair) Ethernet is fully compliant with the IEEE 802.3 specifications for A UI (Attachment Unit Interface) and 10B ASE-T (Twisted-Pair) interfaces and provides the electrical interface between an Ethernet controller and the DB15 ( A UI) and RJ45 (10B ASE-T) connections to an Ethernet local area network. Functions provided by the MB86961A include Manchester encoding and decoding of the serial data stream, level conversion, collision detec- tion, signal quality error (SQE) and link integrity testing, jabber control, loopback, and automatic correction of polarity reversal on the twisted-pair input. Pulse shaping and filtering functions are performed by the MB86961A to eliminate the need for external filtering components and thus reduce overall system cost. The device also provides outputs for receive, transmit, colli- sion and link test LEDs and provides compatibility with both shielded and unshielded twisted pair cables. The receive threshold can be reduced to allow an extended range between nodes in low noise environments. Its wide range of features and its ability to interface to virtually all popular controllers make the MB86961A the ideal device for twisted pair Ethernet applications. The MB86961A is part of a complete family of Ethernet devices available from Fujitsu. It is fabricated in a low- power CMOS technology and is supplied in a 44-pin PLCC and 48-pin PQFP packages. PIN CONFIGUR ATION TPIN TPIP UTP TPONB TPONA VCC2 GND2 TPO PA TPOPB PLR R JAB RLD LI JAB TEST TCLK TXD TEN CL KO CLKI COL AU TOSEL 2827262524232221201918 TOP VIEW MD1 NTH CIN VCC1 DON DOP DIP PAUI DIN CIP MD0 LEDR LEDT/PDN LEDL LEDC/XLBK LBK GND1 RBIAS RCMPT RXD CD RCLK 4041424344123456 (PLCC Package Shown)
PIN ASSIGNMENT - 44-PIN PLCC
12 TXD I
13 TEN I
14 CL KO O
15 CLKI I
16 COL O
17 AU TOSEL I
18 LEDR O
19 LEDT/PDN O/I
20 LEDL O/I
21 LEDC/XLBK O/I
22 LBK I
1 VCC1 —
2 CIP I
3 CIN I
4 NTH I
5 MD0 I
6 MD1 I
7 RLD O
8 LI I
9 JAB O
10 TEST I
11 TCLK O
23 GND1 —
24 RBIAS I
25 RCMPT O
26 RXD O
27 CD O
28 RCLK O
29 R JAB O
30 PLR O
31 TPOPB O
32 TPO PA O
33 GND2 —
34 VCC2 —
35 TPONA O
36 TPONB O
37 UTP I
38 TPIP I
39 TPIN I
40 PAUI I
41 DIP I
42 DIN I
43 DOP O
44 DON O
PACK AGE STYLE PACK AGE CODE VCC = +V+ 5% LCC-44P-M02 MB86961APD- G44-Pin Plastic Leaded Chip Carrier PIN PIN PIN PIN PIN ASSIGNMENT - 48-PIN PQFP
13 RLD O
14 LI I
15 JAB O
16 TEST I
17 TCLK O
18 TXD I
19 VCC —
20 TEN I
21 CLKO O
22 CLKI I
23 COL O
24 AU TOSEL I
1 PAU I I
2 DIP I
3 DIN I
4 DOP O
5 DON O
6 N C —
7 VCC —
8 CIP I
9 CIN I
10 NTH I
11 MD0 I
12 MD1 I
25 LEDR O
26 LEDT/PDN O/I
27 LEDL O/I
28 LEDC/XLBK O/I
29 LBK I
30 GND —
31 NC —
32 RBIAS I
33 RCMPT O
34 RXD O
35 CD O
36 RCLK O
37 R JAB O
38 PLR O
39 TPOPB O
40 TPO PA O
41 GND —
42 VCC —
43 VCC —
44 TPONA O
45 TPONB O
46 UTP I
47 TPIP I
48 TPIN I
FP T-48P-M02 M B86961APF-G48-Pin Plastic Quad Flat Package
& Filter EXL TX AMPRX Slicer Drop Cable Interface Collision Receiver Watch- Dog Timer PAUI LI LBK TCLK CLK1 TEN TXD RLD RJAB RCMPT CD LEDL RXD RCLK COL MD0 MD1 UTP TPOPB TPOPA TPONA TPONB TPIP TPIN DOP DON DIP DIN CIP CIN DO DI CI LEDT/PDN LEDR LEDC/XLBK NTH JAB PLR CMOS TX AMP LPBK CLK0
AUTOSEL I AUTOMATIC PORT SELECT: When AUTOSEL=1, automatic port selection is enabled (The MB86981A defaults to the AUI port only if TP link integrity=Fail). When AUTOSEL=0, manual port selection is enabled (the PAUI pin determines the active port). CD O CARRIER DETECT: An output to notify the controller of activity on the network. CIP CIN I I AUI COLLISION PAIR: Differential input pair connected to the AUI transceiver CI cir- cuit. The input is collision signaling or SQE. CLKO CLKI O I CRYSTAL OSCILLATOR: A 20MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI. COL O COLLISION DETECT: Output which drives the collision detect input of the controller. DIP DIN I I AUI RECEIVE PAIR: Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. DOP DON O O AUI TRANSMIT PAIR: A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. JAB O JABBER INDICATION: Output goes high to indicate Jabber state. LBK I LOOPBACK: When LBK=1, forced loopback is enabled. When LBK=0, normal loop- back is enabled. LEDC/XLBK O/I COLLISION LED: Open drain driver for the collision indicator. Output is pulled low during collision ( half-duplex mode). If externally tied low, the MB86961A disables the internal TP loopback and collision detection circuits in anticipation of external TP loopback or full-duplex operation. MB86961A is ready for loopback testing 16 ms after this pin goes low. No delay is needed when the pin goes high. LEDL O/I LINK LED: Open drain driver for link integrity indicator. Output pulled low during link test pass. If externally tied low, internal circuitry is forced to “Link Pass’ state and the MB86961A will continue to transmit link test pulses. LEDR O RECEIVE LED: Open drain driver for the receive indicator LED. Output is pulled low during receive. LEDT/ PDN O/I TRANSMIT LED/POWER DOWN: Open drain driver for the transmit indicator. Out- put is pulled low during transmit. If externally tied low, the MB86961A goes to power down state. LI I LINK TEST ENABLE: When LI=0, the Link Integrity Test function is disabled. When LI=1, the Link Integrity Test function is enabled. MD0 MD1 I I MODE SELECT: Mode select pins which determine controller compatibility mode. See Table 1. NTH I NORMAL THRESHOLD: When NTH=1, the normal TP squelch threshold is in effect. When NTH=0, the normal TP squelch threshold is reduced by 4.5 dB. PAUI I PORT/AUI SELECT: In Manual Port Select mode (AUTOSEL=0), PAUI selects the active port. When PAUI=1, the AUI port is selected, When PAUI=0, the TP port is selected. In Auto Port Select mode, PAUI is ignored. PLR O POLARITY REVERSE: Output goes high to indicate reversed polarity. RBIAS I BIAS CONTROL: A bias resistor at this pin controls the bias of the operating circuit. RCLK O RECEIVE CLOCK: A recovered 10 MHz clock which is synchronous with the received data and connected to the controller receive clock input.
SIGNAL DESCRIPTIONS (Continued) Symbol Type Description RCMPT O REMOTE COMPATIBILITY: Output goes high to signal the controller that the remote port is compatible with the MB86961A remote signaling features. RJAB O REMOTE JABBER: Output goes high to signal the controller that the remote port is in Jabber condition. RLD O REMOTE LINK DOWN: Output goes high to signal to the controller that the remote port is in link down condition. RXD O RECEIVE DATA: Output signal connected directly to the receive data input of the controller. TCLK O TRANSMIT CLOCK: A 10 MHz clock output. This clock signal is directly connected to the transmit clock input of the controller. TEN I TRANSMIT ENABLE: Enables data transmission and starts the watchdog timer. Synchronous with TCLK (see Figures 14, 20, 26, and 32 for details). TEST I TEST: Input for factory test of the device. Leave open for normal operation. TPIP TPIN O O RECEIVE TWISTED-PAIR: A differential input pair from the twisted-pair cable. Receive filter is integrated in-chip. No external filters are required. TPOPA/B TPONA/B O O TRANSMIT TWISTED PAIR: Two differential driver pair outputs (A and B) to the twisted-pair cable. The output is pre-equalized, no external filter is required. Two pairs are used to provide compatibility with both 100Ω load cable and 150Ω load cable. TXD I TRANSMIT DATA: Input signal containing NRZ data to be transmitted on the net- work. TXD is connected directly to the transmit data output of the controller. UTP I UTP/STP: When UTP=0, 150Ω termination for shielded TP is selected. When UTP=1,100 Ω termination for unshielded TP is selected. VCC1, VCC2 — POWER INPUTS: +5V power supply inputs. GND1 GND2 GROUND RETURNS 1 & 2: Grounds
Figure 2. LAN Adapter Board Application - Auto Port Select with External Loopback Control
12.4 KΩ ±1%
Figure 3. LAN Adapter Board Application - Manual Port Select with Link Test Function
Figure 4. Twisted-Pair Only Application
Figure 5. AUI Encoder/Decoder Only Application
12.4 KΩ± 1%
10BASE-T twisted-pair networks). Data output (DO), Data Input (DI) and Collision (CI). Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). ers for visual status reporting. and drives the AUI DO circuit. Table 1. MB86961A Compatibility Modes
- Mode 1: Figures 12-17
- Mode 2: Figures 18-23
- Mode 3: Figures 24-29
- Mode 4: Figures 30-35 The related timing specifications are provided in the elec- trical characteristics section of this data sheet. MD1 MD0 Mode 0 0 Mode 1: Compatible with Advanced Micro Devices AM7990 con- trollers 0 1 Mode 2: Compatible with Intel 82586 controllers 1 0 Mode 3: Compatible with Fujitsu’s MB86960 controller 1 1 Mode 4: Compatible with National Semiconductor 8390 control- lers
Table 2. ABSOLUTE MAXIMUM R ATINGS implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3. INPUT/OUTPUT CHAR ACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Notes: 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Limited functional test patterns are performed at these input levels. The majority of functional tests are per-
formed at levels 0V and 3 V. Table 4. AUI ELECTRICAL CHAR ACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Note: Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 5. TP ELECTRICAL CHARACTERISTICS (T A = 0°C to +70°C, VCC = 5 V±5%) Notes: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
- Parameter is guaranteed by design, not subject to production testing.
Table 6. SWITCHING CHARACTERISTICS (T A = 0°C to +70°C, VCC = 5 V±5%) Note: Parameter is guaranteed by design; not subject to production testing.
Table 7. RCLK/Start-of-Packet Timing Note: Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Table 8. RCLK/End-of-Packet Timing Notes: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
- CD Turn off delay measured from middle of last bit, so timing specification is unaffected by the value of the
Table 9. Transmit Timing Note: Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Table 10. Collision Detection, COL/CI Output and Loopback Timing Note: Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Figure 24. Mode 3 RCLK/SOP Timing Figure 25. Mode 3 RCLK/EOP Timing Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge. Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
27 Bits
17.53±0.13 SQ 16.59±0.08 SQ (.690±.005) (.653±.003) INDEX Details of “A” part R0.95(.037)TYP 16.03±0.51 (.631±.020) R0.75(.030) TYP 0.20 +0.05 -0.02 (.008 ) +.002 -.001 0.66(.026) TYP 4.30 +0.22 -0.11 (.169 ) +.009 -.004 0.43(.017) TYP 0.51(.020)MIN 0.10(.004) “A” 2.70 +0.60 -0.41 (.106 ) +.024 -.046 1.27±0.13 (050±.005) 16.03±0.51 (.631±.020) 12.70(.500)REF 44-pin plastic QFJ (PLCC) (LCC-44P-MO2) 44-pin plastic QFJ (PLCC) (Case No.: LCC-44P-MO2) 1997 FUJITSU LIMITED C44052S-2C-4 Dimension in mm (inches) No.: LEAD No. ORDERING INFORMATION: MB86961APD-G
inches (millimeters) 121 .006(0.16)M 48-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-48P-M02) 1992 FUJITSU LIMITED F48002S-9C .006(0.15) “A” .002(0.05)MIN .346(8.80) .535±.016 .020(0.50) .006(0.15) .024(0.60) Details of “A” part .106(2.70)MAX .677±.016SQ .472 +.012 (12.0+0.30)INDEX LEAD No. .071±.012 Details of “B” part “B” 0° to 10° ORDERING INFORMATION: MB86961APF-G SQ
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