MB86960

MB86960 FUJITSU | Alldatasheet

Document overview

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Technical content

FEATURES

• High-performance packet buffer architecture pipe- lines data for highest throughput
• 20 Mbyte/second data transfer rate to/from the system bus
• on-chip buffer controller manages pointers, reduces software overhead
• Efficient, configurable two bank transmit buffer and ring receive buffer
• Bus-compatible with most popular microprocessors, including RISC
• Complies with international standards for Ethernet, ISO/ANSI/IEEE 8802-3
• High-speed burst and single transfer DMA
• 64-element hash table for multicast address filtering
• High-speed, low-power CMOS technology
• Power down mode reduces power dissipation for battery-powered equipment
• Available in 100-pin plastic quad flat package GENERAL DESCRIPTION The MB86960 Network Interface Controller with Encoder/Decoder (NICE ) is a high-performance, highly integrated monolithic device which incorporates both network controller, complete with buffer manage- ment, and Manchester encoder/decoder. It allows implementation of a 7-chip solution for an Ethernet interface when used with either of Fujitsu’s bus interface chips, the MB86953 for PC/XT/AT or the MB86954 for Micro Channel , and either of Fujitsu’s transceiver chips, the MBL8392A coaxial transceiver or MB86962 10BASE-T twisted-pair transceiver. The unique buffer management architecture of the MB86960 allows packet data to access a buffer memory area from the host and from the network media simultaneously, with virtually no interaction. The network controller updates all receive and transmit pointers internally, thus reducing the software overhead required to control these operations, resulting in superior benchmark speed and application performance. The NICE device has a partitionable 2, 4, 8, or 16 kilobyte, two-bank, transmit buffer which allows multiple data packets to be “chained” together and transmitted to the network from a single transmit command, thus allowing greater design flexibility and throughput. Receive packets are captured in a ring buffer which can be configured in various sizes from 4 to 62 kilobytes, depending on memory equipped and amount used for the transmit buffer. Possible configurations for the system bus interface include I/O mapping, memory mapping and DMA access, or a combination of these. With a 20 Mbyte/sec bandwidth, the NICE system bus interface allows you to use the full throughput capacity of its unique packet buffering architecture. The NICE controller’s selectable bus modes provide both big- and little-endian byte ordering, permitting an efficient data interface with most microprocessors and higher-level protocols. Implemented in Fujitsu’s high-speed, low-power CMOS process, the MB86960 is supplied in a 100-pin plastic quad flat package for surface mounting. PIN CONFIGURATION 31 50 100 81 100–PIN PLASTIC QUAD FLAT PACK (PQFP) TOP VIEW APRIL1993DATA SHEET MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

PIN ASSIGNMENTS AND DESCRIPTIONS Supplied in a 100-pin plastic quad flat pack, the NICE controller presents a small foot-print to the board design, and is surface-mountable with its gull-wing leads. See Pin Configuration and Pin Assignments for the pin numbering.

26 DREQ O

27 DACK I

28 V CC —

29 RD I

30 WE I

31 RESET I

32 BD0 B

33 BD1 B

34 BD2 B

35 BD3 B

36 BD4 B

37 BD5 B

38 BD6 B

39 BD7 B

40 GND —

41 BD8 B

42 BD9 B

43 BD10 B

44 BD11 B

45 BD12 B

46 BD13 B

47 BD14 B

48 BD15 B

49 BOE

O

50 BWE O

1 SD11 B

2 SD10 B

CC —

4 GND —

5 SD9 B

6 SD8 B

I

8 BHE I

9 SW/SB O

10 SA0 I

11 SA1 I

12 SA2 I

13 SA3 I

14 RDY

(RDY) O

15 GND —

16 SD0 B

17 SD1 B

18 SD2 B

19 SD3 B

20 SD4 B

21 SD5 B

22 SD6 B

23 SD7 B

24 EOP

(EOP) I

25 INT O

NO. PIN NAME TYPE

51 BCS0 O

52 BCS1 O

53 V CC —

54 BA0 O

55 BA1 O

56 BA2 O

57 BA3 O

58 BA4 O

59 BA5 O

60 BA6 O

61 BA7 O

62 BA8 O

63 BA9 O

64 BA10 O

65 GND —

66 BA11 O

67 BA12 O

68 BA13 O

69 BA14 O

70 BA15 O

71 TEN B

72 TXD B

73 GND —

74 TXDATA– O

75 TXDATA+ O

Note: Dual function pins have two names with the second in parentheses ( ). B = Bidirectional I/O I = Standard Input O = Totem Pole Output PIN NO. PIN NAME TYPE PIN NO. PIN NAME TYPE

76 X1 I

77 X2 O

CC —

79 GND —

80 TCK B

81 RXDATA– I

82 RXDATA+ I

83 COL– I

84 COL+ I

CC —

86 LBC B

87 AC/DC I

88 RCK B

89 CKOUT O

90 GND —

91 RXD B

92 COL

B

93 CRS B

94 RDYPOL I

95 CNTRL

O

96 RMT O

97 SD15 B

98 SD14 B

99 SD13 B

100 SD12 B

NO. PIN NAME TYPE PIN ASSIGNMENTS

STATUS & CONTROL REGISTERS HASH TABLE READ/WRITE DMA SYSTEM INTERFACE SW/SB RMT CNTRL RESET RDYPOL RDY (RDY) INT EOP (EOP) DREQ DACK CS WE RD BHE SD00 SA0 COL CRS RCK RXD LBC TEN TCK TXD AC/DC COL+ COL RXDATA+ BUFFER CONTROLLLER RECEIVER MANCHESTER ENCODER/ DECODER TRANSMITTER NETWORK CONTROLLER BSC1 BCS0 BD0 BD15 BA0 BA15 BWE BOE CONTROL SA3 SD15 CONTROL INTERNAL ADDRESS BUS INTERNAL DATA BUS RXDATA TXDATA+ TXDATA Rx DATA Tx DATA CKOUT

RESET I HARDWARE RESET: Active high. A minimum pulse of 300 nanoseconds in duration is required. This pin resets NICE’s internal pointers and registers to the appropriate state. Note: NICE must be reset after power start before using. RDY (RDY) O READY: This output is asserted to indicate to the host that NICE is ready to complete the requested read of write operation. It will also be asserted if the device is unable to respond to the request for a read or write within 2.4 microsecond, In that case, NICE will also assert INT and the bus read error status bit, DLCR1<6>, or bus write error status bit DLCR<0>. RDY(RDY) may be an active low or active high signal as determined by RDYPOL, pin 94. If RDYPOL is a “1”, RDY(RDY) will be active high. If RDYPOL is tied to a “0” RDY(RDY) will be an active low signal. RDYPOL I READY POLARITY SELECT: Control input to select the polarity of RDY(RDY), pin 14. When this pin is tied high, RDY(RDY) will be active high. If RDYPOL is tied low, RDY(RDY) will be an active low signal. WE I WRITE: The WE pin is an active low input that enables a write operation form the host system to the buffer memory port or to internal registers selected by system address inputs SA0-3. RD I READ: Active low input specifies that the current transfer between NICE and the host system is a read from one of NICE’s internal registers or its data port as selected by SA0-3. CS I CHIP SELECT: This active low input signal is the chip select for NICE. BHE I BYTE HIGH ENABLE: Active Low. This is the byte/word control line. It is used only when NICE is configured for a 16-bit data bus by the SB/SW bit of DLCR6. It allows word, upper byte only or lower byte only transfers. The address select pin SA0 is used with BHE for byte or word transfers. as follows. SB/SW BHE SA0 FUNCTION 0 0 0 Word transfer 0 0 1 Byte transfer on upper half of data bus (SD15-8) 0 1 0 Byte transfer on lower half of data bus (SD7-0) 0 1 1 Reserved

1 X X Byte transfer (SD7-0)

INT O INTERRUPT: Active low. Indicates that NICE requires host system attention after successful transmission or reception of a packet, or if any error condition occur, if an EOP (end of process) signal from the host occurs after the completion of the DMA cycle. The Interrupt signal is maskable and can be disabled by writing a 0 to the appropriate mask bit. EOP (EOP) I END OF PROCESS: Indicates to NICE that the DMA transfer is finished. When the host DMA controller asserts EOP(EOP), further assertion of NICE’s bus request output. DREQ, will be discontinued. Note: Dual function pins have two names with the second in parentheses ( ). B = Bidirectional I/O I = Standard Input O = Totem Pole Output

System Bus Interface Pins (continued) SYMBOL TYPE DESCRIPTION CNTRL O CONTROL: This pin is the complement of the register bit CNTRL, DLCR4<2>. It is used to control external functions. RMT O REMOTE CONTROL PACKET: When DLCR5<2> is set high, this pin follows the RMT 0900H bit (DCLR1<4>) which indicates that a complete special packet with type field= 0900H has been received. This is intended for use as a remotely-controlled hardware function from other nodes in the network. DREQ O DMA REQUEST: Issued to the DMA controller to indicate that NICE has data available to be read in its receive buffer, of is ready to accept data into its transmit buffer. DACK I DMA ACKNOWLEDGE: Active low, indicate that the DMA controller is ready to transfer data between the host system and NICE’s buffer memory through BMPR8. SA<3:0> I SYSTEM ADDRESS LINES: Specify which of the internal registers of ports of NICE is selected for read/write operations. SD<15:0> B SYSTEM DATA BUS: All data, command and status transfers between the host system and NICE take place over the bidirectional, 3-state, bus. The direction of the transfer is controlled by RD and WE . The register or buffer port being accessed is selected by a combination of DACK (if active, selecting the Buffer Port), of the address pins SA3-0 and register bank select bits REG BANK 1 and REG BANK 0, DLCR7<3:2>. The portion of the data bus over which the transaction occurs is controlled by SB/SW, BHE , and SA0. SW/SB O SYSTEM WORD/SYSTEM BYTE CONFIGURATION: This signal output reflects the inverse of DCLR6<5>, SB/SW. If SW/SB=1, the system interface is configured for word transfers, If SW/SB=0, the system interface is configured for byte-wide transfer on SD7-0, the lower byte. Note: Dual function pins have two names with the second in parentheses ( ). B = Bidirectional I/O I = Standard Input O = Totem Pole Output

Buffer Memory Interface Pins SYMBOL TYPE DESCRIPTION BCS0 O BUFFER CHIP SELECT: BCS1 and BSC0 are the chip select lines, most significant byte and leastBCS0 BSC1 O O BUFFER CHIP SELECT : BCS1 and BSC0 are the chip select lines, most significant byte and least significant byte respectively, of the dedicated buffer SRAMs, Active low. BOE O BUFFER OUTPUT ENABLE: This active low signal is the output enable for the Buffer SRAM, and is asserted by NICE during buffer memory read cycles. BWE O BUFFER WRITE ENABLE: Active low. Used as a write strobe to the buffer SRAM memory during write operations. BD<15:0> B B BUFFER DATA: Data lines between the SRAM buffer memory and NICE. This SRAM data bus is configurable for an 8-bit or 16-bit data size by BUFFER BYTE/BUFFER WORD, BB/BW, inB configurable for an 8-bit or 16-bit data size by BUFFER BYTE/BUFFER WORD , BB/BW , in DLCR6<4>. The transfer byte order within a word, most significant or least-significant byte first, is determined by DATA_ORDER, DLCR7<1>. BA<15:0> O O BUFFER ADDRESS: These lines address up to 64 kilobytes of SRAM buffer memory. Network Interface Pins SYMBOL TYPE DESCRIPTION TXDATA+ O TRANSMIT INTERFACE PAIR: These are the differential outputs to the transceiver for transmitting.TXDATA+ TXDATA– O O TRANSMIT INTERF ACE PAIR: These are the differential outputs to the transceiver for transmitting. RXDATA+ I RECEIVED DATA: These are the Manchester differential inputs from the transceiver to the receiver.RXDATA+ RXDATA– I I RECEIVED DA TA: These are the Manchester differential inputs from the transceiver to the receiver. COL+ COL– I I COLLISION: These differential inputs are driven with a 10 MHz signal when the transceiver detects a collision on the media. AC/DC I AC/DC COUPLING SELECT: AC/DC = 1 selects AC coupling; 0 selects DC coupling for the TXDATA ± outputs. When AC coupling is selected, both TXDATA+ and TXDATA– are driven to the same output voltage level during the transmit idle period to prevent saturation of the isolation transformer. With DC coupling, these outputs remain at a 1 level during idle periods. System Clock Pins SYMBOL TYPE DESCRIPTION X1 I CRYSTAL INPUT: Connection for one side of the 20 MHz crystal, or input for an external 20 MHz clock source. X2 O CRYSTAL OUTPUT: Connection for the other side of the 20 MHz crystal. Leave unconnected if an external clock is used. CKOUT O CLOCK OUTPUT: 20 MHz free-running clock output provided by the crystal oscillator circuit.

The following eight pins are provided for optional connection to an external encoder/decoder. They can also be used for test purposes, but are not used in a typical network interface application. Special encoder/decoder modes are selected by setting DLCR7<7:6>. Refer to the MEDIUM CONNECTION section under SYSTEM CONFIGURATION for a complete description of these modes. Controller — Encoder/Decoder Interface Pins SYMBOL TYPE DESCRIPTION TXD B TRANSMIT DATA: NRZ transmit serial data. Normally not used. In “Encoder/Decoder Bypass” mode and “NICE + Monitor” mode, an output which can be fed to an external encoder. In “Encoder/Decoder Test” mode, an input to the on-chip encoder. TCK B TRANSMIT DATA CLOCK: Clock synchronous with TXD serial data. Normally not used. In “Encoder/Decoder Bypass” mode, a 10 MHz data clock input used by the controller to synchronize the TXD data signal. In “NICE + Monitor” mode and “Encoder/Decoder Test” mode, an output from the on-chip encoder. TEN B TRANSMIT ENABLE: Normally not used. In “NICE + Monitor” mode and “Encoder/Decoder Bypass” mode, this pin is an output which can be used to control an external encoder. When asserted high, TEN enables the encoding of the transmitted data. In “Encoder/Decoder Test” mode, an input to the on-chip encoder. COL B COLLISION PRESENCE: Normally not used. In “Encoder/Decoder Bypass” mode, an active low input which indicates that the collision inputs COL are active, signifying that the transceiver has detected a collision on the media. In “NICE + Monitor” mode and “Encoder/Decoder Test” mode, this is an output from the on-chip encoder/decoder section. COL is a normally high input which changes to a 10 MHz pulse stream during collision detection. LBC B LOOPBACK CONTROL: Normally not used. In “Encoder/Decoder Bypass” mode and “NICE + Monitor” mode, this output should be connected to the loopback control pin of the external encoder/decoder. When this output is asserted high, the external encoder/decoder is placed in loopback mode. TEN enables the encoding of the transmitted data. In “Encoder/Decoder Test” mode, this is an input with the same function. RXD B RECEIVE SERIAL DATA: Normally not used. In “Encoder/Decoder Bypass” mode, “NICE + Monitor” mode and “Encoder/Decoder Test” mode, an NRZ serial bit stream from a decoder or demodulator to the data link controller. RCK B RECEIVE DATA CLOCK: Normally not used. In “Encoder/Decoder Bypass” mode, “NICE + Monitor” mode and “Encoder/Decoder Test” mode, this pin is an input for the serial data clock as recovered by the external decoder or demodulator. CRS B CARRIER SENSE: Normally not used. In “Encoder/Decoder Bypass” mode, an input indicating the presence of incoming data on the network. In “NICE + Monitor” mode and “Encoder/Decoder Test” mode, an output from the on-chip encoder/decoder. Assertion of this active high input indicates that a carrier has been sensed at the RXDATA inputs.

Mode Configuration and Encoder/Decoder Pin Input/Output Table CNF1 CNF0 MODE TXD TCK TEN LBC RXD RCK CRS COL 0 0 NORMAL NICE Internal E/D is used with NICE controller, no signal appears on pins none none none none none none none none 0 1 NICE + MONITOR Internal E/D is used with NICE controller, signal appears on output O O O O O O O O 1 0 E/D BYPASS External E/D is used with NICE controller, internal E/D is shutdown O I O O I I I I 1 1 E/D TEST Internal E/D is used only, NICE controller section is shutdown I O I I O O O O Device Power Pins SYMBOL DESCRIPTION VCC POWER SUPPLY: A +5 VDC ±5% supply is required. GND SYSTEM GROUND: Ordering Code PACKAGE STYLE PACKAGE CODE ORDERING CODE 100-Pin Plastic Quad Flat Pack FPT-100P–M01 MB86960APF–G

A highly integrated system configuration can be achieved with the NICE controller. Figure 1 illustrates a low chip count LAN controller with NICE, a bus interface chip such as Fujitsu’s MB86953 or MB86954, and either a coaxial transceiver such as Fujitsu’s MBL8392A or a 10BASE-T twisted pair transceiver such as Fujitsu’s MB86962. Because of its high integration and unique, innovative architecture, which handles all aspects of packet management and storage, a local microprocessor is not required. The NICE controller connects to the host system bus to provide command and status interfaces as well as packet data access. Command and status registers can be directly accessed by the host processor when mapped into the I/O or memory space of the host. Through a port on the device, data packets to be transmitted to the media are transferred first from host memory to a dedicated buffer memory for temporary storage until transmitted. Received data packets are first stored in the buffer memory, then later transferred to the host memory. HOST CPU MAIN MEMORY MB86960 NICE BUFFER MEMORY LAN NETWORK MEDIUM AUI SYSTEM BUS MB86953 PC OR MB86954 MCA BUS INTERFACE MBL8392A COAXIAL OR MB86962 10BASE–T TRANSCEIVER Figure 1.Typical System Configuration Medium Connection Connection to the LAN medium can be accomplished with any of the popular connection methods: 1) on-board connection to unshielded twisted pair through a 10BASE-T transceiver, 2) on-board connection to a thin 50-Ohm coaxial cable through a 10BASE2 transceiver or 3) off-board connection to any other type of medium, such as standard Ethernet coaxial cable (10BASE5), through an Attachment Unit Interface (AUI) connector. NICE has an encoder/decoder (E/D) on chip. An external encoder/decoder can be used by making the NICE chip act like a controller alone (depending on customer’s needs). This option can be changed by using bits 7 and 6 of DLCR7. Eight pins related to the on-chip E/D can be configured by DLCR7<7:6> (register DLCR7, bits 7 through 6) to operate in one of four modes. These pins are TXD, TCK, TEN, LBC, RXD, RCK, CRS, and COL . In the “Normal NICE” mode, an internal E/D is used. In this mode, the pins are all electrically isolated and no signals appear on the pins. In “NICE + Monitor” mode, all the pins listed above are outputs whose specific signals appear on the pins and can be monitored externally. In “Encoder/De- coder Bypass” mode, an external encoder/decoder is used with the NICE controller, its own internal E/D is shut down. In this mode, the pins are either outputs or inputs as needed to control the external encoder/decoder. In the “Encoder/Decoder Test” mode, only the E/D on NICE is active and accessible, the NICE controller section is shut down. In this mode, the pins are outputs or inputs for an encoder/decoder, with the opposite control direction of the outputs or inputs in the “Encoder/Decoder Bypass” mode. The various possibilities are shown in Figure 2 and the table below. DLCR7 Bit 7 DLCR7 Bit 6 Function 0 0 Normal NICE 0 1 NICE plus Monitor 1 0 Encoder/Decoder Bypass 1 1 Encoder/Decoder Test

Figure 2. Encoder/Decoder Modes connected between pins X1 and X2 on the NICE chip. 0C to 70C, and 18 pF fundamental load.

20 MHz

Figure 3. Crystal Connection

Figure 4. SRAM Configuration

The MB86960 combines the functions of an Ethernet network controller with packet buffer management, and a 10 Mbit/s Manchester encoder/decoder. It consists of four major functional blocks: buffer controller, system interface, transmit controller with Manchester encoder, and receive controller with Manchester decoder. The receive and transmit sections of the chip fully implement the ISO/ANSI/IEEE 8802-3 CSMA/CD specification for 10 Mbit/sec Ethernet. The transmitter assembles data packets for transmission and the receiver disassembles received data packets. Automatic genera- tion and stripping of the 64-bit preamble, and generation and checking of the 32-bit CRC are provided on-chip. Other network functions provided on-chip include collision resolution by binary exponential backoff and re-transmission, several modes of address recognition, error detection and reporting, and serial/parallel and parallel/serial conversions. BUFFER CONTROLLER The MB86960 uses a dedicated buffer memory as shown in for intermediate storage of data packets to be transmitted, and of data packets received from the network. The buffer memory is connected directly to the controller rather than to a separate local microprocessor bus, thus eliminating the need for a local microprocessor. The buffer controller keeps track of buffer memory partitioning, allocation and updating of all receive and transmit pointers automatically, thus eliminating this task from software overhead. As a result of this automation and its high-performance packet buffering, the NICE controller can typically win benchmark performance tests over competing controllers. Access to the buffer memory is managed by NICE’s on-chip buffer controller. As required, it updates internal address pointers for the tasks of transmit, retransmit, receive, rejection of packets with errors and data transfers to and from the host. Thus the host is relieved of buffer management functions, making NICE easy to operate and substantially reducing software requirements. Packets with errors, such as CRC errors, are auto– matically rejected by NICE unless the host asserts the “accept bad packets” bit. When this bit is asserted, any packets received with alignment, CRC or short length errors are passed on to the host processor, and the appropriate error status bits are set to inform the host of the error. Similarly, by setting the “accept short packets” bit, reception of short packets down to 6 bytes in length is allowed. (Normal operation requires an IEEE minimum length packet of 60 bytes, excluding preamble and CRC.)

62 KBYTES

1. Transmit Size (T) = 2 (one bank), 4 (two banks), 8

(two banks), or 16 (two banks) Kbytes.

1. Receive packets are aligned on an eight byte
2. Each received packet is preceded by a four byte

Figure 5. Buffer Memory Organization for systems that require high throughput transmission. space, using the balance of the available memory.

2 KBYTES

60 KBYTES

4 KBYTES

2 KBYTESBANK 1

56 KBYTES

8 KBYTES

48 KBYTES

16 KBYTES

Figure 6. Transmit Buffer

automatically configured as a “ring buffer” by the chip. processes giving higher throughput. Figure 7. Simultaneous Operations and transmission and/or written in for storage by the receiver. appears to be served independently by the controller.

1. Data from the network is stored in the receive buffer.
2. The host retrieves packets from the receive buffer.
3. The host loads packet data into the transmit buffer.
4. The transmitter obtains data for transmission from
5. Any combination of the above can occur

concurrently, including all four at once.

programming the Buffer Size control bits, BS0 and BS1. section on packet transmission. header which provides the length of the packet in bytes. enabled, generate an interrupt. a two-byte header indicating the packet length in bytes. now be loaded with additional packets. Figure 8. Transmit Buffer Detail

receiver will automatically continue reception. considered in system timing considerations. resident in the receive buffer and available to be read. already received to be “overrun” by incoming packets. Figure 9. Receive Buffer Detail

Receive Packet Data Formats Receive packets, less preamble and CRC fields, are stored in the buffer along with a four-byte header. The first byte gives status information, indicating errors, if any, that occurred during reception of the packet. Normally packets with errors are automatically discarded and eliminated from memory by the chip, but with a mode selection, the chip can allow reception of bad packets, with indication of their errors in the status byte of the header. The second byte of the header is reserved for possible future use. The last two bytes of the header give the byte count of the packet, less preamble and CRC. Refer to Figure 9. SYSTEM INTERFACE The system interface block provides the connection between NICE and the host CPU. NICE supports both 8-bit and 16-bit bus widths and byte or word transfers as determined by DLCR6<5>, SB/SW, the “system byte or system word” configuration bit. Depending on the type of host CPU, NICE will supply the data order, MSB or LSB first according to the setting of DCLR7<0> as described in the detailed register descriptions. NICE supports I/O-mapping, memory mapping, and burst or single transfer DMA modes. An interrupt output, INT , is provided which may be programmed by the user to inform the CPU of transmit and receive status conditions requiring host processing. Three sets of user-accessible registers are contained within the MB86960. All registers are accessible as bytes or words. Register Access All control and status registers on the NICE chip are accessible through its bus interface port, which can be I/O or memory mapped in the system. Eight of the registers in the set, whose addresses are xxx0H through xxx7H, are always directly accessible. For the remaining physical addresses, three different banks of registers can be accessed through indirect addressing of the banks (bank switching). The bank switching bits are part of the first eight registers which are permanently resident. The bank-switched register group consists of three sets or “banks” of registers. One of the sets is for Node ID (Ethernet Address) and TDR diagnostics, another is the Hash Table for multicast address filtering, and the third is for buffer memory access. This third bank is normally selected most of the time, except during initialization or diagnostic routines, as access to the other registers is not needed during normal operation. Buffer Access Buffer Memory Port Register 8 (BMPR<8>) of the buffer memory port register set provides serial access to the receive and transmit buffers through on-chip FIFO’s. This port can be accessed with 8-bit or 16-bit wide data. There is a separate FIFO for each direction of data transfer, so there is no complicated direction control needed. Writes to the transmit buffer can be interleaved with reads from the receive buffer if desired. All buffer memory pointers are automatically maintained by the chip, eliminating software overhead normally needed for this. This port can be accessed with I/O instructions using register address xxx8H, or by using DMA. In the latter case, assertion of the DACK input is sufficient to select the port. Thus data can be transferred from host memory to the transmit buffer, or from the receive buffer to host memory using CPU string moves, single-transfer programmed I/O moves, or DMA. The choice should be made according to which is most efficient at a system level, taking into account that a speedy transfer process will result in the best performance. A slow transfer process may not be satisfactory because it might result in poor throughput and performance, and might allow the receive buffer to overflow, losing packets. DMA Operation The MB86960 supports both single cycle and burst DMA operation for transfers of data between the host system and the dedicated buffer memory. The DREQ and DACK signals are used for handshaking between the external DMA and NICE. There is also an “end of process” input pin which, when asserted by the system DMA controller during a transfer cycle, will terminate the DMA activity after the current cycle completes. If enabled for DMA interrupt, upon completion of the DMA activity, the chip will generate an interrupt. Usually only one DMA operation will be run at a time, although the NICE chip could run two interleaving operations, one reading and one writing. There is only one DMA EOP bit, and only one DREQ pin and one DACK pin, so most hosts could not support more than one DMA operation at a time with NICE.

DMA Write (Transmit) Transmit DMA Enable, TX DMA EN, BMPR12<0>, is set high to enable DMA operation for transfers of data packets from the host memory to NICE’s transmit buffer. Burst transfers can also be enabled by invoking the DMA burst control register BMPR13<1:0>. When NICE is ready to begin to accept data from the host, NICE will assert its DMA request output, DREQ. The host responds by asserting DMA Acknowledge, DACK , followed by write enable, WE, and placing the data on the data bus. NICE will assert its RDY(RDY) output when it is ready to complete the current data transfer cycle (polarity of RDY (RDY) and EOP (EOP) inputs are independently programmable). NICE accepts that data byte/word into its bus write FIFO, and later moves it into buffer memory. At the close of a transfer cycle, the host negates WE . In burst mode, NICE will negate DREQ two cycles before the end of the burst. The host DMA will then complete the last two transfer cycles, then negate DACK to close the burst. To start another burst, NICE will re-assert DREQ. The number of DMA write cycles within one burst can be 1, 4, 8, or 12 data transfers (bytes or words) depending on the burst control bits BURST1, BURST0, BMPR13<1:0>. The DMA controller may assert the end-of-process input, EOP (EOP), concurrently with the last data transfer cycle to indicate that the entire transfer process has been completed. This sets the DMA EOP bit in NICE which causes NICE to discontinue making further data requests. If enabled, the EOP (EOP) signal assertion can also generate an interrupt. When the DMA EOP bit, DLCR1<5>, is set, the INT pin will assert if DLCR3<5>, interrupt enable for DMA EOP , is high. This interrupt can be used by the host to initiate the actions for closing the process. Upon servicing the interrupt, if DMA EOP is high, the host should close the DMA process, reset the NICE chip’s DMA logic and clear the interrupt by writing 00H to BMPR12. Note: Clearing TX DMA EN must be done to close the transmit DMA process before attempting another DMA process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will clear automatically, clearing the EOP status and interrupt, so it is not necessary to clear the interrupt separately. After finishing the loading of packets into the buffer, the host initiates packet transmission. This is done by loading the number of packets to be transmitted into the Transmit Packet Count Register, BMPR10<6:0>, and asserting the Transmit Start bit, TX START, of the same register, BMPR10<7>. DMA Read (Receive) NICE will indicate when it has receive packets to be read with status bits and/or interrupts. Before attempting to read a packet, the host processor first reads the RX BUF EMPTY bit, DLCR5<6>. If this bit is 0, there are one or more packets in the receive buffer to read. After reading each packet, the host will check this bit again to see if there are more. Prior to beginning the transfer of a packet from NICE’s receive buffer to host memory via DMA, the host must first read the four-byte receive packet header from the buffer to obtain the packet status and the length of the packet in bytes. Calculating from the packet length the number of DMA cycles needed to read the packet, the host will load that number into the cycle counter of the host DMA controller. The starting address in system memory will also be loaded into the DMA controller. Next, RX DMA EN, BMPR12<1>, is set high to enable DMA read operation to transfer the packet to host memory. When it is ready to begin, NICE asserts its DMA Request output, DREQ. The host responds by asserting DMA Acknowledge, DACK , followed by Read Enable, RD . NICE will assert its RDY output when it has placed the byte/word on the data bus and is ready to complete the data transfer cycle. The system memory will accept the data, then the host negates RD . NICE shifts the data down into its bus read FIFO, then moves its internal bus read pointer to point to the next byte/word in the buffer, moving it into the FIFO. NICE will negate DREQ two cycles before the end of the burst. After the host negates DACK , if NICE can transfer more data, NICE will re-assert DREQ to repeat the process. The number of DMA read cycles in a burst can be 1, 4, 8, or 12 transfer cycles of data (bytes or words), depending on the burst control bits BURST1, BURST0, BMPR13<1:0>. The DMA controller may assert the end-of-process input, EOP (EOP), concurrently with the last byte/word data transfer to indicate that the entire process has completed. NICE will then discontinue making further data requests. RX DMA EN must be cleared when the DMA process is completed, and set again when the host desires to begin reading another packet from the receive buffer using DMA. When EOP (EOP) is asserted by the host DMA controller, the DMA EOP bit, DLCR1<5>, will be set high, and an interrupt will also be generated, provided it is enabled by a high, DLCR3<5>. This interrupt can be used by the host to initiate the final actions to close the DMA process. The interrupt is cleared and the DMA is disabled and reset by writing 00H to the DMA Enable Register, BMPR12. Note: Clearing RX DMA EN must be done to close the

it is not necessary to clear the interrupt separately. Table 1. Internal Register Address Map

16 COLLISIONS

11 X X X X — RESERVED

1. All registers are both word and byte accessible. In word mode, register bytes are paired to form words starting with registers 0 and 1. The
2. In word mode, BMPR8 is a 16-bit port. In byte mode, it is an 8-bit port. The byte ordering Is determined by DLCR7<0>

Table 2. Summary of Control and Status Bits: DLCR0-7, BMPR8-15

0 CNTRL LBC EN TX

0 RX BUF

40 BIT

1 AF1 AF0

16 COL

Table 3. Summary of Control and Status Bits:DLCR8-15, HT8-15, Packet Buffer Headers

Interrupt Enable register. See Table 4. transmitter (by writing 1 to TX START, BMPR10<7>). Table 4. DLCR0 — Transmit Status Register

7 TX DONE R

generate interrupt if enabled by DLCR2<7>. 6 NET BSY R NET BUSY: This is a real-time image of the Carrier Sense signal of the receiver.

5 TX-RX R

packet. This bit is cleared as each transmission begins.

4 CR LOST R

cleared as each transmission begins.

2 COL R

collision counter, DLCR4<7:4>. Can generate interrupt if enabled by DLCR2<2>.

16 COLLISIONS: This bit is set after the sixteenth unsuccessful transmission of the same

packet. Can generate interrupt if enabled by DLCR2<1>.

interrupts if enabled by the corresponding bit in DLCR3. packet is successfully received and stored in the buffer. The bits in this register are cleared by writing 1 to the bit. the interrupt will clear both the bit itself and the interrupt. those that are set. See Table 5. which has just been set and not yet read by the system. Table 5. DLCR1 — Receive Status Register

7 RX PKT R

generate interrupt if enabled by DLCR3<7>.

6 BUS RD

5 DMA

generate interrupt if enabled by DLCR3<5>.

4 RMT

generate interrupt if enabled by DLCR3<4>.

3 SHORT

enabled by DLCR3<3>. See also Table 8.

2 ALIGN

1 CRC

not get set in loopback mode.

Table 6. DLCR2 — Transmit Interrupt Enable Register

7 INT EN R

INTERRUPT ENABLE: When high, enables TX DONE to generate interrupt.

5 INT EN N

2 INT EN R

INTERRUPT ENABLE: When high, enables COL to generate interrupt.

1 INT EN R

INTERRUPT ENABLE: When high, enables 16 COL to generate interrupt.

Receive Interrupt Enable Register This register provides control for enabling or masking interrupts based on the assertion of status bits in DCLR1, the Receive Status Register. See Table 7. Transmit Mode Register This register contains two control bits associated with transmission, a general-purpose control bit which drives a pin on the chip, and a collision counter. See Table 9. Table 7. DLCR3 — Receive Interrupt Enable Register INTERRUPT ENABLE: When high, enables RX PKT to generate interrupt.

6 INT EN R

INTERRUPT ENABLE: When high, enables BUS RD ERR to generate interrupt.

5 INT EN R

INTERRUPT ENABLE: When high, enables DMA EOP to generate interrupt.

4 INT EN R

INTERRUPT ENABLE: When high, enables RMT 0900H to generate interrupt.

3 INT EN R

INTERRUPT ENABLE: When high, enables SHORT ERR to generate interrupt. See also DLCR1<3> and Table 8. INTERRUPT ENABLE: When high, enables ALIGN ERR to generate interrupt. See also DLCR1<2> and Table 8. INTERRUPT ENABLE: When high, enables CRC ERR to generate interrupt. See also DLCR1<1> and Table 8.

0 INT EN R

INTERRUPT ENABLE: When high, enables RBUF OVRFLO to generate interrupt. Table 8. Network Error Monitoring Modes

Description

0 0 0 0 0 Normal non-monitor mode. 0 0 1/0 1/0 1/0 Error interrupts only, if enabled. 0 1 0 1/0 1/0 Save short packets if otherwise error free in buffer; interrupts only for alignment and CRC errors, if enabled. RX PKT will be set high if short packet received. 1 0 0 0 0 Save packets with short, alignment and/or CRC errors in buffer; RX PKT will be set high if packet with error received. All others Do Not Use. Note: Packet acceptance requires both error filter acceptance and address filter acceptance.

Table 9. DLCR4 — Transmit Mode Register

7 COL

encountered by the current transmit packet. (Read only). See Table 10.

6 COL

encountered by the current transmit packet. (Read only). See Table 10.

5 COL

encountered by the current transmit packet. (Read only). See Table 10.

4 COL

2 CNTRL R

CONTROL OUTPUT: The inverse of this is bit is output for general use on pin 95.

1 LBC R

encoder/decoder. A 0 in this bit places the chip in internal loopback mode.

0 EN TX

high, the transmitter will not defer to traffic on the network. Table 10. Collision Count function, and one receive buffer status bit. See Table 11. then exits to do other tasks.

Table 11. DLCR5 — Receive Mode Register

6 RX BUF

any complete packets to read. (Read only).

5 ACPT

automatically by the receiver and removed from the buffer. See also Table 8.

40 BIT ADDRESS: When set high, instead of the customary 48-bit NODE ID address filter,

only the first 40 bits of the NODE ID are compared (NODE ID 0–4).

3 ACPT

1 AF1 R

incoming packets. See table below under AF0.

0 AF0 R

self-received, except in “Reject all packets” mode.

Table 12. DLCR6 — Configuration Register 0

7 DLC EN R

5 SB/SW R

mode; when low, 16-bit data mode is selected. See also BB/BW below.

4 BB/BW R

Table 13. DLCR7 — Configuration Register 1 00 Normal NICE: Internal encoder/decoder active. 01 NICE + Monitor: Internal encoder/decoder active.

10 Encoder/Decoder Bypass: Internal encoder/

interface controller to external encoder/decoder.

11 Encoder/Decoder Test: Controller inactive,

5 PWRDN R

places chip in power down mode for power conservation.

4 RDYPOL R

READY PIN POLARITY: Reads the state of the RDY POL pin 94. sets of registers to access when the physical register address is xxx8H–xxxFH.

1 EOPPOL R

byte of the system bus. Note that header bytes are also swapped.

Note to software engineers regarding NICE/Ether- Star compatibility: If you desire to use the same node driver for Fujitsu’s NICE and EtherStar controllers, the driver can determine which chip is being used by reading DLCR7 and/or DLCR6 after hardware reset. NICE will read 30B6H or 20BGH (30 or 20 for DLCR7 and B6 for DLCR6); EtherStar will read 0000H. Power-down mode saves power when the device is not in use. When ready to place the NICE chip in Power Down Mode, first write 1 to DLCR6<7>, DLC EN , to turn the receiver and transmitter off, then write 0 to DLCR7<5>, PWRDN . To exit the power-down mode, write 1 to PWRDN. Register contents will be preserved, unless a hardware reset is issued. Hardware reset will also terminate the power-down mode. Byte order control provided by the Most..Least/ Least..Most bit, DLCR7<0>, provides compatibility with various higher-level protocols, such as TCP/IP and XNS. These protocols may have different transmission the least significant byte of the word is transmitted first, high, the byte order is reversed. This feature applies only when the system bus is operated in 16-bit (word) mode. The byte order control works by reversing or not reversing the bytes of all words as they pass between the buffer memory and the system bus. Thus all data stored in the transmit buffer or retrieved from the receive buffer is affected, including the nontransmitted headers. The NICE registers, other than the Buffer Memory Port, BMPR8:9, are not affected by this control bit. Care must be taken in the software driver code to reverse the header information as well as the packet data when using this feature. Examples follow. Example of using Least..Most Byte Ordering: System Bus Transmit Packet: High Byte Low Byte TX Length, high byte TX Length, low byte Destination Addr, 2nd byte Destination Addr, 1st byte… Source Addr, 2nd byte Source Addr, 1st byte… Length Field, low byte* Length Field, high byte* Data Field, 2nd byte Data Field, 1st byte… Receive Packet: High Byte Low Byte Unused; reserved Receive Packet Status RX Length, high byte RX Length, low byte Destination Addr, 2nd byte Destination Addr, 1st byte … Source Addr, 2nd byte Source Addr, 1st byte… Length Field, low byte* Length Field, high byte* Data Field, 2nd byte Data Field, 1st byte… Example of using Most..Least Byte Ordering: System Bus Transmit Packet: High Byte Low Byte TX Length, low byte * TX Length, high byte* Destination Addr, 1st byte Destination Addr, 2nd byte… Source Addr, 1st byte Source Addr, 2nd byte… Length Field, high byte Length Field, low byte Data Field, 1st byte Data Field, 2nd byte… Receive Packet: High Byte Low Byte Receive Packet Status Unused; reserved RX Length, low byte * RX Length, high byte* Destination Addr, 1st byte Destination Addr, 2nd byte… Source Addr, 1st byte Source Addr, 2nd byte… Length Field, high byte Length Field, low byte Data Field, 1st byte Data Field, 2nd byte… Note: Asterisk indicates numerically reversed byte ordering.

The Node ID Registers are accessed in register bank “0” at register addresses xxx8H–xxxDH. During initialization of the node, the unique Ethernet address assigned to the node is loaded into these registers. The first register at xxx8H corresponds to the first byte of the Node ID, which corresponds to the first address byte to be received as a packet arrives from the network. If the chip is configured to do so in its Address Filter mode bits, DLCR5<1:0>, the destination address field of an incoming packet will be compared to the Node ID stored in these registers. If there is a match, provided the packet passes the error filter, it will be accepted. These registers are readable as well as writable, but they should not be accessed while the receiver is enabled. To avoid interaction with the receiver, access these registers only when DLC EN is 1. It is recommended that they be written and read only during initialization before enabling the receiver, i.e. before writing 0 to DLC EN DLCR6<7>. The address contained in these registers is used only for receive (destination) address filtering, not for the source address of outgoing packets. Outgoing packet addresses must be provided by the system as part of the packet data. Within each byte, the bits are transmitted and received on the network least-significant bit first. See Table 3 for the transmission bit order, which follows the bit numbering in this table. Time Domain Reflectometry (TDR) Counter The TDR Counter can be used to get a rough indication of the location of a fault on the network, if one exists. When a node transmits, a short or open on the network would cause a reflected signal to the node’s receiver which can sometimes be detected. The reflection will cause the carrier sense to fail and/or a false collision to be detected. This affect, time domain reflectometry, can be used to estimate the distance along the network cable from the node to the fault. The TDR Counter counts the number of bits transmitted before either a collision occurs, or carrier sense is lost, whichever comes first. If neither occur during transmission of the packet, the count is cleared. The amount of elapsed time this represents is two (2) times the signal delay from the node to the fault. An open on the network will usually cause a false collision, whereas a short is more likely to cause loss of carrier sense. The TDR Count comes from DLCR14 and 15. DLCR14 is the least-significant byte, DLCR15 the most-signifi- cant. Only the lower 14 bits of the counter are equipped, which is more than is needed for an IEEE or Ethernet LAN. (The top two bits, DLCR15<7:6>, are always 0.) To perform the TDR test for a fault, first enable interrupts for transmitter done (TX DONE). This is done by setting DLCR2<7> high. (An alternative to using the interrupt would be polling the TX DONE bit looking for a high level.) Set the 16 Collisions Register, BMPR11, to 07H for this test (no halt, skip failed packet). Clear all status bits by writing FF86H to the Receive and Transmit Status Registers. Next, transmit, or attempt to transmit, a packet of 600 bits or more in length. Up to 16 attempts may be made automatically if collisions are being indicated. Upon completion of the transmission attempt(s) TX DONE will go high, generating an interrupt if enabled. When this occurs, read the Transmit Status Register and the TDR Register. Interpreting the results: If the count is zero, no fault was detected. If the count is greater than zero but smaller than the packet length, it may indicate a cable fault. If the count is less than 525, there may have been a real collision occurring during the test. Real collisions normally occur within the first 65 bytes of the packet, including preamble. Take note of the error messages, COL and CR LOST. COL high suggests a cable open, whereas CR LOST suggests a short. It is best to repeat the measurement several times, then throw out the anomalous values, if any, and average the rest. A cluster of readings at about the same value is a strong indicator of a valid fault measurement. If such a cluster of readings occurs, multiply the average of the cluster by 39 feet to estimate the distance from the node to the fault. (39 ft. = (100 ns x .8 x 186,282 mi/s x 5280 ft/mi)/2 ... this assumes the network is mostly coaxial cable with signal propagation speed of approximately .8 x C, the speed of light.)

The Hash Table provides a means for filtering incoming multicast packets so that the host processor does not have to process ones that are not of interest. The principle employed in this filtering scheme was originally developed by computer science to arrange a large number of elements of an array or database in such a way that facilitates searching for elements associated with a given key or datum. The ‘hash function’ is a mathematical or logical function which maps all possible elements in a domain onto a smaller domain called the ‘hash table’. As an example, suppose the following hashing function is used: “Treating the multicast address as a non-negative 48-bit integer, divide this number by 64 and take the remainder.” This function will map all multicast addresses into a 64-element hash table since the remainder can be only the integer values 0 through 63. Applying this hashing function results in taking the least-significant 6 bits of the multicast address as an integer. In the hash table, for each element, 0 through 63, a single bit is stored which indicates whether the address is to be accepted (1) or rejected (0). If, for example, the node belongs to three multicast groups, only three or fewer of the hash table elements will store 1’s, the rest 0’s. The scheme allows the acceptance of any number of the addresses, including all of them. The limitation is that there may be addresses not of interest used on the network which also fall into the ‘accept’ elements, so in this case the filtering is imperfect. But in any case, most of the nonapplying addresses can be filtered out in this way. The actual hashing function used in the NICE chip is this: “Calculate the CRC on the multicast address and take the high-order 6 bits of this calculation”. The six bits are used to address the elements of the hash table. If a 1 is stored in an element of the table, associated packets are accepted. The hash filter criterium is only used on multicast addresses, which all start with a 1. Node ID’s, which start with a 0, are not filtered by the hash filter. The broadcast address, a special case of the multicast set wherein all the bits are 1’s, will be accepted anyway unless the “Reject all packets” mode is selected. Figure 12 shows the register core, a modified shift-right register, used in generating and checking CRC’s. Whereas some controllers share a single such core between transmitter and receiver, NICE has two of these, one for the generator and one for the checker, allowing both to operate concurrently for self-receive. To begin the calculation, the register is first set to all 1’s. For the generator case, as the packet is transmitted, the data is clocked serially into the left-hand end of the register starting with the 48 bits of the destination address (the preamble is skipped). After the last bit of the ‘data’ field is clocked into the register, the CRC calculation is finished. The feedback line is then forced low and the register becomes a simple shift-right register. Its contents are then shifted out serially and transmitted, appending the CRC to the end of the packet. For the CRC checker, the calculation starts out the same way as for CRC generation feeding the incoming data into the register. But in this case, the CRC field of the packet is also fed into the calculation. The result is a fixed constant in the register if no CRC error has occurred. For the Hash Filter, after the last bit of the destination address has been clocked into the register, the left-hand six register bits are stored in another register used to address the Hash Table elements. The left-most bit is most significant. The left-most three bits are used as the Hash Table register address and the right-most three as the bit address within a register byte. Having selected a Hash Table element in this way, a 1 in the table will indicate the packet is to be accepted, provided it is a multicast packet (first bit of destination address must be 1), and passes the error filters. The hash filter is only employed when the address filter mode select bits, AF1, AF0 are 0, 1, selecting the “NODE ID, Broadcast, Multicast + Hash Table” mode. Like the NODE ID registers, the Hash Table registers should only be accessed when the receiver is disabled, i.e. when DLC EN is high, to avoid interaction with the receiver. There are eight bytes of registers in the Hash Table containing the 64 1-bit elements (refer to Table 1 for location). Source code software examples showing how to calculate entries for the Hash Table are available from Fujitsu Microelectronics, Semiconductor Division, in C and assembly language.

Figure 10. CRC Register Core

packet. Bits 0, 6 and 7 are unused and are always 0. Table 1 for location of these registers. Table 14. BMPR10 — Transmit Start Register

7 TX START W

packets remain to be transmitted.

16 Collisions Control Register

clear either Receive Read DMA or Transmit Write DMA. Refer to Table 14 for the codes. operation. The burst length can be 1, 4, 8 or 12 transfers. Table 15. 16 Collision Action Codes (written to BMPR11) 02H or 03H MODE SETUP: Halt after 16 Collisions. 02H COMMAND: Resume transmitting, repeat failed packet (for use following a halt). Terminates the halt. allowing up to 16 additional attempts to be made. Halt after 16 collisions. 03H COMMAND: Resume transmitting, skip failed packet (for use following a halt). Terminates the halt. transmitter will deactivate, setting TX DONE as it does so. Halt after 16 collisions. indefinitely. Interrupt or periodic polling of the status bits should be used to detect this condition. is rare on a healthy network, but it does happen. To avoid this, use mode 06H. Table 16. DMA Enable Register (BMPR12) response to End of Process (DMA EOP) interrupt.

Skip Packet Register (BMPR14) Only one bit in this register is active, bit 2, the rest are 0. Writing 04H to this register commands the buffer controller to skip the balance of the current receive packet in memory. The bit can then be read to see when the skip process is complete (within 300 ns). The bit returns to 0 when the chip is ready to read the next packet, if there is another packet, or stop reading if there is not. Limitation of use: Do not use this feature before reading at least four (4) times from the beginning of the packet, nor if there are only eight (8) or fewer bytes left of the packet in the buffer. Doing so may corrupt the receive buffer pointers. BMPR15 is unused and reserved for possible future use. Write only 0’s to this register. TRANSMITTER CIRCUITS Circuits within the transmitter include a transmitter state machine, a small FIFO for pipe-lining the packet data, preamble generator, CRC generator, parallel to serial converter, backoff generator, inter-packet gap timer and a time domain reflectometer (TDR) counter. The transmitter state machine provides sequencing of events for the transmitter, including idle, preamble, data, CRC, inter-packet gap, jam and backoff. It detects various transmit error conditions and sets appropriate bits within the DLCR registers. The pipeline FIFO provides elastic buffering that the buffer controller can load with data to be transmitted. NICE’s CRC generator calculates the Ethernet 32-bit CRC on the destination and source address, the length field and the data field as specified by the ISO/ANSI/ IEEE 8802-3 specification for Ethernet. This value is appended to the end of the packet. Transmit Error Processing NICE has four transmit error status bits in its Transmit Status Register (DLCR0) for reporting the three possible transmit errors. The errors are: 1) loss of carrier during transmission, which usually indicates a medium fault or a collision, 2) collision, and 3) 16 consecutive collisions. The latter two can be enabled separately to generate interrupts. If NICE detects a collision during transmission, it will automatically try to retransmit the packet until sixteen at- tempts have been made. Collision counter DLCR4<7:4>, automatically increments after each collision up to the sixteenth collision, at which time it rolls over to zero. (Bit 7 is the most-significant of the four bits.) Appropriate status bits in the Transmit Status Register and Transmit Mode Register are set in case of a collision-terminating transmission. Another status bit (16 COL) indicates that sixteen consecutive attempts to transmit a packet have been made and all have been terminated by collision. This case may indicate a network problem. For example, a disconnected cable or terminator will produce false collisions. But 16 collisions can occur normally, although rarely. A pseudo-random number generator provides the collision backoff function. This is clocked at the bit rate,

10 MHz, so that distances between stations become part

of the randomizing function. It is sampled at the time of collision, masking all but the appropriate number of bits specified by the 8802–3 backoff algorithm. This value is then counted down at the slot-time rate (512 bits) to generate the backoff interval. For a first collision, only one bit is used, giving a backoff of either 51.2 microseconds or 0. For a second consecutive collision, two bits are used, and so forth, up to ten bits. From the tenth to the 16th collision, 10 bits are used. This gives a pseudo-random backoff interval of from 0 to 52.38 ms, the so-called ‘binary exponential backoff’ for collisions per 8802-3. Time Domain Reflectometry The TDR function provided counts the actual number of bits transmitted for each packet before an indication of either collision or carrier loss occurs, or the transmission completes. If a transmission completes without error indications, the TDR counter is cleared. See also the register description for DLCR14 and DLCR15. Media Access Control NICE’s transmitter state machine implements the media access protocol for 8802-3 networks called CSMA/CD, Carrier Sense, Multiple Access with Collision Detection. The ‘carrier sense’ part means that the controller monitors the network for carrier from other nodes, and defers transmission while other nodes are transmitting (collision avoidance). But collisions can still occur when two nodes, perhaps separated on the network by several microseconds, start to transmit at nearly the same time. This is handled by the ‘collision detection’ part. All nodes are required to monitor the network for collisions and, when involved in one, transmit a 32-bit ‘Jam’ to reinforce the collision, then terminate transmission. Later, after waiting a pseudo-random backoff interval, the node automatically re-attempts to transmit the packet. Between packets, there must be a gap of at least 9.6 microseconds during which time the trunk cabling is idle. NICE’s transmitter state machine measures this interval starting from the end of a packet on the network. It will not transmit until this interval has expired. During the

block diagram of the encoder/decoder section. system turns the transmitter on to initiate transmission. Figures 11 and 12 for suggested cable interfacing. the TX START bit and the packet count to TX PKT CNT. Note:Transformers are 1:1 and 27 H minimum. Figure 11. Transceiver Interface Termination

other buffer memory access requests. Figure 14. Encoder/Decoder Block Diagram

Error, traffic and performance statistics can be collected continuously or on a sampled basis. The Receive Status Register and Transmit Status Register indicate any errors detected. Such data can be collected in two ways. Either interrupts can be used after each packet, and the status read from the status register by the interrupt service routine, or, for the receive case, the packets can be accepted for storage in the receive buffer, allowing their contents and error statuses (stored in the header) to be read later in batch mode. To get maximum statistics for the network, the “Accept all packets” mode can be used. In this mode, all packets can be counted, including their lengths. But of course, this use will maximize host overhead, so it should be used sparingly in user terminal equipment. Carrier detection can be sampled as a means of estimating network bandwidth utilization. This bit is available in the Transmit Status Register (NET BSY). An estimate of the average media-access waiting time can be calculated from the elapsed time between starting the Transmitter and TX DONE going high. The transmit collision count (DLCR4<7:4>) can be used to determine the number of collisions encountered by the last outgoing packet. (The counter is reset at the start of transmitting each new packet.)

ELECTRICAL CHARACTERISTICS

Table 17. ABSOLUTE MAXIMUM RATINGS

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

1. Not more than one output may be shorted to ground or VCC at a time for a maximum duration of one second.

Table 18. RECOMMENDED OPERATING CONDITIONS

Table 19. DC SPECIFICATIONS (At recommended operating conditions unless otherwise noted.) Table 20. GENERAL CAPACITANCE (TA = 25°C, VDD = VI = 0 V, f = 1 MHz)

Figure 16. Read Cycle Table 21. Read Cycle

1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the read cycle begins. For port access only, 175 ns

are active in “loopback” reception. 2.15 µs max for bus read error.

1. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system read cycles at

less than 100 ns intervals, and both the transmitter and receiver are active in “loopback” reception. 2.15 µs max for bus read error.

Figure 17. Write Cycle Table 22. Write Cycle

1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the write cycle begins. For port access only, 175 ns

are active in “loopback” reception.

1. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system write cycles at

less than 100 ns intervals, and both the transmitter and receiver are active in “loopback” reception.

Figure 18. Single-Cycle DMA Timing Table 23. Single-Cycle DMA Timing

1. An asserted EOP terminates any further DREQ after DACK returns high.
2. The DMA cycle uses DACK as the chip select. DACK overrides CS and SA3-0 if they are both asserted at the same time, forcing

selection of the Buffer Memory Port as in a DMA cycle.

1. For RDY(RDY) timing and SD15-0 timing, see Figure 16, t4-t11, and Figure 17, t4-t9.

Figure 19. Burst DMA Timing Table 24. Burst DMA Timing

1. DREQ goes low during the next-to-last transfer of the burst. DACK should not go high until after the RD or WE pulse of the last transfer
2. The DMA cycle uses DACK as the chip select. DACK overrides CS and SA3-0 if they are both asserted at the same time, forcing

selection of the Buffer Memory Port as in a DMA cycle.

1. For RDY(RDY) timing and SD15-0 timing, see Figure 16, t4-t11, and Figure 17, t4-t9.

Figure 20. Burst DMA Interrupted by DACK Notes: Burst can be interrupted by DACK high-going pulse during the burst. Burst will resume when DACK returns low.

Figure 21. Burst DMA Terminated by EOP Table 25. Burst DMA Terminated by EOP Note: EOP can be asserted during any transfer of the burst to terminate the process following that transfer.

Figure 24. LBC, CNTRL, AND INT Timing Table 28. LBC CNTRL and INT Timing

Figure 25. SRAM Read Timing Table 29. SRAM Read Timing Note: Use SRAM with address access time of 80 ns or less.

Figure 26. SRAM Write Timing Table 30. SRAM Write Timing Note: Use SRAM with address access time of 80 ns or less.

Figure 30. Transmit Timing Table 31. Transmit Timing: Figures 27–30 (for Encoder/Decoder Bypass mode)

1. The 32 jam bits include eight data bits and 24 ‘0’ bits.

Figure 31. Transmit Start Timing

Figure 32. Transmit End Timing Table 32. Transmit Start and End Timing: Figures 31–32 (for Encoder/Decoder Test mode)

Figure 33. Loopback Timing Table 33. Loopback Timing (for Encoder/Decoder bypass mode)

Figure 34. Collision Timing Table 34. Collision Timing (for Encoder/Decoder Test mode)

Figure 35. Receive Timing Table 35. Receive Timing (for Encoder/Decoder Bypass mode)

Figure 36. Receive Start Timing

Figure 37. Receive End Timing Table 36. Receive Timing: Figures 36–37 (for Encoder/Decoder Test mode)

Figure 38. Test Conditions

100-Pin Plastic Flat Package 100-Lead Plastic Flat Package (Case No. FPT-100P-M06)