MB86604

MB86604L FUJITSU | Alldatasheet

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DS04-22415-1EFUJITSU SEMICONDUCTOR DATA SHEET ASSP Communication Control CMOS SCSI-II Protocol Controller (with single-ended driver/receiver) MB86604L n DESCRIPTION The Fujitsu MB86604L is a single-ended transmission type SCSI-II Protocol Controller (SPC) with a single-ended driver/receiver. The MB86604L facilitates interface control between small/medium host computer and peripheral devices (such as a hard disk and printer). The specifications conform to the SCSI-II Standard. The MB86604L supports high-speed synchronous transfer, the MPU/DMA independent system data bus, and user programmable command set to enable configuration of high-performance systems. It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU. The MB86604L incorporate with a single-ended type SCSI driver/receiver which can drive 48 mA of large-current, and so, the device can be directly connected with the SCSI bus. The device can operate with +5 V single-power supply and in up to 40 MHz clock frequency. As for package, a 100-pin plastic small quad flat package is available. n FEATURES SCSI Bus Interface:

Conforming to the SCSI-II standard
Operatable as Initiator and target (Continued) n PACKAGE 100 pin, Plastic LQFP (FPT-100P-M05)

(Continued)

T wo types of high-speed data transfer: – Synchronous data transfer (Max. 10 Mbytes/s, max. 32 offsets, 32-step transfer rate) – Asynchronous data transfer (Max. 5 Mbyte/s)
T ransfer parameters (transfer mode, transfer rate, transfer offset) can be set for up to 7 connected devices.
Single-ended transmission type (Maximum cable length: 6 m): – On-chip single-ended driver/receiver which can drive 48 mA of "L" level output current – Directly connectable with the SCSI bus
On-chip three-state bidirectional I/O buffers for SCSI REQ and ACK pins (DB7-DB0, DBP, A TN, MSG, C/D, I/ O pins can be selected from either three-state or open-drain buffer by controlling the TEST pins input.) Transfer Operation:
Automatic response to selection/reselection (Preset receiving operation can perform at the selection/ reselection.): – Initiator: Automatically operates until message received without command issue. – T arget: Automatically operates until command received without command issue.
Automatic receiving: – Initiator: Automatically receives information for new phase to which target transited without command issue. – T arget: Automatically receives message from initiator when initiator generates attention condition.
On-chip 32-byte data register (FIFO) for data phase
On-chip two (send-only and receive-only) 32-byte data buffers for message, command, and status phases
On-chip 16-bit transfer block register and 24-bit transfer byte register enabling 1 Tbytes transfer (1 Tbytes: 16 Mbytes · 64 k blocks)
On-chip independent data transfer bus enabling the MPU operation during the data transfer
Parity through/generate can be specified. System Bus Interface:
8-bit or 16-bit separate MPU and DMA buses
Directly connectable with a 80 series or 68 series MPU
T wo types of transfer operation: – Program transfer – DMA transfer (Burst/Handshake) Command Set:
Supports sequential commands and programmable commands in addition to ordinary commands
Command queuing (Command can be continuously issued by putting tags to commands in command phase.)
On-chip 256-byte memory for command programming memory and command queuing buffer Others
Process: CMOS process
Supply Voltage: Single +5 V
Input System Clock: 20 MHz/30 MHz/40 MHz
Package: 100-pin plastic LQFP

V SS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 LDP CS 1 V SS V DD CS 0 WR RD V DD V SS CLK RESET INT MODE DBP V SS DB 7 DB 6 DB 5 V DD V SS V SS DB 4 DB 3 DB 2 DB 1 V SS DB 0 TEST 1 TMOUT ATN V SS BSY ACK RST V SS V SS V DD MSG SEL C/D REQ V SS I/O TEST2 TP V SS V DD DREQ DACK (FPT-100P-M05) I OWR I ORD V DD V SS DMA 0 LDMDP DMD 0 DMD 1 DMD 2 DMD 3 DMD 4 DMD 5 DMD 6 DMD 7 V SS DMD 8 DMD 9 DMD 10 DMD 11 DMD 12 DMD 13 DMD 14 DMD 15 UDMDP DMBHE (OPEN) (OPEN) (TOP VIEW)

SCSI Interface * : Regarding the status of information transfer which is indicated by MSG, C/D, and I/O pins, See T able Phase Status. Pin number Symbol Pin name I/O Function

60 REQ Request I/O T ransfer request signal in the information transfer phases from

target to initiator. The input signal to this pin is used for the timing control of data transfer sequence. This is a three-state I/O pin and an active low pin.

68 ACK Acknowledge I/O This pin is for the acknowledge signal from initiator to target for

the REQ signal in the information transfer phases. The input signal to this pin is used for the timing control of data transfer sequence. This is a three-state I/O pin and an active low pin.

71 A TN

Attention I/O This pin is for the attention signal that initiator requests target for the message transfer phase. This is an active-low pin.

63 MSG * Message I/O This pin is for the message signal that specifies type of

information transferred on the data bus. This is an active-low pin and becomes “L” when message phase is specified.

61 C/D * Control/data I/O This pin is for the control/data signal that specifies type of

information transferred on the data bus. This an active-low pin and becomes “L” level when command, status, or message phase is specified.

58 I/O

Input/output I/O This pin is for the input/output signal that specifies direction of information transferred on the data bus. This is an active-low pin. When this pin is “L” level, the information is transferred from target to initiator. When this pin is “H” level, the information is transferred from initiator to target.

69 BSY

Busy I/O This pin is for the SCSI bus busy signal. In the arbitration phase, this is for the request signal for the use of bus acquisition. This is an active-low pin.

62 SEL Select I/O This pin is for the select signal used by initiator to select target

during the selection phase and by target to reselect initiator during the reselection phase. This is an active-low pin. 67 RST Reset I/O This pin is for the reset signal used by any device on the bus. When the device is an input operation, the reset signal is input to this pin. When output operation, the reset signal is output from this pin. This is an active-low pin. 11, 12, 13, 17, 18, 19, 20, 22 DB7 to DB0 Data bus 7 to data bus 0 I/O These pins are for the bidirectional 8-bit SCSI data bus and 1-bit odd parity line. 9D B P Data bus parity

Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus. 2. MPU Interface (Continued) Phase name MSG C/D I/O Transfer direction Initiator Target Data-out phase H H H ﬁ Data-in phase H H L ‹ Command phase H L H ﬁ Status phase H L L ‹ Message-out phase L L H ﬁ Message-in phase L L L ‹ Pin number Symbol* Pin name I/O Function

77 CS0 Chip select 0 I This is a chip select 0 pin used by MPU to select the SPC as an

I/O device. This is an active-low pin.

80 CS1 Chip select 1 I This is a chip select 1 pin to select when MPU inputs/outputs the

data on DMA bus through SPC. This is an active-low pin. 98, 97, 96, 95, 94, 93, 92, 91 D15 to Data 15 to data 8 I/O These pins are for the upper byte and parity bit of MPU data bus. When the CS0 input is valid, these pins serve as I/O ports for the SPC internal registers. When the CS1 input is valid, these pins serve as I/O ports for the DMA bus data.99 UDP Upper data parity 89, 88, 87, 86, 85, 84, 83, 82 to Data 7 to data 0 I/O These pins are for the lower byte and parity bit of the MPU data bus. When the CS0 input is valid, these pins serve as I/O ports for the SPC internal registers. When the CS1 input is valid, these pins serve as I/O ports for the DMA bus data.81 LDP Lower data parity 76, 75, 74, 73, 72 to Address 4 to address 0 I These are address input pins to select the SPC internal registers. 2R D (R/W) Read (read/write) I In the 80-series mode, this is a read signal input pin (IORD or RD ) that MPU reads the SPC. This read signal pin is an active- low. In the 68-series mode, this pin functions as the control signal input (R/W) to control the read/write operation to the SPC. In the read operation, this pin is an active-high. In the write operation, this pin is an active-low. 1W R (LDS) Write (lower data strobe) I In the 80-series mode, this pin is a write signal input pin (IOWR or WR) that MPU writes to the SPC. This write signal input pin is active-low. In the 68-series mode, this pin function as the lower data strobe signal input (LDS) that MPU outputs when the lower byte of data bus is valid. The LDS pin is an active-low.

(Continued) * : The pin symbols in parenthesis are the ones when the MODE input is “L”. 3. DMA Interface (Continued) Pin number Symbol* Pin name I/O Function

100 BHE

(UDS ) Bus high enable (strobe) I In the 80-series mode, this pin is used for input of the bus high enable signal (BHE ) output from the MPU when the upper byte of the data bus is valid. The BHE pin is an active-low. In the 68- series mode, this pin functions as the upper data strobe signal input pin (UDS ) output from the MPU when the upper byte of the data bus is valid. The UDS pin is also an active-low. 7I N T (INT) Interrupt request O The INT and INT pins are the interrupt request signal output. The INT pins is used for the 80-series mode (an active-high pin), and the INT signal is used for the 68-series mode (an active-low pin).

8 MODE Mode I This input pin is used to select the type of the MPU and DMA

buses. In the 80-series mode, a high level is input. In the 68- series mode, a low level is input. Pin number Symbol* Pin name I/O Function

52 DREQ DMA request O This is an output pin of DMA transfer request signal to the DMA

controller. The data transfer between the SPC and memory via the DMA bus is requested. This pin is an active-high.

51 DACK DMA

I This is a DMA acknowledge signal input pin output from the DMA controller that enables the DMA transfer. This pin is an active-low. When this pin is an active state, the DMA cycle (read/ write) is valid. 48, 47, 46, 45, 44, 43, 42, 41 DMD15 to DMD8 DMA data 15 to DMA data 8 I/O These pins are the input/output pins of the upper byte and parity bit of the DMA data bus. When the signal input to the CS1 pin (pin 80) is valid, these pins are connected directly to the MPU data bus.49 UDMDP Upper DMA data parity 39, 38, 37, 36, 35, 34, 33, 32 DMD7 to DMD0 DMA data 7 to DMA data 0 I/O These pins are the input/output pins of the lower byte and parity bit of the DMA data bus. When the CS1 (pin 80) input is valid, these pins are connected directly to the MPU data bus.

31 LDMDP Lower DMA

27 IORD

(DMR/W ) I/O read (DMA read/ write) I In the 80-series mode, this pin (IORD or RD) is used for the input pin to output the data from the SPC to the DMA bus. This is an active-low pin. In the 68-series mode, this pin functions as a control signal input pin (DMR/W ) to input/output the data to the SPC by the DMA controller. In the output operation, this pin is on the high-state (active-high state). In the input operation, this pin is on the low-state (active-low state).

26 IOWR

(DMLDS ) I/O write (DMA lower data strobe) I In the 80-series mode, this (IOWR or WR) is used for the input pin to input the DMA bus data to the SPC. In the 68-series mode, this pin functions as a DMA lower data strobe input (DMLDS) that DMA controller outputs when the lower byte of the DMA bus data is valid. Both IOWR and DMLDS pins are an active-low.

(Continued) * : The pin symbols in parenthesis are the ones when the MODE input is “L”. 4. Others * : The pin symbols in parenthesis are the symbols when the MODE input is “L”. Pin number Symbol* Pin name I/O Function

50 DMBHE

(DMUDS ) DMA bus high enable (DMA upper data strobe) I In the 80-series mode, this pin is for the DMA bus high enable signal input pin (DMBHE ) output from the DMA controller when the upper byte of the DMA data bus is valid. This is an active-low pin. In the 68-series mode, this pin functions as the DMA upper data strobe signal input pin (DMUDS) output from the DMA controller when the upper byte of data bus is valid. The DMUDS pin is also an active-low.

30 DMA0 DMA

I In the 80-series mode, this pin is used for the DMA address 0 input pin output from the DMA controller. In the 68-series mode, a high level should be input to this pin.

55 TP T ransfer

I This is a DMA transfer permission signal input pin. When this pin is in active-state, the SPC does the DMA transfer. In case that this pin becomes inactive during the DMA transfer, the DMA transfer is paused on the block boundary. This pin is an active high. Pin number Symbol* Pin name I/O Function

6 RESET

Reset I System reset input pin. The input reset active pulse width must have 4 times of the clock cycle at least. This is an active-low pin. 5 CLK Clock I Clock signal input pin. 20 MHz, 30 MHz, or 40 MHz can be applied as the input clock frequency. 3, 14, 28 53, 64, 78 VDD Power supply — +5 V power supply pins. 4, 10, 15 16, 21, 29 40, 54, 59 65, 66, 70 79, 90 V SS Ground — Ground pins.

23 TEST1 TEST I This pin is used to select the type of I/O buffer on SCSI data bus

pins. In case that DBP, DB7 – DB0 pins are used as an open- drain I/O, connect this pin to VSS . In case of three-state I/O, connect to VDD . 57 TEST2 TEST I This pin is used to select the type of I/O buffer on SCSI pins. In case that MSG, C/D, I/O, and A TN pins are used as an open- drain I/O, connect this pin to VSS . In case of three-state I/O, connect to VDD .

24 TMOUT TIMEOUT O This is a SCSI Timeout pin that indicates the SPC has been

busy longer than the specified time. A high level is output on this pin if the SPC busy time exceeds the specified time. This pin can be used for the timeout counter. 25, 26 (OPEN) (Open) — These are open pins. Those pins are not connected with the device internally. Those pins must be left open.

TMOUT INT WR RD CS0 CS1 A4 to A0 BHE MODE D15 to D8, UDP D7 to D0, LDP MPU interface Internal processor Timer Registers Phase controller Transfer controller SCSI interface Data register (32 bytes) Command user program memory (256 bytes) Send MCS buffer (32 bytes) Receive MCS buffer (32 bytes) DMA interface

International Processor (Sequencer) Performs sequence control between the SCSI bus phases. 2. Timer Manages the SCSI time standards. Also, conducts the following time managements.

Time until the REQ or ACK signal is asserted for asychronous transfer data
Time until selection or reselection is retried
R E Q and ACK timeout time during transfers: Asychronous transfer case T arget: After the REQ is asserted, the time until the initiator asserts the ACK Initiator: After the ACK is asserted, the time until the target negates the REQ Synchronous transfer case T arget: After the REQ is sent, the time until an ACK signal which makes the offset 0 is received from the initiator
SPC Timeout Manages the SPC timeout indicating the SPC busy time longer than the specified time. 3. Phase Controller Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command, status, and message in/out. 4. Transfer Controller Controls the information (data, command, status, message) transfer phases executed by SCSI. The following two types of transfer phases are used. Asychronous transfer: Controls interlock (response confirmation format) between the REQ and ACK signals. Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phase. The following two modes exist for the data phase. Program transfer: Uses data register (address 00/01) via the MPU interface DMA transfer: Uses DREQ and DACK signals via the DMA interface. The transfer parameter setting values for synchronous transfer (T ransfer mode, transfer rate, transfer offset) can be strobe for individual ID device and are automatically established when the data phase is initiated. The number of transfer bytes is defined as block length · number of blocks. Bus free phase Arbitration phase Selection phase Information transfer phase Information transfer phase:
Command phase
Data phase
Status phase
Message phase

Command register Command is specified by an 8-bit code. Specifies the program head address assigned to the user program memory for user program applications.
Chip status register Shows the chip's operating state, nexus counterpart ID, and data register state.
SCSI bus status register Shows the SCSI control signal state.
Interrupt status register Shows 8-bit code.
Command step register Shows 8-bit code indicating the command execution state. Error analysis can be performed by referring to the information in this register and the interrupt status register.
Group 6/7 command length setting register Sets the group 6/7 command length which is undefined by the SCSI standard. By setting the command length in this register, the SPC can determine the command length. 6. Receive-MCS Buffer A receive only, 32-byte data buffer which stores information received via SCSI (message, command, status) M: Message, C: Command, S: Status 7. Send-MCS Buffer A send only, 32-byte data buffer which stores information sent via SCSI (message, command, status) 8. Command User Program Memory Program memory used for establishing programmable commands (256 bytes). 9. Data Register FIFO-type data register which stores data in SCSI data phase (32 bytes).

n ABSOLUTE MAXIMUM RATINGS (See WARNING) * : VSS = 0 V WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. n RECOMMENDED OPERATING CONDITIONS *1: VSS = 0 V *2: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, A TN, REQ, ACK, MSG, C/D, I/O Note: The recommended operating conditions are the values recommended to ensure correct logic operation of the LSI. The standard values of the electrical characteristics (DC and AC characteristics) are guaranteed within the range of the recommended operating conditions. Parameter Symbol Rating Unit Min. Max. Power supply voltage* V DD VSS – 0.5 6.0 V Input voltage* V I VSS – 0.5 V DD + 0.5 V Output voltage* V O VSS – 0.5 V DD + 0.5 V Operating ambient temperature Top –25 +85 °C Storage temperature Tstg –40 +125 °C Parameter Symbol Value Unit Min. Typ. Max. Power supply voltage *1 VDD 4.75 5.0 5.25 V “H” level input voltage *1 CLK VIH 3.5 — — V Except SCSI and CLK pins 2.2 — — V SCSI pins 2.0 — — V “L” level input voltage * CLK VIL —— 1 . 5V Except CLK pin — — 0.8 V “H” level output current *2 Except SCSI pins IOH — — –2.0 mA SCSI pins Three-state — — –8.0 mA Open-drain — — — mA “L” level output current *2 Except SCSI pins IOL —— + 3 . 2 m A SCSI pins — — +48 mA Operating ambient temperature Ta 0 — +70 °C

n ELECTRICAL CHARACTERISTICS 1. DC Characteristics (VDD = +5 V±5%, VSS = 0 V , T a = 0°C to +70°C) *1: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, A TN, REQ, ACK, MSG, C/D, I/O Note: Leakage current in the above spec indicates the following currents. (1) Leakage current at the high-Z state on the three-state output pins. (2) Leakage current at the output high-Z state (input state) on the bidirectional bus pins. Parameter Symbol Condition Value Unit Min. Max. “H” level input voltage CLK VIH — 3.5 — V Except SCSI and CLK pins 2.2 — V SCSI pins 2.0 — V “L” level input voltage CLK VIL — —1 . 5 V Except CLK pin — 0.8 V Input hysteresis of SCSI pins *1 VHW —0 . 3 — V “H” level output voltage *1 Except SCSI pins VOH IOH = –2.0 mA 4.2 V DD V SCSI pins Three-state I OH = –8.0 mA 2.0 — V Open-drain — — — V “L” level output voltage *1 Except SCSI pins VOL IOL = +3.2 mA V SS 0.4 V SCSI pins I OL = +48.0 mA — 0.5 V Input leakage current I LI VSS £ VI £ VDD –10 +10 mA Input/output leakage current I LOZ VSS £ VI £ VDD , See Note below –10 +10 mA Power supply current I DD All output pins opened CLK input = 20 MHz SPC operating clock = 10 MHz 45 mA CLK input = 30 MHz SPC operating clock = 10 MHz 48 mA CLK input = 40 MHz SPC operating clock = 13.3 MHz 55 mA CLK input = 30 MHz SPC operating clock = 15 MHz 65 mA CLK input = 20 MHz SPC operating clock = 20 MHz 60 mA CLK input = 40 MHz SPC operating clock = 20 MHz 70 mA

I/O Pin Capacitance (VDD = VI = 0 V , f = 1 MHz, T a = +25°C) 3. Load Conditions for AC Characteristics (VDD = +5 V±5%, VSS = 0 V , T a = 0°C to +70°C) Parameter Symbol Value Unit Min. Max. Input pin capacitance C IN —6p F Output pin capacitance C OUT —6p F I/O pin capacitance Except SCSI pins C I/O —6p F SCSI pins — 25 pF R L1 = 110 W Load resistance R L2 = 165 W Load capacitance R L = 200 pF INT , DREQ 60 pF D15 to D8, UDP , D7 to D0, LDP DMD15 to DMD8, UDMDP 85 pF DMD7 to DMD0, LDMDP Pin Symbol C L C L: Load capacitanceC L Measurement point Measurement pin MB86604L C L V DD R L1 R L2 MB86604L Measurement point Measurement pin Non-SCSI pins SCSI pins

AC Characteristics (1) System clock * : The position number indicates the position in the waveform. Note: In case that the internal clock frequency and the input clock frequency are the same (i.e. when using the divided-by-one mode), the clock pulse width (for “H” and “L”) must have at least 20 ns or longer. (2) System reset Parameter Symbol Value Unit Position* Min. Max. Clock cycle time (CLK) t CLK A 25.0 50.0 ns Clock “H” pulse width t wCKH B 10.0 — ns Clock “L” pulse width t wCKL C 10.0 — ns Clock rise time t CR D — 10.0 ns Clock fall time t CF E — 10.0 ns Parameter Symbol Value Unit Min. Max. RESET “L” level pulse width t wRSL 4 tCLK —n s CLK BA DE C 3.5 V 1.5 V t wCKH t CLK t CR t wCKL t CF t wRSL RESET

(3) MPU interface (80 series)

Register write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A4 to A0), BHE set up time WR “L” t suA A4 0 — n s Address (A4 to A0), hold time WR “H” t hA B2 0 — n s CS0 set up time WR “L” t suCS0 C2 0 — n s CS0 hold time WR “H” t hCS0 D1 0 — n s WR “L” level pulse width — t wWRL E7 0 — n s Data set up time WR “H” t suD F4 0 — n s Data hold time WR “H” t hD G1 0 — n s A C E B t hA D GF Data A4 to A0 BHE CS0 WR D15 to D8, UDP D7 to D0, LDP t suA t suCS0 t wWRL t hCS0 t hDt suD

Register read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A4 to A0), BHE set up time RD “L” t suA A4 0— n s Address (A4 to A0), Hold time RD “H” t hA B2 0— n s CS0 set up time RD “L” t suCS0 C2 0— n s CS0 hold time RD “H” t hCS0 D1 0— n s RD “L” level pulse width — t wRDL E7 0— n s Data output defined time RD “L” t vD F — 70 ns Data output disable time RD “H” t DZ G1 0— n s INT signal clear time for INT non-hold mode RD “L” t DL H — 50 ns for INT hold mode RD “H” t DL2 I— n tCLK + 50 ns A C E B D GF Valid data A4 to A0 CS0 RD D15 to D8, UDP H I INT INT t suA t suCS0 t wRDL t hCS0 t DZt vD t DL t DL2* t hA D7 to D0, LDP BHE *: t DL2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. Also, “n” indicates the division ratio.

Register write timing (for external access) * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A0), BHE set up time WR “L” t suAE A4 0— n s Address (A0), BHE hold time WR “H” t hAE B2 0— n s CS1 set up time WR “L” t suCS1 C2 0— n s CS1 hold time WR “H” t hCS1 D1 0— n s DMA data bus output delay time WR “L” t vDMD E — 70 ns DMA data bus output undefined time WR “H” t WRDMD F1 0— n s MPU data ﬁ DMA data bus output delay time — t DDMD G — 40 ns A C B D FE Data BHE CS1 WR D15 to D8, UDP D7 to D0, LDP G DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP Valid data t suAE t hAE t hCS1 t suCS1 t vDMD t WRDMD t DDMD

Register read timing (for external access) * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A0), BHE set up time RD “L” t suAE A4 0— n s Address (A0), BHE hold time RD “H” t hAE B2 0— n s CS1 set up time RD “L” t suCS1 C2 0— n s CS1 hold time RD “H” t hCS1 D1 0— n s MPU data bus output enable time RD “L” t ZD E — 70 ns MPU data bus output disable time RD “H” t DZ F1 0— n s DMA data ﬁ MPU data bus output delay time — t DMDD G — 40 ns A C B D F BHE CS1 RD D15 to D8, UDP D7 to D0, LDP E DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP Valid data G t suAE t hAE t hCS1 t ZDt DMDD t DZ t suCS1 Data

(4) MPU interface (68 series)

Register write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A4 to A0) set up time UDS /LDS “L” t suA A4 0— n s Address (A4 to A0) hold time UDS /LDS “H” t hA B2 0— n s CS0 set up time UDS /LDS “L” t suCS0 C2 0— n s CS0 hold time UDS /LDS “H” t hCS0 D1 0— n s R/W set up time UDS /LDS “L” t suRW E2 0— n s R/W hold time UDS /LDS “H” t hRW F2 0— n s UDS /LDS “L” level pulse width — t wDS G7 0— n s Data set up time UDS /LDS “H” t suD H4 0— n s Data hold time UDS /LDS “H” t hD I1 0 — n s A C G B D IH Data A4 to A0 CS0 R/W D15 to D8, UDP D7 to D0, LDP E F UDS/LDS t suA t suCS0 t suRW t wDS t suD t hD t hRW t hCS0 t hA

Register read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A4 to A0) set up time UDS /LDS “L” t suA A4 0— n s Address (A4 to A0) hold time UDS /LDS “H” t hA B2 0— n s CS0 set up time UDS /LDS “L” t suCS0 C2 0— n s CS0 hold time UDS /LDS “H” t hCS0 D1 0— n s R/W set up time UDS /LDS “L” t suRW E2 0— n s R/W hold time UDS /LDS “H” t hRW F2 0— n s UDS /LDS “L” level pulse time — t wDS G7 0— n s Data output confirmation time UDS /LDS “L” t vD H — 70 ns Data output disable time UDS /LDS “H” t DZ I1 0 — n s INT signal clear time for INT non-hold mode UDS /LDS “L” t DH J — 50 ns for INT hold mode UDS /LDS “H” t DH2 K— n tCLK + 50 ns A C G B D I Valid data A4 to A0 CS0 R/W D15 to D8, UDP D7 to D0, LDP E F UDS/LDS H J KINT INT t suA t suCS0 t suRW t wDS t vD t DH t DH2 t DZ t hRW t hCS0 t hA *: t DH2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. Also, “n” indicates the division ratio.

Register write timing (for external access) * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A0) set up time UDS /LDS “L” t suAE A4 0— n s Address (A0) hold time UDS /LDS “H” t hAE B2 0— n s CS1 set up time UDS /LDS “L” t suCS1 C2 0— n s CS1 hold time UDS /LDS “H” t hCS1 D1 0— n s R/W set up time UDS /LDS “L” t suRW E2 0— n s R/W hold time UDS /LDS “H” t hRW F2 0— n s DMA data bus output delay time UDS /LDS “L” t vDMD G — 70 ns DMA data bus output undefined time UDS /LDS “H” t DSDMD H1 0— n s MPU data ﬁ DMA data bus output delay time — t DDMD I — 40 ns A B D F Data CS1 R/W UDS/LDS I Valid data G H DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP D15 to D8, UDP D7 to D0, LDP t suAE t suCS1 t suRW t vDMD t DDMD t DSDMD t hRW t hCS1 t hAE C E

Register read timing (for external access) * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Address (A0) set up time UDS /LDS “L” t suAE A4 0— n s Address (A0) hold time UDS /LDS “H” t hAE B2 0— n s CS1 set up time UDS /LDS “L” t suCS1 C2 0— n s CS1 hold time UDS /LDS “H” t hCS1 D1 0— n s R/W set up time UDS /LDS “L” t suRW E2 0— n s R/W hold time UDS /LDS “H” t hRW F2 0— n s Data output enable time UDS /LDS “L” t ZD G — 70 ns Data output disable time UDS /LDS “H” t DZ H1 0— n s DMA data ﬁ MPU data bus output delay time — t DMDD I — 40 ns A C B D FE CS1 R/W UDS/LDS I /!/*/+/,/5/6/7/@A Valid data H DMD15 to DMD8, UDMDP D15 to D8, UDP D7 to D0, LDP G DMD7 to DMD0, LDMDP t ZD t DZ t DMDD t hRW t hCS1 t hAEt suAE t suCS1 t suRW Data

(5) DMA interface The DMA access timing described in this section is not applicable in the following cases. During SCSI input, when the data buffer is EMPTY or when one byte is stored During SCSI output, when the data buffer is FULL or when 31 bytes are stored When a parity error is detected (target) When an error which pauses the transfer occurs at the SCSI interface

80 series handshake mode (a) Write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DACK “L” t AKRQ B — 40 ns DREQ “H” assert time (8 bit) DACK “H” t AKRQ1 C — 50 ns DREQ “H” assert time (16 bit) DACK “H” t AKRQ2 C— 2 tCLK + 40 ns IOWR “L” assert time DACK “L” t AKWR D0— n s DMBHE , DMA0 set up time IOWR “L” t suDA E2 0— n s DMBHE , DMA0 hold time IOWR “H” t hDA F2 0— n s IOWR “L” level pulse width — t wWRL G4 0— n s DACK “H” negate time IOWR “L” t WRAK1 H1 t CLK —n s IOWR “H” t WRAK2 I0 — n s Input data set up time IOWR “H” t suDMD J3 0— n s Input data hold time IOWR “H” t hDMD K5— n s

E J F K Data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D BA C DACK DMBHE DMA0 IOWR t RQAK t AKRQ t AKWR t suDA t wWRL t suDMD t hDMD t hDA t WRAK2 t AKRQ1/2 t WRAK1

(b) Read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DACK “L” t AKRQ B — 40 ns DREQ “H” assert time (8 bit) DACK “H” t AKRQ1 C — 50 ns DREQ “H” assert time (16 bit) DACK “H” t AKRQ2 C— 2 tCLK + 40 ns IORD “L” assert time DACK “L” t AKRD D0— n s DMBHE , DMA0 set up time IORD “L” t suDA E2 0— n s DMBHE , DMA0 hold time IORD “H” t hDA F2 0— n s IORD “L” level pulse width — t wRDL G4 0— n s DACK “H” negate time IORD “L” t RDAK1 H1 t CLK —n s IORD “H” t RDAK2 I0 — n s Data output defined time IORD “L” t vDMD J — 40 ns Data output hold time IORD “H” t hDMD K1 0— n s J F K Valid data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D A C DACK DMBHE DMA0 IORD t RQAK t AKRQ t AKRD t RDAK1 t RDAK2 t hDA t wRDL t hDMDt vDMD t suDA t AKRQ1/2 E B

68 series handshake mode (a) Write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DACK “L” t AKRQ B — 40 ns DREQ “H” assert time (8 bit) DACK “H” t AKRQ1 C — 50 ns DREQ “H” assert time (16 bit) DACK “H” t AKRQ2 C— 2 tCLK + 40 ns DMUDS /DMLDS “L” assert time DACK “L” t AKDS D0— n s DMR/W set up time DMUDS /DMLDS “L” t suRW E2 0— n s DMR/W hold time DMUDS /DMLDS “H” t hRW F2 0— n s DMUDS /DMLDS “L” level pulse width — t wDSL G4 0— n s DACK “H” negate time DMUDS /DMLDS “L” t DSAK1 H1 t CLK —n s DMUDS /DMLDS “H” t DSAK2 I0 — n s Input data set up time DMUDS /DMLDS “H” t suDMD J3 0— n s Input data hold time DMUDS /DMLDS “H” t hDMD K5— n s E J F K Data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D BA C DACK DMR/W DMUDS/DMLDS t RQAK t AKRQ t AKRQ1/2 t DSAK2 t hRW t hDMDt suDMD t suRW t AKDS t DSAK1 t wDSL

(b) Read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DACK “L” t AKRQ B — 40 ns DREQ “H” assert time (8 bit) DACK “H” t AKRQ1 C — 50 ns DREQ “H” assert time (16 bit) DACK “H” t AKRQ2 C— 2 tCLK + 40 ns DMUDS /DMLDS “L” assert time DACK “L” t AKDS D0— n s DMR/W set up time DMUDS /DMLDS “L” t suRW E2 0— n s DMR/W hold time DMUDS /DMLDS “H” t hRW F2 0— n s DMUDS /DMLDS “L” level pulse width — t wDSL G4 0— n s DACK “H” negate time DMUDS /DMLDS “L” t DSAK1 H1 t CLK —n s DMUDS /DMLDS “H” t DSAK2 I0 — n s Data output defined time DMUDS /DMLDS “L” t vDMD J — 40 ns Data output hold time DMUDS /DMLDS “H” t hDMD K1 0— n s E J F K Valid data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D BA C DACK DMR/W DMUDS/DMLDS t RQAK t AKRQ t AKDS t suRW t vDMD t wDSL t hRW t hDMD t DSAK2 t DSAK1 t AKRQ1/2

Burst mode (80 series/68 series common) (a) Data register access cycle time (8 bit) * : The position number indicates the position in the waveform. (b) Data register access cycle time (16 bit) * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. Data register access cycle time 1 — t DCY1 At CLK —n s Data register access cycle time 2 — t DCY2 B3 t CLK —n s Data register access cycle time 3 — t DCY3 C4 t CLK —n s Parameter Symbol Value Unit Base signal Position* Min. Max. Data register access cycle time 1 — t DCY1 A4 t CLK —n s Data register access cycle time 2 — t DCY2 B3 t CLK —n s IOWR/IORD DMUDS/DMLDS A B C t DCY1 t DCY2 t DCY3 IOWR/IORD DMUDS/DMLDS A B t DCY1 t DCY2

80 series burst mode (a) Write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time IOWR “L” t WRRQ B — 55 ns DREQ “L” ﬁ DREQ “H” return time — t RQLH C0— n s IOWR “L” assert time DACK “L” t AKWR D0— n s DMBHE , DMA0 set up time IOWR “L” t suDA E2 0— n s DMBHE , DMA0 hold time IOWR “H” t hDA F2 0— n s IOWR “L” level pulse width — t wWRL G4 0— n s DACK “H” negate time IOWR “H” t WRAK H0— n s Input data set up time IOWR “H” t suDMD I3 0 — n s Input data hold time IOWR “H” t hDMD J5— n s E F Data DREQ DMD15 to DMD0 UDMDP, LDMDP G HD A C DACK DMBHE DMA0 IOWR JI t RQAK t WRRQ t RQLH t WRAK t hDA t hDMDt suDMD t wWRL t AKWR t suDA B

(b) Read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time IORD “L” t RDRQ B — 55 ns DREQ “L” ﬁ DREQ “H” return time — t RQLH C0— n s IORD “L” assert time DACK “L” t AKRD D0— n s DMBHE , DMA0 set up time IORD “L” t suDA E2 0— n s DMBHE , DMA0 hold time IORD “H” t hDA F2 0— n s IORD “L” level pulse width — t wRDL G4 0— n s DACK “H” negate time IORD “H” t RDAK H0— n s Data output defined time IORD “L” t vDMD I — 40 ns Data output hold time IORD “H” t hDMD J1 0— n s E F J Valid data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D BAC DACK DMBHE DMA0 IORD t RQAK t RDRQ t RQLH t RDAK t hDA t hDMDt vDMD t wRDL t suDA t AKRD

68 series burst mode (a) Write timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DMUDS /DMLDS “L” t DSRQ B — 55 ns DREQ “L” ﬁ DREQ “H” return time — t RQLH C0— n s DMUDS /DMLDS “L” assert time DACK “L” t AKDS D0— n s DMR/W set up time DMUDS /DMLDS “L” t suRW E2 0— n s DMR/W hold time DMUDS /DMLDS “H” t hRW F2 0— n s DMUDS /DMLDS “L” level pulse width — t wDSL G4 0— n s DACK “H” negate time DMUDS /DMLDS “H” t DSAK H0— n s Input data set up time DMUDS /DMLDS “H” t suDMD I3 0 — n s Input data hold time DMUDS /DMLDS “H” t hDMD J5— n s E F Data DREQ DMD15 to DMD0 UDMDP, LDMDP G HD BA C DACK DMR/W DMUDS/DMLDS JI t RQAK t AKDS t DSRQ t RQLH t DSAK t hRW t hDMDt suDMD t suRW t wDSL

(b) Read timing * : The position number indicates the position in the waveform. Parameter Symbol Value Unit Base signal Position* Min. Max. DACK “L” assert time DREQ “H” t RQAK A0— n s DREQ “L” negate time DMUDS /DMLDS “L” t DSRQ B — 55 ns DREQ “L” ﬁ DREQ “H” return time — t RQLH C0— n s DMUDS /DMLDS “L” assert time DACK “L” t AKDS D0— n s DMR/W set up time DMUDS /DMLDS “L” t suRW E2 0— n s DMR/W hold time DMUDS /DMLDS “H” t hRW F2 0— n s DMUDS /DMLDS “L” level pulse width — t wDSL G4 0— n s DACK “H” negate time DMUDS /DMLDS “H” t DSAK H0— n s Data output defined time DMUDS /DMLDS “L” t vDMD I — 40 ns Data output hold time DMUDS /DMLDS “H” t hDMD J1 0— n s E F J Valid data DREQ DMD15 to DMD0 UDMDP, LDMDP G H I D BA C DACK DMR/W DMUDS/DMLDS t RQAK t DSRQ t RQLH t DSAK t hRW t wDSL t suRW t vDMD t AKDS t hDMD

(6) SCSI interface (as initiator)

Asynchronous transfer mode (a) Input timing (target ﬁ initiator) *1: The position number indicates the position in the waveform. *2: The REQ “H” ﬁ ACK “L” time (tRQAK2 ) is compared with (tRQAKH + tAKRQL + tRQAK1 ) and the longer value is chosen. Note: The input timing definition is not applied in the following cases.
When the data register is FULL in the data phase
When the final byte is being transferred Parameter Symbol Value Unit Base signal Position*1 Min. Max. REQ “H” negate time ACK “L” t AKRQH A0— n s ACK “H” negate time REQ “H” t RQAKH B — 60 ns REQ “L” assert time ACK “H” t AKRQL C1 0— n s Input data set up time REQ “L” t suDB D1 0— n s Input data hold time REQ “L” t hDB E2 0— n s ACK “L” assert time 1 REQ “L” t RQAK1 F — 40 ns ACK “L” assert time 2 *2 REQ “H” t RQAK2 G— 3 tCLK + 40 ns A F Data DB7 to DB0 DBP G E REQ ACK CB D t AKRQH t RQAKH t AKRQL t RQAK1 t RQAK2 t hDBt suDB

(b) Output timing (initiator ﬁ target) *1: The position number indicates the position in the waveform. *2: “S” value is based on the asychronous set up time setting register (address 17h). Note: The output timing definitions are not applied when the data register is EMPTY in the data phase. Parameter Symbol Value Unit Base signal Position*1 Min. Max. REQ “H” negate time ACK “L” t AKRQH A0 — n s ACK “H” negate time REQ “H” t RQAKH B— 6 0 n s REQ “L” assert time ACK “H” t AKRQL C1 0 — n s Time from output data valid to ACK “L” assert *2 —t DBAK D S • tCLK – 10 —n s Output data hold time REQ “H” t hDB E2 t CLK —n s ACK “L” assert time REQ “L” t RQAK1 F— 4 0 n s A F Valid dataDB7 to DB0 DBP E REQ ACK CB D Valid data D t RQAK2 t RQAK1t AKRQLt RQAKHt AKRQH t DBAK t hDB t DBAK *: The REQ “H” ﬁ ACK “L” time (tRQAK2 ) is defined by either longer of (tRQAKH + tAKRQL + tRQAK1 ) or (thDB + tDBAK ) (see the output timing waveform).

Synchronous transfer mode (a) REQ/ACK signal period *1: The position number indicates the position in the waveform. *2: “A” and “N” values are based on the transfer period register (address 0Dh) setting. Parameter Symbol Value Unit Base signal Position*1 Min. Max. ACK assert time *2 —t AKAP A A • tCLK – 12 —n s ACK negate time *2 —t AKNP B N • tCLK + 2 —n s REQ assert time — t RQAP C2 0 — n s REQ negate time — t RQNP D2 0 — n s REQ input cycle time 1 — t RQCY1 E1 t CLK —n s REQ input cycle time 2 — t RQCY2 F3 t CLK —n s A E REQ ACK B F C D t AKAP t AKNP t RQNPt RQAP t RQCY1 t RQCY2

(b) Input timing (target ﬁ initiator) * : The position number indicates the position in the waveform. (c) Input timing (target ﬁ initiator) *1: The position number indicates the position in the waveform. *2: “A” and “N” values are based on the transfer period register (address 0Dh) setting. Parameter Symbol Value Unit Base signal Position* Min. Max. Input data set up time REQ “L” t suDB A5— n s Input data hold time REQ “L” t hDB B1 5— n s Parameter Symbol Value Unit Base signal Position*1 Min. Max. Time from output data valid to ACK “L” assert *2 —t DBAK A N • tCLK + 2 —n s Output data hold time *2 ACK “L” t hDB B A • tCLK – 12 —n s REQ DB7 to DB0 DBP B DataData ABA t hDBt suDBt hDBt suDB ACK DB7 to DB0 DBP B Valid dataValid data ABA t DBAK t hDB t hDBt DBAK

(7) SCSI interface (as initiator)

Asynchronous transfer mode (a) Input timing (initiator ﬁ target) *1: The position number indicates the position in the waveform. *2: The REQ “L” ﬁ REQ “L” time (tAKRQ2 ) is compared with (tAKRQH + tRQAKH + tAKRQ1 ) and the longer value is chosen. Note: The input timing definition is not applied in the following cases.
When the data register is FULL in the data phase
When the final byte is being transferred Parameter Symbol Value Unit Base signal Position*1 Min. Max. ACK “L” assert time REQ “L” t RQAKL A0— n s REQ “H” negate time ACK “L” t AKRQH B — 60 ns ACK “H” negate time REQ “H” t RQAKH C0— n s Input data set up time ACK “L” t suDB D1 0— n s Input data hold time ACK “L” t hDB E2 0— n s ACK “L” assert time 1 ACK “H” t AKRQ1 F — 40 ns ACK “L” assert time 2 *2 ACK “H” t ALRQ2 G— 3 tCLK + 40 ns A DataDB7 to DB0 DBP G E REQ ACK FC D B t AKRQ2 t RQAKL t AKRQH t RQAKH t AKRQ1 t hDBt suDB

(b) Output timing (target ﬁ initiator) *1: The position number indicates the position in the waveform. *2: “S” value is based on the asychronous set up time setting register (address 17h). Note: The output timing definitions are not applied when the data register is EMPTY in the data phase. Parameter Symbol Value Unit Base signal Position*1 Min. Max. ACK “L” assert time REQ “L” t RQAKL A0 — n s REQ “H” negate time ACK “L” t AKRQH B— 6 0 n s ACK “H” negate time REQ “H” t RQAKH C0 — n s Time from output data valid to REQ “L” assert *2 —t DBRQ D S • tCLK – 10 —n s Output data hold time ACK “L” t hDB E2 t CLK —n s REQ “L” assert time ACK “H” t AKRQ1 F— 4 0 n s A Valid data E REQ ACK FC D B D Valid dataDB7 to DB0 DBP t AKRQ2 t AKRQ1t RQAKH t RQAKL t hDB t DBRQt DBRQ t AKRQH *: The ACK “L” ﬁ REQ “L” time (tAKRQ2 ) is defined by either longer of (tAKRQH + tRQAKH + tAKRQ1 ) or (thDB + tDBRQ ).

Synchronous transfer mode (a) REQ/ACK signal period *1: The position number indicates the position in the waveform. *2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values. Parameter Symbol Value Unit Position*1 Min. Max. REQ assert time *2 tRQAP A A • tCLK – 12 —n s REQ negate time *2 tRQNP B N • tCLK + 2 —n s ACK assert time t AKAP C2 0 — n s ACK negate time t AKNP D2 0 — n s ACK input cycle time 1 t AKCY1 E1 t CLK —n s ACK input cycle time 2 t AKCY2 F3 t CLK —n s A t RQAP E REQ ACK t AKCY1 B F t AKCY2 t RQNP C t AKAP D t AKNP

(b) Input timing (initiator ﬁ target) * : The position number indicates the position in the waveform. (c) Output timing (target ﬁ initiator) *1: The position number indicates the position in the waveform. *2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values. Parameter Symbol Value Unit Base signal Position* Min. Max. Input data set up time ACK “L” t suDB A5— n s Input data hold time ACK “L” t hDB B1 5— n s Parameter Symbol Value Unit Base signal Position*1 Min. Max. Time from output data valid to REQ “L” assert *2 —t DBRQ A N • tCLK + 2 —n s Output data hold time *2 REQ “L” t hDB B A • tCLK – 12 —n s ACK DB7 to DB0 DBP t hDB B t hDB DataData At suDB BAt suDB REQ DB7 to DB0 DBP B Valid dataValid data ABA t DBRQ t hDB t hDBt DBRQ

(8) A/N/S values in the SCSI interface timing specification

Transfer period register (address 0Dh) and A/N values Note: The A and N values set in the register are the assert period and the negate period respectively (unit is clock cycles) For the AC characteristics, A/N use numerals.
Asynchronous setup time register (address 17h) setting and the S value. Note: The S (setup time) value established in the set up time register during asynchronous data transfers indicates the time from setting data in the data bus until the REQ /ACK signals are asserted. For the AC characteristics, S uses numerals. Transfer period register AN Transfer period register AN Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00001 P r o h i b i t P r o h i b i t 10001 9 8

Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 0001 1 1001 9 0010 2 1010 1 0 0011 3 1011 1 1 0100 4 1100 1 2 0101 5 1101 1 3 0110 6 1110 1 4 0111 7 1111 1 5 1000 8 0000 1 6

BASIC Control Registers (for write) 2. BASIC Control Registers (for read) Note: X indicates data is undefined. (0 or 1). Address Register name Bit assignment Hex. A4 A3 A2 A1 A0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 000000 O u t p u t d a t a r e g i s t e r ( f i r s t ) D O 7D O 6D O 5D O 4D O 3D O 2D O 1D O 0 0 100001 Output data register (second)DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 0 200010 D i r e c t c o n t r o l r e g i s t e r D C 7 0 0 D O 40000 0 300011 ( R e s e r v e d ) 0 0 0 00000 0 400100 S E L / R ESEL ID register SI7 0 0 0 0 SI2 SI1 SI0 0 500101 C o m m and register CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 0 600110 D a t a b l o c k r e g i s t e r ( M S B ) B L 1 5 B L 1 4 B L 1 3 B L 1 2 B L 1 1 B L 1 0B L 9 B L 8 0 700111 D a t a b l o c k r e g i s t e r ( L S B ) B L 7 B L 6 B L 5 B L 4 B L 3 B L 2 B L 1 B L 0 0 801000 D a t a b y t e r e g i s t e r ( M S B ) B Y 2 3 B Y 2 2 B Y 2 1 B Y 2 0 B Y 1 9 B Y 1 8 B Y 1 7 B Y 1 6 0 901001 D a t a b y t e r e g i s t e r B Y 1 5 B Y 1 4 B Y 1 3 B Y 1 2 B Y 1 1 B Y 1 0B Y 9 B Y 8

0 A01010 Data byte register (LSB)BY7 BY6 BY5 BY4 BY3 BY2 BY1 BY0MC byte register

0 B01011 D i a gnostic control register DG7 DG6 DG5 0 DG3 DG2 DG1 DG0

0 C01100 T r a n s f e r m o d e r e g i s t e r T M 7 0 0 00000

0 D01101 T r a n s f e r p e r i o d r e g i s t e r 0 0 0 T P 4 T P 3 T P 2 T P 1 T P 0

0 E01110 T r a n s f e r o f f s e t r e g i s t e r 0 0 0 T O 4 T O 3 T O 2 T O 1 T O 0

0 F01111 W i n d o w address register WA7 WA6 0 0 WA3 WA2 WA1 WA0

Address Register name Bit assignment Hex. A4 A3 A2 A1 A0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 000000 I nput data register (first) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 100001 I nput data register (second) DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 0 200010 S P C s t a t u s r e g i s t e r S S 7 S S 6 S S 5 S S 4 X S S 2 S S 1 S S 0 0 300011 N e x u s s t a t u s r e g i s t e r N S 7 N S 6 N S 5 X X N S 2 N S 1 N S 0 0 400100 I n t e r r u p t s t a t u s r e g i s t e r I S 7 I S 6 I S 5 I S 4 I S 3 I S 2 I S 1 I S 0 0 500101 C o m m and step register CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 0 600110 D a t a b l o c k r e g i s t e r ( M S B ) B L 1 5 B L 1 4 B L 1 3 B L 1 2 B L 1 1 B L 1 0B L 9 B L 8 0 700111 D a t a b l o c k r e g i s t e r ( L S B ) B L 7 B L 6 B L 5 B L 4 B L 3 B L 2 B L 1 B L 0 0 801000 D a t a b y t e r e g i s t e r ( M S B ) B Y 2 3 B Y 2 2 B Y 2 1 B Y 2 0 B Y 1 9 B Y 1 8 B Y 1 7 B Y 1 6 0 901001 D a t a b y t e r e g i s t e r B Y 1 5 B Y 1 4 B Y 1 3 B Y 1 2 B Y 1 1 B Y 1 0B Y 9 B Y 8

0 B01011

SCSI control signal status registerSC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0

0 C01100 T r a n s f e r m o d e r e g i s t e r T M 7XXXXXXX

0 D01101 T r a n s f e r p e r i o d r e g i s t e r X X X T P 4 T P 3 T P 2 T P 1 T P 0

0 E01110 T r a n s f e r o f f s e t r e g i s t e r X X X T O 4 T O 3 T O 2 T O 1 T O 0

0 F01111 M o d i f i e d b y t e r e g i s t e r X X M B 5B M 4M B 3M B 2M B 1M B 0

Initial Setting Window (for read/write) 4. MCS Buffer Window Address Register name Bit assignment Hex. A4 A3 A2 A1 A0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 10000 C l o c k c o n v e r s i o n s e t t i n g C C 7 C C 6 C C 5 C C 4 C C 3 C C 2 C C 1 C C 0 1 1 10001 S e l f I D s e t t i n g 00000 O I 2 O I 1 O I 0 1 2 10010 R e s p o n s e m o d e s e t t i n g A M 7 A M 6 A M 5 A M 4 0 0 A M 1 A M 0 1 3 10011 S e l e c t i o n / r e s e l e c t i o n mode setting SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 1 4 10100 S e l e c t i o n / r e s e l e c t i o n r e t r y s e t t i n g S R 7 S R 6 S R 5 S R 4 S R 3 S R 2 S R 1 S R 0 1 5 10101 Selection/reselection timeout settingS T 7S T 6S T 5S T 4S T 3S T 2S T 1S T 0 1 6 10110 R E Q / A C K t i m e o u t s e t t i n g R T 7 R T 6 R T 5 R T 4 R T 3 R T 2 R T 1 R T 0 1 7 10111 A s y n c h r o n o u s s e t u p t i m e s e t t i n g0000 A T 3 A T 2 A T 1 A T 0 1 8 11000 P a r i t y e r r o r d e t e c t i o n s e t t i n g P E 7 P E 6 P E 5 P E 4 P E 3 0 P E 1 P E 0 1 9 11001 I n t e r r u p t enable setting IE7 0 IE5 IE4 IE3 IE2 IE1 IE0 1 A11010 G r o u p 6 / 7 c o m m a n d l e n g t h s e t t i n g G L 7 G L 6 G L 5 G L 4 G L 3 G L 2 G L 1 G L 0

1 B11011 D M A s y s t e m s e t t i n g 0 0 D M 5 M D 4 0 0 0 0

1 C11100 A u t o m a t i c o p e r a t i o n m o d e s e t t i n g O M 7 O M 6 O M 5 O M 4 O M 3 O M 2 O M 1 O M 0

1 D11101 S P C T i m e o u t s e t t i n g T O 7 T O 6 T O 5 T O 4 T O 3 T O 2 T O 1 T O 0

1 F11111 D e v i c e r e v i s i o n i n d i c a t i o n R V 7 R V 6 R V 5 R V 4 R V 3 R V 2 R V 1 R V 0 Address For write For read Hex. A4 A3 A2 A1 A0 1 0 10000 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 1 10001 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 2 10010 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 3 10011 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 4 10100 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 5 10101 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 6 10110 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 7 10111 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 8 11000 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r 1 9 11001 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 A 11010 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 B 11011 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 C 11100 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 D 11101 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 E 11110 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

1 F 11111 S E N D M C S b u f f e r R E C E I V E M C S b u f f e r

User Program Memory Window Address For write For read Hex. A4 A3 A2 A1 A0 1 0 10000 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 1 10001 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 2 10010 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 3 10011 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 4 10100 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 5 10101 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 6 10110 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 7 10111 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 8 11000 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y 1 9 11001 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

1 A 11010 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

1 B 11011 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

1 C 11100 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

1 D 11101 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

I E11110 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

1 F 11111 U s e r p r o g r a m m e m o r y U s e r p r o g r a m m e m o r y

SPC commands can be specified in the command register or the user program memory and divided into the following main groups.

Sequential commands Commands that perform a consecutive (including phase transitions) sequence operation. Can only be specified in the command register (1-byte).
Discrete commands Commands which perform operations from disassembled sequential commands. Can be specified in the command register (1-byte command) or the user program memory (1/2-byte command).
Special commands Can only be specified in the user program memory (1/2-byte command). 1. Initiator Commands (1) Sequential commands No Command code Operand (for program) Command name 1 0 0 H00000000 ( n o t p o s s i b l e ) S e l e c t & C M D 2 0 1 H00000001 ( n o t p o s s i b l e ) S e l e c t & 1 - M S G & C M D 3 0 2 H00000010 ( n o t p o s s i b l e ) S e l e c t & N - B y t e - M S G & C M D 4 0 3 H00000011 ( n o t p o s s i b l e ) S e l e c t & 1 - M S G 5 0 4 H00000100 ( n o t p o s s i b l e ) S e l e c t & N - B y t e - M S G 6 0 5 H00000101 ( n o t p o s s i b l e ) S end N-Byte-MSG 7 0 6 H00000110 ( n o t p o s s i b l e ) S end N-Byte-CMD 8 0 7 H00000111 ( n o t p o s s i b l e ) R e c e i v e N - B y t e - M S G

(2) Discrete commands No Command code Operand (for program) Command name 9 0 8 H00001000 — S e l e c t 1 00 9 H00001001 — S e l e c t w i t h A T N 1 1 0 A H00001010 — S e t A T N 1 2 0 B H00001011 — R e s e t A T N 1 3 0 C H 00001100 — S e t A C K 1 4 0 D H 00001101 — R e s e t A C K 1 51 0 H00010000 — S end Data from MPU 1 61 1 H00010001 — S end Data from DMA 1 71 2 H00010010 — R e c e i v e D a t a t o M P U 1 81 3 H00010011 — R e c e i v e D a t a t o D M A 1 91 4 H00010100 — S end DA T A from MPU Padding 2 01 5 H00010101 — S end DA T A from DMA Padding 2 11 6 H00010110 — R e c e i v e D a t a t o M P U P a d d i n g 2 21 7 H00010111 — R e c e i v e D a t a t o D M A P a d d i n g 2 31 8 H00011000 A d d r e s s o f M S G s e n t S end 1-MSG 2 41 9 H00011001 A d d r e s s o f M S G s e n t S end 1-MSG with A TN 2 5 1 A H00011010 S A V E a d d r e s s o f M S G R e c e i v e M S G 2 6 1 B H00011011 A d d r e s s o f C M D s e n t S end CMD 2 7 1 C H 00011100 S A V E a d d r e s s o f S T A T U S R e c e i v e S T A T U S

Target Commands (1) Sequential commands No Command code Operand (for program) Command name 1 2 0 H00100000 ( n o t p o s s i b l e ) R e s e l e c t & 1 - M S G 2 2 1 H00100001 ( n o t p o s s i b l e ) R e s e l e c t & N - B y t e - M S G 3 2 2 H00100010 ( n o t p o s s i b l e ) R e s e l e c t & 1 - M S G & T e r m i n a t e 4 2 3 H00100011 ( n o t p o s s i b l e ) R e s e l e c t & 1 - M S G & L i n k - T e r m i n a t e 5 2 4 H00100100 ( n o t p o s s i b l e ) T e r m i n a t e 6 2 5 H00100101 ( n o t p o s s i b l e ) L i n k - T e r m i n a t e 7 2 6 H00100110 ( n o t p o s s i b l e ) D i s c onnect-Sequence 8 2 7 H00100111 ( n o t p o s s i b l e ) S e n d N - B y t e - M S G 9 2 8 H00101000 ( n o t p o s s i b l e ) R e c e i v e N - B y t e - C M D 1 02 9 H00101001 ( n o t p o s s i b l e ) R e c e i v e N - B y t e - M S G 1 1 2 A H00101010 ( n o t p o s s i b l e ) R e s e l e c t & N - B y t e - M S G & T e r m i n a t e 1 2 2 B H00101011 ( n o t p o s s i b l e ) R e s e l e c t & N - B y t e - M S G & L i n k - T e r m i n a t e 1 3 2 C H 00101100 ( n o t p o s s i b l e ) D i s c onnect-Sequence 2

(2) Discrete commands 3. Common Commands No Command code Operand (for program) Command name 1 43 0 H00110000 — R e s e l e c t 1 53 1 H00110001 — S e t R E Q 1 63 2 H00110010 — R e s e t R E Q 1 73 3 H00110011 — D i s c onnect 1 83 4 H00110100 — S e n d D a t a f r o m M P U 1 93 5 H00110101 — S e n d D a t a f r o m D M A 2 03 6 H00110110 — R e c e i v e D a t a t o M P U 2 13 7 H00110111 — R e c e i v e D a t a t o D M A 2 23 8 H00111000 A d d r e s s o f M S G s e n t S e n d 1 M S G 2 33 9 H00111001 S A V E a d d r e s s o f M S G R e c e i v e M S G 2 4 3 A H00111010 S end-status address Send Status 2 5 3 B H00111011 S A V E a d d r e s s o f C D B R e c e i v e C M D No Command code Operand (for program) Command name 1 4 0 H01000000 ( n o t p o s s i b l e ) S O F T W A R E R ESET 2 4 1 H01000001 ( n o t p o s s i b l e ) T R A N S F E R R ESET 3 4 2 H01000010 ( n o t p o s s i b l e ) S C S I R ESET 4 4 3 H01000011 ( n o t p o s s i b l e ) S E T U P R E G 5 4 4 H01000100 ( n o t p o s s i b l e ) I N I T D I A G S T A R T 6 4 5 H01000101 ( n o t p o s s i b l e ) T A R G D I A G S T A R T 7 4 6 H01000110 ( n o t p o s s i b l e ) D I A G E N D 8 4 7 H01000111 ( n o t p o s s i b l e ) C O M M A N D P A U S E 9 4 8 H01001000 ( n o t p o s s i b l e ) S E T R S T 1 04 9 H01001001 ( n o t p o s s i b l e ) R E S E T R S T

Programmable Commands The user program is stored in the user program memory and begins operation when the user program head address is written in the command register. Programmable commands are composed of discrete and special commands and have a command length of one (1) or two (2) bytes.

Command field assign Command type Command code (1st byte) Operand (2nd byte) Discrete commands Message, command, or status phases send command Memory address of the data to be sent. Message, command, or status phases receive command Memory address of received data being stored. Data phase receive/send command or do not perform transfer command — Special commands AND command Data for AND operation or memory address of data for AND operation. TEST AND command Data for AND operation or memory address of data for AND operation. COMP ARE command Data for COMP ARE operation or memory address of data for COMP ARE operation. Conditional branch command Jump head address MOVE command Memory address to be moved. STOP command User status code NOP command —

n SYSTEM CONFIGURATION EXAMPLE 1. 80-Series, Separate Bus Type MB86604L DB7 to 0 DBP ACK ATN REQ MSG C/D I/O BSY SEL RST CLK RESET MODE INT TMOUT CS0 CS1 A4 to A0 D15 to D0 UDP LDP BHE RD WR DMD15 to 0 UDMDP LDMDP DREQ DACK DMBHE IORD IOWR DMA0 TP DMA controller Address DATA buffer memory DMA bus Data bus Address bus Address decoder MPU RESET circuit Oscillation circuit SCSI bus

80-Series, Common Bus Type MB86604L DB7 to 0 DBP ACK ATN REQ MSG C/D I/O BSY SEL RST CLK RESET MODE INT TMOUT CS1 CS0 A4 to A0 D15 to D0 UDP LDP BHE RD WR DMD15 to 0 UDMDP LDMDP DREQ DACK DMBHE IORD IOWR DMA0 TP DMA controller Address decoder MPU RESET circuit Oscillation circuit Address bus Data bus DMA bus SCSI bus

68-Series, Separate Bus Type MB86604L DB7 to 0 DBP ACK ATN REQ MSG C/D I/O BSY SEL RST CLK RESET MODE INT TMOUT CS0 CS1 A4 to A1 D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP DREQ DACK DMR/W DMUDS DMLDS DMA0 TP DMA controller Address DATA buffer memory DMA bus Data bus Address bus Address decoder MPU RESET circuit Oscillation circuit SCSI bus

68-Series, Common Bus Type MB86604L DB7 to 0 DBP ACK ATN REQ MSG C/D I/O BSY SEL RST CLK RESET MODE INT TMOUT CS1 CS0 A4 to A1 D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP DREQ DACK DMR/W DMUDS DMLDS DMA0 TP DMA controller Address decoder MPU RESET circuit Oscillation circuit Address bus Data bus DMA bus SCSI bus

Part number Package Remarks MB86604LPFV 100 pin Plastic LQFP (FPT-100P-M05)

(FPT-100P-M05) C 1995 FUJITSU LIMITED F100007S-2C-3 Details of "B" part 0.50(.0197)TYP .007−.001 +.003 −0.03 +0.08 0.18 INDEX 0.10(.004) 0.08(.003)M .059−.004 +.008 −0.10 +0.20 1.50 .005−.001 +.002 −0.02 +0.05 0.127 15.0012.00 (.472) REF (.591) NOM "B" "A" 100 75 51 5076 Details of "A" part 0.40(.016)MAX 0.15(.006)MAX 0.15(.006) 0.15(.006) 0.10±0.10 (.004±.004)(STAND OFF) 0~10˚ LEAD No. Dimensions in mm (inches) (MOUNTING HEIGHT)

For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan T el: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A. T el: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10

63303 Dreieich-Buchschlag

T el: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New T ech Park Singapore 556741 T el: (65) 281-0770 Fax: (65) 281-0220 F9702 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Com- plete information sufficient for construction purposes is not nec- essarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu as- sumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

Summary

SCSI-II Protocol Controller (with single-ended driver/receiver)

Description