MB86292PFFS-G-BND

MB86292 FUJITSU | Alldatasheet

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DS04-31103-1EFUJITSU SEMICONDUCTOR DATA SHEET ASSP for Graphics Control Graphics Display Controller MB86292 nnnn DESCRIPTION The MB86292 is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car navigation system or amusement equipment. The MB86292 is a graphics display controller with an on-chip geometry processor and digital video capture facility. It can be connected to FCRAM. Connecting the MB86292 to FCRAM which has lower latency upon a paging error speeds up the random access to memory, resulting in faster display and drawing. In addition, integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system. nnnn FEATURES

• Operating frequency : 100 MHz (External clock of 14.32 MHz Max)
• Geometry processor : Capable of executing operations for geometric transformation and surface front/rear evaluation.
• Memory block : Capable of connecting SDRAM and FCRAM
• Video capture block : Embedded facility to capture digital video images, for example, from TV , capable of easily implementing “Picture in Picture” and video graphics superimposing.
• Host interface : Enables direct connection to various CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) . (Continued) nnnn PACKAGE 256-pin plastic QFP (FPT-256P-M09)

(Continued)

• Drawing features :
• Drawing at a peak rate of 800 Mpixel/s (at an internal operating frequency of 100 MHz)
• 2D drawing functions : Point, line, triangle, polygon, BLT and pattern drawing
• 3D drawing functions : Point, line, triangle drawing and hidden surface removal by Z-buffering
• Special effects : Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture map- ping (bilinear filtering, perspective correct) , and tiling
• Display features :
• Maximum display resolution supported : 1024 · 768 pixels
• Color display either with a color palette of 8 Bit/Pixel or directly using 5-bit RGB colors of 16 Bit/Pixel
• Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts
• Supporting two 64 Pixel · 64 Pixel hardware cursors
• Output of analog RGB and digital RGB signals
• Capable of superimposing using an external synchronization mode
• Power-supply voltage : T wo power supplies at 2.5 – 0.2 V, for internal circuits and 3.3 – 0.2 V for I/O parts
• Package : PlasticQFP with 256 pins (with a lead pitch of 0.4 mm)
• Process technology : CMOS 0.25 mm

(TOP VIEW) 256 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 255 234 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 233 212 210 209 208 207 206 205 204 203 202 201 200 199 188 187 186 185 184 183 211 CS RD RESET VSS VDDL VDDH DTACK/TC DRACK/DMAAK A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 VSS VDDL BS A13 A11 A10 VSS VDDH OSCCNT PLLVDD S OSCOUT PLLVSS CLK VSS VDDL CLKSEL0 A12 CLKSEL1 VI7 VI6 VI5 VI4 VI3 VI2 VI1 VI0 CCLK VSS VDDL VDDH DCLKI TESTH TESTH TESTH TESTH CKM 192 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 191 170 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 169 148 146 145 144 143 142 140 138 141 139 137 136 135 134 133 132 131 130 129 147 TESTH VSYNC HSYNC CSYNC DISPE DCLKO VDDH VSS VDDL GV VSS VDDL VDDH MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 VSS VDDL MD46 MD45 MD44 MD43 MD40 MD38 MD42 MD41 MD39 MD37 MD36 MD35 MD34 MD33 MD32 VSS VDDH MD47 100 101 102 103 104 105 106 107 108 109 111 112 113 114 115 117 119 116 118 120 121 122 123 124 125 126 127 128 110 VDDL MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 VDDH VDDL VSS MD23 MD24 VSS MD25 MD27 MD28 MD29 MD30 MD31 MA0 MA1 MA2 MA3 MA4 VDDH VSS MCLKO MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MD26 MA13 VDDH VDDL VSS MDQM0 MDQM3 MDQM5 MDQM1 MDQM2 MDQM4 MDQM6 MDQM7 MRAS MCAS VDDL VSS MCLKI RGBEN MWE WE0 WE2 WE3 BCLKI MODE0 MODE1 MODE2 TESTH TESTH VDDH VDDL VSS RDY DREQ INT WE1 VDDH VDDL D10 D11 D12 D13 D14 D15 D16 D17 D18 VSS VDDL D19 D20 D21 D22 D23 VSS D24 D26 D27 D28 D29 VDDH VSS D30 D31 VDDL MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 D25 VSS/PLLVSS VDDH VDDL/PLLVDD PLLVDD OPEN TESTH Notes : • The PLLVDD should be separated on the board.

• Insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. Place the capacitor as near the pins as possible. : Ground : 3.3 V power supply : 2.5 V power supply : PLL power supply : Do not connect anything. : Input the high level.

TESTL, TESTH CLK S CKM OSCOUT OSCCNT DCLKO DCLKI HSYNC VSYNC CSYNC DISPE GV R3-R7 G3-G7 B3-B7 RGBEN CCLK VI0-VI7 MD0-MD63 MA0-MA13 MRAS MCAS MWE MDQM0-MDQM7 MCLKO MCLKI MB86292 Graphics Controller HQFP256 CLKSEL0- CLKSEL1 Video output interface Graphics memory interface Host CPU interface Clock Vide capture interface

• Host Interface Pins Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC, or to the SP ARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below. Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. T o use the MODE2 signal at "H" level, set the software setting to two cycles. Pin Name Input/output Function MODE0- MODE2 Input Host CPU mode/Ready mode select RESET Input Hardware reset D0-D31 Input/output Host CPU bus data A2-A24 Input Host CPU bus address (Connect A24 to MWR in V832 mode.) BCLKI Input Host CPU bus clock BS Input Bus cycle start signal CS Input Chip select signal RD Input Read strobe signal WE0 Input D0-D7 write strobe signal WE1 Input D8-D15 write strobe signal WE2 Input D16-D23 write strobe signal WE3 Input D24-D31 write strobe signal RDY Output Tristate Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4, V832, or SPARClite) DREQ Output DMA request signal (active low with both SH and V832) DRACK/ DMAAK Input DMA request acknowledge signal (Connect this to DMAAK in V832 mode. Active high with both SH and V832.) DTACK/TC Input DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high, V832 = active low) INT Output Host CPU interrupt signal (SH = active low, V832 = active high) TESTH Input Test signal MODE1 pin MODE0 pin CPU Type LL S H 3 LH S H 4 H L V832 H H SPARClite MODE2 pin Ready signal mode LS e t R D Y signal to “Not Ready” level upon completion of bus cycle. HS e t R D Y signal to “Ready” level upon completion of bus cycle.

Notes : • The host interface transfers data signals at a fixed width of 32 bits.

• There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space.
• The external bus can be used at an operating frequency of 100 MHz maximum.
• The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output signal synchronized to the rise of BCLKI.
• The host interface supports DMA transfer using an external DMA controller.
• The host interface generates a host processor interrupt signal.
• The RESET pin requires low level input of at least 300 ms after setting "S" (PLL reset signal) to high level.
• Fix the TEST signal at high level.
• In the V832 mode, connect the following pins as specified :
• Video Output Interface Pins Notes : • The video output interface outputs RGB pieces of five-bit display data by default. It can output RGB pieces of eight-bit display data depending on conditions. R0-2, G0-2, and B0-2 can be output to MD61-MD63, MD58-MD60, and MD58-MD60, respectively, by fixing RGBEN to 0. When eight-bit RGB output is selected, only the 32-bit memory bus width mode can be used.
• Using an additional external circuit, the video output interface can generate composite video signals.
• The video output interface can provide display synchronized with external video. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display.
• The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset.
• The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video. ORCHID Pin Name V832 Signal Name A24 MWR DTACK TC DRACK DMAAK Pin Name Input/output Function DCLKO Output Display dot clock signal output DCLKI Input Dot clock signal input HSYNC Input/output Horizontal sync signal output Horizontal sync signal input in external synchronization mode VSYNC Input/output Vertical sync signal output Vertical sync signal input in external synchronization mode CSYNC Output Composite sync signal output DISPE Output Display effective period signal GV Output Graphics/video select signal R3-R7 Output Digital video (R) signal output G3-G7 Output Digital video (G) signal output B3-B7 Output Digital video (B) signal output RGBEN Input RGB2-0 output/memory bus (MD63-55) select signal

• Video Capture Interface Pins Note : The video capture interface inputs digital video signals in the ITU-RBT -656 format.
• Graphics Memory Interface Pins Notes : • The graphics memory interface connects the MB86292 to the external memory used for graphical image data. The interface can directly accept 128-Mbit SDRAM or 64-Mbit SDRAM (with a 16-bit or 32-bit data bus) without any external circuit.
• Memory bus data can be selected between 64 bits and 32 bits. T o use 32-bit data, leave the MD32-MD63 and MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin = 0) or the MD32-MD54 and MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin = 0).
• Connect the MCLKI pin to the MCLKO pin.
• When RGBEN is fixed to 1, MD55-MD63 can be used as graphics memory bus data. When RGBEN is fixed to 0, RGB0-2 is output.
• Clock Input Pins *1 : Do not connect anything. *2 : Input the "H" level. Notes : • The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. Usually input 4 Fsc ( = 14.31818 MHz for NTSC). The internal PLL generates the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz.
• The internal operating clock signal to be used can be selected between the clock signal (100 MHz) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI input to use the host CPU bus at 100 MHz. Pin Name Input/output Function CCLK Input Digital video input clock signal input VI0-VI7 Input Digital video data input Pin Name Input/output Function MD0-MD54 Input/output Graphics memory bus data MD55-MD63 Input/output Graphics memory bus data or RGB0-RGB2 output MA0-MA13 Output Graphics memory bus data MRAS Output Row address strobe MCAS Output Column address strobe MWE Output Write enable MDQM0-MDQM7 Output Data mask MCLKO Output Graphics memory clock output MCLKI Input Graphics memory clock input Pin Name Input/output Function CLK Input Clock input signal S Input PLL reset signal CKM Input Clock mode signal CLKSEL [1 : 0] Input Clock rate select signal OSCOUT*

1 Input/output For connection of crystal oscillator (Reserved)

OSCCNT* 2 Input Crystal oscillator select pin (Reserved)

• Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM = L. Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300 ms or more. CKM Clock Mode L Select internal PLL output. H Select host CPU bus clock (BCLKI). CLKSEL1 CLKSEL0 Input Clock Frequency Multiplier Display reference clock L L Input 13.5 MHz. · 15 202.5 MHz L H Input 14.32 MHz. · 14 200.48 MHz H L Input 17.73 MHz. · 11 195.03 MHz HH R e s e r v e d ¾¾

• ••• Host Interface This block allows the MB86292 to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC, or to the SP ARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device’s graphics memory or internal register using the external DMA controller.
• ••• External Memory Controller This block connects external SDRAM or FCRAM. The data bus can be selected between 64 bits and 32 bits and the maximum operating frequency is 100 MHz.
• ••• Display Controller This block contains a three-channel, eight-bit D/A converter to output analog RGB signals. The block has eight- bit RGB digital video outputs, allowing an external digital video encoder to be connected. The block supports resolutions of up to XGA (1024·768 pixels), enabling flexible setting.
• ••• Set-up Engine The on-chip geometry engine executes mathematical operations required for graphics processing precisely using the fronting-point format. The geometry engine executes the required geometry processes selected depending on the drawing mode and primitive type settings up to the final drawing process.
• ••• 2D/3D Rendering Engine This block draws images in two or three dimensions. 2D drawing The block provides the anti-aliasing and alpha blending functions to display high-quality images even on a low- resolution LCD. 3D drawing The block provides true 3D drawing functions such as perspective texture mapping and Gouraud shading.

nnnn ABSOLUTE MAXIMUM RATINGS * : The PLL power supply is included. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS * : The PLL power supply is included. Notes : • The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds.

• Do not input the HSYNC, VSYNC, or EO signal with the power-supply voltage not applied. (See “Input voltage” in “n ABSOLUTE MAXIMUM RA TINGS”.)
• After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 ms. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage V DDL * - 0.5 3.0 V VDDH - 0.5 4.0 Input voltage V I - 0.5 V DDH + 0.5 ( < 4.0) V Output current I O - 13 + 13 mA Power pin current I POW 60 60 mA Ambient storage temperature Tstg - 55 + 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage VDDL * 2.3 2.5 2.7 V VDDH 3.0 3.3 3.6 Input voltage (“H” level) V IH 2.0 ¾ VDDH + 0.3 V Input voltage (“L” level) V IL - 0.3 ¾+ 0.8 V Ambient operating temperature T A - 40 ¾+ 85 °C

nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics *1 : Value when -100 mA current flows into output pins. *2 : Value when 100 mA current flows into output pins. *3 : Output characteristics of the MD0-63 and MDQM0-7 signal. *4 : Output characteristics of the signals other than those in *3 and *5 *5 : MCLKO signal output characteristics Paramater Symbol Value Unit Min Typ Max Output voltage (“H” level) * 1 VOH VDDH - 0.2 ¾ VDDH V Output voltage (“L” level) *2 VOL 0.0 ¾ 0.2 V Output current (“H” level) IOH 1*3 - 2.0 ¾¾ mAIOH 2*4 - 4.0 IOH 3*5 - 8.0 Output current (“L” level) IOL 1*3 2.0 ¾¾ mAIOL 2*4 4.0 IOL 3*5 8.0 Input leakage current I L ¾¾ – 5 mA Pin capacitance C ¾¾ 16 pF

1. AC Characteristics (VIH = 2.0 V, VIL = 0.8 V) (VIH + VIL) / 2 tr 80% 20% 80% 20% VIH VIL tf VIH VOH VOL VOL VOH VIL 0.5 V 0.5 V (VIH + VIL) / 2 tpHL , tpZL tpLH , tpZH tpLZ tpHZ VDD /2 VDD /2

• Input measurement conditions
• Output measurement conditions
• tr, tf £ 5 ns
• Input measurement standard : (VIH + VIL) / 2 Input Input Output 1 Output 2 Output 3
• Output measurement standard : tpLZ : VOL + 0.5 V tpHZ : VOH - 0.5 V Else : VDD /2

(1) Host Interface

• Clock
• Host interface signals (Operating condition : External load of 20 pF) * : Hold time for reset cancellation Parameter Symbol Condition Value Unit Min Typ Max BCLKI frequency f BCLKI ¾¾ ¾ 100 MHz BCLKI H period t HBCLKI ¾ 1 ¾¾ ns BCLKI L period t LBCLKI ¾ 1 ¾¾ ns Parameter Symbol Condition Value Unit Min Typ Max Address setup time t ADS ¾ 3.0 ¾¾ ns Address hold time t ADH ¾ 1.0 ¾¾ ns BS setup time t BSS ¾ 3.5 ¾¾ ns BS hold time t BSH ¾ 0.0 ¾¾ ns CS setup time t CSS ¾ 3.5 ¾¾ ns CS hold time t CSH ¾ 0.0 ¾¾ ns RD setup time t RDS ¾ 3.0 ¾¾ ns RD hold time t RDH ¾ 0.0 ¾¾ ns WE setup time t WES ¾ 5.5 ¾¾ ns WE hold time t WEH ¾ 0.0 ¾¾ ns Write data setup time t WDS ¾ 3.5 ¾¾ ns Write data hold time t WDH ¾ 0.0 ¾¾ ns DTACK setup time t DAKS ¾ 3.5 ¾¾ ns DTACK hold time t DAKH ¾ 0.0 ¾¾ ns DRACK setup time t DRKS ¾ 4.0 ¾¾ ns DRACK hold time t DRKH ¾ 0.0 ¾¾ ns Read data delay time (to RD) t RDDZ ¾ 2.5 ¾ 8.5 ns Read data delay time t RDD ¾ 4.0 ¾ 10.5 ns RDY delay time (to CS) t RDYDZ ¾ 2.0 ¾ 6.0 ns RDY delay time t RDYD ¾ 2.5 ¾ 6.5 ns INT delay time t INTD ¾ 2.5 ¾ 7.0 ns DREQ delay time t DRQD ¾ 2.5 ¾ 6.5 ns MODE hold time t MODH * ¾¾ 20.0 ns

• Clock
• Input setup and hold times
• Read/write enable (RD, WE) setup and hold times BCLKI 1/fBCLKI tHBCLKI tLBCLKI BCLKI A2~A24, BS, CS, D0~D31, DTACK, DRACK tADS , tBSS , tCSS , tWDS , tDAKS , tDRKS tADH , tBSH , tCSH , tWDH , tDAKH , tDRKH BCLKI BS RD, WE, A24 (MWR) tRDS , tWES tRDH, tWEH CS

• DREQ/INT output delay time
• RDY delay value (with respect to CS) BCLKI DREQ (output) INT (output) tDRQD , tINTD BCLKI CS RDY (output) High-Z High-Z tRDYDZ tRDYDZ

• RDY , D output delay values (The D pin outputs effective data from the RDY assert cycle.)
• MODE signal hold time BCLKI RD (CS) RDY tRDDZtRDD tRDDZ tRDYD tRDYD D0~D31 (output) High-Z High-Z output data RESET MODE0~ MODE2 tMODH

(2) Video Interface

• Clock
• Input signals *1 : Applied only in PLL synchronization mode (CKS = 0) . The reference clock is the internal PLL ’s output with Cycle = 1/ (14 fCLK ) . *2 : Applied only in DCLKI synchronization mode (CKS = 1) . The reference clock is DCLKI.
• Output signals Parameter Symbol Condition Value Unit Min Typ Max CLK frequency f CLK ¾¾ 14.318 ¾ MHz CLK H period t HCLK ¾ 25 ¾¾ ns CLK L period t LCLK ¾ 25 ¾¾ ns DCLKI frequency f DCLKI ¾¾ ¾ 67 MHz DCLKI H period t HDCLKI ¾ 5 ¾¾ ns DCLKI L period t LDCLKI ¾ 5 ¾¾ ns DCLKO frequency f DCLKO ¾¾ ¾ 67 MHz Parameter Symbol Condition Value Unit Min Typ Max HSYNC input pulse width tWHSYNC0 *1 3 ¾¾ clock tWHSYNC1 *2 3 ¾¾ clock HSYNC input setup time t SHSYNC *2 10 ¾¾ ns HSYNC input hold time t HHSYNC *2 10 ¾¾ ns VSYNC input pulse width t WHSYNC1 ¾ 1 ¾¾ HSYNC cycle Parameter Symbol Condition Value Unit Min Typ Max RGB output delay time t RGB ¾ 2 ¾ 10 ns DISPE output delay time t DEO ¾ 2 ¾ 10 ns HSYNC output delay time t DHSYNC ¾ 2 ¾ 10 ns VSYNC output delay time t DVSYNC ¾ 2 ¾ 10 ns CSYNC output delay time t DCSYNC ¾ 2 ¾ 10 ns GV output delay time t DGV ¾ 2 ¾ 10 ns

• Clock
• HSYNC signal setup and hold
• Output signal delay CLK 1/fCLK tHCLK VIH VIL tLCLK DCLKI HSYNC (input) 1/fDCLKI tHDCLKI tLDCLKI tSHSYNC tHHSYNC DCLKO R7-R3, G7-G3, B7-B3, MD63-MD55*, HSYNC (output), VSYNC (output), CSYNC, GV tRGB , tDEO , tDHSYNC , tDVSYNC , tDCSYNC , tDGV*: Valid if RGBEN = 0

(3) Graphics Memory Interface

• Clock * : In BUS asynchronous mode, the frequency is half the internal PLL oscillation frequency. In Bus synchronous mode, the frequency is the same as BCLKI.
• Input/output signals *1 : Setup/hold time with respect to MCLKO *2 : Setup/hold time with respect to MCLKI Parameter Symbol Condition Value Unit Min Typ Max MCLKO frequency f MCLKO ¾¾ ¾ *M H z MCLKO H period t HMCLKO ¾ 1.0 ¾¾ ns MCLKO L period t LMCLKO ¾ 1.0 ¾¾ ns MCLKI frequency f MCLKI ¾¾ ¾ *M H z MCLKI H period t HMCLKI ¾ 1.0 ¾¾ ns MCLKI L period t LMCLKI ¾ 1.0 ¾¾ ns MCLKI delay to MCLKO t OID ¾ 0.0 ¾ 3.5 ns Parameter Symbol Condition Value Unit Min Typ Max MA, MRAS, MCAS, MWE setup time t MADS *1 3.2 ¾¾ ns MA, MRAS, MCAS, MWE hold time t MADH *1 1.3 ¾¾ ns MDQM data setup time t MDQMDS *1 3.2 ¾¾ ns MDQM data hold time t MDQMDH *1 1.3 ¾¾ ns MD output data setup time t MDODS *1 3.2 ¾¾ ns MD output data hold time t MDODH *1 1.3 ¾¾ ns MD input data setup time t MDIDS *2 3.0 ¾¾ ns MD input data hold time t MDIDH *2 1.0 ¾¾ ns

• Clock
• Input signal setup and hold times
• MCLKI signal delay
• Output signal delay MCLKO, MCLKI 1/fMCLKO , 1/fMCLKI tHMCLKO , tHMCLKI tLMCLKO , tLMCLKI MCLKO MD0~MD63 tMDIDS tMDIDH Input data MCLKO MCLKI tOID MCLKO MA0~MA13, MRAS, MCAS, MWE, MD0~MD63, MDQM0~MDQM7 tMADS , tMDODS , tMDQMDS tMADH , tMDODH , tMDQMDH

(4) PLL Standards Parameter Value Remarks Min Typ Max Input frequency ¾ 14.31818 MHz ¾ Output frequency ¾¾ 200.45452 MHz Multiplied by 14 Duty ratio 101.3 %¾ 93.1 % PLL output clock H/L pulse width ratio Jitter 180 ps ¾- 150 ps Cycle difference between two consecutive cycles

Part Number Package Remarks MB86292PFFS-G-BND 256-pin plastic QFP (FPT-256P-M09)

(FPT-256P-M09) *Pins width and pins thickness include plating thickness. Dimensions in mm (inches) C 2000 FUJITSU LIMITED F256025S-c-2-2 Details of "A" part (Stand off) (.147±.012) 3.73±0.30 0.40 +0.10 –0.15 +.004 –.006 .016 0.18±0.05 (.007±.002) M0.07(.003) 0.40(.016) 208 157 156 105 104 64LEAD No. 1 INDEX 0.145±0.055 (.006±.002) 0.08(.003) "A" 0°~8° (0.50(.020)) 0.60±0.15 (.024±.006) 0.25(.010) (Mounting height)

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