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November, 2010 1/2 Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved NP501-00004-0v01-E FRAM MB85R256G MB85R256G is a 256K-bits FRAM LSI using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. MB85R256G uses a pseudo-SRAM interface compatible with conventional asynchronous SRAM. ■FEATURES Bit configuration ： 32,768 words × 8 bits Read/write endurance ：1010 times/bit Peripheral circuit CMOS construction Operating power supply voltage ：2.7 to 3.6V Operating temperature range ：-40℃ to +85℃ Data retention ：10 years (+70℃) Package ：28-pins, SOP flat package ：28-pins, TSOP(1) flat package ■ORDERING INFORMATION ■PACKAGE EXAMPLE OF REFERENCE Product name Package Remarks TBD Plastic・SOP,28-pins (FPT-28P-M17) 8.60mm×17.75mm,1.27mm pitch TBD Plastic・TSOP,28-pins (FPT-28P-M19) 11.80mm×8.00mm,0.55mm pitch TBD Plastic・SOP,28-pins (FPT-28P-M17) 8.60mm×17.75mm,1.27mm pitch Embossed Carrier tape Plastic ・ TSOP、28-pins (FPT-28P-M19)
N o v e m b e r , 2 0 1 0 2 / 2 Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved ■PIN ASSIGNMENT ■BLOCK DIAGRAM （TOP VIEW） A A12 I/O0 I/O1 I/O2 GND VCC WE A13 A11 OE A10 CE I/O I/O6 I/O5 I/O4 I/O3 1222 A14 A12 A3 A2 I/O0 I/O1 I/O2 GND VCC A13 A11 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 WE OE FPT-28P-M17 FPT-28P-M19 A14 to A10 A7 to A0 A8, A9 CE WE OE I/O0-I/O7 A14 to A0 Row decoder Address latch FRAM array: 32,768 × 8 Block decoder Column decoder Control logic I/O latch bus driver Pseudo-SRAM interface logic circuit I/O7 to I/O0 Pin No. Pin name Description 1 to 10, 21, 23 to 26 A 0 to A14 Address input 11 to 13, 15 to 19 I/O 0 to I/O7 Data input/output
20 CE Chip enable input
27 WE Write enable input
22 OE Output enable input
28 V CC Power supply (＋3.3V Typ.)