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Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.7 Memory FRAM
1 M Bit (64 K × 16)
■ DESCRIPTIONS The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words × 16 bits of nonvolatile memory cells fabricated usi ng ferroelectric process and silicon gate CMOS process technologies. The MB85R1002A is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002A can be used for 10 10 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R1002A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES
- Bit configuration : 65,536 words × 16 bits Read/write endurance : 10 10 times Operating power supply voltage : 3.0 V to 3.6 V Operating temperature range : − 40 °C to + 85 °C Data retention : 10 years ( + 55 °C) L B and UB data byte control Package : 48-pin plastic TSOP (1) DS501-00004-1v0-E
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■ PIN ASSIGNMENTS ■ PIN DESCRIPTIONS Pin Number Pin Name Functional Description 1 to 8, 18 to 25 A0 to A15 Address Input pins 29 to 36, 38 to 45 I/O1 to I/O16 Data Input/Output pins
26 CE 1 Chip Enable 1 Input pin
12 CE2 Chip Enable 2 Input pin
11 WE Write Enable Input pin
28 OE Output Enable Input pin
14, 15 LB , UB Data Byte Control Input pins 16, 37 VDD Supply Voltage pins Connect all two pins to the power supply. 13, 27, 46 VSS Ground pins Connect all three pins to ground. 9, 10, 17, 47, 48 NC No Connect pins A15 A14 A13 A12 A11 A10 NC NC WE CE2 VSS UB LB VDD NC NC NC VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VDD I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE VSS CE1 (FPT-48P-M48) (TOP VIEW)
■ BLOCK DIAGRAM I/O8 I/O1 I/O16 I/O9 A15 CE2 WE OE CE1 LB UB intOE intWE I/O1 to I/O8 I/O9 to I/O16 Address Latch Row Decoder FRAM Array 65,536 × 16 Column Decoder S/A
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■ FUNCTIONAL TRUTH TABLE Note: L = V IL, H = VIH, X can be either VIL or VIH, Hi-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. Mode CE 1C E 2 W E OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current Standby Precharge HXXXXX Hi-Z Hi-Z Standby (ISB) XLXXXX XXHHXX XXXXHH Read HHL L L Data Output Data Output Operation (ICC) L H Data Output Hi-Z H L Hi-Z Data Output LH L L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output Read (Pseudo-SRAM, OE control*1) LHH L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output Write HLH L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input LL H L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input Write (Pseudo-SRAM, WE control*2) LH H L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input
■ ABSOLUTE MAXIMUM RATINGS * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS * : All voltages are referenced to VSS = 0 V. WARNING: The recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power Supply Voltage* V CC −0.5 +4.0 V Input Pin Voltage* V IN −0.5 V CC + 0.5 ( ≤ 4.0) V Output Pin Voltage* V OUT −0.5 V CC + 0.5 ( ≤ 4.0) V Operating Temperature T A −40 +85 oC Storage Temperature T STG −40 +125 oC Parameter Symbol Value Unit Min Typ Max Power Supply Voltage* V CC 3.0 3.3 3.6 V High Level Input Voltage* V IH VCC × 0.8 ⎯ VCC + 0.5 ( ≤ 4.0) V Low Level Input Voltage* V IL −0.5 ⎯+ 0.6 V Operating Temperature T A − 40 ⎯+ 85 oC
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■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. Iout : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V. Parameter Symbol Condition Value Unit Min Typ Max Input Leakage Current |I LI|V IN = 0 V to VCC ⎯⎯ 10 μA Output Leakage Current |I LO| VOUT = 0 V to VCC, CE1 = VIH or OE = VIH ⎯⎯ 10 μA Operating Power Supply Current ICC CE1 = 0.2 V, CE2 = VCC − 0.2 V, Iout = 0 mA*1 ⎯ 10 15 mA Standby Current I SB CE1 ≥ VCC − 0.2 V ⎯ 10 50 μA CE2 ≤ 0.2 V*2 OE ≥ VCC − 0.2 V, WE ≥ VCC − 0.2 V*2 LB ≥ VCC − 0.2 V, UB ≥ VCC − 0.2 V*2 High Level Output Voltage V OH IOH = − 1.0 mA V CC × 0.8 ⎯⎯ V Low Level Output Voltage V OL IOL = 2.0 mA ⎯⎯ 0.4 V
- AC Characteristics
- AC Test Conditions Supply Voltage : 3.0 V to 3.6 V Operating Temperature : −40 oC to +85 oC Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 5 ns Input Falling Time : 5 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Impedance : 50 pF (1) Read Cycle (within recommended operating conditions) Parameter Symbol Value Unit Min Max Read Cycle time t RC 150 ⎯ ns CE1 Active Time t CA1 120 ⎯ ns CE2 Active Time t CA2 120 ⎯ ns OE Active Time t RP 120 ⎯ ns LB, UB Active Time t BP 120 ⎯ ns Precharge Time t PC 20 ⎯ ns Address Setup Time t AS 0 ⎯ ns Address Hold Time t AH 50 ⎯ ns OE Setup Time t ES 0 ⎯ ns LB, UB Setup Time t BS 5 ⎯ ns Output Data Hold time t OH 0 ⎯ ns Output Set Time t LZ 30 ⎯ ns CE1 Access Time t CE1 ⎯ 100 ns CE2 Access Time t CE2 ⎯ 100 ns OE Access Time t OE ⎯ 100 ns Output Floating Time t OHZ ⎯ 20 ns
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(2) Write Cycle (within recommended operating conditions) 3. Pin Capacitance Parameter Symbol Value Unit Min Max Write Cycle Time t WC 150 ⎯ ns CE1 Active Time t CA1 120 ⎯ ns CE2 Active Time t CA2 120 ⎯ ns LB, UB Active Time t BP 120 ⎯ ns Precharge Time t PC 20 ⎯ ns Address Setup Time t AS 0 ⎯ ns Address Hold Time t AH 50 ⎯ ns LB, UB Setup Time t BS 5 ⎯ ns Write Pulse Width t WP 120 ⎯ ns Data Setup Time t DS 0 ⎯ ns Data Hold Time t DH 50 ⎯ ns Write Setup Time t WS 0 ⎯ ns Parameter Symbol Condition Value Unit Min Typ Max Input Capacitance C IN VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 oC ⎯⎯ 10 pF Output Capacitance C OUT ⎯⎯ 10 pF
■ TIMING DIAGRAMS 1. Read Cycle Timing (CE 1, CE2 Control) 2. Read Cycle Timing (OE Control) CE1 A0 to A15 OE I/O1 to I/O16 CE2 tRC tCA1 tPC tCA2 tAS tAH tES Valid tRP tOHZ Hi-Z LB, UB tBPtBS Valid H or L tOH tLZ Invalid In valid tCE1, tCE2 CE1 A0 to A15 OE I/O1 to I/O16 CE2 tCA1 tCA2 tAS tAH tRC tOE tOHZ Hi-Z LB, UB tBPtBS Valid tOHtLZ Valid H or L tRP Invalid In valid tPC
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- Write Cycle Timing (CE1, CE2 Control) 4. Write Cycle Timing (WE Control) CE1 A0 to A15 WE Data In CE2 tCA1 tCA2 tWP tDH Hi-Z LB, UB tAHtAS tDS Valid H or L Valid H or L tBPtBS tWC tPC tWS CE1 A0 to A15 CE2 tCA1 tCA2 tWP tWC tDH Hi-Z LB, UB tAHtAS tDS Valid H or L Valid H or L tPC tBPtBS WE Data In
■ POWER ON/OFF SEQUENCE (within recommended operating conditions) ■ NOTES ON USE After the IR reflow completed, it is not guaranteed to hold the data written prior to the IR reflow. Parameter Symbol Value Unit Min Typ Max CE1 LEVEL hold time for Power OFF t PD 85 ⎯⎯ ns CE1 LEVEL hold time for Power ON t PU 85 ⎯⎯ ns Power supply rising time t R 0.05 ⎯ 200 ms CE1 > VCC × 0.8* CE1 : Don't Care CE1 > V CC × 0.8* tPUtRtPD VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) 0 V CE1 CE1 VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) 0 V * : CE1 (Max) < VCC + 0.5 V Notes: Use either of CE 1 or CE2, or both for disable control of the device. Because turning the power on from an intermediate level may cause malfunctions, when the power is turned on, VCC is required to be started from 0 V. If the device does not operate within the specified conditions of read cycle, write cycle, power on/off sequence, memory data can not be guaranteed. When turning the power on or off, it is recommended that CE2 is connected to ground to prevent unexpected writing. CE2 ≤ 0.2 V
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■ ORDERING INFOMATION Part number Package MB85R1002ANC-GE1 48-pin plastic TSOP(1) (FPT-48P-M48)
■ PACKAGE DIMENSIONS Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 48-pin plastic TSOP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.40 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.36 g 48-pin plastic TSOP (FPT -48P-M48) (FPT-48P-M48) C 2010 FUJITSU SEMICONDUCTOR LIMITED F48048Sc-1-1 #12.00±0.10 (.472±.004) 0.08(.003) 0.50(.020) 0.22 (.009 ) 2524 A0.145 (.006 ) M0.10(.004) Details of A part 0~8 (.024±.006) 0.60±0.15 INDEX (STAND OFF) +0.05 –0.03 +.002 –.001 +.002 –.002 +0.05 –0.04 (MOUNTING HEIGHT) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) # : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) * : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
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