MB85R1002

MB85R1002_07 FUJITSU | Alldatasheet

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DS05-13104-3EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©2005-2007 FUJITSU LIMITED All rights reserved Memory FRAM CMOS

1 M Bit (64 K × 16)

■ DESCRIPTIONS The MB85R1002 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words x 16 bits of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies. The MB85R1002 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002 can be used for at least 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R1002 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES

• Bit configuration : 65,536 words × 16 bits  Read/write endurance : 10 10 times/bit (Min)  Operating power supply voltage : 3.0 V to 3.6 V  Operating temperature range : − 20 °C to +85 °C  Data retention : 10 years ( +55 °C) L B and UB data byte control  Package : 48-pin plastic TSOP (1) : 48-pin plastic FBGA

■ PIN ASSIGNMENT (Continued) A15 A14 A13 A12 A11 A10 NC NC WE CE2 GND UB LB V CC NC NC NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 V CC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE GND CE1 (FPT-48P-M25) (TOP VIEW)

(Continued) ■ PIN DESCRIPTION Pin name Function A0 to A15 Address In I/O1 to I/O16 Data Input/Output CE1 Chip Enable 1 in CE2 Chip Enable 2 in WE Write Enable in OE Output Enable in LB, UB Data Byte Control in VCC Power Supply GND Ground NC No Connection (BGA-48P-M23) 12 3456 654321 AL B OE A0 A1 A2 CE2 A CE2 A2 A1 A0 OE LB BI / O 9 U B A3 A4 CE1 I/O1 B I/O1 CE1 A4 A3 UB I/O9 C I/O10 I/O11 A5 A6 I/O2 I/O3 C I/O3 I/O2 A6 A5 I/O11 I/O10 D GND I/O12 NC A7 I/O4 V CC DV CC I/O4 A7 NC I/O12 GND EV CC I/O13 NC NC I/O5 GND E GND I/O5 NC NC I/O13 V CC F I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O7 I/O6 A15 A14 I/O14 I/O15 G I/O16 NC A12 A13 WE I/O8 G I/O8 WE A13 A12 NC I/O16 H NC A8 A9 A10 A11 NC H NC A11 A10 A9 A8 NC Top View Bottom View INDEX A B C D E F G H 654 3 2112 3 456

■ BLOCK DIAGRAM A15 to Address Latch. Row Dec. Ferro Capacitor Cell Column Dec. S/A I/O1 to I/O8 intCEB intCE2 intWE intOE intCE2 intCEB CE2 intCE2 I/O16 I/O9 to· UB CE1 I/O9 to I/O16 I/O8 I/O1 to· WE LB OE

■ FUNCTION TRUTH TABLE Notes : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. Mode CE 1C E 2 W E OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current Standby Pre-charge HXXXXX High-Z High-Z Standby (ISB) XLXXXX XXHHXX XXXXHH Read L H HL L L Dout Dout Operation (ICC) L H Dout High-Z H L High-Z Dout Read (Pseudo-SRAM, OE control*1) LHH L L Dout Dout L H Dout High-Z H L High-Z Dout Write L H LX LL D i n D i n L H Din High-Z HL H i g h - Z D i n Write (Pseudo-SRAM, WE control*2) LH H LL D i n D i n L H Din High-Z HL H i g h - Z D i n

■ ABSOLUTE MAXIMUM RATINGS * : All voltages are referenced to GND. WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS * : All voltages are referenced to GND. WARNING: The recommended operating condi tions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Supply Voltage* V CC −0.5 +4.0 V Input Voltage* V IN −0.5 V CC + 0.5 V Output Voltage* V OUT −0.5 V CC + 0.5 V Ambient Operating Temperature T A −20 +85 oC Storage Temperature T stg −40 +125 oC Parameter Symbol Value Unit Min Typ Max Supply Voltage* V CC 3.0 3.3 3.6 V Input Voltage (high)* V IH VCC × 0.8 ⎯ VCC + 0.5 V Input Voltage (low)* V IL −0.5 ⎯+ 0.6 V Ambient Operating Temperature T A − 20 ⎯+ 85 oC

■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS (within recommended operating conditions) *1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. Iout : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V. Parameter Symbol Test Conditions Value Unit Min Typ Max Input Leakage Current |I LI|V IN = 0 V to VCC ⎯⎯ 10 µA Output Leakage Current |I LO|V OUT = 0 V to VCC, CE1 = VIH or OE = VIH ⎯⎯ 10 µA Operating Power Supply Current ICC CE1 = 0.2 V, CE2 = VCC−0.2 V, Iout = 0 mA*1 ⎯ 10 15 mA Standby Current I SB CE1 ≥ VCC−0.2 V ⎯ 10 50 µA CE2 ≤ 0.2 V*2 OE ≥ VCC−0.2 V, WE ≥ VCC−0.2 V*2 LB ≥ VCC−0.2 V, UB ≥ VCC−0.2 V*2 Output Voltage (high) V OH IOH = −0.1 mA V CC × 0.8 ⎯⎯ V Output Voltage (low) V OL IOL = 2.0 mA ⎯⎯ 0.4 V

1. AC TEST CONDITIONS Supply Voltage : 3.0 V to 3.6 V Operating Temperature : −20 oC to +85 oC Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 5 ns Input Falling Time : 5 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Impedance : 50 pF (1) Read Operation (within recommended operating conditions) Parameter Symbol Value Unit Min Max Read Cycle time t RC 150 ⎯ ns CE1 Active Time t CA1 120 ⎯ ns CE2 Active Time t CA2 120 ⎯ ns OE Active Time t RP 120 ⎯ ns LB, UB Active Time t BP 120 ⎯ ns Pre-charge Time t PC 20 ⎯ ns Address Setup Time t AS 0 ⎯ ns Address Hold Time t AH 50 ⎯ ns OE Setup Time t ES 0 ⎯ ns LB, UB Setup Time t BS 5 ⎯ ns Output Data Hold time t OH 0 ⎯ ns Output Set Time t LZ 30 ⎯ ns CE1 Access Time t CE1 ⎯ 100 ns CE2 Access Time t CE2 ⎯ 100 ns OE Access Time t OE ⎯ 100 ns Output Floating Time t OHZ ⎯ 20 ns

(2) Write Operation (within recommended operating conditions) (3) Power ON/OFF Sequence (within recommended operating conditions) 3. Pin Capacitance (f = 1 MHz, TA = +25 oC) Parameter Symbol Value Unit Min Max Write Cycle Time t WC 150 ⎯ ns CE1 Active Time t CA1 120 ⎯ ns CE2 Active Time t CA2 120 ⎯ ns LB, UB Active Time t BP 120 ⎯ ns Pre-Charge Time t PC 20 ⎯ ns Address Setup Time t AS 0 ⎯ ns Address Hold Time t AH 50 ⎯ ns LB, UB Setup Time t BS 5 ⎯ ns Write Pulse Width t WP 120 ⎯ ns Data Setup Time t DS 0 ⎯ ns Data Hold Time t DH 50 ⎯ ns Write Setup Time t WS 0 ⎯ ns Parameter Sym- bol Value Unit Min Typ Max CE1 LEVEL hold time for Power OFF t pd 85 ⎯⎯ ns CE1 LEVEL hold time for Power ON t pu 85 ⎯⎯ ns Parameter Symbol Test Condition Value Unit Min Typ Max Input Capacitance C IN VIN = GND ⎯⎯ 10 pF Output Capacitance C OUT VOUT = GND ⎯⎯ 10 pF

■ TIMING DIAGRAMS 1. Read Cycle Timing 1 (CE 1, CE2 Control) 2. Read Cycle Timing 2 (OE Control) CE1 A0 to A15 OE I/O1 to I/O16 CE2 tRC tCA1 tPC tCA2 tAS tAH tES Valid tRP tOHZ High-Z LB, UB tBPtBS Valid H or L tOH tLZ Invalid Inv alid tCE1, tCE2 CE1 A0 to A15 OE I/O1 to I/O16 CE2 tCA1 tCA2 tAS tAH tRC tOE tOHZ High-Z LB, UB tBPtBS Valid tOHtLZ Valid H or L tRP Invalid Inv alid tPC

1. Write Cycle Timing 1 (CE1, CE2 Control) 4. Write Cycle Timing 2 (WE Control) CE1 A0 to A15 WE Data In CE2 tCA1 tCA2 tWP tDH High-Z LB, UB tAHtAS tDS Valid H or L Valid H or L tBPtBS tWC tPC tWS CE1 A0 to A15 CE2 tCA1 tCA2 tWP tWC tDH High-Z LB, UB tAHtAS tDS Valid H or L Valid H or L tPC tBPtBS WE Data In

■ POWER ON/OFF SEQUENCE ■ NOTES ON USE Data that is written prior to IR reflow is not guaranteed to be retained after IR reflow. ■ ORDERING INFOMATION Part number Package MB85R1002PFTN-GE1 48-pin plastic TSOP(1) (FPT-48P-M25) MB85R1002BGT-GE1 48-pin plastic FBGA (BGA-48P-M23) CE1 > VCC × 0.8* CE1 : Don't Care CE1 > V CC × 0.8* tputpd VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) GND CE1 CE1 VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) GND * : CE1 (Max) < VCC + 0.5 V Note : You can choose either of CE1 or CE2, or both for disenable control of the device. CE2 ≤ 0.2 V

■ PACKAGE DIMENSIONS Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 48-pin plastic TSOP(1) Le ad pitch 0.50 mm Package width × package length 12.00 × 12.40 mm Lead shape G ullwing Sealing method Pl astic mold Mounting height 1.20 mm MAX Weight 0. 37 g Code (Reference) P-TSOP(1)48-12×12.4-0.50 48-pin plastic TSOP(1) (FPT -48P-M25) (FPT-48P-M25) C 2003 FUJITSU LIMITED F48043S-c-2-2 1 48 LEAD No. 0.08(.003) .006 –.001 +.002 –0.03 +0.05 0.145 "A" INDEX 12.00±0.10 (.472±.004) 1.13±0.07 0.10±0.05 0.50(.020) .009 –.002 +.002 –0.04 +0.05 0.22 M0.10(.004) (.024±.006) 0˚~8˚ Details of "A" part (.044±.003) (Mounting height) (Stand off)(.004±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusions. Note 3) Pin widths and pin thicknesses include plating thickness. Note 4) Pin widths do not include tie bar cutting burrs.

(Continued) Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 48-pin plastic FBGA Le ad pitch 0.75 mm Package width × package length 8.10 mm × 6.10 mm Lead shape B all Sealing method Pl astic mold Mounting height 1.10 mm M ax Weight 0.0 8 g 48-pin plastic FBGA (BGA-48P-M23) (BGA-48P-M23) C 2007 FUJITSU LIMITED B48023S-c-1-1 (Stand off) (Mounting height) 6.10±0.20 (.240±.008) 0.10(.004) HGFED CBA (INDEX AREA) 48-ø0.35±0.05 .043 –.004 +.006 –0.10 +0.15 0.95 0.75(.030)TYP 5.25(.207) (.148) A B 3.75 S Dimensions in mm (inches). Note: The values in parentheses are reference values.

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