MB85R1001 FUJITSU | Alldatasheet

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DS05-13103-2EFUJITSU SEMICONDUCTOR DATA SHEET Memory FRAM CMOS

1 M Bit (128 K × 8)

■ DESCRIPTIONS The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072 words x 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, MB85R1001 is able to retain data without back-up battery. The memory cells used for the MB85R1001 has improved at least 10 10 times of read/write access, significantly outperforming FLASH memory and E2PROM in endurance. The MB85R1001 used a pseudo - SRAM interface compatible with conventional asynchronous SRAM. ■ FEATURES

  • Bit configuration : 131,072 words x 8bits  Read/write endurance : 10 10 times  Operating power supply voltage : 3.0 V to 3.6 V  Operating temperature range : -20 °C to +85 °C  48-pin, TSOP (1) plastic package ■ PACKAGE 48-pin plastic TSOP(1) (FPT-48P-M25)

■ PIN ASSIGNMENTS ■ PIN DESCRIPTIONS Pin name Function A0 to A16 Address In I/O1 to I/O8 Data Input/Output CE1 Chip Enable 1 in CE2 Chip Enable 2 in WE Write Enable in OE Output Enable in VCC Power Supply GND Ground A11 N.C. A13 WE CE2 A15 N.C. VCC N.C. N.C. GND N.C. N.C. VCC N.C. A16 A14 A12 OE N.C. GND A10 CE1 N.C. I/O8 I/O7 I/O6 I/O5 I/O4 VCC N.C. I/O3 I/O2 I/O1 N.C. N.C. N.C. GND (FPT-48P-M25) (TOP VIEW)

■ BLOCK DIAGRAM ■ FUNCTION TRUTH TABLE L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address at falling edge, : Latch address at rising edge Operation Mode CE 1C E 2 W E OE I/O1 to I/O8 Supply Current Standby Pre-charge HXXX High-Z Standby (ISB)XLXX XXHH Read L H HL Dout Operation (ICC) Read (Pseudo SRAM, OE control) LHH Write L H LH Din Write (Pseudo SRAM, WE control) LH H Output Disable L H H H High-Z A16 to Address Latch. Row Dec. F erro Capacitor Cell Column Dec. S/A I/O1 to I/O8 I/O8 I/O1 tointCEB intCE2 intWE intOE intCE2 intCEB CE2 intCE2 WE OE CE1

■ ABSOLUTE MAXIMUM RATINGS WARNING: Semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS (VCC = 3.0 V to 3.6 V, TA = −20 °C to +85 °C) WARNING: The recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Supply Voltage V CC −0.5 +4.0 V Input Voltage V IN −0.5 V CC+0.5 V Output Voltage V OUT −0.5 V CC+0.5 V Ambient Temperature T A −20 +85 °C Storage Temperature Tstg −40 +125 °C Parameter Symbol Value Unit Min Typ Max Supply Voltage V CC 3.0 3.3 3.6 V Input Voltage (high) V IH VCC x 0.8 ⎯ VCC + 0.5 V Input Voltage (low) V IL −0.5 ⎯ 0.8 V Operating Temperature T A −20 ⎯+ 85 °C

■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −20 °C to +85 °C) *1 : Iout : Output current Parameter Symbol Test Condition Value Unit Min Typ Max Input Leakage Current |ILI| VIN = 0 V to VCC ⎯⎯ 10 µA Output Leakage Current |ILO| VOUT = 0 V to VCC, CE1 = VIH or OE = VIH ⎯⎯ 10 µA Supply Current I CC CE1 = 0.2 V, CE2 = VCC−0.2 V, Iout = 0 mA*1 ⎯⎯ 10 mA Standby Current I SB CE1 ≥ VCC−0.2 V ⎯ 10 100 µACE2 ≤ 0.2 V*2 OE ≥ VCC−0.2 V, WE ≥ VCC−0.2 V*2 Output Voltage (high) V OH IOH = −2.0 mA 0.8 x V CC ⎯⎯ V Output Voltage (low) V OL IOL = 2.0 mA ⎯⎯ 0.4 V

  1. AC CHARACTERISTICS
  • AC TEST CONDITIONS Supply Voltage : 3.0 V to 3.6 V Operating Temperature : −20 °C to +85 °C Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 10 ns Input Falling Time : 10 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Impedance : 50 pF (1) Read Operation CC = 3.0 V to 3.6 V, TA = −20 °C to +85 °C) (2) Write Operation (VCC = 3.0 V to 3.6 V, TA = −20 °C to +85 °C) Parameter Symbol Value UnitMin Max Read Cycle Time t RC 250 ⎯ ns CE1 Active Time t CA1 210 2,000 ns OE Active Time t RP 210 2,000 ns Pre-charge Time t PC 40 ⎯ ns Address Setup Time t AS 10 ⎯ ns Address Hold Time t AH 50 ⎯ ns OE Setup Time t ES 10 ⎯ ns CE1 Access Time t CE1 ⎯ 100 ns CE2 Access Time t CE2 ⎯ 100 ns OE Access Time t OE ⎯ 100 ns OE Output Floating Time t OHZ ⎯ 25 ns Parameter Symbol Value Unit Min Max Write Cycle Time t WC 250 ⎯ ns CE1 Active Time t CA1 210 2,000 ns CE2 Active Time t CA2 210 2,000 ns Pre-charge Time t PC 40 ⎯ ns Address Setup Time t AS 10 ⎯ ns Address Hold Time t AH 50 ⎯ ns Write Pulse Width t WP 210 ⎯ ns Data Setup Time t DS 10 ⎯ ns Data Hold Time t DH 50 ⎯ ns Write Setup Time t WS 0 ⎯ ns

(3) Power ON/OFF Sequence * : Condition for power detection circuit to function 3. Pin Capacitance (f = 1 MHz, TA = +25 °C) 4. Reliability Data retention 10 years (TA = 0 °C to +55 °C) Access endurance 1010 times (TA = −20 °C to +85 °C) Parameter Sym- bol Value Units Min Typ Max CE1 LEVEL holding time in Power OFF t pd 85 ⎯⎯ ns CE1 LEVEL holding time in Power ON t pu 85 ⎯⎯ ns Power interval * t pi 0.5 ⎯⎯ s Parameter Symbol Test Condition Value Unit Min Typ Max Input Capacitance C IN VIN = GND ⎯⎯ 10 pF Output Capacitance C OUT VOUT = GND ⎯⎯ 10 pF

■ TIMING DIAGRAMS 1. Read Cycle Timing C E 1, CE2 Control O E Control CE1 A0 to A16 OE I/O1 to I/O8 CE2 tRC tCA1 tCE1 tPC tCE2 tAS tAH tES Valid tRP tOE tOHZ High-Z Valid CE1 A0 to A16 OE I/O1 to I/O8 CE2 tAHtAS Valid High-Z Valid tCA1 tCA2 tRC tPC tRP tOE tOHZ

  1. Write Cycle Timing C E 1, CE2 Control W E Control tDH CE1 A0 to A16 WE Data In CE2 OE Valid tAHtAS Valid tWS tWP tCA2 tCA1 tWC tPC tDS CE1 A0 to A16 WE Data In CE2 OE tDS Valid tAHtAS Valid tWC tCA1 tCA2 tPC tWP tDH

■ POWER ON/OFF SEQUENCE ■ NOTES ON USE After IR reflow, the hold of data that was written before IR reflow is not guaranteed. ■ ORDERING INFOMATION Part number Package Remarks MB85R1001PFTN 48-pin plastic TSOP(1) (FPT-48P-M25) CE1 > VCC × 0.8* CE1 : Don't Care CE1 > VCC × 0.8* tpi tputpd VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) GND CE1 CE1 VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) GND * : CE1 (Max) < VCC + 0.5 V CE2 ≤ 0.2 V

■ PACKAGE DIMENTION 48-pin plastic TSOP(1) (FPT-48P-M25) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches). Note: The values in parentheses are reference values. C 2003 FUJITSU LIMITED F48043S-c-2-2 1 48 LEAD No. 0.08(.003) .006 –.001 +.002 –0.03 +0.05 0.145 "A" INDEX 12.00±0.10 (.472±.004) 1.13±0.07 0.10±0.05 0.50(.020) .009 –.002 +.002 –0.04 +0.05 0.22 M0.10(.004) (.024±.006) 0˚~8˚ Details of "A" part (.044±.003) (Mounting height) (Stand off)(.004±.002)

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0501 © 2005 FUJITSU LIMITED Printed in Japan