MB8516SR72CA-102 | DigiCamel IC Datasheet

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MB8516SR72CA-102/-103/-102L/-103L 168-pin, 4 Clock, 1-bank, based on 16 M x 4 Bit SDRAMs with SPD @ DESCRIPTION The Fujitsu MB8516SR72CA is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of eighteen MB81F64442C devices which-organized as four banks of 16 M x 4 bits and a 2K-bit serial EEPROM on a 168-pin glass-epoxy substrate. The MB8516SR72CA features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB8516SR72CA is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. This module is ideally suited for server system; workstations, high-end PCs, and other applications where enhanced performance is needed. @ PRODUCT LINE & FEATURES MB8516SR72CA-102/-102L_| MB8516SR72CA-103/-103L 2-2-2 clk min. 3-2-2 clk min. Clock Frequenc’ 100 MHz max. 100 MHz max. Burst Mode Cycle | Registered Time Mode Output Valid from | Registered = | CL=2"| Gms | ns Clock Mode [cL-3[6ns Sid SSS rsd ‘Two Banks Active 13540 mW max. Power Dissipation 495 mW max. (Std. power) Self;Refresh Mode 455 mW max. (Low power Note * : For registered mode, actual CAS Latency is added one cycle to the CAS Latency of device because of a delay by registers. + Registered 168-pin DIMM Socket Type + 4096 Refresh Cycle every 65.6 ms (Lead pitch: 1.27 mm) + Auto and Self Refresh + Conformed to JEDEC Standard + CKE Power Down Mode * Organization: 16,777,216 words x 72 bits + DQM Byte Masking (Read/Write) + Memory: MB81F64442C (16 Mx 4, 4-bank) x 18 pcs + Serial Presence Detect (SPD) with Serial EEPROM: + 3.3 V +0.3 V Supply Voltage Intel SPD spec Rev 1.2A Format + All input/output LVTTL compatible + Module size: * Conformed to Intel PC/100 spec 1.70” (height) x 5.25” (length) x 0.32” (thickness)

MB8516SR72CA-102/-103/-102L/-103L @ PACKAGE 168-pin plastic DIMM (socket type) Under development (MDS-168P-P43) Package and Ordering Information — 168-pin DIMM, order as MB8516SR72CA-xxxDG (DG = Std. power ver., Gold pad) MB8516SR72CA-xxxLDG (LDG = Low power ver., Gold pad)

@ SERIAL-PD INFORMATION Byte Function Described -102/- | -103/- 102L | 103L

0 Defines Number of Bytes Written into Serial Memory at Module 128 Byte 80h 80h

1 Total Number of Bytes of SPD Memory Device 256 Byte 08h 08h

2 Fundamental Memory Type SDRAM 04h 04h

3 Number of Row Addresses 12 0Ch 0Ch

4 Number of Column Addresses 10 OAh OAh

5 Number of Module Banks 1 bank Oth Oth

6 Data Width 72 bit 48h 48h

7 Data Width (Continuation) +0 00h 00h

8 Interface Type LVTTL Oth Oth

9 SDRAM Cycle Time (Highest CAS Latency) 10/10 ns AOh AOh

10 SDRAM Access from Clock (Highest CAS Latency) 6/6 ns 60h 60h

11 DIMM Configuration Type ECC 02h 02h

12 Refresh Rate/ype Self, Normal | 80h 80h

13 Primary SDRAM Width x4 04h 04h

14 Error meexing SDRAM Width x4 04h 04h

15 Minimum Clock Delay for Back to Back Random Column Addresses 1 Cycle Oth Oth

16 Burst Lengths Supported 1,2,4,8, Page| 8Fh 8Fh

17 Number of Banks on Each SDRAM Device 4 bank 04h 04h

18 CAS Latency Supported 2,3 06h 06h

19 CS Latency 0 Oth Oth

20 Write Latenc' 0 Oth Oth

21 SDRAM Module Attributes Registered 1Fh 1Fh

22 SDRAM Device Attributes : General * OEh OEh

23 SDRAM Cycle Time (2nd. {ighest CAS Latency) 10/15 ns AOdh FOh 24 SDRAM Access from Clock (2nd. taighest CAS Latency) 6/8ns 60h 80h 25. |SDRAM Cycle Time (3rd. Highest CAS Latency) No Support | 00h | 00h

26 SDRAM Access from Clock fra, Highest CAS Latency) No Support 00h 00h

27 Minimum Row Precharge Time (tre) 20/20 ns 14h 14h

28 Bow Activate to Row Activate Minimum (tro) 20/20ns 14h 14h

29 RAS to CAS. Delay Min. (taco) 20/20 ns 14h 14h

30 Minimum RAS Pulse Width 50/50 ns 32h 32h

31 Module Bank Density 128 MByte 20h 20h

32 Command and Address Signal Input Setup Time 2ns 20h 20h

33 Command and Address Signal Input Hold Time ins 10h 10h

34 Data Signal Input Setup Time 2ns 20h 20h

35 Data Signal Input Hold Time 1ns 10h 10h

36 to 61 | Unused Storage Locations — 00h | 00h 62 SPD Data Revision Code 1.2 12h 12h

63 Checksum for Byte 0 to 62 *2 3Fh AFh

64 to 71 | Manufacturer's JEDEC ID Code Per JEP-108E Optional 00h 00h

72 Manufacturing Location Optional 00h 00h

126 Intel Specification Frequency 100 MHz 64h 64h

127 | Intel Specification Details for 100 MHz Support CL=2,3/3 | 8Fh 8Dh 128+ _|Unused Storage Locations = = = Note: Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken. *1. Byte 22: SDRAM Device Attributes Bit? | Bité | Bits | Bila | Bits] ita, | Bitty =] BOT Supports Supports Supports Supports _ Tap | Tep | Upper Voo | Lower Vec write 1 Precharge | Auto. Early HAS /Read Burst_| All Precharge _| Precharge Lo fj oof} ot *2. Byte 63: Checksum for Byte 0 to 62 This byte is the checksum for Byte 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of Byte 0 through 62.

SSO Register RSo, RS DQMB» to DAMB’O RDQMBe to RDQMB; SCLO Serial PD SDA BAo, BAO D18,D 19 RBA, RBA: weO Dat Aoto An Ro to RA RASO A Y RAS 47 kQ. CASO RCAS SAo SAr She WEO RWE CKE.O RCKE> Vss 10K LE OE CLK ; VecO CLK, CLKe, CLKs to be terminated REGEO > Vss PLL CLK 10a CLKoO CLK PLL CLES CLR, CLA oT q D20 Each SDRAM 30 pF FBn FBour a RS. O RDQMBo © RDQMB: © 102} pam CS 1007 pam CS DQ (0:3) O DAa(03) po DQ (32:35) O DQ(03) pg Ld || 10a} DAM CS 409] Dam CS Da (4:7) O Da(o3) pt Da(36:39) O DQ(0;3) p10 RDQMB: © RDQMBs O 102] pam CS 100] pam CS DQ (8:11) O DQa(03) pa DQ (40:43) O Da(03) pit Ld || 40a] Dam CS 40a] Dam CS DQ (12:15) O Da(03) ops DQ(44:47) O Da(03) p12 Ld |_| 109] Dam CS 109} DQM CS cB (0:3) O Da(O3) 4 cB (4:7) O DQ(0;3) p13 | Veo o> D0-17 c RS: O RDQMB: O RDQMBe O Ves DO-17 102] pam CS 102] pam CS DQ(16:19) O DQ(0:3) ps DQ (4851) O DQO:3) p14 Ld — 40Q] Dam CS 40a] Dam CS DQ (20:23) O DQ(0:3) oe DaA(’255) O DQ0:3) p15 RDQMB: © RDQMB; © 102} DQM CS 102] Dam CS DQ (24:27) O Da(03) 7 Da(5659) O DQ0:3) 16 TL] [| 102] Dam CS 102] pam CS DQ (28:31) O DQa(03) pa DQ (60:63) O DQ3) p17

@ ABSOLUTE MAXIMUM RATINGS (See WARNING) Perea po Mins | Max, [PowerDisspaton —=SC=d;=SCsCiPPS SOY Output Curent (0) * : Voltages referenced to Vss (= 0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. @ RECOMMENDED OPERATING CONDITIONS Parameter Notes | symbot | jae Lwin | typ. [Max | wes pove [| oo foo foo | Vv | [ambien Tempered] | 0 | | OO *1. Voltages referenced to Vss (=0V) *2. Overshoot limit: Vis (max.) = Voc +1.5 V with a pulse-width < 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MB8516SR72CA-102/-103/-102L/-103L @ CAPACITANCE (Vcc = +3.3 V, f = 1 MHz, Ta = +25°C) ee) AS CRSWE [Oe |S | foxes [oowssiooows [ow | — | ® | F | so | Ow | Si | [su 5e8e [ow | i | a ‘soa me | |

@ DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3 Parameter Notes [ Max. | Ee ver. Burst Length = 1, tac = min for BL = 1, tex = min, One Bank Active, Iccts | Outputs Open, 2130 mA Address changed up to 1 time during tcx(min.), 0V< Vin < Vimax Operating Current 4 Vix min < Vin < Veo (Average Power Supply Current) Burst Length = 1 (each Bank), tac = min for BL = 1 (each Bank), tex = min, Two Banks Active, Icc1o | Outputs Open, 3760 mA Address changed up to 1 time during tcx(min.),

0 V< Vin < Vimax

Vin min < Vin < Veo CKE = Vi, tex = min, All Banks Idle, lccar Power Down Mode, 155 137 mA 0V< Vin < Vimax Vix min < Vin < Veo CKE = Vi, CLK = Vin or Vii, All Banks Idle, Power Down Mode, 187 | 128 | mA 0V< Vin < Vimax Vix min < Vin < Veo Precharge Standby Current CKE = Vin, tex = min, (Power Supply Current) “4 All Banks Idle, NOP commands only, Input signals (except to CMD) mA are changed one time during 3 clock cycles,

0 V< Vin <s Vimax

Vin min < Vin < Veo CKE = Vin, CLK = Vin or Vii, All Banks Idle, Input Signals are Stable, 155 mA

0 V< Vin < Viimax

Vin min < Vin < Veo (Continued)

(Continued) Parameter Notes | Max. | Eid ver. CKE = Vi, tex = min, Any Bank Active, Ieosr QV < Vw < Vmax 155 | 137 Vie min < Vin < Veo CKE = Vii, CLK = Vu or Vir, lecses__| Any Bank Active, 137 | 128 | mA 0V< Vins Viimax Vie min < Vin < Veo . CKE = Vin, tex = min, Active Standby Current *4 Any Bank Active, (Power Supply Current) NOP commands only, Input signals (except to Iccsw | CMD) are changed one time 570 mA during 3 clock cycles, 0V< Vin < Vimax Vix min < Vin < Veco CKE = Vin, CLK = Vu or Vit, Icesns | Any Bank Active, 155 mA 0V< Vin < Vimax Vie min < Vin < Veo tc = min, Gapless data, Burst Length = 4, Burst Mode Current *, Outputs open, (Average Power Supply Current) 4) lot | Multiple-banks Active, 1835 | mA 0V< Vin < Vimax Vie min < Vin < Veo Auto Refresh, tox = min Auto-refresh Current i *4/ — Iccs — |tre = min, 4456 mA (Average Power Supply Current) 0V< Vw Vmax Vie min < Vin < Veo Self-refresh, tok = min, Self-refresh Current * CKE<0.2V, (Average Power Supply Current) 4 loos 0V<Vin< Viimax 137 | 128 | mA Vin min < Vin < Veo Input Leakage Current lu All other pins not pA Output is disabled (Hi-Z) Output Leakage Current Ilo OVE VIN < Veo 10 HA LVTTL Output High Voltage 5 lou = —2.0 mA fea} — [vi LVTTL Output Low Voltage *s] va [in=v20ma_ | | oa Vv

MB8516SR72CA-102/-103/-102L/-103L Notes: *1. An initial pause (DESL on NOP) of 200 us is required after power-on followed by a minimum of eight Auto-refresh cycles. *2. Values of Iccts, lecio and Iccs are for when one side of the double-sided module is in standby mode (lccen)and the other side is in active. *3. DC characteristics is the Serial PD standby state (Vin = GND or Vcc). *4. loc depends on the output termination, load conditions, clock cycle rate and signal clock rate. The specified values are obtained with the output open and no termination resistors. *5. Voltages referenced to Vss (= 0 V)

MB8516SR72CA-102/-103/-102L/-103L @ AC CHARACTERISTICS (SDRAM Component Specifications) Notes 1, 2, 3 (1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Parameter Notes ~102/-102L ~103/-103L lock Period wits? | we | to | — [6 | = | | 2 [cwookHigntime ttm 8 = | 8 | = | 3 |clocktowtime tm | 8 | = I | | 4 [input Setup Time [Registered Mode | ts [36 | — | 36 | — | rs| | 5 |InputHold Time [Registered Mode | ts | 25 | — | 26 | — | ns| Output Valid from Clock *4,°5,*6 june] w= [| -— | 6 | - |e | [7 fowmutintowe ee fo Output in High-z vg 7fee2| we | 3 | 6 | 3 | a | lauss/ ve [3s | 6 | 3 | 6 | [2 [oupatHogtine SSC || | 8 | — [rl [10 [Time betwoenRetesh | ste |< — | (858 | — | 056 | ms) [it [tanstintime | OB | | 8 | 2 [rl lesigr NO nner [as | [as | ~ |

(2) BASE VALUES FOR CLOCK COUNT/LATENCY MB8516SR72CA Parameter Notes Symbol ~102/-103/-102L/-103L 7 |Data-in to Active/Refresh Command Period “4 “ cyes te | = | (eL=3| be [2oeste| — (3) CLOCK COUNT FORMULA (*10) Clock > _Base Value _ Value (Round off a whole number) Ook = “Clock Period (4) LATENCY (The latency values on these parameters are fixed regardless of clock period.) MB8516SR72CA Parameter Notes -102/-103/-102L/-103L Registered Mode Precharge to Output in High Z Dek wghen2 | hoe [8 gy recharge to Output in High-Z Delay cle Burst Stop Command to Output in High 24 CL=2| tee | 8 7 4 Cycle

Notes: *1. An initial pause (DESL on NOP) of 200 us is required after power-up followed by a minimum of eight Auto-refresh cycles. *2. 1.4 V or Vner is the reference level for measuring timing of signals. Transition times are measured between Vin (min) and Vi (max). *3. AC characteristics assume tr = 1 ns and 50 pF of capacitance load. *4. For Registered Mode, actual CAS Latency is added one cycle to the CAS Latency of this value because of a delay by registers. *5. Assumes teco is satisfied. *6. tac also specifies the access time at burst mode except for first access. *7. Specified where output buffer is no longer driven. *8. Actual clock count of tac (Inc) will be sum of clock count of tras (Iras) and tre (InP). *9. Operation within the taco (min) ensures that access time is determined by taco (min) +tac (max) ; if taco is greater than the specified taco (min), access time is determined by tac. *10. Allbase values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *Source: See MB81F64442C Data Sheet for details on the electrical. @ AC OPERATING TEST CONDITION (Example of AC Test Load Circuit) 14V 50a Z=502 vo 50 pF

@ SERIAL PRESENCE DETECT(SPD) FUNCTION 1. PIN DESCRIPTIONS SCL (Serial Clock) SCL input is used to clock all data input/output of SPD. SDA (Serial Data) SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output. SAo, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. 2. SPD OPERATIONS CLOCK and DATA CONVENTION Data states on the SDA can change only during SCL= Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig. 1 below. START CONDITION All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met. STOP CONDITION All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence. Fig. 1- START AND STOP CONDITIONS “START * “ sToP ¢ START = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices —namely up to eight modules— on the bus. The eight addresses for eight SPD devices are defined by the state of the SAo, SA: and SAz inputs. The last bit of the slave address defines the operation to be performed. When RW bit is “1”, a read operation is selected, when R/W bit is “0”, a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SAo, SA1, and SAz inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation. Fig. 2—- SLAVE ADDRESS DEVICE TYPE DEVICE IDENTIFIER ADDRESS ee | Pte ds fe Js] sa] se [ra]

READ OPERATIONS CURRENT ADDRESS READ Internally the SPD contains an address counter that maintains the address of the last data accessed, incriminated by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”, the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 3 for the sequence of address, acknowledge and data transfer. Fig. 3— CURRENT ADDRESS READ s T SLAVE s A __ADDRESS T BUS ACTIVITY: R ° MASTER T P “are UU pS | BUS ACTIVITY : c SPD K DATA RANDOM READ Random Read operations allow the master to access any memory location ina random manner. Prior to issuing the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD. The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/ W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 4 for the sequence of address, acknowledge and data transfer. Fig. 4- RANDOM READ s s T SLAVE WORD. T SLAVE s Bus activity: A ADDRESS ADDRESS A __ADDRESS $ MASTER 0 0 | P “mms CU LT dL] : A A A BUS ACTIVITY : c c c SPD K K K DATA

Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to address 0 and the SPD continues to output data for each acknowledge received. Fig. 5 - SEQUENTIAL READ SLAVE s ADDRESS A A A t BUS ACTIVITY : — Cc c c ° MASTER . K K Ko P SPALINE Ti LE Hil L gusactivity: & J SPD K DATA (n) DATA (n+1) DATA (n+2) DATA (n+x) 4, DC CHARACTERISTICS Note: *1. Referenced to Vss.

AC CHARACTERISTICS ne) amar | sym | iO [ser Go Fea Te oe Noise Suppression Time 2 | Constant at SCL, SDA Inputs q 100 Time the Bus Must Be Free Before Fs [osttowreiod tw a | Fig. 6 -— TIMING WAVEFORM te tr bron Pk ~. rrr Tsu-sta HE tsu:par | tsu:sto re A (input) EF seeee teur pe FY ™ SDA (ou ee.

MB8516SR72CA-102/-103/-102L/-103L @ PACKAGE DIMENSIONS 168-pin plastic DIMM (socket type) (MDS-168P-P43) Dimension in mm (inches)

Product Information

MB8516SR72CA-102 specifications and overview.

Summary

16M X 72 BIT SYNCHRONOUS DYNAMIC RAM DIMM

Description

16M X 72 BIT SYNCHRONOUS DYNAMIC RAM DIMM

Source title MB8516SR72CA-102 Datasheet(PDF) - fujitsu semiconductor

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