MB8508S064CE-100

MB8508S064CE-100 FUJITSU | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

DS05-11147-1EFUJITSU SEMICONDUCTOR DATA SHEET MEMORY Un-buffered

8 M · 64 BIT

SYNCHRONOUS DYNAMIC RAM SO-DIMM MB8508S064CE-100/-100L 144-pin, 2 Clock, 1-bank, based on 8 M · 8 Bit SDRAMs with SPD n DESCRIPTION The Fujitsu MB8508S064CE is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of eight MB81F64842C devices which organized as two banks of 8 M · 8 bits and a 2K-bit serial EEPROM on a 144-pin glass-epoxy substrate. The MB8508S064CE features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB8508S064CE is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface is needed. n PRODUCT LINE & FEATURES Parameter MB8508S064CE -100 -100L Clock Frequency 100 MHz max. Burst Mode Cycle Time 10 ns min. Access Time from Clock 8.5 ns max. (CL = 3) Operating Current 680 mA max. Power Down Mode Current (I CC2P ) 16 mA max. 8 mA max. Self Refresh Current (ICC6 ) 8 mA max. 4 mA max.

• Unbuffered 144-pin SO-DIMM Socket T ype (Lead pitch: 0.8 mm)
• Conformed to JEDEC Standard (2 CLK)
• Organization: 8,388,608 words · 64 bits
• Memory: MB81F64842C (8 M · 8, 4-bank) · 8 pcs.
• 3.3 V –0.3 V Supply Voltage
• All input/output LVTTL compatible
• 4096 Refresh Cycle every 65.6 ms
• Auto and Self Refresh
• CKE Power Down Mode
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with Serial EEPROM: JEDEC Standard SPD Format
• Module size: 1.25” (height) · 2.66” (length) · 0.15” (thickness)
• C L - t RCD -tRP : 3-3-3 clk min. @100 MHz, 2-2-2 clk min. @66 MHz To Top / Lineup / Index

144-pin plastic SO DIMM (socket type) (MDS-144P-P09) Package and Ordering Information – 144-pin SO-DIMM, order as MB8508S064CE-100DG (DG = Std. power ver., Gold Pad) -100LDG (LDG = Low power ver., Gold Pad) To Top / Lineup / Index

No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1V SS 49 DQ 13 97 DQ 22 2V SS 50 DQ 45 98 DQ 54 3D Q 0 51 DQ 14 99 DQ 23 4D Q 32 52 DQ 46 100 DQ 55 5D Q 1 53 DQ 15 101 V CC 6D Q 33 54 DQ 47 102 V CC 7D Q 2 55 V SS 103 A 6 8D Q 34 56 V SS 104 A 7 9D Q 3 57 N.C. 105 A 8 10 DQ 35 58 N.C. 106 BA 0 11 V CC 59 N.C. 107 V SS 12 V CC 60 N.C. 108 V SS

13 DQ 4 61 CLK 0 109 A 9 14 DQ 36 62 CKE 0 110 BA 1

15 DQ 5 63 V CC 111 A 10 16 DQ 37 64 V CC 112 A 11

17 DQ 6 65 RAS 113 V CC 18 DQ 38 66 CAS 114 V CC

19 DQ 7 67 WE 115 DQMB 2 20 DQ 39 68 N.C. 116 DQMB 6 21 V SS 69 CS 0 117 DQMB 3 22 V SS 70 N.C. 118 DQMB 7 23 DQMB 0 71 N.C. 119 V SS 24 DQMB 4 72 N.C. 120 V SS 25 DQMB 1 73 N.C. 121 DQ 24 26 DQMB 5 74 CLK 1 122 DQ 56

27 V CC 75 V SS 123 DQ 25 28 V CC 76 V SS 124 DQ 57

29 A 0 77 N.C. 125 DQ 26 30 A 3 78 N.C. 126 DQ 58 31 A 1 79 N.C. 127 DQ 27 32 A 4 80 N.C. 128 DQ 59

33 A 2 81 V CC 129 V CC 34 A 5 82 V CC 130 V CC

35 V SS 83 DQ 16 131 DQ 28 36 V SS 84 DQ 48 132 DQ 60

37 DQ 8 85 DQ 17 133 DQ 29 38 DQ 40 86 DQ 49 134 DQ 61

39 DQ 9 87 DQ 18 135 DQ 30 40 DQ 41 88 DQ 50 136 DQ 62

41 DQ 10 89 DQ 19 137 DQ 31 42 DQ 42 90 DQ 51 138 DQ 63

43 DQ 11 91 V SS 139 V SS 44 DQ 43 92 V SS 140 V SS

45 V CC 93 DQ 20 141 SDA 46 V CC 94 DQ 52 142 SCL

47 DQ 12 95 DQ 21 143 V CC 48 DQ 44 96 DQ 53 144 V CC

Symbol I/O Function Symbol I/O Function A0 to A11 I Address Input CS 0 IC h i p S e l e c t BA 0, BA1 I Bank Address DQ 0 to DQ63 I/O Data Input/Data Output RAS I Row Address Strobe V CC — Power Supply (+3.3 V) CAS I Column Address Strobe V SS — Ground (0 V) WE I Write Enable N.C. — No Connection DQMB 0 to DQMB7 I Data (DQ) Mask SCL I Serial PD Clock CLK 0, CLK1 I Clock Input SDA I/O Serial PD Address/Data Input/OutputCKE 0 I Clock Enable TOP VIEW Chip 0 Chip 1 Chip 2 Chip 3 11 4 3 31.75 mm 67.60 mm (MDS-144P-P09) Chip 4 Chip 5 Chip 6 Chip 7 21 4 4 To Top / Lineup / Index

Note:Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken. *1. SDRAM Device Attributes *2.Checksum for Bytes 0 to 62 This byte is the checksum for bytes 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of bytes 0 through 62. Byte Function Described Hex Value -100/100L 32 to 61 64 to 98 99 to 125 126 127 128+ Defines Number of Bytes Written into Serial Memory at Module Manufacture T otal Number of Bytes of SPD Memory Device Fundamental Memory T ype Number of Row Addresses Number of Column Addresses Number of Module Banks Data Width Data Width (Continuation) Interface T ype SDRAM Cycle Time (Highest CAS Latency) SDRAM Access from Clock (Highest CAS Latency) DIMM Configuration T ype Refresh Rate/T ype Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay for Back to Back Random Column Addresses Burst Lengths Supported Number of Banks on Each SDRAM Device CAS Latency CS Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes SDRAM Cycle Time (2nd. Highest CAS Latency) SDRAM Access from Clock (2nd. Highest CAS Latency) SDRAM Cycle Time (3rd. Highest CAS Latency) SDRAM Access from Clock (3rd. Highest CAS Latency) Precharge to Activate Min. (t RP ) Row Activate to Row Activate Min. (tRRD ) RAS to CAS Delay Min. (tRCD ) Activate to Precharge Minimum Time (tRAS ) Module Bank Density Unused Storage Locations SPD Data Revision Code Checksum for Byte 0 to 62 Manufacturer’s Information: Unused Storage Vendor Specific Data: Unused Storage Intel Specification Frequency Intel Specification Details for 66 MH Z Support Unused Storage Locations

128 Byte

256 Byte

8.5 ns Non-Parity Self, Normal

1 Cycle

1, 2, 4, 8, Page 4 bank 2, 3 UN-buffer 15 ns 9 ns No Support No Support 30 ns 20 ns 30 ns 60 ns

64 MByte

Z CL=2, 3 80h 08h 04h 0Ch 09h 01h 40h 00h 01h A0h 85h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh F0h 90h 00h 00h 1Eh 14h 1Eh 3Ch 10h 00h 01h 57h 00h 00h 66h CFh Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TBD TBD Upper VCC tolerance 0 = 10% Lower VCC tolerance 0 = 10% Supports Write 1 /Read Burst Supports Precharge All Supports Auto- Precharge Supports Early RAS Precharge 0 0 001110 To Top / Lineup / Index

Add. RAS CAS WE DQM

8 M · 8

Add. RAS CAS WE DQM Add. RAS CAS WE DQM Add. RAS CAS WE DQM Add. RAS CAS WE DQM Add. RAS CAS WE DQM Add. RAS CAS WE DQM Add. RAS CAS WE DQM A0 to A11, BA0, BA1 RAS CAS WE SERIAL EEPROM A0 A1 A2 SDASDASCLSCL CLK CLK 10 W 10 W 10 W 10 W To Top / Lineup / Index

n ABSOLUTE MAXIMUM RATINGS (See WARNING) * : Voltages referenced to VSS (= 0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS *1. Voltages referenced to VSS (= 0 V) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Min. Max. Supply Voltage* V CC –0.5 +4.6 V Input Voltage* V IN –0.5 +4.6 V Output Voltage* V OUT –0.5 +4.6 V Storage T emperature T STG –55 +125 °C Power Dissipation P D —8 . 0 W Output Current (D.C.) I OUT –50 +50 mA Parameter Notes Symbol Value Unit Min. Typ. Max. Supply Voltage *1 VCC 3.0 3.3 3.6 V VSS 000V Input High Voltage, All Inputs *1, 2 V IH 2.0 — V CC +0.5 V Input Low Voltage, All Inputs *1, 3 V IL –0.5 — 0.8 V Ambient T emperature T A 0— + 7 0 °C *3. Undershoot limit: VIL (min) 4.6 V VIH VIL Pulse width £ 5 ns *2. Overshoot limit: VIH (max) 50% of pulse amplitude VIH VIL –1.5V pulse width measured at 50% of pulse amplitude. = 4.6 V for pulse width <= 5 ns acceptable, = VSS –1.5 V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude Pulse width £ 5 ns VIHmin VILmax To Top / Lineup / Index

(VCC = +3.3 V , f = 1 MHz, TA = +25°C) Parameter Symbol Value Unit Min. Max. Input Capacitance A0 to A11, BA0, BA1 C IN1 —4 8 p F RAS , CAS, WE C IN2 —4 2 p F CS 0 C IN3 —4 9 p F CKE 0 C IN4 —4 0 p F CLK 0, CLK1 C IN5 —3 2 p F DQMB 0 to DQMB7 C IN6 —1 3 p F SCL C SCL —6 p F Input/Output Capacitance SDA C SDA —7 p F DQ 0 to DQ63 C DQ —1 0 p F To Top / Lineup / Index

(At recommended operating conditions unless otherwise noted.) Notes 1, 2 (Continued) Parameter Notes Symbol Condition Value Unit Min. Max. Std. ver. Low ver. Operating Current (Average Power Supply Current) *3 I CC1S Burst: Length = 1 tRC = min for BL = 1 tCK = min One Bank Active, Outputs Open Addresses changed up to 1-time during t CK (min.) 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —6 8 0 m A Precharge Standby Current (Power Supply Current) I CC2P CKE = VIL, All Banks Idle tCK = min, Power Down Mode 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —1 6 8 m A ICC2PS CKE = VIL, All Banks Idle CLK = H or L, Power Down Mode 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —8 4 m A ICC2N CKE = VIH, All Banks Idle, tCK = min NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles

0 V £ V

IN £ VIL (max.) VIH (min.) £ VIN £ VCC —8 0 m A ICC2NS CKE = VIH, All Banks Idle CLK = H or L, Input signal are stable 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —1 6 m A Active Standby Current (Power Supply Current) ICC3P CKE = VIL, Any Bank Active tCK = min. 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —1 6 8 m A ICC3PS CKE = VIL, Any Bank Active CLK = H or L IN £ VIL (max.) VIH (min.) £ VIN £ VCC —8 4 m A ICC3N CKE = VIH, Any Bank Active tCK = min., NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles IN £ VIL (max.) VIH (min.) £ VIN £ VCC —1 2 0 m A ICC3NS CKE = VIH, Any Bank Active CLK = H or L IN £ VIL (max.) VIH (min.) £ VIN £ VCC —1 6 m A To Top / Lineup / Index

(Continued) Notes: *1. An initial pause (DESL on NOP) of 200 ms is required after power-on followed by a minimum of eight Auto-refresh cycles. *2. DC characteristics is the Serial PD standby state (VIN = VSS or VCC ). *3. ICC depends on the output termination, load conditions, clock cycle rate and signal clock rate. The specified values are obtained with the output open and no termination register. *4. Voltages referenced to VSS = VSSQ (= 0 V). Parameter Notes Symbol Condition Value Unit Min. Max. Std. ver. Low ver. Burst Mode Current (Average Power Supply Current) *3 I CC4 tCK = min, Burst Length = 4 Outputs Open, All Banks Active Gapless Data IN £ VIL (max.) VIH (min.) £ VIN £ VCC —4 8 0 m A Auto-refresh Current (Average Power Supply Current) *3 I CC5 Auto Refresh tCK = min tRC = min 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC — 1360 mA Self-refresh Current (Average Power Supply Current) *3 I CC6 Self-Refresh tCK = min. CKE £ 0.2 V 0 V £ VIN £ VIL (max.) VIH (min.) £ VIN £ VCC —8 4 m A Input Leakage Current (All Inputs) II (L)

0 V £ VIN £ VCC

All other pins not under test = 0 V–30 30 mA Output Leakage Current I O (L) Output is disabled (Hi-Z) –5 5 mA LVTTL Output High Voltage *4 V OH IOH = –2.0 mA 2.4 — V LVTTL Output Low Voltage *4 V OL IOL = +2.0 mA — 0.4 V To Top / Lineup / Index

(1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3 (2) BASE VALUES FOR CLOCK COUNT/LATENCY No. Parameter Notes Symbol MB8508S064CE -100/100L Unit Min. Max. 1C l o c k P e r i o d CL = 3 t CK3 10 — ns CL = 2 t CK2 15 — ns 2C l o c k H i g h T i m e t CH 3.5 — ns 3C l o c k L o w T i m e t CL 3.5 — ns

4 Input Setup Time t SI 3— n s

5 Input Hold Time t HI 1— n s

6 Output Valid from Clock

(tCLK = min) *4, *5 CL = 3 t AC3 —8 . 5 ns CL = 2 t AC2 —9

7 Output in Low-Z *6 t LZ 0— n s

8 Output in High-Z *6

CL = 3 t HZ3 38 . 5 n s CL = 2 t HZ2 39 n s

9 Output Hold Time *6 t OH 3— n s

10 Time between Refresh t REF — 65.6 ms 11 T ransition Time t T 0.5 2 ns

12 CKE Setup Time for Power Down Exit Time t CKSP 3— n s

No. Parameter Notes Symbol MB8508S064CE -100/100L Unit Min. Max. 1R A S Cycle Time *7 t RC 90 — ns 2R A S Precharge Time t RP 30 — ns 3R A S Active Time t RAS 60 110000 ns 4R A S to CAS Delay Time *8 t RCD 30 — ns 5W r i t e R e c o v e r y T i m e t WR 10 — ns 6R A S to RAS Bank Active Delay Time t RRD 20 — ns

7 Data-in to Precharge Lead Time t DPL 10 — ns

8 Data-in to Active/Refresh Command Period

CL = 3 t DAL3 2 cyc + tRP —n s CL = 2 t DAL2 1 cyc + tRP —n s

9 Mode Register Set Cycle Time t RSC 20 — ns

(3) CLOCK COUNT FORMULA (*9) (4) LATENCY (The latency values on these parameters are fixed regardless of clock period.) Notes: *1. An initial pause (DESL on NOP) of 200 ms is required after power-up followed by a minimum of eight Auto-refresh cycles. *2. 1.4 V or VREF is the reference level for measuring timing of signals. T ransition times are measured between VIH (min) and VIL (max). *3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load. *4. Maximum value of CL = 2 depends on tCK. *5. tAC also specifies the access time at burst mode except for first access. *6. Specified where output buffer is no longer driven. tOH , tLZ, and tHZ define the times at which the output level achieves –200 mV . *7. Actual clock count of tRC (IRC ) will be sum of clock count of tRAS (IRAS ) and tRP (IRP ). *8. Operation within the tRCD (min) ensures that access time is determined by tRCD (min) + tAC (max); if tRCD is greater than the specified tRCD (min), access time is determined by tAC . *9. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *Source: See MB81F64842C Data Sheet for details on the electrical. No. Parameter Symbol MB8508S064CE -100/100L Unit

1 CKE to Clock Disable I

2 DQM to Output in High-Z I DQZ 2C y c l e

3 DQM to Input Data Delay I DQD 0C y c l e

4 Last Output to Write Command Delay I OWD 2C y c l e

5 Write Command to Input Data Delay I DWD 0C y c l e

6 Precharge to Output in High-Z Delay

CL = 3 I ROH3 3C y c l e CL = 2 I ROH2 2C y c l e

7 Burst Stop Command to Output in High-Z Delay

CL = 3 I BSH3 3C y c l e CL = 2 I BSH2 2C y c l e 8C A S to CAS Delay (min) I CCD 1C y c l e 9C A S Bank Delay (min) I CBD 1C y c l e Clock ‡ Base Value Clock Period (Round off a whole number) To Top / Lineup / Index

n AC OPERATING TEST CONDITION (Example of AC Test Load Circuit) I/O Z = 50 W 50 W 1.4 V 50 pF To Top / Lineup / Index

n SERIAL PRESENCE DETECT(SPD) FUNCTION 1. PIN DESCRIPTIONS SCL (Serial Clock) SCL input is used to clock all data input/output of SPD SDA (Serial Data) SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output. SA 0, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. For this module, any address inputs are not required because all addresses (SA 0, SA1, SA2) are driven to VSS on the module. 2. SPD OPERATIONS CLOCK and DATA CONVENTION Data states on the SDA can change only during SCL = Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig. 1 below. START CONDITION All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met. STOP CONDITION All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence. ST ART Fig. 1 – START AND STOP CONDITIONS STOP SCL SDA ST ART = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High To Top / Lineup / Index

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices —namely up to eight modules— on the bus. The eight addresses for eight SPD devices are defined by the state of the SA 0, SA1 and SA2 inputs. For this module, the three bits are fixed as 000[B] because all addresses are driven to VSS on the module. Therefore, no address inputs are required. The last bit of the slave address defines the operation to be performed. When R/W bit is “1”, a read operation is selected, when R/W bit is “0”, a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA0, SA1, and SA2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation. 1 0 1 0 R/WSA 2 SA 1 SA 0 DEVICE TYPE IDENTIFIER DEVICE ADDRESS Fig. 2 – SLAVE ADDRESS To Top / Lineup / Index

1. READ OPERATIONS CURRENT ADDRESS READ Internally the SPD contains an address counter that maintains the address of the last data accessed, incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”, the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 3 for the sequence of address, acknowledge and data transfer. RANDOM READ Random Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD. The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/ W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 4 for the sequence of address, acknowledge and data transfer. Fig. 3 – CURRENT ADDRESS READ S T O P DATA A C K SLAVE ADDRESS S T A R T BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD Fig. 4 – RANDOM READ S T O P DATA A C K SLAVE ADDRESS A C K A C K SLAVE ADDRESS WORD ADDRESS S T A R T S T A R T BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD To Top / Lineup / Index

Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to address0 and the SPD continues to output data for each acknowledge received. 4. DC CHARACTERISTICS Note:*1. Referenced to VSS . Parameter Note Symbol Condition Value Unit Min. Max. Input Leakage Current S ILI 0 V £ VIN £ VCC –10 10 mA Output Leakage Current S ILO 0 V £ VOUT £ VCC –10 10 mA Output Low Voltage *1 S VOL IOL = 3.0 mA — 0.4 V Fig. 5 – SEQUENTIAL READ S T O P A C K A C K A C K DATA (n+x)DATA (n+2)DATA (n+1)DATA (n) SLAVE ADDRESS A C K BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD To Top / Lineup / Index

1. AC CHARACTERISTICS No. Parameter Symbol Value Unit Min. Max.

1 SCL Clock Frequency f SCL — 100 KHz

2 Noise Suppression Time

Constant at SCL, SDA Inputs TI — 100 ns 3 SCL Low to SDA Data Out Valid t AA —3 . 5 ms

4 Time the Bus Must Be Free Before

a New T ransmission Can Start tBUF 4.7 — ms 5 Start Condition Hold Time t HD:STA 4.0 — ms 6C l o c k L o w P e r i o d t LOW 4.7 — ms 7 Clock High Period t HIGH 4.0 — ms 8 Start Condition Setup Time t SU:STA 4.7 — ms

9 Data in Hold Time t HD:DAT 0— ms

10 Data in Setup Time t SU:DAT 250 — ns

11 SDA and SCL Rise Time t R —1 ms

12 SDA and SCL Fall Time t F — 300 ns

13 Stop Condition Setup Time t SU:STO 4.7 — ms

14 Data Out Hold Time t DH 100 — ns

15 Write Cycle Time t WR —1 5 m s

tHD : DA T tSU : DA T tSU : STO tAA tDH tBUF tHD : ST A SCL SDA (input) SDA (output) tSU : ST A Fig. 6 – TIMING WAVEFORM To Top / Lineup / Index

C 1997 FUJITSU LIMITED M144009SC-1-2 4.00±0.10 (.157±.004) 2.50±0.10 (.098±.004) 1.50±0.10 (.059±.004) 4.60±0.13 (.181±.005) Details of "A" part Details of "B" part 0.60±0.05 (.024±.002) 1 143 1442 "A" "B" NOTCHES FULL R 4.00±0.10 (.157±.004) 20.00±0.10 (.787±.004) (.236±.003) 6.00±0.08 31.75±0.13 (1.250±.005) 2.10±0.10 (.083±.004) NOTCHES FULL R Ø1.80±0.05 (Ø.071±.002) 3.30±0.13 (.130±.005) 23.20±0.05 (.913±.002) 24.50(.965)TYP 29.00±0.10 (1.142±.004) 32.80±0.05 (1.291±.002) 2.10±0.10 (.083±.004) 4.60±0.13 (.181±.005) 0.80±0.03 (.031±.001) 23.20±0.05 (1.291±.002) 3.80(.150)MAX 1.00±0.10 (.039±.004) 4.00(.157)MIN Pin No.1 INDEX Dimension in mm (inches). 144-pin plastic SO DIMM (socket type) (MDS-144P-P09) To Top / Lineup / Index

For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan T el: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA T el: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany T el: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New T ech Park Singapore 556741 T el: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9812 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. To Top / Lineup / Index