MB84VD2108XEM-70 SPANSION | Alldatasheet

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This document specifies SP ANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SP ANSION product. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". T o order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SP ANSION memory solutions. TM TM TM SPANSION MCP Data Sheet TM

DS05-50306-1EFUJITSU SEMICONDUCTOR DATA SHEET Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M (·8/·16) FLASH MEMORY & 2M (·8/·16) STATIC RAM MB84VD2108XEM -70/MB84VD2109XEM -70 n FEATURES

  • Power Supply Voltage of 2.7 V to 3.3 V
  • High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM)
  • Operating Temperature
  • Package 56-ball BGA (Continued) n PRODUCT LINE UP Note: Both VCC f and VCC s must be in recommended operation range when either part is being accessed. n PACKAGE Part No. MB84VD2108XEM/MB84VD2109XEM Supply Voltage(V) V CC f= 3.0 V V CC s= 3.0 V Max Address Access Time (ns) 70 70 Max CE Access Time (ns) 70 70 Max OE Access Time (ns) 30 35 56-ball plastic BGA (BGA-56P-M02) +0.3 V –0.3 V +0.3 V –0.3 V

(Continued)

  • ••• FLASH MEMORY
  • Simultaneous Read/Write Operations (Dual Bank) Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMA TION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program
  • Minimum 100,000 Write/Erase Cycles
  • Sector Erase Architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase.
  • Boot Code Sector Architecture MB84VD2108XEM: T op sector MB84VD2109XEM: Bottom sector
  • Embedded Erase TM * Algorithms Automatically pre-programs and erases the chip or any sector
  • Embedded Program TM * Algorithms Automatically writes and verifies data at specified address
  • D a t a Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
  • Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
  • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode.
  • Low V CC Write Inhibit ££££ 2.5 V
  • HiddenROM Region 64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)
  • WP /ACC Input Pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2108XEM:SA37,SA38 MB84VD2109XEM:SA0,SA1) At V IH, allows removal of boot sector protection At VACC , program time will reduse by 40%.
  • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device
  • Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
  • ••• SRAM
  • Power Dissipation Operating : 40 mA Max Standby : 7 mA Max
  • Power Down Features using CE1s and CE2s
  • Data Retention Supply Voltage: 1.5 V to 3.3 V
  • C E 1 s and CE2s Chip Select
  • Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)

(BGA-56P-M02) (Top View) Marking side A13 N.C. RY/BY A18 N.C. SA DQ 6 DQ 1 VSS A16 DQ 15/A-1 DQ 13 DQ 4 DQ 3 DQ 9 OE CEf CIOf A14 A10 INDEX LAND* A17 N.C. DQ 7 DQ 12 Vccs Vccf DQ 10 DQ 0 CE1s Vss DQ 14 DQ 5 CIOs DQ 11 DQ 2 DQ 8 A12 A19 CE2s RESET UB A15 A11 WE WP/ACC LB * : There is no solder ball. This land should be open electrically.

Pin Name Function Input/Output A16 to A0 Address Inputs (Common) I A19 to A17, A-1 Address Input (Flash) I SA Address Input (SRAM) I DQ 15 to DQ0 Data Inputs / Outputs (Common) I/O CE f Chip Enable (Flash) I CE1 s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) Open Drain Output O UB Upper Byte Control (SRAM) I LB Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf=VCC f is Word mode ( ×16), CIOf=VSS is Byte mode ( × 8) I CIOs I/O Configuration (SRAM) CIOs=VCC s is Word mode (×16), CIOs=VSS is Byte mode (× 8) I RESET Hardware Reset Pin / Sector Protection Un- lock (Flash) I WP /ACC Write Protect / Acceleration (Flash) I N.C. No Internal Connection — VSS Device Ground (Common) Power VCC f Device Power Supply (Flash) Power VCC s Device Power Supply (SRAM) Power

16 M bit

2 M bit

DQ 15/A–1 to DQ0 RY/BY LB UB CIOf WP /ACC CE2s DQ 15/A–1 to DQ0 DQ 15 to DQ0 A–1 SA CIOs

User Bus Operations Table (Flash = Word mode; CIOf = VCC f, SRAM = Word mode; CIOs = VCC s) Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP /ACC = VIH; removal of boot sectors protection. WP /ACC = VACC (9 V) ; Program time will reduce by 40%. Operation *1, *3 CE fC E 1sC E 2 s O E WE SA LB UB DQ 7 to DQ 0 DQ 15 to DQ 8 RESET WP / ACC Full Standby H HX XXXXX H i g h - Z H i g h - Z H X XL Output Disable HL H H H X X X High-Z High-Z HX X X X H H High-Z High-Z L HX H H X X X High-Z High-Z XL Read from Flash *2 L HX LHXXX D OUT D OUT HX XL Write to Flash L HX HLXXX D IN D IN HX XL Read from SRAM H L H L H X LL D OUT D OUT HXHL H i g h - Z D OUT LH D OUT High-Z Write to SRAM H L H X L X LL D IN D IN HXHL H i g h - Z D IN LH D IN High-Z Temporary Sector Group Unprotection *4 XX XX X X X X X X V ID X Flash Hardware Reset X HX XXXXX H i g h - Z H i g h - Z L X XL Boot Block Sector Write Protection XX XX X X X X X X X L

User Bus Operations Table (Flash = Word mode; CIOf = VCC f, SRAM = Byte mode; CIOs = VSS ) Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP /ACC = VIL; protection of boot sectors. WP /ACC = VIH; removal of boot sectors protection. WP /ACC = VACC (9 V); Program time will reduce by 40%. Operation *1, *3 CE fC E 1sC E 2 s O E WE SA LB UB DQ 7 to DQ 0 DQ 15 to DQ 8 RESET WP / ACC Full Standby H HX XXXXX H i g h - Z H i g h - Z H X XL Output Disable HL H H H X X X High-Z High-Z HX X X X H H High-Z High-Z L HX H H X X X High-Z High-Z XL Read from Flash *2 L HX LHXXX D OUT D OUT HX XL Write to Flash L HX HLXXX D IN D IN HX XL Read from SRAM H L H L H SA X X D OUT High-Z H X Write to SRAM H L H X L SA X X D IN High-Z H X Temporary Sector Group Unprotection *4 XX XX X X X X X X V ID X Flash Hardware Reset X HX XXXXX H i g h - Z H i g h - Z L X XL Boot Block Sector Write Protection XX XX X X X X X X X L

User Bus Operations Table (Flash = Byte mode; CIOf = VSS , SRAM = Byte mode; CIOs = VSS ) Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP /ACC = VIL; protection of boot sectors. WP /ACC = VIH; removal of boot sectors protection. WP /ACC = VACC (9 V); Program time will reduce by 40%. Operation *1,*3 CE fC E 1sC E 2 sD Q15/A–1 OE WE SA LB UB DQ 7 to DQ 0 DQ 14 to DQ8 RESET WP / ACC Full Standby H HX X X X X X X High-Z High-Z H X XL Output Disable HL H X H H X X X High-Z High-Z HX X X X X H H High-Z High-Z L HX A–1 H H X X X High-Z High-Z XL Read from Flash *2 L HX A–1 LHXX X D OUT High-Z H X XL Write to Flash L HX A–1 HLXX X D IN High-Z H X XL Read from SRAM H L H X L H SA X X D OUT High-Z H X Write to SRAM H L H X X L SA X X D IN High-Z H X Temporary Sector Group Unprotection *4 X X X X XXX X X X X V ID X Flash Hardware Re- set X HX X X X X X X High-Z High-Z L X XL Boot Block Sector Write Protection X X X X XXX X X X X X L

n ABSOLUTE MAXIMUM RATINGS *1 : Minimum DC voltage on input or I/O pins is –0.3 V . During voltage transitions, input or I/O pins may undershoot During voltage transitions, input or I/O pins may overshoot to VCC f+2.0 V or VCC s+2.0 V for periods of up to 20 ns. *2 : Minimum DC input voltage on RESET pin is –0.5 V . During voltage transitions, RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCC f or VCC s) does not exceed +9.0 V . Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on WP/ACC pin is –0.5 V . During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCC f is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Storage Temperature Tstg –55 +125 °C Ambient Temperature with Power Applied T A –40 +85 °C Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VIN, VOUT –0.3 VCC f +0.4 V VCC s +0.4 V VCC f/VCC s Supply *1 VCC f, VCC s –0.3 +4.0 V RESET *2 VIN –0.5 + 13.0 V WP /ACC *3 VIN –0.5 +10.5 V Parameter Symbol Value Unit Min Max Ambient Temperature T A –40 +85 °C VCC f/VCC s Supply Voltages Vccf, Vccs +2.7 +3.3 V

n ELECTRICAL CHARACTERISTICS 1. DC Characteristics (Continued) Parameter Symbol Test Conditions Value Unit Min Typ Max Input Leakage Current I LI VIN = VSS to VCC f, VCC s –1.0 — +1.0 mA Output Leakage Current I LO VOUT = VSS to VCC f, VCC s –1.0 — +1.0 mA RESET Inputs Leakage Current ILIT VCC f = VCC f Max, VCC s = VCC s Max, RESET = 12.5 V — — 35 µA Flash VCC Active Current (Read) *1 ICC1 f CE f = VIL, OE = VIH tCYCLE = 5 MHz Byte — — 13 mA tCYCLE = 5 MHz Word — — 15 tCYCLE = 1 MHz Byte — — 7 mA tCYCLE = 1 MHz Word — — 7 Flash VCC Active Current (Program/Erase) *2 ICC2 f C E f = VIL, OE = VIH —— 3 5 m A Flash VCC Active Current (Read-While-Program) *5 ICC3 fC E f = VIL, OE = VIH Byte — — 48 mA Word — — 50 Flash VCC Active Current (Read-While-Erase) *5 ICC4 fC E f = VIL, OE = VIH Byte — — 48 mA Word — — 50 Flash VCC Active Current (Erase-Suspend-Program) ICC5 fC E f = VIL, OE = VIH —— 3 5 m A ACC Input Leakage Current ILIA VCC f = VCC f Max, VCC s = VCC s Max, WP /ACC = VACC Max —— 2 0 m A SRAM V CC Active Current ICC1 s VCC s = VCC s Max, CE1 s = VIL, CE2s = VIH tCYCLE =10 MHz — — 40 mA SRAM V CC Active Current ICC2 s CE1 s = 0.2 V, CE2s = VCC s – 0.2 V tCYCLE = 10 MHz — — 40 mA tCYCLE = 1 MHz — — 8 mA Flash VCC Standby Current ISB1 f VCC f = VCC f Max, CEf = VCC f ± 0.3 V RESET = VCC f ± 0.3 V, WP /ACC = VCC f± 0.3 V —15 mA Flash VCC Standby Current (RESET ) ISB2 f VCC f = VCC f Max, RESET = VSS ± 0.3 V, WP /ACC = VCC f± 0.3 V —15 mA Flash VCC Current (Automatic Sleep Mode) *3 ISB3 f VCC f = VCC f Max, CEf = VSS ± 0.3 V RESET = VCC f ± 0.3 V, WP /ACC = VCC f± 0.3 V VIN = VCC f± 0.3 V or VSS ± 0.3 V —15 mA

(Continued) * 1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : Applicable for only VCC f applying. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6 : V CC indicates lower of VCC f or VCC s. Parameter Symbol Test Conditions Value Unit Min Typ Max SRAM V CC Standby Current ISB1 s CE1 s > VCC s – 0.2 V, CE2s > VCC s – 0.2 V LB = UB > VCC s–0.2 V or < 0.2 V ——7 mA SRAM V CC Standby Current ISB2 s CE1 s > VCC s – 0.2 V or < 0.2 V, CE2s < 0.2 V LB = UB > VCC s–0.2 V or < 0.2V ——7 mA Input Low Level V IL — –0.3 — 0.5 V Input High Level V IH —2 . 4 — VCC +0.3 *6 V Voltage for Sector Protection, and Temporary Sector Unprotection (RESET ) *4 VID — 11.5 — 12.5 V Voltage for Program Acceleration (WP/ACC) *4 VACC —8 . 5 9 . 0 9 . 5 V SRAM Output Low Level V OL VCC s = VCC s Min, IOL = 4.0 mA — — 0.45 V SRAM Output High Level V OH VCC s = VCC s Min, IOH = –0.5 mA 2.4 — — V Flash Output Low Level V OL VCC f = VCC f Min, IOL = 4.0 mA — — 0.4 V Flash Output High Level V OH VCC f = VCC f Min, IOH = –0.5 mA 2.4 — — V Flash Low VCC f Lock-Out Voltage VLKO —2 . 3 — 2 . 5 V

  1. AC Characteristics
  • CE Timing
  • Timing Diagram for alternating SRAM to Flash
  • Flash Characteristics Please refer to “n 16M FLASH MEMORY CHARACTERISTICS for MCP” part.
  • SRAM Characteristics, Please refer to “n 2M SRAM CHARACTERISTICS for MCP” part. Parameter Symbol Test Setup Value Unit JEDEC Standard Min CE Recover Time — t CCR —0 n s CE f tCCR tCCR CE1 s CE2s tCCR tCCR

n 16M FLASH MEMORY CHARACTERISTICS for MCP 1. Flexible Sector-erase Architecture on Flash Memory

  • Eight 4 K words, and thirty one 32 K words.
  • Individual-sector, multiple-sector, or bulk-erase capability. Bank 1 Bank size 1 Bank 2 Bank 1 Bank size 2 Bank 1 Bank 1 Bank 2 Bank 2 Bank 2 Sector Architecture (Top Boot Block) 010000hSA0 : 64KB (32KW) 000000h 030000h 020000h 050000h 040000h 070000h 060000h 090000h 080000h 0B0000h 0A0000h 0D0000h 0C0000h 0F0000h 0E0000h SA1 : 64KB (32KW) SA2 : 64KB (32KW) SA3 : 64KB (32KW) SA4 : 64KB (32KW) SA5 : 64KB (32KW) SA6 : 64KB (32KW) SA7 : 64KB (32KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 8KB (4KW) SA32 : 8KB (4KW) SA33 : 8KB (4KW) SA34 : 8KB (4KW) SA35 : 8KB (4KW) SA36 : 8KB (4KW) SA37 : 8KB (4KW) SA38 : 8KB (4KW) 110000h 100000h 130000h 120000h 150000h 140000h 170000h 160000h 190000h 180000h 1B0000h 1A0000h 1D0000h 1C0000h 1F0000h 1E0000h 1F2000h 1F6000h 1F4000h 1FA000h 1F8000h 1FE000h 1FC000h 1FFFFFh 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0A8000h 0A0000h 0B8000h 0B0000h 0C8000h 0C0000h 0D8000h 0D0000h 0E8000h 0E0000h 0F8000h 0F0000h 0F9000h 0FB000h 0FA000h 0FD000h 0FC000h 0FF000h 0FE000h 0FFFFFh Word mode Byte modeBank size 3Bank size 4

(Continued) (Continued) Sector Architecture (Bottom Boot Block) Bank 2 Bank 1 Bank 2 Bank 2 Bank 2 Bank 1 Bank 1 Bank 1 010000h Word mode Byte mode SA0 : 8KB (4KW) 000000h 030000h 020000h 050000h 040000h 070000h 060000h 090000h 080000h 0B0000h 0A0000h 0D0000h 0C0000h 0F0000h 0E0000h SA1 : 8KB (4KW) SA2 : 8KB (4KW) SA3 : 8KB (4KW) SA4 : 8KB (4KW) SA5 : 8KB (4KW) SA6 : 8KB (4KW) SA7 : 8KB (4KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 64KB (32KW) SA32 : 64KB (32KW) SA33 : 64KB (32KW) SA34 : 64KB (32KW) SA35 : 64KB (32KW) SA36 : 64KB (32KW) SA37 : 64KB (32KW) SA38 : 64KB (32KW) 110000h 100000h 130000h 120000h 150000h 140000h 170000h 160000h 190000h 180000h 1B0000h 1A0000h 1D0000h 1C0000h 1F0000h 1E0000h 1FFFFFh 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0A8000h 0A0000h 0B8000h 0B0000h 0C8000h 0C0000h 0D8000h 0D0000h 0E8000h 0E0000h 0F8000h 0F0000h 0FFFFFh 002000h 006000h 004000h 00A000h 008000h 00E000h 00C000h 001000h 003000h 002000h 005000h 004000h 007000h 006000h Bank size 1Bank size 2Bank size 3Bank size 4

Sector Address Table (Top Boot Block, Bank Size=1) Bank Sector Sector Address Address Range (Byte mode) Address Range (Word mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh Bank 1 SA31 1 1 1 1 1 0 0 0 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh

Sector Address Table (Bottom Boot Block, Bank Size=1) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 0 0 0 0 0 0 h t o 0 0 1 FFFh 000000h to 000FFFh S A 1 00000001 0 0 2 0 0 0 h t o 0 0 3 FFFh 001000h to 001FFFh S A 2 00000010 0 0 4 0 0 0 h t o 0 0 5 FFFh 002000h to 002FFFh S A 3 00000011 0 0 6 0 0 0 h t o 0 0 7 FFFh 003000h to 003FFFh S A 4 00000100 0 0 8 0 0 0 h t o 0 0 9 FFFh 004000h to 004FFFh S A 5 00000101 0 0 A 0 0 0 h t o 0 0 B FFFh 005000h to 005FFFh S A 6 00000110 0 0 C 0 0 0 h t o 0 0 D FFFh 006000h to 006FFFh S A 7 00000111 0 0 E 0 0 0 h t o 0 0 FFFFh 007000h to 007FFFh Bank 2 SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

Sector Address Table (Top Boot Block, Bank Size=2) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh Bank 1 SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 111111000 1 F 0 0 0 0 h t o 1 F 1 FFFh 0F8000h to 0F8FFFh S A 3 211111001 1 F 2 0 0 0 h t o 1 F 3 FFFh 0F9000h to 0F9FFFh S A 3 311111010 1 F 4 0 0 0 h t o 1 F 5 FFFh 0FA000h to 0FAFFFh S A 3 411111011 1 F 6 0 0 0 h t o 1 F 7 FFFh 0FB000h to 0FBFFFh S A 3 511111100 1 F 8 0 0 0 h t o 1 F 9 FFFh 0FC000h to 0FCFFFh S A 3 611111101 1 F A 0 0 0 h t o 1 F B FFFh 0FD000h to 0FDFFFh S A 3 711111110 1 F C 0 0 0 h t o 1 F D FFFh 0FE000h to 0FEFFFh S A 3 811111111 1 F E 0 0 0 h t o 1 FFFFFh 0FF000h to 0FFFFFh

Sector Address Table (Bottom Boot Block, Bank Size=2) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 SA0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh Bank 2 SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

Sector Address Table (Top Boot Block, Bank Size=3) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh Bank 1 SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 111111000 1 F 0 0 0 0 h t o 1 F 1 FFFh 0F8000h to 0F8FFFh S A 3 211111001 1 F 2 0 0 0 h t o 1 F 3 FFFh 0F9000h to 0F9FFFh S A 3 311111010 1 F 4 0 0 0 h t o 1 F 5 FFFh 0FA000h to 0FAFFFh S A 3 411111011 1 F 6 0 0 0 h t o 1 F 7 FFFh 0FB000h to 0FBFFFh S A 3 511111100 1 F 8 0 0 0 h t o 1 F 9 FFFh 0FC000h to 0FCFFFh S A 3 611111101 1 F A 0 0 0 h t o 1 F B FFFh 0FD000h to 0FDFFFh S A 3 711111110 1 F C 0 0 0 h t o 1 F D FFFh 0FE000h to 0FEFFFh S A 3 811111111 1 F E 0 0 0 h t o 1 FFFFFh 0FF000h to 0FFFFFh

Sector Address Table (Bottom Boot Block, Bank Size=3) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 0 0 0 0 0 0 h t o 0 0 1 FFFh 000000h to 000FFFh S A 1 00000001 0 0 2 0 0 0 h t o 0 0 3 FFFh 001000h to 001FFFh S A 2 00000010 0 0 4 0 0 0 h t o 0 0 5 FFFh 002000h to 002FFFh S A 3 00000011 0 0 6 0 0 0 h t o 0 0 7 FFFh 003000h to 003FFFh S A 4 00000100 0 0 8 0 0 0 h t o 0 0 9 FFFh 004000h to 004FFFh S A 5 00000101 0 0 A 0 0 0 h t o 0 0 B FFFh 005000h to 005FFFh S A 6 00000110 0 0 C 0 0 0 h t o 0 0 D FFFh 006000h to 006FFFh S A 7 00000111 0 0 E 0 0 0 h t o 0 0 FFFFh 007000h to 007FFFh S A 8 00001XXX 0 1 0 0 0 0 h t o 0 1 FFFFh 008000h to 00FFFFh S A 9 00010XXX 0 2 0 0 0 0 h t o 0 2 FFFFh 010000h to 017FFFh S A 1 000011XXX 0 3 0 0 0 0 h t o 0 3 FFFFh 018000h to 01FFFFh S A 1 100100XXX 0 4 0 0 0 0 h t o 0 4 FFFFh 020000h to 027FFFh S A 1 200101XXX 0 5 0 0 0 0 h t o 0 5 FFFFh 028000h to 02FFFFh S A 1 300110XXX 0 6 0 0 0 0 h t o 0 6 FFFFh 030000h to 037FFFh S A 1 400111XXX 0 7 0 0 0 0 h t o 0 7 FFFFh 038000h to 03FFFFh Bank 2 S A 1 501000XXX 0 8 0 0 0 0 h t o 0 8 FFFFh 040000h to 047FFFh S A 1 601001XXX 0 9 0 0 0 0 h t o 0 9 FFFFh 048000h to 04FFFFh S A 1 701010XXX 0 A 0 0 0 0 h t o 0 A FFFFh 050000h to 057FFFh S A 1 801011XXX 0 B 0 0 0 0 h t o 0 B FFFFh 058000h to 05FFFFh S A 1 901100XXX 0 C 0 0 0 0 h t o 0 C FFFFh 060000h to 067FFFh S A 2 001101XXX 0 D 0 0 0 0 h t o 0 D FFFFh 068000h to 06FFFFh S A 2 101110XXX 0 E 0 0 0 0 h t o 0 E FFFFh 070000h to 077FFFh S A 2 201111XXX 0 F 0 0 0 0 h t o 0 F F FFFh 078000h to 07FFFFh S A 2 310000XXX 1 0 0 0 0 0 h t o 1 0 FFFFh 080000h to 087FFFh S A 2 410001XXX 1 1 0 0 0 0 h t o 1 1 FFFFh 088000h to 08FFFFh S A 2 510010XXX 1 2 0 0 0 0 h t o 1 2 FFFFh 090000h to 097FFFh S A 2 610011XXX 1 3 0 0 0 0 h t o 1 3 FFFFh 098000h to 09FFFFh S A 2 710100XXX 1 4 0 0 0 0 h t o 1 4 FFFFh 0A0000h to 0A7FFFh S A 2 810101XXX 1 5 0 0 0 0 h t o 1 5 FFFFh 0A8000h to 0AFFFFh S A 2 910110XXX 1 6 0 0 0 0 h t o 1 6 FFFFh 0B0000h to 0B7FFFh S A 3 010111XXX 1 7 0 0 0 0 h t o 1 7 FFFFh 0B8000h to 0BFFFFh S A 3 111000XXX 1 8 0 0 0 0 h t o 1 8 FFFFh 0C0000h to 0C7FFFh S A 3 211001XXX 1 9 0 0 0 0 h t o 1 9 FFFFh 0C8000h to 0CFFFFh S A 3 311010XXX 1 A 0 0 0 0 h t o 1 A FFFFh 0D0000h to 0D7FFFh S A 3 411011XXX 1 B 0 0 0 0 h t o 1 B FFFFh 0D8000h to 0DFFFFh S A 3 511100XXX 1 C 0 0 0 0 h t o 1 C FFFFh 0E0000h to 0E7FFFh S A 3 611101XXX 1 D 0 0 0 0 h t o 1 D FFFFh 0E8000h to 0EFFFFh S A 3 711110XXX 1 E 0 0 0 0 h t o 1 E FFFFh 0F0000h to 0F7FFFh S A 3 811111XXX 1 F 0 0 0 0 h t o 1 F F FFFh 0F8000h to 0FFFFFh

Sector Address Table (Top Boot Block, Bank Size=4) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh Bank 1 SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh S A 3 111111000 1 F 0 0 0 0 h t o 1 F 1 FFFh 0F8000h to 0F8FFFh S A 3 211111001 1 F 2 0 0 0 h t o 1 F 3 FFFh 0F9000h to 0F9FFFh S A 3 311111010 1 F 4 0 0 0 h t o 1 F 5 FFFh 0FA000h to 0FAFFFh S A 3 411111011 1 F 6 0 0 0 h t o 1 F 7 FFFh 0FB000h to 0FBFFFh S A 3 511111100 1 F 8 0 0 0 h t o 1 F 9 FFFh 0FC000h to 0FCFFFh S A 3 611111101 1 F A 0 0 0 h t o 1 F B FFFh 0FD000h to 0FDFFFh S A 3 711111110 1 F C 0 0 0 h t o 1 F D F F F h 0 F E 0 0 0 h t o 0 F E FFFh S A 3 811111111 1 F E 0 0 0 h t o 1 F F F F F h 0 F F 0 0 0 h t o 0 FFFFFh

Sector Address Table (Bottom Boot Block, Bank Size=4) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode)Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 0 0 0 0 0 0 h t o 0 0 1 FFFh 000000h to 000FFFh S A 1 00000001 0 0 2 0 0 0 h t o 0 0 3 FFFh 001000h to 001FFFh S A 2 00000010 0 0 4 0 0 0 h t o 0 0 5 FFFh 002000h to 002FFFh S A 3 00000011 0 0 6 0 0 0 h t o 0 0 7 FFFh 003000h to 003FFFh S A 4 00000100 0 0 8 0 0 0 h t o 0 0 9 FFFh 004000h to 004FFFh S A 5 00000101 0 0 A 0 0 0 h t o 0 0 B F F F h 0 0 5 0 0 0 h t o 0 0 5 FFFh S A 6 00000110 0 0 C 0 0 0 h t o 0 0 D FFFh 006000h to 006FFFh S A 7 00000111 0 0 E 0 0 0 h t o 0 0 FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh Bank 2 SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

Sector Group Addresses Table (Top Boot Block) Sector Group Addresses Table (Bottom Boot Block) Sector Group A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors S G A 0 00000XXX S A 0 SGA1 00001XXX SA1 to SA300010XXX 00011XXX S G A 2 001XXXXXS A 4 t o S A 7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 SGA8 11100XXX SA28 to SA3011101XXX 11110XXX S G A 9 11111000 S A 3 1 S G A 1 011111001 S A 3 2 S G A 1 111111010 S A 3 3 S G A 1 211111011 S A 3 4 S G A 1 311111100 S A 3 5 S G A 1 411111101 S A 3 6 S G A 1 511111110 S A 3 7 S G A 1 611111111 S A 3 8 Sector Group A

19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors

SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 SGA15 11100XXX SA35 to SA3711101XXX 11110XXX SGA16 1 1 1 1 1 X X X SA38

Flash Memory Autoselect Codes Table *1: A–1 is for Byte mode. *2: Output 01h at protected sector address and output 00h at unprotected sector address. Type A 19 to A12 A 6 A 1 A 0 A –1*1 Code (HEX) Manufacturer’s Code X V IL VIL VIL VIL 04h Device Code Top Boot Block Bank Size=1 Byte XV IL VIL VIH VIL 36h Word X 2236h Bottom Boot Block Bank Size=1 Byte XV IL VIL VIH VIL 39 Word X 2239h Top Boot Block Bank Size=2 Byte XV IL VIL VIH VIL 2D Word X 222Dh Bottom Boot Block Bank Size=2 Byte XV IL VIL VIH VIL 2E Word X 222Eh Top Boot Block Bank Size=3 Byte XV IL VIL VIH VIL 28h Word X 2228h Bottom Boot Block Bank Size=3 Byte XV IL VIL VIH VIL 2Bh Word X 222Bh Top Boot Block Bank Size=4 Byte XV IL VIL VIH VIL 33h Word X 2233h Bottom Boot Block Bank Size=4 Byte XV IL VIL VIH VIL 35 Word X 2235h Sector Group protect Sector Group Address VIL VIH VIL VIL 01h*2

Flash Memory Command Definitions Table Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Read/Reset *1 Word 555h AAh 2AAh 55h 555h F0h RA RD — — — — Byte AAAh 555h AAAh Autoselect Word 555h AAh 2AAh 55h (BA) 555h Byte AAAh 555h (BA) AAAh Program Word 555h AAh 2AAh 55h 555h A0h PA PD — — — — Byte AAAh 555h AAAh Chip Erase Word 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Byte AAAh 555h AAAh AAAh 555h AAAh Sector Erase Word 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h Byte AAAh 555h AAAh AAAh 555h Sector Erase Sector Erase Set to Fast Mode Word 555h AAh 2AAh 55h 555h Byte AAAh 555h AAAh Fast Program*2 Word Byte Reset from Fast Mode *2 Word

2 BA 90h XXXh F0h

Protection * Word

4 XXXh 60h SPA 60h SPA 40h SPA SD — — — —

Query *4 Word 55h Byte AAh HiddenROM Entry Word 555h AAh 2AAh 55h 555h Byte AAAh 555h AAAh HiddenROM Program *5 Word 555h AAh 2AAh 55h 555h A0h PA PD — — — — Byte AAAh 555h AAAh HiddenROM Erase *5 Word 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h Byte AAAh 555h AAAh AAAh 555h HiddenROM Exit *5 Word 555h AAh 2AAh 55h (HRBA) 555h 90h XXXh 00h — — — — Byte AAAh 555h (HRBA) AAAh

*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid while Fast Mode. *3: This command is valid while RESET =V ID. *4: The valid Address is A6 to A0. *5: This command is valid while HiddenROM mode. *6: The data “00h” is also acceptable. Notes : • Address bits A19 to A12 = X = “H” or “L” for all address commands except for Program Address (P A), Sector Address (SA), and Bank Address (BA). Bus operations are defined in T able 2 “User Bus Operations”. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse.

  • SA = Address of the sector to be erased. The combination of A 19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A19 to A15) SP A = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the HiddenROM area. T op Boot Block Word mode : 0F8000h to 0FFFFFh Byte mode : 1F0000h to 1FFFFFh Bottom Boot Block Word mode : 000000h to 007FFFh Byte mode : 000000h to 00FFFFh HRBA = Bank address of the HiddenROM area. T op Boot Block : A15 = A16 = A17 = A18 = A19 = A20 = 1 Bottom Boot Block : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location P A. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses.
  • The system should generate the following address patterns; Word mode : 555h or 2AAh to addresses A10 to A0 Byte mode : AAAh or 555h to addresses A10 to A0 and A–1
  • Read Only Operations Characteristics (Flash) * : T est Conditions Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V Parameter Symbol Test Setup Value* Unit JEDEC Standard Min Max Read Cycle Time t AVAV tRC —7 0 — n s Address to Output Delay t AVQV tACC CE f = VIL OE = VIL —7 0 n s Chip Enable to Output Delay t ELQV tCE fO E = VIL —7 0 n s Output Enable to Output Delay t GLQV tOE — — 30 ns Chip Enable to Output High-Z t EHQZ tDF — — 25 ns Output Enable to Output High-Z t GHQZ tDF — — 25 ns Output Hold Time From Addresses, CE f or OE, Whichever Occurs First tAXQX tOH —0 — n s RESET Pin Low to Read Mode — t READY — — 20 µs
  • Read Cycle (Flash) WE OE CE f tCEf tOE DQ Address Stable High-Z Output Valid High-Z tOEH tACC tRC RESET tACC tOH DQ tRC Address Stable High-Z Output Valid tRH tDF Address Address tRH tCEftRP CE f
  • Erase/Program Operations (Flash) Parameter Symbol Value Unit JEDEC Standard Min Typ Max Write Cycle Time t AVAV tWC 70 — — ns Address Setup Time (WE to Addr.) t AVWL tAS 0—— n s Address Setup Time to CEf Low During Toggle Bit Polling — t ASO 12 — — ns Address Hold Time (WE to Addr.) t WLAX tAH 45 — — ns Address Hold Time from CEf or OE High During Toggle Bit Polling —t AHT 0—— n s Data Setup Time t DVWH tDS 30 — — ns Data Hold Time t WHDX tDH 0—— n s Output Enable Setup Time — t OES 0—— n s Output Enable Hold Time Read —t OEH 0—— n s Toggle and Data Polling 10 — — ns CE f High During Toggle Bit Polling — t CEPH 20 — — ns OE High During Toggle Bit Polling — t OEPH 20 — — ns Read Recover Time Before Write (OE to CEf) t GHEL tGHEL 0—— n s Read Recover Time Before Write (OE to WE)t GHWL tGHWL 0—— n s WE Setup Time (CEf to WE)t WLEL tWS 0—— n s CEf Setup Time (WE to CEf) t ELWL tCS 0—— n s WE Hold Time (CEf to WE)t EHWH tWH 0—— n s CEf Hold Time (WE to CEf) t WHEH tCH 0—— n s Write Pulse Width t WLWH tWP 35 — — ns CE f Pulse Width t ELEH tCP 35 — — ns Write Pulse Width High t WHWL tWPH 25 — — ns CEf Pulse Width High t EHEL tCPH 25 — — ns Byte Programming Operation tWHWH1 tWHWH1 —8— µ s Word Programming Operation — 16 — µs Sector Erase Operation * 1 tWHWH2 tWHWH2 —1—s VCC f Setup Time — t VCS 50 — — µs Voltage Transition Time *2 —t VLHT 4—— µ s Rise Time to VID *2 —t VIDR 500 — — ns Rise Time to VACC —t VACCR 500 — — ns Recover Time from RY/BY —t RB 0—— n s RESET Pulse Width — t RP 500 — — ns Delay Time from Embedded Output Enable — t EOE — — 70 ns RESET Hold Time Before Read — t RH 200 — — ns Program/Erase Valid to RY/BY Delay — t BUSY — — 90 ns Erase Time-out Time *3 —t TOW 50 — — µs Erase Suspend Transition Time *4 —t SPD — — 20 µs

*1 : This does not include the preprogramming time. *2 : This timing is for Sector Protection Operation. *3 : The time between writes must be less than “t TOW ” otherwise that command will not be accepted and erasure will start. A time-out or “tTOW ” from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command(s). *4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD ” to suspend the erase operation.

  • Write Cycle (WE control) (Flash) tCH tWP tWHWH1 tWC tAH CE f OE tRC DQ tAS tOE tWPH tGHWL tDH DQ 7PDA0h D OUT WE 555h PA PA tOH Data Polling3rd Bus Cycle tCS tCEf tDS D OUT Address Notes : • P A is address of the memory location to be programmed.
  • PD is data to be programmed at byte address.
  • DQ 7 is the output of the complement of the data written to the device.
  • D OUT is the output of the data written to the device.
  • Figure indicates last two bus cycles out of four bus cycle sequence.
  • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
  • Write Cycle (CEf control) (Flash) Notes : • P A is address of the memory location to be programmed.
  • PD is data to be programmed at byte address.
  • DQ 7 is the output of the complement of the data written to the device.
  • D OUT is the output of the data written to the device.
  • Figure indicates last two bus cycles out of four bus cycle sequence.
  • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) tCP tDS tWHWH1 tWC tAH WE OE DQ tAS tCPH tDH DQ 7A0h D OUT CE f 555h PA PA Data Polling3rd Bus Cycle tWS tWH tGHEL PD Address
  • AC Waveforms Chip/Sector Erase Operations (Flash) Address VCC f CE f OE DQ WE 555h 2AAh 555h 555h 2AAh SA *1 tDS tCH tAS tAH tCS tWPH tDH tGHWL tVCS tWC tWP AAh 55h 80h AAh 55h 10h/ 30h for Sector Erase 30h * : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. Note : These waveform are for the ×16 mode. (The addresses differ from ×8 mode.)
  • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) * : DQ7 = Valid Data (The device has completed the Embedded operation.) tOEH tOE tWHWH1 or 2 CE f OE WE DQ 7 tDFtCH tCEf DQ 7 = Valid DataDQ 7 DQ DQ 6 to DQ0 = Output Flag tEOE DQ 6 to DQ0 Valid Data High-Z High-Z (DQ 6 to DQ0) Data In Data In tBUSY RY/BY
  • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) * : DQ6 stops toggling (The device has completed the Embedded operation). Address RY/BY CE f WE DQ 6/DQ2 OE tAS tBUSY Toggle tAHTtAHT tASO tOEH tOEH tOE Data Toggle Data Toggle Data Stop TogglingData tCEf * Output Valid tDH tCEPH tOEPH
  • Bank-to-bank Read/Write Timing Diagram (Flash) CEf DQ WE Address BA1 BA1 BA1 BA2(555h) BA2(PA) BA2(PA) OE ValidOutput ValidOutput ValidOutput StatusValidIntput ValidIntput tRC tRC tRC tRCtWC tWC tAHT tAStAS tAH tACC tCE tOE tOEH tWP tGHWL tDS tDFtDH tDF tCEPH Read Command Command Read Read Read (A0h) (PD) Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. CE f OE DQ WE Address
  • R Y / B Y Timing Diagram during Write/Erase Operations (Flash)
  • RESET , RY/BY Timing Diagram (Flash) Rising edge of the last write pulse CE f RY/BY WE tBUSY Entire programming or erase operations tRP RESET tREADY RY/BY WE tRB
  • Temporary Sector Unprotection (Flash)
  • Acceleration Mode Timing Diagram (Flash) RESET VCC f CE f WE RY/BY tVLHT Program or Erase Command Sequence tVLHT tVCS tVIDR VID tVLHT Unprotection period VIH VCC f VACC WP /ACC VIH CE f WE RY/BY tVACCR tVLHTtVCS tVLHT tVLHT Acceleration Mode Period
  • Extended Sector Protection (Flash) SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 ms (Min) SGAy RESET OE WE CE f Data VCC f Add SGAxSGAx 60h01h40h60h60h TIME-OUT tVCS tVLHT tVIDR tOE tWP tWC tWC
  1. Erase and Programming Performance (Flash) Parameter Limit Unit Comment Min Typ Max Sector Erase Time — 1 10 s Excludes programming time prior to erasure Byte Programming Time — 8 300 ms Excludes system-level overhead Word Programming Time — 16 360 ms Excludes system-level overhead Chip Programming Time — — 50 s Excludes system-level overhead Erase/Program Cycle 100,000 — — cycle

n 2M SRAM CHARACTERISTICS for MCP 1. AC Characteristics

  • Read Cycle (SRAM) Note: T est Conditions Output Load:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to V CC s Timing measurement reference level Input: 0.5×VCC s Output: 0.5×VCC s Parameter Symbol Value Unit Min Max Read Cycle Time t RC 70 — ns Address Access Time t AA —7 0 n s Chip Enable (CE1s) Access Time t CO1 —7 0 n s Chip Enable (CE2s) Access Time t CO2 —7 0 n s Output Enable Access Time t OE —3 5 n s LB, UB to Output Valid t BA —7 0 n s Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5— n s Output Enable Low to Output Active t OEE 0— n s UB , LB Enable Low to Output Active t BE 0— n s Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD —2 5 n s Output Enable High to Output High-Z t ODO —2 5 n s UB , LB Output Enable to Output High-Z t BD —2 5 n s Output Data Hold Time t OH 10 — ns
  • R e a d C y c l e ( S R A M ) Note : WE remains “H” for the read cycle. tRC tAA tOH tCO1 tOD tODOtOEE tCOE Valid Data Out Address CE1 s OE DQ CE2s tCOE tOE tCO2 tOD LB, UB tBA tBD tBE
  • Write Cycle (SRAM) Parameter Symbol Value Unit Min Max Write Cycle Time t WC 70 — ns Write Pulse Width t WP 50 — ns Chip Enable to End of Write t CW 55 — ns Address valid to End of Write t AW 55 — ns UB , LB to End of Write t BW 55 — ns Address Setup Time t AS 0—n s Write Recovery Time t WR 0—n s WE Low to Output High-Z t ODW —2 5 n s WE High to Output Active t OEW 0—n s Data Setup Time t DS 30 — ns Data Hold Time t DH 0—n s
  • Write Cycle *3 (WE control) (SRAM) tWC tAS tWP tWR tCW tODW tOEW tDS tDH Valid Data In Address WE CE1 s D OUT D IN CE2s tCW *1 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will remain at High-Z. *2 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will remain at High-Z. *3 : If OE is “H” during the write cycle, the outputs will remain at High-Z. *4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. tBW LB, UB tAW
  • W r i t e C y c l e *1 (CE1s control) (SRAM) tWC tAS tWP tWR tCW tODWtCOE tDS tDH Valid Data In Address WE CE1 s D OUT D IN CE2s tCW *1 : If OE is “H” during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. LB, UB tBW tBE tAW
  • W r i t e C y c l e *1 (CE2s Control) (SRAM) tWC tAS tWP tWR tCW tODWtCOE tDS tDH Valid Data In Address WE CE1 s D OUT D IN CE2s *1 : If OE is “H” during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. tCW LB, UB tBW tBE tAW
  • W r i t e C y c l e *1 (LB, UB Control) (SRAM) tWC tDS tDH Address LB, UB WE D IN *1 : If OE is “H” during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. tWP CE2s tCW CE1 s tAS tWR tBW tODWtCOE D OUT tBE Valid Data In*2 tCW tAW
  1. Data Retention Characteristics (SRAM) Note : tRC : Read cycle time
  • CE1 s Controlled Data Retention Mode *1 *1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to Vccs+0.3 V . *2 : When CE1 s is operating at the VIH Min level (2.2 V), the standby current is given by ISB1 s during the transition of VCC s from 3.3 V to 2.2 V .
  • CE2s Controlled Data Retention Mode * * : In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V to Vccs+0.3 V . Parameter Symbol Value Unit Min Typ Max Data Retention Supply Voltage V DH 1.5 — 3.3 V Standby Current V DH = 1.5 V I DDS2 —1 4 mA Chip Deselect to Data Retention Mode Time t CDR 0— —n s Recovery Time t R tRC ——n s VCC s 2.7 V VIH GND DATA RETENTION MODE tCDRCE1 s VCCS –0.2 V tR VDH VCC s 2.7 V GND DATA RETENTION MODE VIH VIL CE2s tCDR tR 0.2 V VDH

Note : T est conditions TA = +25°C, f = 1.0 MHz n HANDLING OF PACKAGE Please handle this package carefully since the sides of package create acute angles. n CAUTION

  • The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.
  • Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group Protection” command. Parameter Symbol Test Setup Value Unit Typ Max Input Capacitance C IN VIN = 0 11 14 pF Output Capacitance C OUT VOUT = 0 12 16 pF Control Pin Capacitance C IN2 VIN = 0 14 16 pF WP /ACC Pin Capacitance C IN3 VIN = 0 17 20 pF

16Mega-bit (2M · 8-bit or 1M · 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

2Mega-bit (256k · 8-bit or 128K · 16-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2108 = Top sector 84VD2109 = Bottom sector PACKAGE TYPE PBS = 56-ball BGA EM -70 PBSX SPEED OPTION See Product Selector Guide Device Revision (Valid Combination) EM Bank Size 1 = 0.5Mbit / 15.5Mbit 2 = 2Mbit / 14Mbit 3 = 4Mbit / 12Mbit 4 = 8Mbit / 8Mbit

(BGA-56P-M02) Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2002 FUJITSU LIMITED B56002S-c-1-1 7.00±0.10 (.276±.004) INDEX-MARK AREA 0.39±0.10 (.015±.004)(Stand off) .043–.004 +.004 –0.10 +0.11 1.09 (Mounting height) 0.40(.016) REF 0.40(.016) REF ABCDEFGH 56-ø.018 –.002 +.004 –0.05 +0.10 56-ø0.45 INDEX B A 0.08(.003)M S A B 0.80(.031) REF 0.80(.031) REF S0.10(.004) BS0.20(.008) 0.20(.008)S A S

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