MB84VD2108X FUJITSU | Alldatasheet

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DS05-50201-2EFUJITSU SEMICONDUCTOR DATA SHEET Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M (·8/·16) FLASH MEMORY & 2M (·8/·16) STATIC RAM MB84VD2108X -85/MB84VD2109X -85 nnnn FEATURES

  • Power supply voltage of 2.7 to 3.6 V
  • High performance 85 ns maximum access time
  • Operating Temperature -25 to +85 °C
  • Package 61-ball FBGA, 56-pin TSOP(I) (Continued) nnnn PRODUCT LINE UP nnnn PACKAGES Flash Memory SRAM Max. Address Access Time (ns) 85 85 Max. CE Access Time (ns) 85 85 Max. OE Access Time (ns) 35 45 +0.6 V -0.3 V 61-ball plastic FBGA 56-pin plastic TSOP(I) (BGA-61P-M02) (FPT-56P-M04)

MB84VD2108X -85/MB84VD2109X -85 (Continued) 1. FLASH MEMORY

  • Simultaneous Read/Write operations (dual bank) Miltiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program
  • Minimum 100,000 write/erase cycles
  • Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase.
  • Boot Code Sector Architecture MB84VD2108X : T op sector MB84VD2109X : Bottom sector
  • Embedded Erase TM * Algorithms Automatically pre-programs and erases the chip or any sector
  • Embedded Program TM * Algorithms Automatically writes and verifies data at specified address
  • Data Polling and Toggle Bit feature for detection of program or erase cycle completion
  • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
  • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
  • Low V CC f write inhibit £ 2.5 V
  • Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)
  • WP /ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2108X : SA37, SA38 MB84VD2109X : SA0, SA1) At V IH, allows removal of boot sector protection At VACC , program time will reduse by 40%.
  • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device
  • Please refer to “MBM29DL16XTD/BD” data sheet in detailed function 2. SRAM
  • Power dissipation Operating: 50 mA max. Standby: 7 mA max.
  • Power down features using CE1s and CE2s
  • Data retention supply voltage : 1.5 V to 3.6 V
  • CE1s and CE2s Chip Select
  • Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MB84VD2108X -85/MB84VD2109X -85 1234567 9 1 0 8 C D E F G H J K DQ 8 DQ 2 DQ 11 DQ 14DQ 5CIOS DQ 6 SA A 16 N.C.VSSA0 DQ 1N.C. DQ 13DQ 4DQ 3DQ 9 DQ 15/ A-1 CIOfCEf OE DQ 0 DQ 10 VCC fV CC s DQ 12 DQ 7 VSSCE1 S A9 A13 N.C.N.C.A5A2 A18 RY/BY A19 A12 A15CE2 SA6A3 UB S RESET B WE A 8 A11N.C. A 7 LBS WP/ ACC nnnn PIN ASSIGNMENTS (Top View) 61-ball FBGA

MB84VD2108X -85/MB84VD2109X -85 (Top View) 56-pin TSOP (I) N.C. A A14 A13 A12 A11 A10 A19 N.C. WE CE2s RESET WP/ACC RY/BY UBs LBs A18 A17 N.C. A CIOf VSS SA DQ 15/A-1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 CIOs V CC s VCC f DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE V SS CE1s CEf A

MB84VD2108X -85/MB84VD2109X -85 nnnn PIN DESCRIPTION Pin Function Input/Output A0 to A16 Address Inputs (Common) I A–1, A17 to A19 Address Input (Flash) I SA Address Input (SRAM) I DQ 0 to DQ15 Data Inputs/Outputs (Common) I/O CE f Chip Enable (Flash) I CE1 s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) Open Drain Output O UB s Upper Byte Control (SRAM) I LBs Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf = VIH is Word mode (·16) , CIOf = VIL is Byte mode (·8) I CIOs I/O Configuration (SRAM) CIOs = VIH is Word mode (·16) , CIOs = VIL is Byte mode (·8) I RESET Hardware Reset Pin/Sector Protection Unlock (Flash) I WP /ACC Write Protect/Acceleration (Flash) I N.C. No Internal Connection ¾ VSS Device Ground (Common) Power VCC f Device Power Supply (Flash) Power VCC s Device Power Supply (SRAM) Power

MB84VD2108X -85/MB84VD2109X -85 nnnn BLOCK DIAGRAM VCC fV SS VCC sV SS RY/BY A0 to A19 A0 to A16 A0 to A19 A-1 WP/ACC RESET CEf CIOf SA LBs UBs WE OE CE1s CE2s CIOs

16 M bit

2 M bit

MB84VD2108X -85/MB84VD2109X -85 nnnn DEVICE BUS OPERATIONS Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCC f, SRAM = Word mode; CIOs = VCC s) Legend : L = VIL, H = VIH, X = VIL or VIH, See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP /ACC = VIL ; protection of boot sectors. WP /ACC = VIH ; removal of boot sectors protection. WP /ACC = VACC (9 V) ; Program time will reduce by 40%. 6. SA ; Don’t care or Open. Operation (Note1, 3) CE fC E 1sC E 2 sO E WE SA (Note 6) LB sU B s DQ 0 to DQ 7 DQ 8 to DQ 15 RESET WP /ACC (Note 5) Full Standby H HX X X X X X HIGH-Z HIGH-Z H X XL Output Disable HL H H H X X X HIGH-Z HIGH-Z HX X X X H H HIGH-Z HIGH-Z L HX H H X X X HIGH-Z HIGH-Z XL Read from Flash (Note 2) L HX LH X X X D OUT D OUT HX XL Write to Flash L HX HL X X X D IN D IN HX XL Read from SRAM H L H L H X LL D OUT D OUT HXHL H I G H - Z D OUT LH D OUT HIGH-Z Write to SRAM H L H X L X LL D IN D IN HXHL H I G H - Z D IN LH D IN HIGH-Z Temporary Sector Group Unprotection (Note 4) XX X X X X X X X X V ID X Flash Hardware Reset X HX X X X X X HIGH-Z HIGH-Z L X XL Boot Block Sector Write Protection XX X X X X X X X X X L

MB84VD2108X -85/MB84VD2109X -85 Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCC f, SRAM = Byte mode; CIOs = VSS ) Legend : L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP /ACC = VIL ; protection of boot sectors. WP /ACC = VIH ; removal of boot sectors protection. WP /ACC = VACC (9 V) ; Program time will reduce by 40%. 6. LBS, UBS ; Don’t care or Open. Operation (Note 1, 3) CE fC E 1sC E 2 sO E WE SA LB s (Note 6) UB s (Note 6) DQ 0 to DQ 7 DQ 8 to DQ 15 RESET WP /ACC (Note 5) Full Standby H HX X X X X X HIGH-Z HIGH-Z H X XL Output Disable HL H H H X X X HIGH-Z HIGH-Z HX X X X X X HIGH-Z HIGH-Z L HX H H X X X HIGH-Z HIGH-Z XL Read from Flash (Note 2) L HX LHX X X D OUT D OUT HX XL Write to Flash L HX HLX X X D IN D IN HX XL Read from SRAM H L H L H SA X X D OUT HIGH-Z H X Write to SRAM H L H X L SA X X D IN HIGH-Z H X Temporary Sector Group Unprotection (Note 4) X X X XXX X X X X V ID X Flash Hardware Reset X HX X X X X X HIGH-Z HIGH-Z L X XL Boot Block Sector Write Protection X X X XXX X X X X X L

MB84VD2108X -85/MB84VD2109X -85 Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS , SRAM = Byte mode; CIOs = VSS ) Legend : L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP /ACC = VIL ; protection of boot sectors. WP /ACC = VIH ; removal of boot sectors protection. WP /ACC = VACC (9 V) ; Program time will reduce by 40%. 6. LBS, UBS ; Don’t care or Open. Operation (Note 1, 3) CE fC E 1sC E 2 s DQ 15/ A-1 OE WE SA LB s (Note 6) UB s (Note 6) DQ 0 to DQ 7 DQ 8 to DQ 14 RESET WP / ACC (Note 5) Full Standby H HX X X X X X X HIGH-Z HIGH-Z H X XL Output Disable HL H X H H X X X HIGH-Z HIGH-Z HX X X X X X X HIGH-Z HIGH-Z L HX A-1 H H X X X HIGH-Z HIGH-Z XL Read from Flash (Note 2) L HX A -1 LHX X X D OUT XH X XL Write to Flash L HX A-1 HLX X X D IN XH X XL Read from SRAM HL H XL H S AX X D OUT HIGH-Z H X Write to SRAM HL H X X L S AX X D IN HIGH-Z H X Temporary Sector Group Unprotection (Note 4) X X X X XXX X X X X V ID X Flash Hard- ware Reset X HX X X X X X X HIGH-Z HIGH-Z L X XL Boot Block Sector Write Protection X X X X XXX X X X X X L

MB84VD2108X -85/MB84VD2109X -85 nnnn FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

  • Eight 4 K words, and thirty one 32 K words.
  • Individual-sector, multiple-sector, or bulk-erase capability. Word Mode Byte Mode SA38 : SA37 : SA36 : SA35 : SA34 : SA33 : SA32 : SA31 : SA30 : SA29 : SA28 : SA27 : SA26 : SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : SA14 : SA13 : SA12 : SA11 : SA10 : SA9 : SA8 : SA7 : SA6 : SA5 : SA4 : SA3 : SA2 : SA1 : SA0 : 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) 0FFFFFH 0FF000H 0FE000H 0FD000H 0FC000H 0FB000H 0FA000H 0F9000H 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 000000H 1FFFFFH 1FE000H 1FC000H 1FA000H 1F8000H 1F6000H 1F4000H 1F2000H 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 000000H Bank 1 MB84VD21081 Bank 2 MB84VD21081 Bank 1 MB84VD21082 Bank 1 MB84VD21083 Bank 1 MB84VD21084 Bank 2 MB84VD21082 Bank 2 MB84VD21083 Bank 2 MB84VD21084 MB84VD2108X Sector Architecture (Top Boot Block)

MB84VD2108X -85/MB84VD2109X -85

  • Eight 4 K words, and thirty one 32 K words.
  • Individual-sector, multiple-sector, or bulk-erase capability. Word Mode Byte Mode SA38 : SA37 : SA36 : SA35 : SA34 : SA33 : SA32 : SA31 : SA30 : SA29 : SA28 : SA27 : SA26 : SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : SA14 : SA13 : SA12 : SA11 : SA10 : SA9 : SA8 : SA7 : SA6 : SA5 : SA4 : SA3 : SA2 : SA1 : SA0 : 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (32 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) (4 KW) 0FFFFFH 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 007000H 006000H 005000H 004000H 003000H 002000H 001000H 000000H 1FFFFFH 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 00E000H 00C000H 00A000H 008000H 006000H 004000H 002000H 000000H Bank 1 MB84VD21091 Bank 2 MB84VD21091 Bank 1 MB84VD21092 Bank 1 MB84VD21093 Bank 1 MB84VD21094 Bank 2 MB84VD21092 Bank 2 MB84VD21093 Bank 2 MB84VD21094 MB84VD2109X Sector Architecture (Top Boot Block)

MB84VD2108X -85/MB84VD2109X -85 Table 3.1 Sector Address Tables (MB84VD21081) Bank Sector Sector Address Address Range (Byte mode) Address Range (Word mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 S A 0 00000XXX 0 00000H to 00FFFFH 000000H to 007FFFH S A 1 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 2 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 3 00011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 4 00100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 5 00101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 6 00110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 7 00111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH S A 8 01000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 9 01001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 001010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 101011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 201100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 1 301101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 1 401110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 1 501111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH S A 1 610000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 1 710001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 1 810010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 1 910011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 010100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 110101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 210110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 2 310111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH S A 2 411000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 2 511001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 2 611010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 2 711011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH S A 2 811100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 2 911101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 011110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH Bank 1 S A 3 111111000 1 F 0 0 0 0 H t o 1 F 1 FFFH 0F8000H to 0F8FFFH S A 3 211111001 1 F 2 0 0 0 H t o 1 F 3 FFFH 0F9000H to 0F9FFFH S A 3 311111010 1 F 4 0 0 0 H t o 1 F 5 FFFH 0FA000H to 0FAFFFH S A 3 411111011 1 F 6 0 0 0 H t o 1 F 7 FFFH 0FB000H to 0FBFFFH S A 3 511111100 1 F 8 0 0 0 H t o 1 F 9 FFFH 0FC000H to 0FCFFFH S A 3 611111101 1 F A 0 0 0 H t o 1 F B F F F H 0 F D 0 0 0 H t o 0 F D FFFH S A 3 711111110 1 F C 0 0 0 H t o 1 F D FFFH 0FE000H to 0FEFFFH S A 3 811111111 1 F E 000H to 1FFFFFH 0FF000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.2 Sector Address Tables (MB84VD21091) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 000000H to 001FFFH 000000H to 000FFFH S A 1 00000001 002000H to 003FFFH 001000H to 001FFFH S A 2 00000010 004000H to 005FFFH 002000H to 002FFFH S A 3 00000011 006000H to 007FFFH 003000H to 003FFFH S A 4 00000100 008000H to 009FFFH 004000H to 004FFFH S A 5 00000101 0 0 A 0 0 0 H t o 0 0 B FFFH 005000H to 005FFFH S A 6 00000110 0 0 C 0 0 0 H t o 0 0 D F F F H 0 06000H to 006FFFH S A 7 00000111 0 0 E 000H to 00FFFFH 007000H to 007FFFH Bank 2 S A 8 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 9 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 1 000011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 1 100100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 1 200101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 1 300110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 1 400111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH S A 1 501000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 1 601001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 701010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 801011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 901100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 2 001101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 2 101110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 2 201111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH S A 2 310000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 2 410001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 2 510010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 2 610011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 710100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 810101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 910110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 3 010111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH S A 3 111000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 3 211001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 3 311010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 3 411011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH S A 3 511100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 3 611101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 711110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH S A 3 811111XXX 1 F 0000H to 1FFFFFH 0F8000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.3 Sector Address Tables (MB84VD21082) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 S A 0 00000XXX 0 00000H to 00FFFFH 000000H to 007FFFH S A 1 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 2 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 3 00011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 4 00100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 5 00101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 6 00110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 7 00111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH S A 8 01000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 9 01001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 001010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 101011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 201100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 1 301101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 1 401110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 1 501111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH S A 1 610000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 1 710001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 1 810010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 1 910011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 010100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 110101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 210110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 2 310111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH S A 2 411000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 2 511001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 2 611010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 2 711011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH Bank 1 S A 2 811100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 2 911101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 011110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH S A 3 111111000 1 F 0 0 0 0 H t o 1 F 1 FFFH 0F8000H to 0F8FFFH S A 3 211111001 1 F 2 0 0 0 H t o 1 F 3 FFFH 0F9000H to 0F9FFFH S A 3 311111010 1 F 4 0 0 0 H t o 1 F 5 FFFH 0FA000H to 0FAFFFH S A 3 411111011 1 F 6 0 0 0 H t o 1 F 7 FFFH 0FB000H to 0FBFFFH S A 3 511111100 1 F 8 0 0 0 H t o 1 F 9 FFFH 0FC000H to 0FCFFFH S A 3 611111101 1 F A 0 0 0 H t o 1 F B F F F H 0 F D 0 0 0 H t o 0 F D FFFH S A 3 711111110 1 F C 0 0 0 H t o 1 F D FFFH 0FE000H to 0FEFFFH S A 3 811111111 1 F E 000H to 1FFFFFH 0FF000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.4 Sector Address Tables (MB84VD21092) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 0 00000H to 001FFFH 000000H to 000FFFH S A 1 00000001 0 02000H to 003FFFH 001000H to 001FFFH S A 2 00000010 0 04000H to 005FFFH 002000H to 002FFFH S A 3 00000011 0 06000H to 007FFFH 003000H to 003FFFH S A 4 00000100 0 08000H to 009FFFH 004000H to 004FFFH S A 5 00000101 0 0 A 000H to 00BFFFH 005000H to 005FFFH S A 6 00000110 0 0 C 000H to 00DFFFH 006000H to 006FFFH S A 7 00000111 0 0 E 0 0 0 H t o 0 0 FFFFH 007000H to 007FFFH SA8 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA9 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA10 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH Bank 2 SA11 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA12 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA13 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA14 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA15 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA16 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA17 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA18 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA19 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA20 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA21 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA22 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA23 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA24 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA25 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA26 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA27 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA28 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA29 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA30 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA31 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA32 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA33 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA34 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA35 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA36 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA37 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA38 1 1 1 1 1 X X X 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.5 Sector Address Tables (MB84VD21083) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 S A 0 00000XXX 0 00000H to 00FFFFH 000000H to 007FFFH S A 1 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 2 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 3 00011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 4 00100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 5 00101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 6 00110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 7 00111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH S A 8 01000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 9 01001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 001010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 101011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 201100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 1 301101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 1 401110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 1 501111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH S A 1 610000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 1 710001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 1 810010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 1 910011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 010100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 110101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 210110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 2 310111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH Bank 1 S A 2 411000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 2 511001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 2 611010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 2 711011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH S A 2 811100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 2 911101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 011110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH S A 3 111111000 1 F 0 0 0 0 H t o 1 F 1 FFFH 0F8000H to 0F8FFFH S A 3 211111001 1 F 2 0 0 0 H t o 1 F 3 FFFH 0F9000H to 0F9FFFH S A 3 311111010 1 F 4 0 0 0 H t o 1 F 5 FFFH 0FA000H to 0FAFFFH S A 3 411111011 1 F 6 0 0 0 H t o 1 F 7 FFFH 0FB000H to 0FBFFFH S A 3 511111100 1 F 8 0 0 0 H t o 1 F 9 FFFH 0FC000H to 0FCFFFH S A 3 611111101 1 F A 0 0 0 H t o 1 F B F F F H 0 F D 0 0 0 H t o 0 F D FFFH S A 3 711111110 1 F C 0 0 0 H t o 1 F D FFFH 0FE000H to 0FEFFFH S A 3 811111111 1 F E 000H to 1FFFFFH 0FF000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.6 Sector Address Tables (MB84VD21093) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 000000H to 001FFFH 000000H to 000FFFH S A 1 00000001 002000H to 003FFFH 001000H to 001FFFH S A 2 00000010 004000H to 005FFFH 002000H to 002FFFH S A 3 00000011 006000H to 007FFFH 003000H to 003FFFH S A 4 00000100 008000H to 009FFFH 004000H to 004FFFH S A 5 00000101 0 0 A 0 0 0 H t o 0 0 B FFFH 005000H to 005FFFH S A 6 00000110 0 0 C 0 0 0 H t o 0 0 D F F F H 0 06000H to 006FFFH S A 7 00000111 0 0 E 000H to 00FFFFH 007000H to 007FFFH S A 8 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 9 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 1 000011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 1 100100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 1 200101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 1 300110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 1 400111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH Bank 2 S A 1 501000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 1 601001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 701010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 801011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 901100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 2 001101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 2 101110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 2 201111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH S A 2 310000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 2 410001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 2 510010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 2 610011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 710100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 810101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 910110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 3 010111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH S A 3 111000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 3 211001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 3 311010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 3 411011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH S A 3 511100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 3 611101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 711110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH S A 3 811111XXX 1 F 0000H to 1FFFFFH 0F8000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.7 Sector Address Tables (MB84VD21084) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 2 S A 0 00000XXX 0 00000H to 00FFFFH 000000H to 007FFFH S A 1 00001XXX 0 10000H to 01FFFFH 008000H to 00FFFFH S A 2 00010XXX 0 20000H to 02FFFFH 010000H to 017FFFH S A 3 00011XXX 0 30000H to 03FFFFH 018000H to 01FFFFH S A 4 00100XXX 0 40000H to 04FFFFH 020000H to 027FFFH S A 5 00101XXX 0 50000H to 05FFFFH 028000H to 02FFFFH S A 6 00110XXX 0 60000H to 06FFFFH 030000H to 037FFFH S A 7 00111XXX 0 70000H to 07FFFFH 038000H to 03FFFFH S A 8 01000XXX 0 80000H to 08FFFFH 040000H to 047FFFH S A 9 01001XXX 0 90000H to 09FFFFH 048000H to 04FFFFH S A 1 001010XXX 0 A 0000H to 0AFFFFH 050000H to 057FFFH S A 1 101011XXX 0 B 0000H to 0BFFFFH 058000H to 05FFFFH S A 1 201100XXX 0 C 0000H to 0CFFFFH 060000H to 067FFFH S A 1 301101XXX 0 D 0000H to 0DFFFFH 068000H to 06FFFFH S A 1 401110XXX 0 E 0000H to 0EFFFFH 070000H to 077FFFH S A 1 501111XXX 0 F 0000H to 0FFFFFH 078000H to 07FFFFH Bank 1 S A 1 610000XXX 1 00000H to 10FFFFH 080000H to 087FFFH S A 1 710001XXX 1 10000H to 11FFFFH 088000H to 08FFFFH S A 1 810010XXX 1 20000H to 12FFFFH 090000H to 097FFFH S A 1 910011XXX 1 30000H to 13FFFFH 098000H to 09FFFFH S A 2 010100XXX 1 40000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 110101XXX 1 50000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 210110XXX 1 60000H to 16FFFFH 0B0000H to 0B7FFFH S A 2 310111XXX 1 70000H to 17FFFFH 0B8000H to 0BFFFFH S A 2 411000XXX 1 80000H to 18FFFFH 0C0000H to 0C7FFFH S A 2 511001XXX 1 90000H to 19FFFFH 0C8000H to 0CFFFFH S A 2 611010XXX 1 A 0000H to 1AFFFFH 0D0000H to 0D7FFFH S A 2 711011XXX 1 B 0000H to 1BFFFFH 0D8000H to 0DFFFFH S A 2 811100XXX 1 C 0000H to 1CFFFFH 0E0000H to 0E7FFFH S A 2 911101XXX 1 D 0000H to 1DFFFFH 0E8000H to 0EFFFFH S A 3 011110XXX 1 E 0000H to 1EFFFFH 0F0000H to 0F7FFFH S A 3 111111000 1 F 0 0 0 0 H t o 1 F 1 FFFH 0F8000H to 0F8FFFH S A 3 211111001 1 F 2 0 0 0 H t o 1 F 3 FFFH 0F9000H to 0F9FFFH S A 3 311111010 1 F 4 0 0 0 H t o 1 F 5 FFFH 0FA000H to 0FAFFFH S A 3 411111011 1 F 6 0 0 0 H t o 1 F 7 FFFH 0FB000H to 0FBFFFH S A 3 511111100 1 F 8 0 0 0 H t o 1 F 9 FFFH 0FC000H to 0FCFFFH S A 3 611111101 1 F A 0 0 0 H t o 1 F B F F F H 0 F D 0 0 0 H t o 0 F D FFFH S A 3 711111110 1 F C 0 0 0 H t o 1 F D FFFH 0FE000H to 0FEFFFH S A 3 811111111 1 F E 000H to 1FFFFFH 0FF000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 3.8 Sector Address Tables (MB84VD21094) Bank Sector Sector Address Address Range (BYTE mode) Address Range (WORD mode) Bank Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Bank 1 S A 0 00000000 0 0 0 000H to 001FFFH 000000H to 000FFFH S A 1 00000001 0 0 2 000H to 003FFFH 001000H to 001FFFH S A 2 00000010 0 0 4 000H to 005FFFH 002000H to 002FFFH S A 3 00000011 0 0 6 000H to 007FFFH 003000H to 003FFFH S A 4 00000100 0 0 8 000H to 009FFFH 004000H to 004FFFH S A 5 00000101 0 0 A 000H to 00BFFFH 005000H to 005FFFH S A 6 00000110 0 0 C 000H to 00DFFFH 006000H to 006FFFH S A 7 00000111 0 0 E 0 0 0 H t o 0 0 F F F F H 007000H to 007FFFH S A 8 00001XXX 010000H to 01FFFFH 008000H to 00FFFFH S A 9 00010XXX 020000H to 02FFFFH 010000H to 017FFFH S A 1 000011XXX 030000H to 03FFFFH 018000H to 01FFFFH S A 1 100100XXX 040000H to 04FFFFH 020000H to 027FFFH S A 1 200101XXX 050000H to 05FFFFH 028000H to 02FFFFH S A 1 300110XXX 060000H to 06FFFFH 030000H to 037FFFH S A 1 400111XXX 070000H to 07FFFFH 038000H to 03FFFFH S A 1 501000XXX 080000H to 08FFFFH 040000H to 047FFFH S A 1 601001XXX 090000H to 09FFFFH 048000H to 04FFFFH S A 1 701010XXX 0 A 0 0 0 0 H t o 0 A F F F F H 050000H to 057FFFH S A 1 801011XXX 0 B 0 0 0 0 H t o 0 B F F F F H 0 58000H to 05FFFFH S A 1 901100XXX 0 C 0 0 0 0 H t o 0 C FFFFH 060000H to 067FFFH S A 2 001101XXX 0 D 0 0 0 0 H t o 0 D FFFFH 068000H to 06FFFFH S A 2 101110XXX 0 E 0 0 0 0 H t o 0 E F F F F H 070000H to 077FFFH S A 2 201111XXX 0 F 0 0 0 0 H t o 0 FFFFFH 078000H to 07FFFFH Bank 2 S A 2 310000XXX 100000H to 10FFFFH 080000H to 087FFFH S A 2 410001XXX 110000H to 11FFFFH 088000H to 08FFFFH S A 2 510010XXX 120000H to 12FFFFH 090000H to 097FFFH S A 2 610011XXX 130000H to 13FFFFH 098000H to 09FFFFH S A 2 710100XXX 140000H to 14FFFFH 0A0000H to 0A7FFFH S A 2 810101XXX 150000H to 15FFFFH 0A8000H to 0AFFFFH S A 2 910110XXX 160000H to 16FFFFH 0B0000H to 0B7FFFH S A 3 010111XXX 170000H to 17FFFFH 0B8000H to 0BFFFFH S A 3 111000XXX 180000H to 18FFFFH 0C0000H to 0C7FFFH S A 3 211001XXX 190000H to 19FFFFH 0C8000H to 0CFFFFH S A 3 311010XXX 1 A 0 0 0 0 H t o 1 A F F F F H 0 D 0 0 0 0 H t o 0 D 7 F F F H S A 3 411011XXX 1 B 0 0 0 0 H t o 1 B F F F F H 0 D 8000H to 0DFFFFH S A 3 511100XXX 1 C 0 0 0 0 H t o 1 C FFFFH 0E0000H to 0E7FFFH S A 3 611101XXX 1 D 0 0 0 0 H t o 1 D FFFFH 0E8000H to 0EFFFFH S A 3 711110XXX 1 E 0 0 0 0 H t o 1 E F F F F H 0 F 0 0 0 0 H t o 0 F 7 FFFH S A 3 811111XXX 1 F 0 0 0 0 H t o 1 FFFFFH 0F8000H to 0FFFFFH

MB84VD2108X -85/MB84VD2109X -85 Table 4.1 Sector Group Addresses (MB84VD2108X) (Top Boot Block) Sector Group A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors S G A 0 00000XXX S A 0 SGA1 00001XXX SA1 to SA300010XXX 00011XXX S G A 2 001XXXXXS A 4 t o S A 7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 SGA8 11100XXX SA28 to SA3011101XXX 11110XXX S G A 9 11111000 S A 3 1 S G A 1 011111001 S A 3 2 S G A 1 111111010 S A 3 3 S G A 1 211111011 S A 3 4 S G A 1 311111100 S A 3 5 S G A 1 411111101 S A 3 6 S G A 1 511111110 S A 3 7 S G A 1 611111111 S A 3 8

MB84VD2108X -85/MB84VD2109X -85 Table 4.2 Sector Group Addresses (MB84VD2109X) (Bottom Boot Block) Sector Group A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Sectors S G A 0 00000000 S A 0 S G A 1 00000001 S A 1 S G A 2 00000010 S A 2 S G A 3 00000011 S A 3 S G A 4 00000100 S A 4 S G A 5 00000101 S A 5 S G A 6 00000110 S A 6 S G A 7 00000111 S A 7 SGA8 00001XXX SA8 to SA1000010XXX 00011XXX SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 SGA15 11100XXX SA35 to SA3711101XXX 11110XXX SGA16 1 1 1 1 1 X X X SA38

MB84VD2108X -85/MB84VD2109X -85 Table 5 Flash Memory Autoselect Codes *1 : A-1 is for Byte mode. *2 : Output 01H at protected sector address and output 00H at unprotected sector address. Type A 12 to A19 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacturer’s Code X V IL VIL VIL VIL 04H Device Code MB84VD21081 Byte XV IL VIL VIH VIL 36H Word X 2236H MB84VD21091 Byte XV IL VIL VIH VIL 39 Word X 2239H MB84VD21082 Byte XV IL VIL VIH VIL 2D Word X 222DH MB84VD21092 Byte XV IL VIL VIH VIL 2E Word X 222EH MB84VD21083 Byte XV IL VIL VIH VIL 28H Word X 2228H MB84VD21093 Byte XV IL VIL VIH VIL 2BH Word X 222BH MB84VD21084 Byte XV IL VIL VIH VIL 33H Word X 2233H MB84VD21094 Byte XV IL VIL VIH VIL 35 Word X 2235H Sector Group protect Sector Group Address VIL VIH VIL VIL 01H*2

MB84VD2108X -85/MB84VD2109X -85 Table 6 Flash Memory Command Definitions Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Read/Reset (Note 1) 1 XXXH F0H ¾ ¾ ¾ ¾¾¾¾¾¾¾ Read/Reset (Note 1) Word 555H AAH 2AAH 55H 555H F0H RA RD ¾¾¾¾ Byte AAAH 555H AAAH Autoselect Word 555H AAH 2AAH 55H (BA) 555H 90H ¾¾¾¾¾¾ Byte AAAH 555H (BA) AAAH Program Word 555H AAH 2AAH 55H 555H A0H PA PD ¾¾¾¾ Byte AAAH 555H AAAH Chip Erase Word 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte AAAH 555H AAAH AAAH 555H AAAH Sector Erase Word 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte AAAH 555H AAAH AAAH 555H Sector Erase Suspend 1 BA B0H ¾ ¾ ¾ ¾¾¾¾¾¾¾ Sector Erase Resume 1 BA 30H ¾ ¾ ¾ ¾¾¾¾¾¾¾ Set to Fast Mode Word 555H AAH 2AAH 55H 555H 20H ¾¾¾¾¾¾ Byte AAAH 555H AAAH Fast Program (Note 2) Word

2 XXXH A0H PA PD ¾ ¾¾¾¾¾¾¾

(Note 2) Word

2 BA 90H XXXH F0H

(Note6) ¾ ¾¾¾¾¾¾¾ Byte Extended Sector Group Protection (Note 3) Word

4 XXXH 60H SPA 60H SPA 40H SPA SD ¾¾¾¾

(Note 4) Word 55H 98H ¾ ¾ ¾ ¾¾¾¾¾¾¾ Byte AAH Hi-ROM Entry Word 555H AAH 2AAH 55H 555H 88H ¾¾¾¾¾¾ Byte AAAH 555H AAAH Hi-ROM Program (Note 5) Word 555H AAH 2AAH 55H 555H A0H PA PD ¾¾¾¾ Byte AAAH 555H AAAH Hi-ROM Erase (Note 5) Word 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H HRA 30H Byte AAAH 555H AAAH AAAH 555H Hi-ROM Exit (Note 5) Word 555H AAH 2AAH 55H (HRBA) 555H 90H XXXH 00H ¾¾¾¾ Byte AAAH 555H (HRBA) AAAH

MB84VD2108X -85/MB84VD2109X -85 1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2 : This command is valid while Fast Mode. 3 : This command is valid while RESET = VID. 4 : The valid Address is A0 to A6. 5 : This command is valid while Hi-ROM mode. 6 : The data “00H” is also acceptable. Address bits A12 to A19 = X = “H” or “L” for all address commands except for Program Address (P A) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in T able 2 “User Bus Operations”. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A 19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A15 to A19) SP A = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) . HRA = Address of the Hidden-ROM area. MB84VD2108X (T op Boot T ype) Word mode : 0F8000H to 0FFFFFH Byte mode : 1F0000H to 1FFFFFH MB84VD2109X (Bottom Boot T ype) Word mode : 000000H to 007FFFH Byte mode : 000000H to 00FFFFH HRBA = Bank address of the Hidden-ROM area. MB84VD2108X (T op Boot T ype) : A15 = A16 = A17 = A18 = A19 = A20 = 1 MB84VD2109X (Bottom Boot T ype) : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location P A. SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotectedsector addresses. The system should generate the following address patterns; Word mode : 555H or 2AAH to addresses A0 to A10 Byte mode : AAAH or 555H to addresses A-1 and A0 to A10

MB84VD2108X -85/MB84VD2109X -85 nnnn ABSOLUTE MAXIMUM RATINGS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Notes 1. Minimum DC voltage on input or I/O pins is –0.3 V . During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC f V for periods of up to 20 ns. 2. Minimum DC input voltage on A9 and OE pin is –0.3 V . Minimum DC input voltage on RESET pin is –0.5 V . During voltage transitions, A9, OE, and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-V CC f or VCC s) does not exceed 9.0 V . Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. 3. Minimum DC input voltage on WP/ACC pin is –0.5 V . During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to 12.0 V for periods of up to 20 ns, when VCC f is applied. nnnn RECOMMENDED OPERATING RANGES Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min. Max. Storage Temperature Tstg -55 +125 °C Ambient Temperature with Power Applied T A -25 +85 °C Voltage with Respect to Ground All pins except A9, OE, RESET, WP /ACC (Note 1) VIN, VOUT -0.3 VCC f +0.4 V VCC s +0.4 VCC f/VCC s Supply (Note 1) V CC f, VCC s -0.3 +4.0 V A9 and OE (Note 2) V IN -0.3 +13.0 V RESET (Note 2) V IN -0.5 +13.0 V WP /ACC (Note 3) V IN -0.5 +10.5 V Parameter Symbol Value Unit Min. Max. Ambient T emperature T A -25 +85 °C VCC f/VCC s Supply Voltages V CC f, VCC s +2.7 +3.6 V

MB84VD2108X -85/MB84VD2109X -85 nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics (Continued) Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit ILI Input Leakage Current V IN = VSS to VCC f, VCC s -1.0 ¾+ 1.0 mA ILO Output Leakage Current VOUT = VSS to VCC f, VCC s -1.0 ¾+ 1.0 mA ILIT RESET Inputs Leakage Current VCC f = VCC f Max., VCC s = VCC s Max., RESET = 12.5 V ¾¾ 35 mA ILIA ACC Input Leakage Current VCC f = VCC f Max., VCC s = VCC s Max., WP /ACC = VACC Max. ¾¾ 20 mA ICC1 f Flash VCC Active Current (Read) (Note 1) CE f = VIL, OE = VIH tCYCLE = 5 MHz Byte ¾¾ 13 mA tCYCLE = 5 MHz Word ¾¾ 15 tCYCLE = 1 MHz Byte ¾¾ 7 mA tCYCLE = 1 MHz Word ¾¾ 7 ICC2 f Flash VCC Active Current (Program/Erase) (Note 2) CE f = VIL, OE = VIH ¾¾ 35 mA ICC3 f Flash VCC Active Current (Read-While-Program) (Note 5) CE f = VIL, OE = VIH Byte ¾¾ 48 mA Word ¾¾ 50 ICC4 f Flash VCC Active Current (Read-While-Erase) (Note 5) CE f = VIL, OE = VIH Byte ¾¾ 48 mA Word ¾¾ 50 ICC5 f Flash VCC Active Current (Erase-Suspend-Program) CE f = VIL, OE = VIH ¾¾ 35 mA ICC1 sS R A M VCC Active Current VCC s = VCC Max., CE1 s = VIL, CE2s = VIH tCYCLE = 10 MHz ¾¾ 50 mA ICC2 sS R A M VCC Active CurrentCE1 s = 0.2 V, CE2s = VCC s - 0.2 V tCYCLE = 10 MHz ¾¾ 40 mA tCYCLE = 1 MHz ¾¾ 8m A ISB1 fF l a s h VCC Standby Current VCC f = VCC Max., CEf = VCC f – 0.3 V RESET = VCC f – 0.3 V, WP /ACC = VCC f – 0.3 V ¾ 15 mA ISB2 f Flash VCC Standby Current (RESET ) VCC f = VCC Max., RESET = VSS – 0.3 V, WP /ACC = VCC f – 0.3 V ¾ 15 mA ISB3 f Flash VCC Current (Automatic Sleep Mode) (Note 3) V CC f = VCC Max., CEf = VSS – 0.3 V RESET = VCC f – 0.3 V, WP /ACC = VCC f – 0.3 V VIN = VCC f – 0.3 V or VSS – 0.3 V ¾ 15 mA ISB1 sS R A M VCC Standby Current CE1s ‡ VCC s - 0.2 V, CE2s ‡ VCC s - 0.2 V ¾ 0.2 7 mA ISB2 sS R A M VCC Standby Current CE2s £ 0.2 V ¾ 0.2 7 mA

MB84VD2108X -85/MB84VD2109X -85 (Continued) *: VCC indicates lower of VCC f or VCC s Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. Applicable for only V CC f applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz) Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit VIL Input Low Level ¾- 0.3 ¾ 0.5 V VIH Input High Level ¾ 2.4 ¾ VCC +0.3* V VID Voltage for Sector Protection, and Temporary Sector Unprotection (RESET ) (Note 4) ¾ 11.5 ¾ 12.5 V VACC Voltage for Program Acceleration (WP/ACC) (Note4) ¾ 8.5 9.0 9.5 V VOL Output Low Voltage LevelVCC f = VCC f Min., VCC s = VCC s Min., IOL = 1.0 mA ¾¾ 0.4 V VOH Output High Voltage LevelVCC f = VCC f Min., VCC s = VCC s Min., IOH = -0.5 mA 2.4 ¾¾ V VLKO Flash Low VCC f Lock-Out Voltage ¾ 2.3 ¾ 2.5 V

MB84VD2108X -85/MB84VD2109X -85 2. AC Characteristics

  • CE Timing
  • Timing Diagram for alternating SRAM to Flash Parameter Symbols Description Test Setup -85 Unit JEDEC Standard ¾ tCCR CE Recover Time ¾ Min. 0 ns tCCR tCCR tCCR tCCR CEf CE1s CE2s

MB84VD2108X -85/MB84VD2109X -85

  • Read Only Operations Characteristics (Flash) Note : T est Conditions-Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V Parameter Symbols Description Test Setup -85 (Note) Unit JEDEC Standard Min. Max. t AVAV tRC Read Cycle Time ¾ 85 ¾ ns tAVQV tACC Address to Output Delay CE f = VIL OE = VIL ¾ 85 ns tELQV tCE f Chip Enable to Output Delay OE = VIL ¾ 85 ns tGLQV tOE Output Enable to Output Delay ¾¾ 35 ns tEHQZ tDF Chip Enable to Output High-Z ¾¾ 30 ns tGHQZ tDF Output Enable to Output High-Z ¾¾ 30 ns tAXQX tOH Output Hold Time From Addresses, CE f or OE, Whichever Occurs First ¾ 0 ¾ ns ¾ tREADY RESET Pin Low to Read Mode ¾¾ 20 ms

MB84VD2108X -85/MB84VD2109X -85

  • Read Cycle (Flash) Addresses CEf OE WE DQ Output Valid Addresses Stable tRC tACC tOE tDF tOEH tCE f HIGH-Z HIGH-Z Addresses CEf RESET DQ Output Valid Addresses Stable tRC tACCtRH tCE ftRHtRP tOH HIGH-Z

MB84VD2108X -85/MB84VD2109X -85

  • Erase/Program Operations (Flash) (Continued) Parameter Symbols

Description

-85 Unit JEDEC Standard Min. Typ. Max. tAVAV tWC Write Cycle Time 85 ¾¾ ns tAVWL tAS Address Setup Time (WE to Addr.) 0 ¾¾ ns ¾ tASO Address Setup Time to CEf Low During Toggle Bit Polling 15¾¾ ns tWLAX tAH Address Hold Time (WE to Addr.) 45 ¾¾ ns ¾ tAHT Address Hold Time from CEf or OE High During Toggle Bit Polling 0 ¾¾ ns tDVWH tDS Data Setup Time 35 ¾¾ ns tWHDX tDH Data Hold Time 0 ¾¾ ns ¾ tOES Output Enable Setup Time 0 ¾¾ ns ¾ tOEH Output Enable Hold Time Read 0 ¾¾ ns Toggle and Data Polling 10 ¾¾ ns ¾ tCEPH CE f High During Toggle Bit Polling 20 ¾¾ ns ¾ tOEPH OE High During Toggle Bit Polling 20 ¾¾ ns tGHEL tGHEL Read Recover Time Before Write (OE to CEf) 0 ¾¾ ns tGHWL tGHWL Read Recover Time Before Write (OE to WE) 0 ¾¾ ns tWLEL tWS WE Setup Time (CEf to WE) 0 ¾¾ ns tELWL tCS CE f Setup Time (WE to CEf) 0 ¾¾ ns tEHWH tWH WE Hold Time (CEf to WE) 0 ¾¾ ns tWHEH tCH CE f Hold Time (WE to CEf) 0 ¾¾ ns tWLWH tWP Write Pulse Width 35 ¾¾ ns tELEH tCP CE f Pulse Width 35 ¾¾ ns tWHWL tWPH Write Pulse Width High 30 ¾¾ ns tEHEL tCPH CE f Pulse Width High 30 ¾¾ ns tWHWH1 tWHWH1 Byte Programming Operation ¾ 8 ¾m s Word Programming Operation ¾ 16 ¾m s tWHWH2 tWHWH2 Sector Erase Operation (Note 1) ¾ 1 ¾ s

MB84VD2108X -85/MB84VD2109X -85 (Continued) Notes : 1.This does not include the preprogramming time. 2.This timing is for Sector Protection Operation. 3.The time between writes must be less than “t TOW ” otherwise that command will not be accepted and erasure will start. A time-out or “tTOW ” from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . 4.When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD ” to suspend the erase operation. Parameter Symbols -85 Unit JEDEC Standard Min. Typ. Max. ¾ tVCS VCC f Setup Time 50 ¾¾ m s ¾ tVLHT Voltage Transition Time (Note 2) 4 ¾¾ m s ¾ tVIDR Rise Time to VID (Note 2) 500 ¾¾ ns ¾ tVACCR Rise Time to VACC 500 ¾¾ ns ¾ tRB Recover Time from RY/BY 0 ¾¾ ns ¾ tRP RESET Pulse Width 500 ¾¾ ns ¾ tEOE Delay Time from Embedded Output Enable ¾¾ 85 ns ¾ tRH RESET High Level Period Before Read 200 ¾¾ ns ¾ tBUSY Program/Erase Valid to RY/BY Delay ¾¾ 90 ns ¾ tTOW Erase Time-out Time (Note 3) 50 ¾¾ m s ¾ tSPD Erase Suspend Transition Time (Note 4) ¾¾ 20 ms

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (WE control) (Flash) Addresses WE OE CEf DQ 3rd Bus Cycle 555H A0H PD DQ 7 D OUT D OUT PA PA Data Polling tWC tCS tWP tDS tDH tOH tOE tCE f tWPH tWHWH1 tGHWL tCH tAS tAH tRC Notes : 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ 7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (CEf control) (Flash) Addresses WE OE CEf DQ 3rd Bus Cycle 555H A0H PD DQ 7 D OUT PA PA Data Polling tWC tWS tCP tDS tDH tCPH tWHWH1 tGHEL tWH tAS tAH Notes : 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ 7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

MB84VD2108X -85/MB84VD2109X -85

  • AC Waveforms Chip/Sector Erase Operations (Flash) 555H 2AAH 2AAH 555H 555H tWC tGHWL tAS tAH SA *Addresses WE OE CEf DQ VCC f tCS tCH tVCS tWPHtWP tDS tDH AAH 55H 80H AAH 55H 10H/ 30H 30H for Sector Erase Note : These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.) * : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.

MB84VD2108X -85/MB84VD2109X -85

  • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) WE OE CEf DQ 7 DQ (DQ 0 to DQ6) RY/BY Data In Data In DQ 7 = Valid Data DQ 0 to DQ6 Valid Data tEOE DQ 7 DQ 0 to DQ6 = Output Flag tCH tOE tDF tOEH tCE f tWHWH1 or 2 tBUSY High-Z High-Z * : DQ7 = Valid Data (The device has completed the Embedded operation.)

MB84VD2108X -85/MB84VD2109X -85

  • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Addresses WE CEf OE DQ 6/DQ2 RY/BY Toggle DataData Toggle Data Toggle Data Stop Toggling Output Valid tDH tOEH tOEPH tBUSY tOE tCE f* tOEH tAHT tCEPH tAStAHT tASO * : DQ6 stops toggling (The device has completed the Embedded operation) .

MB84VD2108X -85/MB84VD2109X -85

  • Back-to-back Read/Write Timing Diagram (Flash) Address WE OE CEf DQ Valid Output Valid Input (A0H) Valid Output Valid Output StatusValid Input (PD) tRC tAS tWC tRC tWC tRC tAS tAHT tCEPH tRC Read Command Read Command Read Read BA1 BA2 (555H) BA2 (PA) BA2 (PA)BA1 BA1 tAH tCE f tOE tGHWL tOEH tDF tDF tWP tDS tDH tACC Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address of Bank 1. BA2 : Address of Bank 2.

MB84VD2108X -85/MB84VD2109X -85

  • RY/BY Timing Diagram during Write/Erase Operations (Flash)
  • RESET , RY/BY Timing Diagram (Flash) The rising edge of the last write pulse Entire programming or erase operations tBUSY RY/BY WE CEf RY/BY RESET WE tREADY tRP tRB

MB84VD2108X -85/MB84VD2109X -85

  • Temporary Sector Unprotection (Flash) RY/BY RESET VCC f 3 V 3 V CEf WE VID Program or Erase Command Sequence Unprotection Period tVCS tVIDR tVLHT tVLHT tVLHT

MB84VD2108X -85/MB84VD2109X -85

  • Extended Sector Protection (Flash) VCC f RESET Address CEf Data 60H 60H 40H 01H 60H tVCS tVIDR tVLHT tWC tWC tWP TIME - OUT tOE SGAx SGAx SGAy OE WE SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 ms (min.)

MB84VD2108X -85/MB84VD2109X -85

  • Accelerated Program (Flash) 3 V WP/ACC VCC CE WE RY/BY tVLHT Program or Erase Command Sequence 3 V tVLHT tVCS tVACCR VACC tVLHT Acceleration period

MB84VD2108X -85/MB84VD2109X -85

  • Read Cycle (SRAM ) Parameter Symbol Parameter Description Min. Max. Unit tRC Read Cycle Time 85 ¾ ns tAA Address Access Time ¾ 85 ns tCO1 Chip Enable (CE1s) Access Time ¾ 85 ns tCO2 Chip Enable (CE2s) Access Time ¾ 85 ns tOE Output Enable Access Time ¾ 45 ns tBA UB S, LBS to Output Valid ¾ 85 ns tCOE Chip Enable (CE1s Low and CE2s High) to Output Active 5 ¾ ns tOEE Output Enable Low to Output Active 0 ¾ ns tBE UB S, LBS Enable Low to Output Active 0 ¾ ns tOD Chip Enable (CE1s High or CE2s Low) to Output High-Z ¾ 35 ns tODO Output Enable High to Output High-Z ¾ 35 ns tBD UB S, LBS Output Enable to Output High-Z ¾ 35 ns tOH Output Data Hold Time 10 ¾ ns

MB84VD2108X -85/MB84VD2109X -85

  • Read Cycle (Note) (SRAM) Note : WE remains HIGH for the read cycle. Addresses OE CE2s CE1s LBs, UBs DQ tRC tOH tOD tOD tODO tBD tAA tCO1 tCO2 tOE tOEE tBA tBE tCOE tCOE VALID DATA OUT

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit tWC Write Cycle Time 85 ¾ ns tWP Write Pulse Width 55 ¾ ns tCW Chip Enable to End of Write 70 ¾ ns tAW Address valid to End of Write 70 ¾ ns tBW UB S, LBS to End of Write 55 ¾ ns tAS Address Setup Time 0 ¾ ns tWR Write Recovery Time 0 ¾ ns tODW WE Low to Output High-Z ¾ 35 ns tOEW WE High to Output Active 0 ¾ ns tDS Data Setup Time 35 ¾ ns tDH Data Hold Time 0 ¾ ns

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (Note 3) (WE control) (SRAM) tWC tAS tWP tWR tAW tCW tCW tBW tODW tDS tDH tOEW Addresses WE LBs, UBs CE1s CE2s D OUT D IN Note 1 Note 2 Note 4Note 4 VALID DATA IN Notes : 1.If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 2.If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 3.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 4.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (Note 1) (CE1s control) (SRAM) tWC tAS tWP tWR tAW tCW tCW tBW tODW tDS tDH tCOE tBE VALID DATA IN Addresses WE LBs, UBs CE1s CE2s D OUT D IN Note 2 Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (Note 1) (CE2s Control) (SRAM) Addresses WE CE1s CE2s LBs, UBs D OUT D IN Note 2 VALID DATA IN tDS tODWtCOE tBE tBW tCW tCW tWP tWC tAS tWR tAW tDH Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.

MB84VD2108X -85/MB84VD2109X -85

  • Write Cycle (Note 1) (LBS, UBS Control) (SRAM) Addresses WE CE1s CE2s LBs, UBs D OUT D IN VALID DATA IN tDS tODWtCOE tBE tBWtAS tAW tCW tCW tWP tWC tWR tDH Note 2 Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.

MB84VD2108X -85/MB84VD2109X -85 nnnn ERASE AND PROGRAMMING PERFORMANCE ( Flash) nnnn DATA RETENTION CHARACTERISTICS ( SRAM ) Note : tRC : Read cycle time * : 1 mA Max. at TA £ 40 °C

  • CE1 s Controlled Data Retention Mode (Note 1) Parameter Limits Unit Comment Min. Typ. Max. Sector Erase Time ¾ 11 0 s Excludes programming time prior to erasure Byte Programming Time ¾ 8 300 ms Excludes system-level overhead Word Programming Time ¾ 16 360 ms Excludes system-level overhead Chip Programming Time ¾¾ 50 s Excludes system-level overhead Erase/Program Cycle 100,000 ¾¾ cycle Parameter Symbol Parameter Description Min. Typ. Max. Unit VDH Data Retention Supply Voltage 1.5 ¾ 3.6 V IDDS2 Standby Current V DH = 3.0 V ¾ 0.2 5* mA tCDR Chip Deselect to Data Retention Mode Time 0 ¾¾ ns tR Recovery Time t RC ¾¾ ns DATA RETENTION MODE See Note 2See Note 2 tRtCDR VCCS -0.2 V VCC s VIH VDH CE1s 2.7 V GND

MB84VD2108X -85/MB84VD2109X -85

  • CE2s Controlled Data Retention Mode (Note 3) Notes : 1.In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V and Vccs + 0.3 V . 2.When CE1s is operating at the VIH min. level (2.2 V) , the standby current is given by ISB1 s during the transition of VCC s from 3.6 to 2.2 V . 3.In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V and Vccs + 0.3 V . nnnn PIN CAPACITANCE Note : T est conditions TA = 25 °C, f = 1.0 MHz nnnn HANDLING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. nnnn CAUTION 1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector using “Extended sector protect” command. Parameter Symbol Parameter Description Test Setup Typ. Max. Unit C IN Input Capacitance V IN = 01 1 1 4 p F C OUT Output Capacitance V OUT = 01 2 1 6 p F C IN2 Control Pin Capacitance V IN = 01 4 1 6 p F C IN3 WP /ACC Pin Capacitance V IN = 01 7 2 0 p F 0.2 V DATA RETENTION MODEVCC s CE2s VDH VIH VIL tCDR tR GND 2.7 V

MB84VD2108X -85/MB84VD2109X -85 nnnn ORDERING INFORMATION MB84VD2108 X -85 -PBS DEVICE NUMBER/DESCRIPTION

16 Mega-bit (2 M · 8-bit or 1 M · 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

2 Mega-bit (256 K · 8-bit or 128 K · 16-bit) SRAM

BOOT CODE SECTOR ARCHITECTURE 84VD2108 = Top sector 84VD2109 = Bottom sector PACKAGE TYPE PBS = 61-ball FBGA PTS = 56-pin TSOP (I) SPEED OPTION See Product Selector Guide Device Revision Bank Size 1 = 0.5 Mbit/ 15.5 Mbit 2 = 2 Mbit/ 14 Mbit 3 = 4 Mbit/ 12 Mbit 4 = 8 Mbit/ 8 Mbit

MB84VD2108X -85/MB84VD2109X -85 nnnn PACKAGE DIMENSIONS (Continued) 61-ball plastic FBGA (BGA-61P-M02) Dimensions in mm (inches) C 1999 FUJITSU LIMITED B61002S-1C-1 .049–.004 +.006 –0.10 +0.15 1.25 (Mounting height) 0.38±0.10 (.015±.004)(Stand off) ABCDEFGH 0.80(.031) 5.60(.220)REF 0.80(.031) 7.20(.283) REF 5.60(.220) INDEX BALL 61-Ø0.18–.002 +.004 –0.05 +0.10 0.10(.004) INDEX-MARK AREA

MB84VD2108X -85/MB84VD2109X -85 (Continued) 56-pin plastic TSOP(I) (FPT-56P-M04) Dimensions in mm (inches) 0.145 +0.05 –0.03 +.002 –.001 .006 0°~8° Details of "A" part 0.25(.010) (.018/.030) 0.45/0.75 "A" 0.08(.003) (Mounting height) (.045±.002) 1.15±0.05 (Stand off) (.004±.002) 0.10±0.05 INDEX 12.00±0.10 (.472±.004) 0.10(.004)M (.007±.001) 0.18±0.035 TYP 0.40(.016)

1998 FUJITSU LIMITED F56004S-1C-1C

MB84VD2108X -85/MB84VD2109X -85 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan T el: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC.

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