MB84VA2101

MB84VA2100 FUJITSU | Alldatasheet

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DS05-50103-2EFUJITSU SEMICONDUCTOR DATA SHEET MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M (· 8) FLASH MEMORY & 2M (· 8) STATIC RAM MB84VA2100 -10/MB84VA2101 -10 n FEATURES

• Power supply voltage of 2.7 to 3.6 V
• High performance 100 ns maximum access time
• Operating Temperature –20 to +85°C —F L A S H M E M O R Y
• Minimum 100,000 write/erase cycles
• Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture MB84VA2100: T op sector MB84VA2101: Bottom sector
• Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded Program TM Algorithms Automatically writes and verifies data at specified address
• D a t a Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
• L o w VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device Please refer to "MBM29LV160T/B" data sheet in detailed function —S R A M
• Power dissipation Operating : 35 mA max. Standby : 50 mA max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MB84VA2100 -10/MB84VA2101 -10 n BLOCK DIAGRAM VSSVCC s

16 M bit

MB84VA2100 -10/MB84VA2101 -10 n PIN ASSIGNMENTS (Top View) ABCDEFGH 6C E 1 sV SS DQ 1 A1 A2 A4 CE2s A 9 5A 10 DQ 5 DQ 2 A0 A3 A7 RY/BY A15 4O E DQ 7 DQ 4 DQ 0 A6 A19 RESET A16 3A 11 A8 A5 N.C. DQ 3 N.C. A 13 A20 2A 14 A18 N.C. CE fN . C . V CC fD Q 6 A12 Table 1 Pin Configuration Pin Function Input/ Output A0 to A17 Address Inputs (Common) I A18 to A20 Address Input (Flash) I DQ 0 to DQ7 Data Inputs/Outputs (Common) I/O CE f Chip Enable (Flash) I CE1 s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) O RESET Hardware Reset Pin/Sector Protection Unlock (Flash) I N.C. No Internal Connection — VSS Device Ground (Common) Power VCC f Device Power Supply (Flash) Power VCC s Device Power Supply (SRAM) Power

MB84VA2100 -10/MB84VA2101 -10 n PRODUCT LINE UP n BUS OPERATIONS Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes:1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. Flash Memory SRAM Max. Address Access Time (ns) 100 100 Max. CE Access Time (ns) 100 100 Max. OE Access Time (ns) 40 50 Table 2 User Bus Operations Operation (1), (3) CE fC E 1 sC E 2 s O E WE DQ 0 to DQ7 RESET Full Standby H HX XX H I G H - Z H XL Output Disable X X X H H HIGH-Z H Read from Flash (2) L HX LH D OUT H XL Write to Flash L HX HL D IN H XL Read from SRAM H L H L H D OUT H Write to SRAM H L H X L D IN H Flash Hardware Reset X HX XX H I G H - Z L XL +0.6 V –0.3 V

MB84VA2100 -10/MB84VA2101 -10 n FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

• One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes. Individual-sector, multiple-sector, or bulk-erase capability. MB84VA2100 Sector Architecture Sector Size Address Range

64 Kbytes 00000H to 0FFFFH

64 Kbytes 10000H to 1FFFFH

64 Kbytes 20000H to 2FFFFH

64 Kbytes 30000H to 3FFFFH

64 Kbytes 40000H to 4FFFFH

64 Kbytes 50000H to 5FFFFH

64 Kbytes 60000H to 6FFFFH

64 Kbytes 70000H to 7FFFFH

64 Kbytes 80000H to 8FFFFH

64 Kbytes 90000H to 9FFFFH

64 Kbytes A0000H to AFFFFH

64 Kbytes B0000H to BFFFFH

64 Kbytes C0000H to CFFFFH

64 Kbytes D0000H to DFFFFH

64 Kbytes E0000H to EFFFFH

64 Kbytes F0000H to FFFFFH

64 Kbytes 100000H to 10FFFFH

64 Kbytes 110000H to 11FFFFH

64 Kbytes 120000H to 12FFFFH

64 Kbytes 130000H to 13FFFFH

64 Kbytes 140000H to 14FFFFH

64 Kbytes 150000H to 15FFFFH

64 Kbytes 160000H to 16FFFFH

64 Kbytes 170000H to 17FFFFH

64 Kbytes 180000H to 18FFFFH

64 Kbytes 190000H to 19FFFFH

64 Kbytes 1A0000H to 1AFFFFH

64 Kbytes 1B0000H to 1BFFFFH

64 Kbytes 1C0000H to 1CFFFFH

64 Kbytes 1D0000H to 1DFFFFH

64 Kbytes 1E0000H to 1EFFFFH

32 Kbytes 1F0000H to 1F7FFFH

8 Kbytes 1F8000H to 1F9FFFH

8 Kbytes 1FA000H to 1FBFFFH

16 Kbytes 1FC000H to 1FFFFFH

MB84VA2101 Sector Architecture Sector Size Address Range

16 Kbytes 00000H to 03FFFH

8 Kbytes 04000H to 05FFFH

8 Kbytes 06000H to 07FFFH

32 Kbytes 08000H to 0FFFFH

64 Kbytes 1F0000H to 1FFFFFH

MB84VA2100 -10/MB84VA2101 -10 Table 3 Sector Address Tables (MB84VA2100) Sector Address A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 Address Range SA0 0 0 0 0 0 X X X 00000H to 0FFFFH SA1 0 0 0 0 1 X X X 10000H to 1FFFFH SA2 0 0 0 1 0 X X X 20000H to 2FFFFH SA3 0 0 0 1 1 X X X 30000H to 3FFFFH SA4 0 0 1 0 0 X X X 40000H to 4FFFFH SA5 0 0 1 0 1 X X X 50000H to 5FFFFH SA6 0 0 1 1 0 X X X 60000H to 6FFFFH SA7 0 0 1 1 1 X X X 70000H to 7FFFFH SA8 0 1 0 0 0 X X X 80000H to 8FFFFH SA9 0 1 0 0 1 X X X 90000H to 9FFFFH SA10 0 1 0 1 0 X X X A0000H to AFFFFH SA11 0 1 0 1 1 X X X B0000H to BFFFFH SA12 0 1 1 0 0 X X X C0000H to CFFFFH SA13 0 1 1 0 1 X X X D0000H to DFFFFH SA14 0 1 1 1 0 X X X E0000H to EFFFFH SA15 0 1 1 1 1 X X X F0000H to FFFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH S A 3 1 111110XX 1 F 0000H to 1F7FFFH S A 3 2 11111100 1 F 8000H to 1F9FFFH S A 3 3 11111101 1 F A 0 0 0 H t o 1 F B F F F H S A 3 4 1111111X 1 F C 0 0 0 H t o 1 F F F F F H

MB84VA2100 -10/MB84VA2101 -10 Table 4 Sector Address Tables (MB84VA2101) Sector Address A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 Address Range S A 0 0000000X 0 0000H to 03FFFH S A 1 00000010 0 4000H to 05FFFH S A 2 00000011 0 6000H to 07FFFH S A 3 0000010X 0 8 000H to 0FFFFH SA4 0 0 0 0 1 X X X 10000H to 1FFFFH SA5 0 0 0 1 0 X X X 20000H to 2FFFFH SA6 0 0 0 1 1 X X X 30000H to 3FFFFH SA7 0 0 1 0 0 X X X 40000H to 4FFFFH SA8 0 0 1 0 1 X X X 50000H to 5FFFFH SA9 0 0 1 1 0 X X X 60000H to 6FFFFH SA10 0 0 1 1 1 X X X 70000H to 7FFFFH SA11 0 1 0 0 0 X X X 80000H to 8FFFFH SA12 0 1 0 0 1 X X X 90000H to 9FFFFH SA13 0 1 0 1 0 X X X A0000H to AFFFFH SA14 0 1 0 1 1 X X X B0000H to BFFFFH SA15 0 1 1 0 0 X X X C0000H to CFFFFH SA16 0 1 1 0 1 X X X D0000H to DFFFFH SA17 0 1 1 1 0 X X X E0000H to EFFFFH SA18 0 1 1 1 1 X X X F0000H to FFFFFH SA19 1 0 0 0 0 X X X 100000H to 10FFFFH SA20 1 0 0 0 1 X X X 110000H to 11FFFFH SA21 1 0 0 1 0 X X X 120000H to 12FFFFH SA22 1 0 0 1 1 X X X 130000H to 13FFFFH SA23 1 0 1 0 0 X X X 140000H to 14FFFFH SA24 1 0 1 0 1 X X X 150000H to 15FFFFH SA25 1 0 1 1 0 X X X 160000H to 16FFFFH SA26 1 0 1 1 1 X X X 170000H to 17FFFFH SA27 1 1 0 0 0 X X X 180000H to 18FFFFH SA28 1 1 0 0 1 X X X 190000H to 19FFFFH SA29 1 1 0 1 0 X X X 1A0000H to 1AFFFFH SA30 1 1 0 1 1 X X X 1B0000H to 1BFFFFH SA31 1 1 1 0 0 X X X 1C0000H to 1CFFFFH SA32 1 1 1 0 1 X X X 1D0000H to 1DFFFFH SA33 1 1 1 1 0 X X X 1E0000H to 1EFFFFH SA34 1 1 1 1 1 X X X 1F0000H to 1FFFFFH

Table 5. 1 Flash Memory Autoselect Code Table 5. 2 Expanded Autoselect Code Table

MB84VA2100 -10/MB84VA2101 -10 Address bits A11 to A20 = X = “H” or “L” for all address commands except for Program Address (P A) and Sector Address (SA). Bus operations are defined in T able 2. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. RA =Address of the memory location to be read. P A =Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A 20, A19, A18, A17, A16, A15, A14, and A13 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location P A. SP A =Sector address to be protected. Set sector address (SA) and (A SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. Note:This command is valid while Fast Mode. Table 6 Flash Memory Command Definitions Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle R e a d / R e s e t 1X X X H F 0 H — ——— — — — ——— Read/Reset 3 555H AAH 2AAH 55H 555H F0H RA RD — — — — Autoselect 3 555H AAH 2AAH 55H 555H 90H — — — — — — Program 4 555H AAH 2AAH 55H 555H A0H PA PD — — — — Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0H) Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”). Data (30H) Set to Fast Mode 3 555H AAH 2AAH 55H 555H 20H — — — — — — Fast Program Reset from Fast Mode (Note) 2X X X H 9 0 H X X X H F 0 H — ————— — — Extended Sector Protect

4 XXXH 60H SPA 60H SPA 40H SPA SD — — — —

MB84VA2100 -10/MB84VA2101 -10 n ABSOLUTE MAXIMUM RATINGS –0.3 V to VCC s +0.5 V Note:Minimum DC voltage on input or I/O pins are –0.5 V . During voltage transitions, inputs may negativeovershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC f +0.5 V or VCC s +0.5 V . During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum rating conditions. Do not exceed these ratings. n RECOMMENDED OPERATING RANGES Commercial Devices Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.

MB84VA2100 -10/MB84VA2101 -10 n DC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit ILI Input Leakage Current — –1.0 — +1.0 mA ILO Output Leakage Current — –1.0 — +1.0 mA ICC1 f Flash VCC Active Current (Read) VCC f = VCC Max., CEf = VIL OE = VIH tCYCLE = 10 MHz — — 30 mA tCYCLE = 5 MHz — — 15 ICC2 f Flash VCC Active Current (Program/Erase) VCC f = VCC Max., CEf = VIL, OE = VIH ——3 5 m A ICC1 s SRAM V CC Active Current VCC s = VCC Max., CE1 s = VIL, CE2s = VIH ttCYCLE =10 MHz — — 40 mA tCYCLE = 1 MHz — — 12 mA ICC2 s SRAM V CC Active Current CE1 s = 0.2 V , CE2s = VCC s – 0.2 V , WE = VCC s – 0.2 V tCYCLE = 10 MHz — — 35 mA tCYCLE = 1 MHz — — 6 mA ISB1 f Flash VCC Standby Current VCC f = VCC Max., CEf = VCC f ± 0.3 V RESET = VCC f ± 0.3 V —— 5 mA ISB2 f Flash VCC Standby Current (RESET) VCC f = VCC Max., RESET = VSS ± 0.3 V — — 5 mA ISB1 s SRAM V CC Standby Current CE1 s = VIH or CE2s = VIL —— 2 m A ISB2 s** SRAM V CC Standby Current CE1 s = VCC –

0.2 V or CE2s

= 0.2 V VCC s = 3.0 V ±10% TA = 25°C — 1 2.5 mA TA = –20 to +85°C ——5 5 mA VCC s = 3.3 V ±0.3 V T A = 25°C — 1.5 3 mA TA = –20 to +85°C ——6 0 mA VCC s = 3.0 V TA = 25°C — 1 2 mA TA = –20 to +40°C —— 5 mA TA = –20 to +85°C —— 50 mA VIL Input Low Level — –0.3 — 0.6 V VIH Input High Level — 2.2 — VCC +0.3* V VOL Output Low Voltage Level IOL = 2.1 mA, VCC f = VCC s = VCC Min. —— 0 . 4 V VOH Output High Voltage Level IOH = –500 mA, VCC f = VCC s = VCC Min. VCC – 0.5 —— V VLKO Flash Low VCC Lock-Out Voltage —2 . 3 — 2 . 5 V * : VCC indicate lower of VCC f or VCC s ** :During standby mode with CE1s = VCCS – 0.2 V , CE2s should be CE2s < 0.2V or CE2s > VCCS – 0.2V

MB84VA2100 -10/MB84VA2101 -10 n AC CHARACTERISTICS

• C E Timing
• Timing Diagram for alternating SRAM to Flash Parameter Symbols Description Test Setup -10 Unit JEDEC Standard —t CCR CE Recover Time — Min. 0 ns CE f tCCR tCCR CE1 s CE2s tCCR tCCR

MB84VA2100 -10/MB84VA2101 -10

• Read Only Operations Characteristics (Flash) Note: T est Conditions–Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Parameter Symbols Description Test Setup -10 (Note) Unit JEDEC Standard Min. Max. t AVAV tRC Read Cycle Time — 100 — ns tAVQV tACC Address to Output Delay CE f = VIL OE = VIL —1 0 0 n s tELQV tCE f Chip Enable to Output Delay OE = VIL —1 0 0 n s tGLQV tOE Output Enable to Output Delay — — 40 ns tEHQZ tDF Chip Enable to Output High-Z — — 30 ns tGHQZ tDF Output Enable to Output High-Z — — 30 ns tAXQX tOH Output Hold Time From Addresses, CE f or OE, Whichever Occurs First —0 — n s —t READY RESET Pin Low to Read Mode — — 20 µs

MB84VA2100 -10/MB84VA2101 -10

• Read Cycle (Flash) WE OE CE f tCE tOE DQ Addresses Stable HIGH-Z Output Valid HIGH-Z tOEH tACC tRC RESET tACC tOH DQ tRC Addresses Stable HIGH-Z Output Valid tRH tDF ADDRESSES ADDRESSES

MB84VA2100 -10/MB84VA2101 -10

• Erase/Program Operations (Flash) Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. Parameter Symbols

Description

-10 Unit JEDEC Standard Min. Typ. Max. tAVAV tWC Write Cycle Time 100 — — ns tAVWL tAS Address Setup Time (WE to Addr.) 0 — — ns tAVEL tAS Address Setup Time (CEf to Addr.) 0 — — ns tWLAX tAH Address Hold Time (WE to Addr.) 50 — — ns tELAX tAH Address Hold Time (CEf to Addr.) 50 — — ns tDVWH tDS Data Setup Time 50 — — ns tWHDX tDH Data Hold Time 0 — — ns —t OES Output Enable Setup Time 0 — — ns —t OEH Output Enable Hold Time Read 0 — — ns T oggle and Data Polling 10 — — ns tGHEL tGHEL Read Recover Time Before Write (OE to CEf) 0 — — ns tGHWL tGHWL Read Recover Time Before Write (OE to WE)0 — — n s tWLEL tWS WE Setup Time (CEf to WE)0 — — n s tELWL tCS CEf Setup Time (WE to CEf) 0 — — ns tEHWH tWH WE Hold Time (CEf to WE)0 — — n s tWHEH tCH CEf Hold Time (WE to CEf) 0 — — ns tWLWH tWP Write Pulse Width 50 — — ns tELEH tCP CE f Pulse Width 50 — — ns tWHWL tWPH Write Pulse Width High 30 — — ns tEHEL tCPH CEf Pulse Width High 30 — — ns tWHWH1 tWHWH1 Byte Programming Operation — 8 — µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) —1— s e c ——1 5 s e c —t VCS VCC f Setup Time 50 — — µs —t VLHT Voltage T ransition Time (Note 2) 4 — — µs —t VIDR Rise Time to VID (Note 2) 500 — — ns —t RB Recover Time from RY/BY 0—— n s —t RP RESET Pulse Width 500 — — ns —t RH RESET Hold Time Before Read 200 — — ns —t EOE Delay Time from Embedded Output Enable — — 100 ns —t BUSY Program/Erase Valid to RY/BY Delay — — 90 ns

MB84VA2100 -10/MB84VA2101 -10

• Write Cycle (WE control) (Flash) tCH tWP tWHWH1 tWC tAH CE f OE tRC DQ tAS tFOE tWPH tGHWL tDH DQ 7PDA0H D OUT WE 555H PA PA tOH Data Polling3rd Bus Cycle tCS tCO tDS D OUT ADDRESSES

MB84VA2100 -10/MB84VA2101 -10

• Write Cycle (CEf control) (Flash) Notes:1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. tCP tDS tWHWH1 tWC tAH WE OE DQ tAS tCPH tDH DQ 7A0H D OUT CE f 555H PA PA Data Polling3rd Bus Cycle tWS tWH tGHEL PD ADDRESSES

MB84VA2100 -10/MB84VA2101 -10

• AC Waveforms Chip/Sector Erase Operations (Flash) ADDRESSES VCC CE f OE DQ WE 555H 2AAH 555H 555H 2AAH SA *1 tDS tCH tAS tAH tCS tWPH tDH tGHWL tVCS tWC tWP AAH 55H 80H AAH 55H 10H/ 30H for Sector Erase Note: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase. 30H

MB84VA2100 -10/MB84VA2101 -10

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
• AC Waveforms for Taggle Bit during Embedded Algorithm Operations (Flash) *DQ 7 = Valid Data (The device has completed the Embedded operation.) tOEH tFOE tWHWH1 or 2 CE f OE WE DQ 7 tO DtCH tCO DQ 7 = Valid DataDQ 7 DQ DQ 0 to DQ6 = Invalid tEOE DQ 0 to DQ6 Valid Data High-Z High-Z (DQ 0 to DQ6) Data In Data In *DQ 6 = Stops toggling. (The device has completed the Embedded operation.) CE f WE OE Data In DQ 6 = Toggle DQ 6 = Stop Toggling DQ 0 to DQ7 Data Valid tEOE DQ 6 = tOEH tOES DQ 6 Toggle

MB84VA2100 -10/MB84VA2101 -10

• R Y / B Y Timing Diagram during Write/Erase Operations (Flash)
• RESET , RY/BY Timing Diagram (Flash)
• Temporary Sector Unprotection (Flash) The rising edge of the last WE signal CE f RY/BY WE tBUSY Entire programming or erase operations tRP RESET tREADY RY/BY WE tRB 3 V RESET VCC CE WE RY/BY tVLHT Program or Erase Command Sequence 3 V tVLHT tVCS tVIDR VID tVLHT Unprotection period

MB84VA2100 -10/MB84VA2101 -10

• Extended Sector Protection (Flash) SP AX : Sector Address to be protected SP AY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 ms (min) SPAY RESET OE WE CE Data VCC Add SPAXSPAX 60H01H40H60H60H TIME-OUT tVCS tVLHT tVIDR tOE

MB84VA2100 -10/MB84VA2101 -10

• Read Cycle (SRAM)
• Read Cycle (Note 1) (SRAM) Note: 1. WE remains HIGH for the read cycle. Parameter Symbol Parameter Description Min. Max. Unit tRC Read Cycle Time 100 — ns tAA Address Access Time — 100 ns tCO1 Chip Enable (CE1s) Access Time — 100 ns tCO2 Chip Enable (CE2s) Access Time — 100 ns tOE Output Enable Access Time — 50 ns tCOE Chip Enable (CE1s Low and CE2s High) to Output Active 5 — ns tOEE Output Enable Low to Output Active 0 — ns tOD Chip Enable (CE1s High or CE2s Low) to Output High-Z — 40 ns tODO Output Enable High to Output High-Z — 40 ns tOH Output Data Hold Time 10 — ns tRC tAA tOH tCO1 tOD tODOtOEE tCOE VALID DATA OUT ADDRESSES CE1 s OE DQ CE2s tCOE tOE tCO2 tOD

MB84VA2100 -10/MB84VA2101 -10

• Write Cycle (SRAM)
• Write Cycle (Note 4) (WE control) (SRAM) Parameter Symbol Parameter Description Min. Max. Unit tWC Write Cycle Time 100 — ns tWP Write Pulse Width 60 — ns tCW Chip Enable to End of Write 80 — ns tAS Address Setup Time 0 — ns tWR Write Recovery Time 0 — ns tODW WE Low to Output High-Z — 40 ns tOEW WE High to Output Active 0 — ns tDS Data Setup Time 40 — ns tDH Data Hold Time 0 — ns tWC tAS tWP tWR tCW tODW tOEW tDS tDH VALID DATA IN ADDRESSES WE CE1 s D OUT D IN CE2s tCW Notes:2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. Note 2 Note 5 Note 3 Note 5

MB84VA2100 -10/MB84VA2101 -10

• Write Cycle (Note 4) (CE1s control) (SRAM) tWC tAS tWP tWR tCW tODWtCOE tDS tDH VALID DATA IN ADDRESSES WE CE1 s D OUT D IN CE2s tCW Notes:2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. Note 5 Note 5

MB84VA2100 -10/MB84VA2101 -10

• Write Cycle (Note 4) (CE2s Control) (SRAM) tWC tAS tWP tWR tCW tODWtCOE tDS tDH VALID DATA IN ADDRESSES WE CE1 s D OUT D IN CE2s Notes:2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. Note 5Note 5 tCW

MB84VA2100 -10/MB84VA2101 -10 n ERASE AND PROGRAMMING PERFORMANCE (Flash) n DATA RETENTION CHARACTERISTICS (SRAM) * : 5 mA (Max.) at TA = –20°C to +40°C

• C E 1s Controlled Data Retention Mode (Note 1) Parameter Limits Unit Comment Min. Typ. Max. Sector Erase Time — 1 15 sec Excludes programming time prior to erasure Byte Programming Time — 8 3,600 ms Excludes system-level overhead Chip Programming Time — 16.8 100 sec Excludes system-level overhead Erase/Program Cycle 100,000 — — cycles Parameter Symbol Parameter Description Min. Typ. Max. Unit VDH Data Retention Supply Voltage 2.0 — 3.6 V IDDS2 Standby Current VDH = 3.0 V — — 50* mA VDH = 3.6 V — — 60 mA tCDR Chip Deselect to Data Retention Mode Time 0 — — ns tR Recovery Time 5 — — ms VCC s 2.7 V VIH GND DATA RETENTION MODE See Note 2 tCDRCE1 s VCCS –0.2 V See Note 2 tR

MB84VA2100 -10/MB84VA2101 -10

• CE2s Controlled Data Retention Mode (Note 3) Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to Vccs+0.3V . 2.When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1 s during the transition of VCC s from 3.6 to 2.2 V . 3. In CE2s controlled data retention mode, input and input/output pins can be used between between -0.3V to Vccs+0.3V . n PIN CAPACITANCE Note: T est conditions TA = 25°C, f = 1.0 MHz Note: T est conditions TA = 25°C, f = 1.0 MHz n HANDLING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. n CAUTION 1. )The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. )For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command. Parameter Symbol Parameter Description Test Setup Typ. Max. Unit C IN Input Capacitance V IN = 0 T.B.D T.B.D pF C OUT Output Capacitance V OUT = 0 T.B.D T.B.D pF C IN2 Control Pin Capacitance V IN = 0 T.B.D T.B.D pF VCC s 2.7 V GND DATA RETENTION MODE VIH VIL CE2s tCDR tR 0.2 V

MB84VA2100 -10/MB84VA2101 -10 n PACKAGE n PACKAGE DIMENSIONS 48-pin plastic FBGA (BGA-48P-M10) C 1998 FUJITSU LIMITED MCM-M002-3-2 10.00±0.15 0.30±0.10 (.012±.004) 1.40±0.20 (.055±.008) 5.00±0.15 1.00±0.15 (.039±.006) 0.15(.006) INDEX 1st PIN Ø0.40±0.10 (Ø.016±.004) INDEX Dimension in mm (inches). 48-pin plastic BGA (BGA-48P-M10) Note: The actual shape of coners may differ from the dimension.

MB84VA2100 -10/MB84VA2101 -10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan T el: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA T el: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany T el: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New T ech Park Singapore 556741 T el: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9805 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.